TI1 MSP430F5171IYFFT Mixed-signal microcontroller Datasheet

Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
Reference
Design
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
MSP430F51x2, MSP430F51x1 Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply-Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low Power Consumption
– Active Mode (AM): 180 µA/MHz
– Standby Mode (LPM3 WDT Mode, 3 V): 1.1 µA
– Off Mode (LPM4 RAM Retention, 3 V): 0.9 µA
– Shutdown Mode (LPM4.5, 3 V): 0.25 µA
• Wake up From Standby Mode in Less Than 5 µs
• 16-Bit RISC Architecture, Extended Memory, 40-ns
Instruction Cycle Time
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals up to 25 MHz (XT1)
• Hardware Multiplier Supports 32-Bit Operations
• 3-Channel DMA
• Up to Twelve 5-V-Tolerant Digital Push/Pull I/Os
With up to 20-mA Drive Strength(1)
• 16-Bit Timer TD0 With Three Capture/Compare
Registers and Support of High-Resolution Mode
• 16-Bit Timer TD1 With Three Capture/Compare
Registers and Support of High-Resolution Mode
• 16-Bit Timer TA0 With Three Capture/Compare
Registers
• Universal Serial Communication Interfaces
(USCIs) (1)
– USCI_A0 Supports:
• Enhanced UART Supports Automatic BaudRate Detection
• IrDA Encoder and Decoder
• Synchronous SPI
– USCI_B0 Supports:
• I2C
• Synchronous SPI
• 10-Bit 200-ksps Analog-to-Digital Converter (ADC)
– Internal Reference
– Sample-and-Hold
– Autoscan Feature
– Up to 8 External Channels and 2 Internal
Channels, Including Temperature Sensor(1)
• Up to 16-Channel On-Chip Comparator Including
an Ultra-Low-Power Mode(1)
• Serial Onboard Programming, No External
Programming Voltage Needed
• Section 3 Summarizes Available Family Members
• Available in 40-Pin QFN (RSB), 38-Pin TSSOP
(DA), and 40-Pin Die-Sized BGA (YFF) Packages
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide
(1)
1.2
•
•
•
Full functionality in the 40-pin QFN package options. For the
available features of other packages, see Section 4.2.
Applications
Analog and Digital Sensor Systems
LED Lighting
Digital Power Supplies
•
•
•
Motor Controls
Remote Controls
Thermostats
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
1.3
www.ti.com
Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets
of peripherals targeted for various applications. The architecture, combined with five low-power modes, is
optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to
active mode in less than 5 µs.
The MSP430F51x2 microcontrollers include two 16-bit high-resolution timers, two USCIs (USCI_A0 and
USCI_B0), a 32-bit hardware multiplier, a high-performance 10-bit ADC, an on-chip comparator, a 3channel DMA, 5-V tolerant I/Os, and up to 29 I/O pins.
The MSP430F51x1 microcontrollers include two 16-bit high-resolution timers, two USCIs (USCI_A0 and
USCI_B0), a 32-bit hardware multiplier, an on-chip comparator, a 3-channel DMA, 5-V tolerant I/Os, and
up to 29 I/O pins.
Typical applications for these devices include analog and digital sensor systems, LED lighting, digital
power supplies, motor controls, remote controls, thermostats, digital timers, and hand-held meters.
Device Information (1)
PART NUMBER
MSP430F5172IYFF
BODY SIZE (2)
DSBGA (40)
3.1 mm × 2.8 mm
MSP430F5172IRSB
WQFN (40)
5 mm × 5 mm
MSP430F5172IDA
TSSOP (38)
12.5 mm × 6.2 mm
(1)
(2)
2
PACKAGE
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
The dimensions shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Device Overview
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
1.4
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Functional Block Diagrams
Figure 1-1 shows the functional block diagram for the MSP430F51x2 devices.
DVCC
AVCC
RST/NMI
DVSS
AVSS
XIN XOUT
Unified
Clock
System
DVIO
DVSS
ACLK
SMCLK
32KB
16KB
8KB
2KB
2KB
1KB
Flash
RAM
MCLK
Power
Management
SYS
Watchdog
LDO
SVM/SVS
Brownout
Port
Mapping
Controller
P1.x
8
P2.x
8
P3.x
8
PJ.x
7
I/O Ports
I/O Ports
I/O Ports
I/O Ports
P1
8 I/Os
2x 5 V, 20 mA
Interrupt
and Wakeup,
Pullup or
Pulldown
Resistors
P2
8 I/Os
8x 5 V, 20 mA
Interrupt
and Wakeup,
Pullup or
Pulldown
Resistors
P3
8 I/Os
2x 5 V, 20 mA
PJ
7 I/Os
Pullup or
Pulldown
Resistors
Pullup or
Pulldown
Resistors
CPUXV2
and
Working
Registers
3 DMA
Channel
EEM
(S: 3+1)
JTAG,
SBW
Interface
TA0
MPY32
Timer_A
3 CC
Registers
TD0
TD1
Timer_D
≤256 MHz
3 CC
Registers
With Buffer
Event
Control
Timer_D
≤256 MHz
3 CC
Registers
With Buffer
Event
Control
COMP_B
USCI
ADC10_A
A0: UART,
IrDA, SPI
10 Bit
200 KSPS
2
B0: SPI, I C
9 Channels
REF
16 Channels
High-,
Medium-, and
Ultra-LowPower
Modes
CRC16
Voltage
Reference
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram, MSP430F51x2
Figure 1-2 shows the functional block diagram for the MSP430F51x1 devices.
Device Overview
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
3
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
AVCC
DVCC
RST/NMI
DVSS
AVSS
XIN XOUT
Unified
Clock
System
www.ti.com
DVIO
DVSS
ACLK
SMCLK
32KB
16KB
8KB
2KB
2KB
1KB
Flash
RAM
MCLK
Power
Management
SYS
Watchdog
LDO
SVM/SVS
Brownout
Port
Mapping
Controller
P1.x
8
P2.x
8
I/O Ports
I/O Ports
P1
8 I/Os
2x 5 V, 20 mA
Interrupt
and Wakeup,
Pullup or
Pulldown
Resistors
P2
8 I/Os
8x 5 V, 20 mA
Interrupt
and Wakeup,
Pullup or
Pulldown
Resistors
P3.x
8
PJ.x
7
I/O Ports
I/O Ports
P3
8 I/Os
2x 5 V, 20 mA
PJ
7 I/Os
Pullup or
Pulldown
Resistors
Pullup or
Pulldown
Resistors
CPUXV2
and
Working
Registers
3 DMA
Channel
EEM
(S: 3+1)
JTAG,
SBW
Interface
TA0
MPY32
Timer_A
3 CC
Registers
TD0
TD1
Timer_D
≤256 MHz
3 CC
Registers
With Buffer
Event
Control
Timer_D
≤256 MHz
3 CC
Registers
With Buffer
Event
Control
COMP_B
USCI
REF
16 Channels
A0: UART,
IrDA, SPI
2
B0: SPI, I C
High-,
Medium-, and
Ultra-LowPower
Modes
CRC16
Voltage
Reference
Copyright © 2016, Texas Instruments Incorporated
Figure 1-2. Functional Block Diagram, MSP430F51x1
4
Device Overview
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table of Contents
1
Device Overview ......................................... 1
5.26
PMM, Brownout Reset (BOR)....................... 31
1.1
Features .............................................. 1
5.27
PMM, Core Voltage ................................. 31
1.2
Applications ........................................... 1
5.28
PMM, SVS High Side
1.3
Description ............................................ 2
5.29
PMM, SVM High Side ............................... 33
1.4
...............................
32
Functional Block Diagrams ........................... 3
5.30
PMM, SVS Low Side ................................ 33
2
3
Revision History ......................................... 6
Device Comparison ..................................... 7
5.31
PMM, SVM Low Side
33
5.32
Wake-up Times From Low-Power Modes
34
Related Products ..................................... 8
5.33
4
Terminal Configuration and Functions .............. 9
5.34
4.1
Pin Diagrams ......................................... 9
5.35
4.2
Signal Descriptions .................................. 11
5.36
Specifications ........................................... 14
5.37
5.38
3.1
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
........................
ESD Ratings ........................................
Recommended Operating Conditions ...............
Absolute Maximum Ratings
...........................
Inputs – Ports P1 and P2
Leakage Current – General-Purpose I/O ...........
Outputs – Ports P1, P3, PJ (Full Drive Strength,
P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6) ...........
Outputs – Ports P1 to P3 (Full Drive Strength, P1.6
and P1.7, P2.0 to P2.7, P3.0 and P3.1) ............
Outputs – Ports P1, P3, PJ (Reduced Drive
Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6).
Outputs – Ports P1 to P3 (Reduced Drive Strength,
P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1) .......
Output Frequency – Ports P1.0 to P1.5, P3.2 to
P3.7, PJ.0 to PJ.6 ...................................
Output Frequency – Ports P1.6 and P1.7, P2.0 to
P2.7, P3.0 and P3.1.................................
Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to
P3.7, PJ.0 to PJ.6 ...................................
Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to
P3.7, PJ.0 to PJ.6 ...................................
Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to
P2.7, P3.0 and P3.1.................................
Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to
P2.7, P3.0 and P3.1.................................
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
5.39
5.40
5.41
Thermal Resistance Characteristics ................ 17
Schmitt-Trigger Inputs – General-Purpose I/O (P1.0
to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6) ............ 17
Schmitt-Trigger Inputs – General-Purpose I/O (P1.6
and P1.7, P2.0 to P2.7, and P3.0 and P3.1) ........ 17
5.10
5.11
5.13
14
14
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 16
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 16
5.9
5.12
14
5.42
17
18
18
6
19
20
20
21
22
23
7
10-Bit ADC, Power Supply and Input Range
Conditions (MSP430F51x2 Devices Only) ..........
10-Bit ADC, Timing Parameters (MSP430F51x2
Devices Only) .......................................
10-Bit ADC, Linearity Parameters (MSP430F51x2
Devices Only) .......................................
REF, External Reference (MSP430F51x2 Devices
Only) .................................................
REF, Built-In Reference (MSP430F51x2 Devices
Only) .................................................
34
34
35
37
39
40
40
41
41
42
5.43
5.44
Comparator_B ....................................... 43
Timer_D, Power Supply and Reference Clock
Conditions ........................................... 44
5.45
Timer_D, Local Clock Generator Frequency ........ 45
5.46
Timer_D, Trimmed Clock Frequencies.............. 47
5.47
5.48
Timer_D, Frequency Multiplication Mode ........... 47
Timer_D, Input Capture and Output Compare
Timing ............................................... 48
5.49
Flash Memory ....................................... 49
5.50
JTAG and Spy-Bi-Wire Interface .................... 49
18
19
...............................
..........
Timer_A .............................................
USCI (UART Mode) .................................
USCI (SPI Master Mode)............................
USCI (SPI Slave Mode) .............................
USCI (I2C Mode) ....................................
Detailed Description ................................... 50
.................................................
6.1
CPU
6.2
Instruction Set ....................................... 51
6.3
Operating Modes .................................... 52
6.4
Interrupt Vector Addresses.......................... 53
6.5
Memory Organization ............................... 54
6.6
Bootloader (BSL) .................................... 54
6.7
Flash Memory ....................................... 55
6.8
RAM ................................................. 55
..........................................
50
6.9
Peripherals
6.10
Input/Output Diagrams .............................. 74
55
6.11
Device Descriptors .................................. 91
Device and Documentation Support ............... 97
7.1
Getting Started and Next Steps ..................... 97
25
7.2
Device Nomenclature ............................... 97
27
7.3
Tools and Software
28
7.4
Documentation Support ............................ 101
Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 29
Internal Reference, Low-Frequency Oscillator
(REFO) .............................................. 29
7.5
Related Links
.....
Crystal Oscillator, XT1, High-Frequency Mode ....
Crystal Oscillator, XT1, Low-Frequency Mode
DCO Frequency ..................................... 30
7.6
7.7
7.8
.................................
......................................
Community Resources.............................
Trademarks ........................................
Electrostatic Discharge Caution ...................
Table of Contents
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
99
102
103
103
103
5
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
7.9
Export Control Notice .............................. 103
7.10
Glossary............................................ 103
www.ti.com
8
Mechanical, Packaging, and Orderable
Information ............................................. 104
2 Revision History
Changes from May 13, 2015 to May 9, 2016
•
•
•
•
•
•
•
6
Page
Added Section 3.1, Related Products ............................................................................................. 8
Added "with reconfigurable port mapping secondary function" to applicable GPIO descriptions (ports P1, P2, and
P3) in Table 4-1, Terminal Functions ............................................................................................. 11
Changed all MIN, TYP, and MAX values for the VREF parameter in Section 5.43, Comparator_B ....................... 43
Changed all instances of "bootstrap loader" to "bootloader" .................................................................. 54
Corrected spelling of NMIIFG in Table 6-8, System Module Interrupt Vector Registers ................................... 59
Replaced former section Development Tools Support with Section 7.3, Tools and Software ........................... 99
Changed format and added content to Section 7.4, Documentation Support ............................................ 101
Revision History
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
USCI
DEVICE
FLASH
(KB)
SRAM
(KB)
MSP430F5172
32
2
MSP430F5152
MSP430F5132
MSP430F5171
MSP430F5151
MSP430F5131
(1)
(2)
(3)
(4)
16
8
32
16
8
2
1
2
2
1
Timer_A (3) Timer_D (4)
3
3
3
3
3
3
3, 3
3, 3
3, 3
3, 3
3, 3
3, 3
CHANNEL A:
UART, IrDA,
SPI
CHANNEL B:
SPI, I2C
1
1
1
1
1
1
1
1
1
1
1
1
ADC10_A
(Ch)
Comp_B
(Ch)
I/O
9 ext, 2 int
16
31
8 ext, 2 int
15
29
9 ext, 2 int
16
31
8 ext, 2 int
15
29
9 ext, 2 int
16
31
8 ext, 2 int
15
29
16
31
15
29
16
31
15
29
16
31
15
29
–
–
–
PACKAGE
40 QFN
40 DSBGA
38 TSSOP
40 QFN
40 DSBGA
38 TSSOP
40 QFN
40 DSBGA
38 TSSOP
40 QFN
40 DSBGA
38 TSSOP
40 QFN
40 DSBGA
38 TSSOP
40 QFN
40 DSBGA
38 TSSOP
For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at
www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_D with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_D, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Device Comparison
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
7
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
3.1
www.ti.com
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for MSP 16-Bit and 32-Bit MCUs Low-power mixed-signal processors with smart analog and
digital peripherals for a wide range of industrial and consumer applications.
Products for Low Power + Performance MCUs MSP low power + performance microcontrollers from TI
provide designers with increased processing capability, smart analog, advanced security,
and display and communication peripherals while using less watts than ever before for the
development of “always on” embedded applications.
Products for MSP430F5x/6x MCUs MSP430F5x/6x microcontrollers from the MSP Low-Power +
Performance MCU series offer low power with added performance and increased design
options. These 16-bit devices feature new and innovative integrated peripherals such as
USB and LCD on chip, in addition to higher CPU speeds and more memory.
Companion Products for MSP430F5172 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for MSP430F5172 TI Designs Reference Design Library is a robust reference design
library that spans analog, embedded processor, and connectivity. Created by TI experts to
help you jump start your system design, all TI Designs include schematic or block diagrams,
BOMs, and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
8
Device Comparison
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
4 Terminal Configuration and Functions
4.1
Pin Diagrams
AVSS
PJ.5/XIN
PJ.4/XOUT
AVCC
P3.7/PM_TA0.0/A6*/CB10
P3.6/PM_TA0.1/A7*/VEREF-*/CB11
P3.5/PM_TA0.2/A8*/VEREF+*/CB12
RST/NMI/SBWTDIO
TEST/SBWTCK
P3.4/PM_TD0CLK/PM_MCLK
Figure 4-1 shows the pinout for the 40-pin RSB package.
1 39 38 37 36 35 34 33 32
2
3
4
5
6
7
8
9
12 13 14 15 16 17 18 19
29
28
27
26
25
24
23
22
P3.3/PM_TA0CLK/PM_CBOUT/CB13
P3.2/PM_TD0.0/PM_SMCLK/CB14
PJ.6/TD1CLK/TD0.1/CB15
DVCC
DVSS
VCORE
P3.1/PM_TEC1FLT0/PM_TD1.2
P3.0/PM_TEC1FLT2/PM_TD1.1
P2.7/PM_TEC1CLR/PM_TEC1FLT1/PM_TD1.0
P2.6/PM_TEC0FLT1/PM_TD0.2
P1.6/PM_TD0.0
P1.7/PM_TD0.1
P2.0/PM_TD0.2
P2.1/PM_TD1.0
P2.2/PM_TD1.1
P2.3/PM_TD1.2
DVIO
DVSS
P2.4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0.0
P2.5/PM_TEC0FLT0/PM_TD0.1
P1.0/PM_UCA0CLK/PM_UCB0STE/A0*/CB0
P1.1/PM_UCA0TXD/PM_UCA0SIMO/A1*/CB1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A2*/CB2
P1.3/PM_UCB0CLK/PM_UCA0STE/A3*/CB3
P1.4/PM_UCB0SIMO/PM_UCB0SDA/A4*/CB4
P1.5/PM_UCB0SOMI/PM_UCB0SCL/A5*/CB5
PJ.0/SMCLK/TDO/CB6
PJ.1/MCLK/TDI/TCLK/CB7
PJ.2/ADC10CLK/TMS/CB8
PJ.3/ACLK/TCK/CB9
* Only MSP430F51x2 devices
Figure 4-1. 40-Pin RSB Package (Top View)
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
9
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Figure 4-2 shows the pinout for the 38-pin DA package.
AVCC
PJ.4/XOUT
PJ.5/XIN
AVSS
P1.0/PM_UCA0CLK/PM_UCB0STE/A0*/CB0
P1.1/PM_UCA0TXD/PM_UCA0SIMO/A1*/CB1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A2*/CB2
P1.3/PM_UCB0CLK/PM_UCA0STE/A3*/CB3
P1.4/PM_UCB0SIMO/PM_UCB0SDA/A4*/CB4
P1.5/PM_UCB0SOMI/PM_UCB0SCL/A5*/CB5
PJ.0/SMCLK/TDO/CB6
PJ.1/MCLK/TDI/TCLK/CB7
PJ.2/ADC10CLK/TMS/CB8
PJ.3/ACLK/TCK/CB9
P1.6/PM_TD0.0
P1.7/PM_TD0.1
P2.0/PM_TD0.2
P2.1/PM_TD1.0
P2.2/PM_TD1.1
* Only MSP430F51x2
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
P3.6/PM_TA0.1/A7*/VEREF-*-/CB11
P3.5/PM_TA0.2/A8*/VEREF+*/CB12
RST/NMI/SBWTDIO
TEST/SBWTCK
P3.3/PM_TA0CLK/PM_CBOUT/CB13
P3.2/PM_TD0.0/PM_SMCLK/CB14
PJ.6/TD1CLK/TD0.1/CB15
DVCC
DVSS
VCORE
P3.1/PM_TEC1FLT0/PM_TD1.2
P3.0/PM_TEC1FLT2/PM_TD1.1
P2.7/PM_TEC1CLR/PM_TEC1FLT1/PM_TD1.0
P2.6/PM_TEC0FLT1/PM_TD0.2
P2.5/PM_TEC0FLT0/PM_TD0.1
P2.4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0.0
DVSS
DVIO
P2.3/PM_TD1.2
Figure 4-2. 38-Pin DA Package (Top View)
Figure 4-3 shows the pinout for the 40-pin YFF package.
Top View
D
Ball-Side View
P1.6
P2.1
P2.2
DVIO
DVSS
P2.5
P2.5
DVSS
DVIO
P2.2
P2.1
P1.6
G6
G5
G4
G3
G2
G1
G1
G2
G3
G4
G5
G6
PJ.2
P1.7
P2.0
P2.4
P2.6
P3.0
P3.0
P2.6
P2.4
P2.0
P1.7
PJ.2
F6
F5
F4
F3
F2
F1
F1
F2
F3
F4
F5
F6
PJ.0
PJ.1
PJ.3
P2.3
P2.7
P3.1
P3.1
PJ.1
PJ.0
E6
E5
E4
E3
E2
E1
E1
E2
E5
E6
P1.5
P1.4
TEST
VCORE
VCORE
TEST
P1.4
P1.5
D6
D5
D2
D1
D1
D2
D5
D6
P1.3
P1.2
AVSS
AVCC
PJ.6
DVSS
DVSS
PJ.6
AVCC
AVSS
P1.2
P1.3
C6
C5
C4
C3
C2
C1
C1
C2
C3
C4
C5
C6
P1.1
P1.0
P3.7
RST
P3.2
DVCC
DVCC
P3.2
RST
P3.7
P1.0
P1.1
B6
B5
B4
B3
B2
B1
B1
B2
B3
B4
B5
B6
XIN
XOUT
P3.6
P3.5
P3.4
P3.3
P3.3
P3.4
P3.5
P3.6
XOUT
XIN
A6
A5
A4
A3
A2
A1
A1
A2
A3
A4
A5
A6
E
D
P2.7 P2.3
PJ.3
E3
E4
E
Figure 4-3. 40-Pin YFF Package (Top and Bottom Views)
10
Terminal Configuration and Functions
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
4.2
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Signal Descriptions
Table 4-1 describes the signals for all device and package variants.
Table 4-1. Terminal Functions
TERMINAL
NAME
P1.0/
PM_UCA0CLK/
<br/>
PM_UCB0STE/
A0 (3)/
CB0
P1.1/
PM_UCA0TXD/
PM_UCA0SIMO/
A1 (3)/
CB1
P1.2/
PM_UCA0RXD/
PM_UCA0SOMI/
A2 (3)/
CB2
P1.3/
PM_UCB0CLK/
<br/>
PM_UCA0STE/
A3 (3)/
CB3
P1.4/
PM_UCB0SIMO/
PM_UCB0SDA/
A4 (3)/
CB4
P1.5/
PM_UCB0SOMI/
PM_UCB0SCL/
A5 (3)/
CB5
PJ.0/
SMCLK/
TDO/
CB6
NO. (2)
RSB
1
2
3
4
5
6
7
PJ.1/
MCLK/
TDI/TCLK/
CB7
8
PJ.2/
ADC10CLK/
TMS/
CB8
9
DA
5
6
7
8
9
10
11
12
13
I/O (1)
YFF
B5
B6
C5
C6
D5
D6
E6
E5
F6
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function (4)
Default mapping: Clock signal input – USCI_A0 SPI slave mode; Clock signal output –
USCI_A0 SPI master mode
Default mapping: Slave transmit enable – USCI_B0 SPI mode
Analog input A0 – 10-bit ADC (3)
Comparator_B Input 0
I/O
General-purpose digital I/O
Default mapping: Transmit data – USCI_A0 UART mode
Default mapping: Slave in, master out – USCI_A0 SPI mode
Analog input A1 – 10-bit ADC (3)
Comparator_B Input 1
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A0 UART mode
Default mapping: Slave out, master in – USCI_A0 SPI mode
Analog input A2 – 10-bit ADC (3)
Comparator_B Input 2
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input – USCI_B0 SPI slave mode; Clock signal output –
USCI_B0 SPI master mode
Default mapping: Slave transmit enable – USCI_A0 SPI mode
Analog input A3 – 10-bit ADC (3)
Comparator_B Input 3
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_B0 SPI mode
Default mapping: I2C data – USCI_B0 I2C mode
Analog input A4 – 10-bit ADC (3)
Comparator_B Input 4
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_B0 SPI mode
Default mapping: I2C clock – USCI_B0 I2C mode
Analog input A5 – 10-bit ADC (3)
Comparator_B Input 5
I/O
General-purpose digital I/O
SMCLK clock output
Test data output port
Comparator_B Input 6
I/O
General-purpose digital I/O
MCLK clock output
Test data input or test clock input
Comparator_B Input 7
I/O
General-purpose digital I/O
ADC10_A clock output
Test mode select
Comparator_B Input 8
General-purpose digital I/O
ACLK output port
Test clock
Comparator_B Input 9
PJ.3/
ACLK/
TCK/
CB9
10
14
E4
I/O
P1.6/
PM_TD0.0
11
15
G6
I/O,
DVIO
(1)
(2)
(3)
(4)
DESCRIPTION
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR0 compare output/capture input
I = input, O = output
N/A = not available on this package offering
The ADC10_A module is available on MSP430F51x2 devices. The secondary pin functions Ax (ADC10_A channel x) available only in
MSP430F51x2 devices.
For details on the Port Mapping Controller, see Section 6.9.2.
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
11
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
NO. (2)
I/O (1)
DESCRIPTION
RSB
DA
YFF
P1.7/
PM_TD0.1
12
16
F5
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR1 compare output/capture input
P2.0/
PM_TD0.2
13
17
F4
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR2 compare output/capture input
P2.1/
PM_TD1.0
14
18
G5
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR0 compare output/capture input
P2.2/
PM_TD1.1
15
19
G4
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR1 compare output/capture input
P2.3/
PM_TD1.2
16
20
E3
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR2 compare output/capture input
DVIO
17
21
G3
5-V tolerant digital I/O power supply
DVSS
18
22
G2
Digital ground supply
P2.4/
PM_TEC0CLR/
PM_TEC0FLT2/
PM_TD0.0
F3
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 external clear input
Default mapping: TD0 fault input channel 2 (controlled by module input enable)
Default mapping: TD0 CCR0 compare output
19
23
P2.5/
PM_TEC0FLT0/
PM_TD0.1
20
24
G1
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 fault input channel 0
Default mapping: TD0 CCR1 compare output
P2.6/
PM_TEC0FLT1/
PM_TD0.2
21
25
F2
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 fault input channel 1
Default mapping: TD0 CCR2 compare output
P2.7/
PM_TEC1CLR/
PM_TEC1FLT1/
PM_TD1.0
22
26
E2
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 external clear
Default mapping: TD1 fault input channel 1 (controlled by module input enable)
Default mapping: TD1 CCR0 compare output
P3.0/
PM_TEC1FLT2/
PM_TD1.1
23
27
F1
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 fault input channel 2
Default mapping: TD1 CCR1 compare output
P3.1/
PM_TEC1FLT0/
PM_TD1.2
24
28
E1
I/O,
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 fault input channel 0
Default mapping: TD1 CCR2 compare output
VCORE
25
29
D1
Regulated core power supply
DVSS
26
30
C1
Digital ground supply
DVCC
27
31
B1
Digital power supply
PJ.6/
TD1CLK/
TD0.1/
CB15
28
32
C2
I/O
General-purpose digital I/O
TD1 clock input
TD0 CCR1 compare output
Comparator_B Input 15
P3.2/
PM_TD0.0/
PM_SMCLK/
CB14
29
33
B2
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR0 capture input
Default mapping: SMCLK output
Comparator_B Input 14
P3.3/
PM_TA0CLK/
PM_CBOUT/
CB13
30
34
A1
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 clock input
Default mapping: Comparator_B output
Comparator_B Input 13
P3.4/
PM_TD0CLK/
PM_MCLK
31
–
A2
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 clock input
Default mapping: MCLK output
TEST/
SBWTCK
32
35
D2
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
RST/
NMI/
SBWTDIO
33
36
B3
Reset input active low (5)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
(5)
12
When this pin is configured as reset, the internal pullup resistor is enabled by default.
Terminal Configuration and Functions
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
P3.5/
PM_TA0.2/
A8 (3)
VEREF+/
CB12
NO. (2)
RSB
34
DA
37
I/O (1)
DESCRIPTION
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR2 compare output/capture input
Analog input A8 – 10-bit ADC (3)
Positive terminal for the ADC reference voltage for an external applied reference voltage
Comparator_B Input 12
YFF
A3
P3.6/
PM_TA0.1/
A7 (3)/
VEREF-/
CB11
35
38
A4
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR1 compare output/capture input
Analog input A7 – 10-bit ADC (3)
Negative terminal for the ADC reference voltage for an external applied reference
voltage
Comparator_B Input 11
P3.7/
PM_TA0.0/
A6 (3)/
CB10
36
–
B4
I/O
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR0 compare output/capture input
Analog input A6 – 10-bit ADC (3)
Comparator_B Input 10
AVCC
37
1
C3
PJ.4/
XOUT
38
2
A5
I/O
General-purpose digital I/O
Output terminal of crystal oscillator
PJ.5/
XIN
39
3
A6
I/O
General-purpose digital I/O
Input terminal for crystal oscillator
AVSS
40
4
C4
Analog ground supply
QFN pad
–
NA
NA
Recommended to connect to DVSS externally
Analog power supply
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
13
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage VCC applied at DVCC to DVSS
–0.3
4.1 V
V
Voltage VIO applied at VIO to DVSS
–0.3
6.1 V
V
Voltage applied to any pin (excluding VCORE) (2)
–0.3
VCC + 0.3
V
Diode current at any device pin
±2
mA
Maximum operating junction temperature, TJ
95
°C
150
°C
Storage temperature, Tstg
(1)
(2)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
5.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
NOM
MAX
PMMCOREVx = 0
1.8
3.6
PMMCOREVx = 0, 1
2.0
3.6
PMMCOREVx = 0, 1, 2
2.2
3.6
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
VCC
Supply voltage during program execution and flash
programming
V(AVCC) = V(DVCC) = VCC (1) (2)
VIO
Supply voltage of pins P1.6, P1.7, P2.0 to P2.7, P3.0, and P3.1 supplied by VIO (3)
VSS
Supply voltage V(AVSS) = V(DVSS) = VSS
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
85
C(VCORE)
Recommended capacitor at VCORE (4)
C(DVCC)/
C(VCORE)
Capacitor ratio of DVCC to VCORE
(1)
(2)
(3)
(4)
14
1.8
5.5
0
UNIT
V
V
V
470
°C
°C
nF
10
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can
be tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for
the exact values and further details.
TI recommends powering DVCC and AVCC before powering DVIO. At DVCC and AVCC voltages higher than 1.8 V, the maximum
difference of 0.3 V between DVIO and DVCC and AVCC can be exceeded.
A capacitor tolerance of ±20% or better is required.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
fSYSTEM
PINT
Processor frequency (maximum MCLK frequency) (5)
(see Figure 5-1)
(6)
NOM
MAX
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
12
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
0
16
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
20
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
25
Internal power dissipation
UNIT
MHz
VCC × I(DVCC)
W
W
PIO
I/O power dissipation of the I/O pins powered by DVCC
(VCC – VIOH) × IIOH +
VIOL × IIOL
PIO5
I/O power dissipation of the I/O pins powered by VIO
(VIO – VIOH5) × IIOH5 +
VIOL5 × IIOL5
W
PMAX
Maximum allowed power dissipation, PMAX > PIO + PIO5 + PINT
(TJ – TA) / RθJA
W
(5)
(6)
The MSP430™ CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
16
12
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Frequency vs Supply Voltage
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
15
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.4
www.ti.com
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
IAM,
IAM,
Flash
Flash
RAM
RAM
5.5
EXECUTION
MEMORY
VCC
3V
3V
PMMCOREVx
PARAMETER
FREQUENCY (fDCO = fMCLK = fSMCLK)
1 MHz
8 MHz
12 MHz
20 MHz
25 MHz
UNIT
TYP
MAX
TYP
MAX
0
0.24
0.27
1.48
1.60
1
0.26
–
1.66
–
2
0.28
–
1.83
–
3
0.28
–
1.83
0
0.17
0.2
0.89
1
0.18
–
1.00
2
0.20
–
3
0.20
–
TYP
MAX
TYP
MAX
TYP
MAX
–
–
–
–
–
–
2.48
2.7
–
–
–
–
2.72
–
4.50
4.8
–
–
–
2.66
–
4.40
–
5.60
6.15
0.97
–
–
–
–
–
–
–
1.49
1.62
–
–
–
–
1.14
–
1.68
–
2.75
3.0
–
–
1.20
–
1.78
–
2.92
–
3.64
4.0
ILPM0, 1MHz
Low-power mode 0
ILPM2
Low-power mode 2
VCC
PMMCOREVx
PARAMETER
2.2 V
0
3V
3
2.2 V
3V
2.2 V
3V
2.2 V
ILPM3, XT1LF
Low-power mode 3,
crystal mode
3V
2.2 V
3V
2.2 V
3V
2.2 V
3V
2.2 V
ILPM3, VLO
Low-power mode 3,
VLO mode
3V
2.2 V
3V
2.2 V
3V
ILPM4
Low-power mode 4
ILPM4.5
16
mA
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(1)
(2)
mA
Low-power mode 4.5
3V
–40°C
MAX
TYP
82
90
88
100
0
10
3
9
0
1
2
3
0
1
2
3
TYP
25°C
60°C
MAX
TYP
85
90
85
100
12.5
10
11.5
11
1.7
–
2.0
–
1.8
(2)
85°C
MAX
TYP
MAX
87
95
85
100
90
104
88
104
12
10
12.5
12.5
13
13
11
15
12
14
1.8
2.0
2.5
–
3.5
6.0
2.0
2.2
3.0
–
3.7
6.0
–
1.9
–
2.5
–
4.0
–
2.1
–
2.2
–
2.5
–
4.0
–
1.8
–
2.0
–
2.5
–
4.2
–
2.0
–
2.2
–
2.8
–
4.2
–
1.9
–
2.0
2.5
2.9
–
4.8
6.5
2.1
–
2.2
2.5
3.0
–
5.2
7.0
1.0
–
1.0
1.25
1.6
–
3.5
4.5
1.1
–
1.2
1.4
1.5
–
3.6
5.0
1.0
–
1.1
–
1.8
–
3.0
–
1.3
–
1.1
–
2.0
–
3.2
–
1.1
–
1.1
–
1.8
–
3.1
–
1.1
–
1.2
–
2.0
–
3.2
–
1.1
–
1.1
1.4
1.9
–
3.5
5.0
1.1
–
1.2
1.5
2.1
–
4.0
5.2
0
0.8
–
0.9
1.3
1.4
–
3.5
4.7
1
0.8
–
1.0
–
1.4
–
3.5
–
2
0.8
–
1.0
–
1.5
–
3.6
–
3
0.9
–
1.0
1.3
1.6
–
3.6
5.0
2.2 V
x
0.06
–
0.20
0.26
0.33
–
0.60
0.9
3V
x
0.07
–
0.25
0.29
0.37
–
0.77
0.9
UNIT
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. DVIO = DVCC = AVCC.
The currents are characterized with a Micro Crystal MS1V-T1K SMD crystal with a load capacitance of 12.5 pF. The internal and
external load capacitance are chosen to closely match the required 9 pF.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
5.6
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Thermal Resistance Characteristics
VALUE
Low-K board (JESD51-3)
θJA
Junction-to-ambient thermal resistance, still air
High-K board (JESD51-7)
θJC
Junction-to-case thermal resistance
5.7
QFN (RSB)
87
TSSOP (DA)
109
QFN (RSB)
35
TSSOP (DA)
69
QFN (RSB)
36
TSSOP (DA)
19
UNIT
°C/W
°C/W
Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor (1)
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
TYP
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Also applies to RST pin when pullup or pulldown resistor is enabled.
5.8
Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0
and P3.1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
5.9
VIO
MIN
1.8 V
0.80
1.40
3V
1.20
2.00
5V
2.10
2.50
1.8 V
0.45
0.90
3V
0.75
1.30
5V
1.10
1.60
1.8 V
0.27
0.45
3V
0.45
0.65
5V
0.9
1.2
20
TYP
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
External interrupt timing
(2)
TEST CONDITIONS
VCC or VIO
Port P1.0 to P1.5, External trigger pulse duration to
set interrupt flag
1.8 V to 3.6 V
20
1.8 V to 5 V
25
Port P1.6 and P1.7, and P2.0 to P2.7, External
trigger pulse duration to set interrupt flag
MIN
MAX
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
17
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.10 Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
High-impedance
leakage current
TEST CONDITIONS
Port P1.0 to P1.5, P3.0 to P3.7,
PJ.0 to PJ.6
(1) (2)
Port P1.6 and P1.7, P2.0 to P2.7
VCC
MIN
TYP
MAX
1.8 V to 3.6 V
±1
±50
1.8 V to 5 V
±1
±50
UNIT
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (2)
I(OHmax) = –5 mA (1)
I(OHmax) = –15 mA (2)
I(OLmax) = 3 mA (1)
VOL
Low-level output voltage
(2)
1.8 V
3V
1.8 V
I(OLmax) = 10 mA (2)
I(OLmax) = 5 mA (1)
3V
I(OLmax) = 15 mA (2)
(1)
VCC
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OH5max) = –3 mA
I(OH5max) = –10 mA (2)
VOH5
High-level output voltage
I(OH5max) = –5 mA (1)
I(OH5max) = –15 mA
(2)
I(OH5max) = –7 mA (1)
I(OH5max) = –20 mA (2)
I(OL5max) = 3 mA
Low-level output voltage
I(OL5max) = 5 mA (1)
I(OL5max) = 15 mA (2)
I(OL5max) = 7 mA (1)
I(OL5max) = 20 mA (2)
(1)
(2)
18
1.8 V
3V
5V
(1)
I(OL5max) = 10 mA (2)
VOL5
VIO
(1)
1.8 V
3V
5V
MIN
MAX
VIO – 0.25
VIO
VIO – 0.60
VIO
VIO – 0.25
VIO
VIO – 0.60
VIO
VIO – 0.25
VIO
VIO – 0.60
VIO
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OH5max) and I(OL5max), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OH5max) and I(OL5max), for all outputs combined should not exceed ±200 mA to hold the maximum voltage
drop specified.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0
to PJ.6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA (2)
VOH
High-level output voltage
I(OHmax) = –3 mA (3)
I(OHmax) = –2 mA (2)
I(OHmax) = –6 mA (3)
I(OLmax) = 1 mA (2)
VOL
Low-level output voltage
(3)
1.8 V
3V
1.8 V
I(OLmax) = 3 mA (3)
I(OLmax) = 2 mA (2)
3V
I(OLmax) = 6 mA (3)
(1)
(2)
VCC
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0
and P3.1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OH5max) = –1 mA
I(OH5max) = –3 mA (3)
VOH5
High-level output voltage
I(OH5max) = –2 mA (2)
I(OH5max) = –6 mA
(3)
I(OH5max) = –4 mA (2)
I(OH5max) = –12 mA (3)
I(OL5max) = 1 mA
Low-level output voltage
I(OL5max) = 2 mA (2)
I(OL5max) = 6 mA (3)
I(OH5max) = 4 mA (2)
I(OL5max) = 12 mA (3)
(1)
(2)
(3)
1.8 V
3V
5.0 V
(2)
I(OL5max) = 3 mA (3)
VOL5
VIO
(2)
1.8 V
3V
5.0 V
MIN
MAX
VIO – 0.25
VIO
VIO – 0.60
VIO
VIO – 0.25
VIO
VIO – 0.60
VIO
VIO – 0.25
VIO
VIO – 0.60
VIO
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OH5max) and I(OL5max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OH5max) and I(OL5max), for all outputs combined, should not exceed ±200 mA to hold the maximum voltage
drop specified.
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
19
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
fPort_CLK
(1)
(2)
TEST CONDITIONS
Port output frequency
(with load)
PJ.0/SMCLK
CL = 20 pF, RL = 1 kΩ (1)
Clock output frequency
PJ.3/ACLK
PJ.0/SMCLK
PJ.1/MCLK
CL = 20 pF (2)
(2)
MIN
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
MAX
UNIT
MHz
MHz
A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
20
Clock output frequency
TEST CONDITIONS
P1.6 port mapper SMCLK from P3.4,
CL = 20 pF, RL = 1 kΩ (1) (2)
P1.6 port mapper SMCLK from P3.4,
CL = 20 pF (2)
MIN
VCC = 1.8 V, VIO = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V, VIO = 3 V,
PMMCOREVx = 3
25
VCC = 3 V, VIO = 5 V,
PMMCOREVx = 3
25
VCC = 1.8 V, VIO = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V, VIO = 3 V,
PMMCOREVx = 3
25
VCC = 3 V, VIO = 5 V,
PMMCOREVx = 3
25
MAX
UNIT
MHz
MHz
A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0
to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
VCC = 3.0 V
Px.y
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
−5.0
−10.0
−25.0
0.0
4.0
3.0
2.0
1.0
0.5
1.0
1.5
2.0
0.0
VCC = 3.0 V
Px.y
−20.0
5.0
VOL – Low-Level Output Voltage – V
Figure 5-3. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
−15.0
TA = 85°C
6.0
0.0
0.0
3.5
VOL – Low-Level Output Voltage – V
Figure 5-2. Typical Low-Level Output Current vs Low-Level
Output Voltage
7.0
TA = 25°C
VCC = 1.8 V
Px.y
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5-4. Typical High-Level Output Current vs High-Level
Output Voltage
−1.0
VCC = 1.8 V
Px.y
−2.0
−3.0
−4.0
−5.0
−6.0
TA = 85°C
TA = 25°C
−7.0
−8.0
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
Figure 5-5. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
21
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to
P1.5, P3.2 to P3.7, PJ.0 to PJ.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
55.0
24
TA = 25°C
VCC = 3.0 V
Px.y
50.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
0.5
1.0
1.5
2.0
2.5
3.0
TA = 85°C
16
12
8
4
0
0.0
3.5
VOL – Low-Level Output Voltage – V
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
−50.0
TA = 85°C
−55.0
−60.0
0.0
1.0
1.5
2.0
0
VCC = 3.0 V
Px.y
IOH – Typical High-Level Output Current – mA
−5.0
0.5
VOL – Low-Level Output Voltage – V
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
IOH – Typical High-Level Output Current – mA
TA = 25°C
20
5.0
0.0
0.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage
22
VCC = 1.8 V
Px.y
Specifications
VCC = 1.8 V
Px.y
−4
−8
−12
TA = 85°C
−16
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6
and P1.7, P2.0 to P2.7, P3.0 and P3.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
30
DVCC = 3.0 V
DVIO = 5.0 V
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
60
TA = 25°C
50
40
TA = 85°C
30
20
10
0
25
TA = 25°C
20
TA = 85°C
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V OL - Low-Level Output Voltage - V
Figure 5-10. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0.5
1
1.5
2
2.5
3
3.5
V OL - Low-Level Output Voltage - V
Figure 5-11. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
10
DVCC = 1.8 V
V DD = 1.8
5.5 V
DVIO
TA = 25°C
IOH - Typical High-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
DVCC = 3.0 V
V DD = 3.0
5.5 V
DVIO
8
TA = 85°C
6
4
2
0
DVCC = 3.0 V
V CC= =5.0
3.0VV
DVIO
-10
-20
-30
-40
TA = 85°C
-50
-60
TA = 25°C
-70
-80
0
0.5
1
1.5
2
V OL - Low-Level Output Voltage - V
Figure 5-12. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V OH - High-Level Output Voltage - V
Figure 5-13. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
5.5
23
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7,
P2.0 to P2.7, P3.0 and P3.1 (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
0
DVCC = 3.0 V
V DD = 5.5
DVIO
3.0 V
IOH - Typical High-Level Output Current - mA
IOH - Typical High-Level Output Current - mA
0
-5
-10
-15
TA = 85°C
-20
-25
TA = 25°C
-2
-4
-6
TA = 85°C
-8
TA = 25°C
-10
-30
0
0.5
1
1.5
2
2.5
3
3.5
V OH - High-Level Output Voltage - V
Figure 5-14. Typical High-Level Output Current vs High-Level
Output Voltage
24
DVCC = 1.8 V
V DD = 5.5
DVIO
1.8 V
Specifications
0
0.5
1
1.5
2
V OH - High-Level Output Voltage - V
Figure 5-15. Typical High-Level Output Current vs High-Level
Output Voltage
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and
P1.7, P2.0 to P2.7, P3.0 and P3.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DVCC = 3.0 V
DVIO = 5.0 V
130
120
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
140
TA = 25°C
110
100
TA = 85°C
90
80
70
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IOH - Typical High-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
TA = 25°C
25
20
TA = 85°C
15
10
5
0
0
0.5
1
1.5
2
V OL - Low-Level Output Voltage - V
Figure 5-18. Typical Low-Level Output Current vs Low-Level
Output Voltage
TA = 25°C
TA = 85°C
0.5
1
1.5
2
2.5
3
3.5
V OL - Low-Level Output Voltage - V
Figure 5-17. Typical Low-Level Output Current vs Low-Level
Output Voltage
30
DVCC = 1.8 V
V DD = 1.8
5.5 V
DVIO
DVCC = 3.0 V
V DD = 3.0
5.5 V
DVIO
0
5.5
V OL - Low-Level Output Voltage - V
Figure 5-16. Typical Low-Level Output Current vs Low-Level
Output Voltage
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
DVCC = 3.0 V
V CC==5.0
3.0VV
DVIO
TA = 85°C
TA = 25°C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V OH - High-Level Output Voltage - V
Figure 5-19. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
5.5
25
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to
P2.7, P3.0 and P3.1 (continued)
0
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
DVCC = 3.0 V
V DD = 5.5
DVIO
3.0 V
IOH - Typical High-Level Output Current - mA
IOH - Typical High-Level Output Current - mA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA = 85°C
TA = 25°C
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-25
-30
0
0.5
1
1.5
2
2.5
3
3.5
V OH - High-Level Output Voltage - V
Figure 5-20. Typical High-Level Output Current vs High-Level
Output Voltage
26
DVCC = 1.8 V
V DD = 5.5
DVIO
1.8 V
Specifications
0
0.5
1
1.5
2
V OH - High-Level Output Voltage - V
Figure 5-21. Typical High-Level Output Current vs High-Level
Output Voltage
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.21 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
IDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1
CL,eff
fFault,LF
tSTART,LF
Integrated effective load
capacitance, LF mode
10
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Duty cycle, LF mode
Oscillator fault frequency,
LF mode
XTS = 0
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 12 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
µA
Hz
50
kHz
pF
30%
70%
10
10000
Hz
1000
3V
ms
500
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
UNIT
kΩ
XTS = 0, XCAPx = 0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Start-up time, LF mode
0.170
32768
XTS = 0, XT1BYPASS = 0
OALF
3V
0.290
XT1 oscillator crystal frequency,
LF mode
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals
TYP
27
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.22 Crystal Oscillator, XT1, High-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDVCC,HF
TEST CONDITIONS
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, HF mode
VCC
MIN
TYP
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
MAX
UNIT
µA
3V
325
fOSC = 32 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
450
fXT1,HF0
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0 (2)
4
8
MHz
fXT1,HF1
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1 (2)
8
16
MHz
fXT1,HF2
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2 (2)
16
24
MHz
fXT1,HF3
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3 (2)
24
32
MHz
fXT1,HF,SW
XT1 oscillator logic-level squarewave input frequency, HF mode
XTS = 1,
XT1BYPASS = 1 (3)
0.7
32
MHz
Oscillation allowance for
HF crystals (4)
OAHF
tSTART,HF
CL,eff
(1)
(2)
(3)
(4)
(5)
(6)
28
Start-up time, HF mode
Integrated effective load
capacitance, HF mode (5)
(2)
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,HF = 6 MHz, CL,eff = 15 pF
450
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,HF = 12 MHz, CL,eff = 15 pF
320
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
fXT1,HF = 20 MHz, CL,eff = 15 pF
200
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3,
fXT1,HF = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
(6)
XTS = 1
Ω
3V
ms
0.3
1
pF
To improve EMI on the XT1 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT1BYPASS is set, the VLO, REFO, XT1 circuits are automatically powered down.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Crystal Oscillator, XT1, High-Frequency Mode(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fFault,HF
(7)
(8)
TEST CONDITIONS
Duty cycle, HF mode
XTS = 1, Measured at ACLK,
fXT1,HF2 = 20 MHz
Oscillator fault frequency,
HF mode (7)
XTS = 1 (8)
VCC
MIN
TYP
MAX
40%
50%
60%
30
300
UNIT
kHz
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
0.5
50%
kHz
%/°C
4
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(85°C – (–40°C)). The coefficient is negative.
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V). The coefficient is
positive.
5.24 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
tSTART
(1)
(2)
MIN
TYP
MAX
UNIT
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
Full temperature range
1.8 V to 3.6 V
REFO frequency temperature drift
dfREFO/dVCC
VCC
TA = 25°C
REFO absolute tolerance calibrated
dfREFO/dT
TEST CONDITIONS
REFO oscillator current consumption
TA = 25°C
±3.5%
3V
Measured at ACLK (1)
1.8 V to 3.6 V
(2)
1.8 V to 3.6 V
REFO frequency supply voltage drift
Measured at ACLK
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
±1.5%
0.01
%/°C
1.0
40%
50%
%/V
60%
25
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
29
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.25 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-22)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31) (1)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.38
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
(1)
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31) (1)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
(1)
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0) (1)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
(1)
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31) (1)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
(1)
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31) (1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.4
ratio
SDCO
Frequency step between tap DCO
and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
40%
DCO frequency temperature drift
fDCO = 1 MHz, VCORE = 1.2 V, 2.0 V
0.1
%/°C
fDCO = 1 MHz
1.9
%/V
dfDCO/dT
dfDCO/dVCORE DCO frequency voltage drift
(1)
50%
60%
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx
= 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO
frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-22. Typical DCO Frequency
30
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.26 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.45
V
1.50
V
40
275
mV
V(DVCC_BOR_IT-)
BORH on voltage,
DVCC falling level
dDVCC/dt < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage,
DVCC rising level
dDVCC/dt < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
V(VCORE_BOR_IT-)
BORL on voltage,
VCORE falling level
DVCC = 1.8 V to 3.6 V
0.69
0.87
V
V(VCORE_BOR_IT+)
BORL off voltage,
VCORE rising level
DVCC = 1.8 V to 3.6 V
0.83
1.05
V
V(VCORE_BOR_hys)
BORL hysteresis
200
mV
tdBOR
BORL reset release time
2000
µs
tRESET
Pulse duration required at RST/NMI
pin to accept a reset
0.80
1.30
60
2
µs
5.27 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active
mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 25 mA
1.90
V
VCORE2(AM)
Core voltage, active
mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.80
V
VCORE1(AM)
Core voltage, active
mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
1.60
V
VCORE0(AM)
Core voltage, active
mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
1.40
V
VCORE3(LPM)
Core voltage, active
mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 30 µA
1.94
V
VCORE2(LPM)
Core voltage, low-current
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
mode, PMMCOREV = 2
1.84
V
VCORE1(LPM)
Core voltage, low-current
2.0 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
mode, PMMCOREV = 1
1.64
V
VCORE0(LPM)
Core voltage, low-current
1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
mode, PMMCOREV = 0
1.44
V
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
31
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.28 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
SVSH on voltage level
SVSH off voltage level
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
32
Specifications
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
2
µA
SVSHE = 1, SVSHRVL = 0
1.59
1.64
1.69
SVSHE = 1, SVSHRVL = 1
1.79
1.84
1.91
SVSHE = 1, SVSHRVL = 2
1.98
2.04
2.11
SVSHE = 1, SVSHRVL = 3
2.10
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.81
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.01
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.20
2.26
2.33
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVSHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVSHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVSHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = ±1 mV/µs, SVSHFP = 0
25
SVSHE = 0 -> 1, SVSHFP = 1
12.5
SVSHE = 0 -> 1, SVSHFP = 0
100
0
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
µs
1000
V/s
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.29 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMH on or off voltage level
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
UNIT
nA
200
2.0
µA
SVMHE = 1, SVSMHRRL = 0
1.65
1.74
1.86
SVMHE = 1, SVSMHRRL = 1
1.85
1.94
2.02
SVMHE = 1, SVSMHRRL = 2
2.02
2.14
2.22
SVMHE = 1, SVSMHRRL = 3
2.18
2.26
2.35
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVMHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVMHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVMHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
MAX
0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
µs
SVMHE = 0 -> 1, SVSHFP = 1
12.5
SVMHE = 0 -> 1, SVSHFP = 0
100
µs
5.30 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
t(SVSL)
SVSL on or off delay time
tpd(SVSL)
SVSL propagation delay
TYP
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
2.0
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
6
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
50
SVMHE = 0 -> 1, SVSLFP = 1
12.5
SVMHE = 0 -> 1, SVSLFP = 0
100
UNIT
nA
µA
µs
µs
5.31 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on or off delay time
MIN
TYP
MAX
0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
2.0
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
30
SVMLE = 0 -> 1, SVSLFP = 1
12.5
SVMLE = 0 -> 1, SVSLFP = 0
100
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
UNIT
nA
µA
µs
µs
33
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.32 Wake-up Times From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
fMCLK ≥ 4 MHz
3
6.5
1 MHz < fMCLK <
4 MHz
4
8.0
150
165
µs
Wake-up time from LPM4.5 to
active mode
2
3
ms
Wake-up time from RST or
BOR event to active mode
2
3
ms
tFAST-WAKE-UP
Wake-up time from LPM2,
LPM3, or LPM4 to active mode
PMMCOREVx = SVSMLRRLx = n
(where n = 0, 1, 2, or 3), SVSLFP = 1
tSLOW-WAKE-UP
Wake-up time from LPM2,
LPM3, or LPM4 to active mode
PMMCOREVx = SVSMLRRLx = n
(where n = 0, 1, 2, or 3), SVSLFP = 0
tWAKE-UP LPM5
tWAKE-UP-RESET
µs
5.33 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse duration required for
capture.
1.8 V, 3 V
MAX
UNIT
25
MHz
20
ns
5.34 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baud rate in MBaud) (1)
tτ
UART receive deglitch time
(1)
34
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
150
200
3V
50
150
200
ns
The DCO wake-up time must be considered in LPM3 and LPM4. The wake-up time must be considered in LPMx.5.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.35 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-23
and Figure 5-24)
PARAMETER
fUSCI
USCI input clock frequency
TEST CONDITIONS
PMMCOREV = 0
tSU,MI
SOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,MI
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
SIMO output data valid time (2)
(2)
(3)
1.8 V
55
3V
38
2.4 V
30
3V
25
1.8 V
0
3V
0
2.4 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
20
3V
18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
16
SIMO output data hold time (3)
CL = 20 pF, PMMCOREV = 3
(1)
MIN
1.8 V
CL = 20 pF, PMMCOREV = 0
tHD,MO
VCC
SMCLK, ACLK
Duty cycle = 50% ±10%
3V
1.8 V
ns
15
–10
3V
–8
2.4 V
–10
3V
–8
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave parameters tSU,SI(Slave) and
tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-23 and Figure 5-24.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 523 and Figure 5-24.
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
35
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 5-23. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-24. SPI Master Mode, CKPH = 1
36
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.36 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-25
and Figure 5-26)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, Last clock to STE high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
SOMI output data valid time (2)
(2)
(3)
11
3V
8
2.4 V
7
3V
6
1.8 V
3
3V
3
2.4 V
3
3V
3
MAX
ns
1.8 V
66
3V
50
2.4 V
36
3V
30
1.8 V
30
3V
23
2.4 V
16
3V
ns
ns
13
1.8 V
5
3V
5
2.4 V
2
3V
2
1.8 V
5
3V
5
2.4 V
5
3V
5
ns
ns
76
3V
60
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
44
3V
40
SOMI output data hold time (3)
UNIT
ns
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
(1)
MIN
1.8 V
CL = 20 pF, PMMCOREV = 0
tHD,SO
VCC
1.8 V
1.8 V
18
3V
12
2.4 V
10
3V
8
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master parameters tSU,MI(Master)
and tVALID,MO(Master), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-25 and Figure 5-26.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-25
and Figure 5-26.
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
37
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 5-25. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-26. SPI Slave Mode, CKPH = 1
38
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.37 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-27)
PARAMETER
TEST CONDITIONS
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz
tSP
Pulse duration of spikes suppressed by
input filter
tSU,STA
tHD,STA
4.7
µs
0.6
4.0
2.2 V, 3 V
fSCL > 100 kHz
µs
0.6
2.2 V, 3 V
fSCL > 100 kHz
Setup time for STOP
4.0
2.2 V, 3 V
fSCL > 100 kHz
tSU,STO
0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-27. I2C Mode Timing
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
39
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7
terminals
Operating supply current into
AVCC terminal, REF module
and reference buffer off
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 00
Operating supply current into
AVCC terminal, REF module
on, reference buffer on
MIN
TYP
MAX
1.8
3.6
V
0
AVCC
V
2.2 V
60
90
3V
75
100
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 01
3V
113
130
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 10, VEREF = 2.5 V
3V
105
125
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 11, VEREF = 2.5 V
3V
70
95
CI
Input capacitance
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad
2.2 V
3.5
RI
Input MUX ON resistance
IADC10_A
(1)
(2)
UNIT
µA
pF
AVCC > 2.0V, 0 V ≤ VAx ≤ AVCC
36
1.8V < AVCC < 2.0V, 0 V ≤ VAx ≤ AVCC
96
kΩ
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ().
5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A linearity
parameters
2.2 V, 3 V
0.45
5
5.5
MHz
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.2
4.8
5.4
MHz
2.2 V, 3 V
2.4
Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
µs
External fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSEL ≠ 0
tADC10ON
Turnon settling time of
the ADC
tSample
Sampling time
(1)
(2)
(3)
(4)
40
See
(2)
(3)
100
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (4)
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF
3.0
(4)
1.8 V
3
3V
1
ns
µs
The ADC10OSC is sourced directly from MODOSC inside the UCS.
12 × ADC10DIV × 1/fADC10CLK
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately eight Tau (τ) are required for an error of less than ±0.5 LSB
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±1.0
1.6 V < (VEREF+ – VEREF-) ≤ VAVCC, CVEREF+ = 20 pF
±1.0
Differential linearity error
1.4 V ≤ (VEREF+ – VEREF-),
CVEREF+ = 20 pF
±1.0
LSB
Offset error
1.4 V ≤ (VEREF+ – VEREF-), CVEREF+ = 20 pF,
Internal impedance of source RS < 100 Ω
±1.0
LSB
Integral linearity error
ED
EO
Gain error, external reference
ET
(1)
UNIT
1.4 V ≤ (VEREF+ – VEREF-) ≤ 1.6 V, CVEREF+ = 20 pF
EI
EG
MAX
LSB
±1.0
Gain error, external reference,
buffered
1.4 V ≤ (VEREF+ – VEREF-), CVEREF+ = 20 pF
Gain error, internal reference
See
Total unadjusted error, internal
reference
See
±5
(1)
(1)
LSB
±1.5%
VREF
±1.5%
VREF
Dominated by the absolute voltage of the integrated reference voltage.
5.41 REF, External Reference (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MAX
UNIT
1.4
AVCC
V
(3)
0
1.2
V
(4)
1.4
AVCC
V
VEREF+
Positive external reference
voltage input
VEREF+ > VEREF-
(2)
VEREF-
Negative external reference
voltage input
VEREF+ > VEREF-
VEREF+ –
VEREF-
Differential external
reference voltage input
VEREF+ > VEREF-
I(VEREF+),
I(VEREF-)
C(VEREF+/-)
(1)
(2)
(3)
(4)
(5)
Static input current
Capacitance at VEREF+
and VEREF- terminals
VCC
1.4 V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
See
(5)
MIN
TYP
±8.5
±26
µA
±1
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VEREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide.
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
41
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
Positive built-in
reference voltage
VREF+
AVCC(min)
AVCC minimum
voltage, Positive built-in
reference active
Operating supply
current into AVCC
terminal (2)
IREF+
TEST CONDITIONS
VCC
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
MIN
TYP
MAX
3V
2.51
±1.5%
3V
1.99
±1.5%
2.2 V,
3V
1.5
±1.5%
REFVSEL = {0} for 1.5 V
1.8
REFVSEL = {1} for 2.0 V
2.3
REFVSEL = {2} for 2.5 V
2.8
UNIT
V
V
fADC10CLK = 5 MHz, REFON = 1,
REFBURST = 0, REFVSEL = {0} for 1.5 V
3V
15.5
19
fADC10CLK = 5 MHz, REFON = 1,
REFBURST = 0, REFVSEL = {1} for 2.0 V
3V
18
24
fADC10CLK = 5 MHz, REFON = 1,
REFBURST = 0, REFVSEL = {2} for 2.5 V
3V
21
30
30
50
2.2 V
150
180
3V
150
190
REFON = 1, INCH = 0Ah,
ADC10ON = 1, TA = 30°C
2.2 V
765
3V
765
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
µA
TCREF+
Temperature coefficient
of built-in reference (3)
REFVSEL = {0, 1, 2}, REFON = 1
ISENSOR
Operating supply
current into AVCC
terminal (4)
REFON = 1, INCH = 0Ah,
ADC10ON = 1, TA = 30°C
VSENSOR
See
VMID
AVCC divider at
channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is approximately 0.5 × VAVCC
tSENSOR
Sample time required if
channel 10 is
selected (6)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
µs
Sample time required if
channel 11 is
selected (7)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
1
µs
PSRR_DC
Power supply rejection
ratio (DC)
AVCC = AVCC(min) through AVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1
120
PSRR_AC
Power supply rejection
ratio (AC)
AVCC = AVCC(min) through AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = {0, 1, 2}, REFON = 1
6.4
tSETTLE
Settling time of
reference voltage (8)
AVCC = AVCC(min) through
AVCC(max),
REFVSEL = {0, 1, 2},
REFON = 0 → 1
(sample)
tVMID
(sample)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
42
(5)
ppm/
°C
µA
mV
300
V
µV/V
mV/V
TA = –40°C to 85°C
23
125
TA = 25°C
23
50
TA = 85°C
16
25
µs
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The internal reference current is supplied through terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)).
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.43 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
CBPWRMD = 00, CBON = 1,
CBRSx = 00
IAVCC_COMP
VREF
IAVCC_REF
VIC
Comparator operating supply
current into AVCC, Excludes
reference resistor ladder
Reference voltage level
Quiescent current of resistor
ladder into AVCC, Including
REF module current
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
tPD
Propagation delay, response
time
tPD,filter
tEN_CMP
31
38
3V
32
39
CBPWRMD = 01, CBON = 1,
CBRSx = 00
2.2 V, 3 V
10
17
CBPWRMD = 10, CBON = 1,
CBRSx = 00
2.2 V, 3 V
0.2
0.85
Propagation delay with filter
active
Comparator enable time
tEN_REF
Resistor reference enable time
TCCB_REF
Temperature coefficient
reference of VCB_REF
VCB_REF
Reference voltage for a given
tap
≥1.8 V
1.42
1.44
1.46
CBREFLx = 10, CBREFACC = 0
≥2.2 V
1.89
1.92
1.95
CBREFLx = 11, CBREFACC = 0
≥3.0 V
2.35
2.39
2.43
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V, 3 V
10
17
CBREFACC = 0, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V, 3 V
33
40
0
VCC – 1
±20
CBPWRMD = 01, 10
±10
5
ON (switch closed)
3
V
mV
pF
4
50
kΩ
MΩ
CBPWRMD = 00, CBF = 0
450
CBPWRMD = 01, CBF = 0
600
CBPWRMD = 10, CBF = 0
50
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.5
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
0.6
1.0
1.8
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
1.0
1.8
3.4
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
1.8
3.4
6.5
1
2
ns
µs
µs
CBON = 0 to CBON = 1,
CBPWRMD = 00 or 01
µs
CBON = 0 to CBON = 1,
CBPWRMD = 10
1.5
CBON = 0 to CBON = 1
1.0
VIN ×
(n + 0.5)
/ 32
VIN ×
(n + 1)
/ 32
1.5
µs
50
ppm/
°C
VIN ×
(n + 1.5)
/ 32
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
V
µA
CBPWRMD = 00
VIN = reference into resistor ladder,
n = 0 to 31
V
µA
CBREFLx = 01, CBREFACC = 0
OFF (switch opened)
UNIT
38
2.2 V
Common mode input range
VOFFSET
MAX
V
43
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.44 Timer_D, Power Supply and Reference Clock Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
DVCC
Digital supply voltage
fREF,DCO
Timer_D input
reference clock
frequency
I(DVCC) at 64-MHz
Timer_D clock, clock
generator only
TEST CONDITIONS
VCC
V(DVSS) = 0 V
MIN
TYP MAX UNIT
1.8
3.6
PMMCOREVx = 0
1.8 V
≤ VCC
≤ 3.6 V
8
12.0
PMMCOREVx = 1
2.0 V
≤ VCC
≤ 3.6 V
8
16.0
PMMCOREVx = 2
2.2 V
≤ VCC
≤ 3.6 V
8
20.0
PMMCOREVx = 3
2.4 V
≤ VCC
≤ 3.6 V
8
25.5
V
MHz
freference = 8 MHz, MCx = 0, TDHREGEN = 1,
TDHMx = 0, TDHCLKCR = 0
253
320
µA
I(DVCC) at 128-MHz
I(128MHz) Timer_D clock, clock
generator only
freference = 16 MHz, MCx = 0, TDHREGEN = 1,
TDHMx = 0, TDHCLKCR = 0
285
360
µA
I(DVCC) at 200-MHz
I(200MHz) Timer_D clock, clock
generator only
freference = 25 MHz, MCx = 0, TDHREGEN = 1,
TDHMx = 0, TDHCLKCR = 1
280
345
µA
I(DVCC) at 256-MHz
I(256MHz) Timer_D clock, clock
generator only
freference = 16 MHz, MCx = 0, TDHREGEN = 1,
TDHMx = 1, TDHCLKCR = 1
265
330
µA
I(0,16,64)
I(DVCC)
TDHCLKRx = 0, TDHCLKSRx = 16, TDHCLKTRIM = 64
I(1,16,64)
I(DVCC)
TDHCLKRx = 1, TDHCLKSRx = 16, TDHCLKTRIM = 64
I(2,16,64)
I(DVCC)
TDHCLKRx = 2, TDHCLKSRx = 16, TDHCLKTRIM = 64
I(64MHz)
(1)
44
2.2 V
244
3.0 V
295
2.2 V
282
3.0 V
300
2.2 V
358
3.0 V
414
325
400
470
µA
µA
µA
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
Specifications
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.45 Timer_D, Local Clock Generator Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fHRCG(0,0,64)
fHRCG(0,7,64)
fHRCG(0,15,64)
fHRCG(0,23,64)
fHRCG(0,31,0)
fHRCG(0,31,64)
fHRCG(0,31,128)
fHRCG(1,0,64)
fHRCG(1,7,64)
fHRCG(1,15,64)
fHRCG(1,23,64)
fHRCG(1,31,0)
fHRCG(1,31,64)
HRCG frequency (0, 0, 64)
HRCG frequency (0, 7, 64)
HRCG frequency (0, 15, 64)
HRCG frequency (0, 23, 64)
HRCG frequency (0, 31, 0)
HRCG frequency (0, 31, 64)
HRCG frequency (0, 31, 128)
HRCG frequency (1, 0, 64)
HRCG frequency (1, 7, 64)
HRCG frequency (1, 15, 64)
HRCG frequency (1, 23, 64)
HRCG frequency (1, 31, 0)
HRCG frequency (1, 31, 64)
TEST CONDITIONS
MIN
TYP
MAX
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 0, TDHCLKTRIM = 64
39
56
73
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 0, TDHCLKTRIM = 64
78
112
146
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 7, TDHCLKTRIM = 64
46
66
86
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 7, TDHCLKTRIM = 64
92
132
172
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 15, TDHCLKTRIM = 64
55
78
101
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 15, TDHCLKTRIM = 64
110
156
202
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 23, TDHCLKTRIM = 64
61
87
113
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 23, TDHCLKTRIM = 64
122
174
226
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 0
36
56
73
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 0
72
112
146
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 64
68
98
128
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 31, TDHCLKTRIM = 64
136
196
256
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 31,
TDHCLKTRIM = 128
97
138
180
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 0, TDHCLKSRx = 31,
TDHCLKTRIM = 128
196
176
360
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 0, TDHCLKTRIM = 64
71
101
131
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 0, TDHCLKTRIM = 64
142
202
262
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 7, TDHCLKTRIM = 64
84
120
156
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 7, TDHCLKTRIM = 64
168
240
312
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 15, TDHCLKTRIM = 64
97
139
182
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 15, TDHCLKTRIM = 64
196
278
364
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 23, TDHCLKTRIM = 64
108
154
200
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 23, TDHCLKTRIM = 64
216
308
400
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 0
68
97
126
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 0
136
194
252
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 64
123
175
227
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 31, TDHCLKTRIM = 64
246
350
454
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
UNIT
45
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Timer_D, Local Clock Generator Frequency (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fHRCG(1,31,128)
fHRCG(2,0,64)
fHRCG(2,7,64)
fHRCG(2,15,64)
fHRCG(2,23,64)
fHRCG(2,31,0)
fHRCG(2,31,64)
fHRCG(2,31,128)
HRCG frequency (1, 31, 128)
HRCG frequency (2, 0, 64)
HRCG frequency (2, 7, 64)
HRCG frequency (2, 15, 64)
HRCG frequency (2, 23, 64)
HRCG frequency (2, 31, 0)
HRCG frequency (2, 31, 64)
HRCG frequency (2, 31, 128)
MIN
TYP
MAX
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 31,
TDHCLKTRIM = 128
TEST CONDITIONS
169
241
313
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 0,
TDHCLKRx = 1, TDHCLKSRx = 31,
TDHCLKTRIM = 128
338
482
616
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 0, TDHCLKTRIM = 64
126
180
234
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 1, TDHCLKSRx = 0, TDHCLKTRIM = 64
252
360
468
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 7, TDHCLKTRIM = 64
138
208
270
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 7, TDHCLKTRIM = 6
276
416
540
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 15, TDHCLKTRIM = 64
168
240
312
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 15, TDHCLKTRIM = 64
336
480
624
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 23, TDHCLKTRIM = 64
189
270
351
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 23, TDHCLKTRIM = 64
378
540
702
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 31, TDHCLKTRIM = 0
119
170
221
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 31, TDHCLKTRIM = 0
238
340
442
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, DHCLKSRx = 31, TDHCLKTRIM = 64
212
303
394
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 2, DHCLKSRx = 31, TDHCLKTRIM = 64
424
606
788
TDHREGEN = 0, TDHMx = 0, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 31,
TDHCLKTRIM = 128
290
413
537
TDHREGEN = 0, TDHMx = 1, TDHCLKCR = 1,
TDHCLKRx = 2, TDHCLKSRx = 31,
TDHCLKTRIM = 128
580
826
1074
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
SHRCG,0,SR
TDHCLKSRx step size in
range 0
SHRCGSR = fHRCGSR(HRCGSR+1) – fHRCG(HRCGSR)
120
185
225
kHz
SHRCG,1,SR
TDHCLKSRx step size in
range 1
SHRCGSR = fHRCGSR(HRCGSR+1) – fHRCG(HRCGSR)
220
325
395
kHz
SHRCG,2,SR
TDHCLKSRx step size in
range 2
SHRCGSR = fHRCGSR(HRCGSR+1) – fHRCG(HRCGSR)
400
555
700
kHz
55
85
120
40
85
130
48 < TDHCLKTRIMx < 64,
step size in range 2
40
85
120
0 > = TDHCLKTRIMx < 16,
step size in range 0
90
160
230
80
160
230
80
160
230
0 > = TDHCLKTRIMx < 16,
step size in range 0
SHRCG,0,TRIM
SHRCG,1,TRIM
15 < TDHCLKTRIMx < 49,
step size in range 1
15 < TDHCLKTRIMx < 49,
step size in range 1
48 < TDHCLKTRIMx < 64,
step size in range 2
46
Specifications
SHRCGSR = fHRCGSR(HRCGTRIM+1) – fHRCG(HRCGTRIM),
TDHCLKSRx = X, Y, Z
SHRCGSR = fHRCGSR(HRCGTRIM+1) – fHRCG(HRCGTRIM),
TDHCLKSRx = X, Y, Z
kHz
kHz
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Timer_D, Local Clock Generator Frequency (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
0 > = TDHCLKTRIMx < 16,
step size in range 0
SHRCG,2,TRIM
15 < TDHCLKTRIMx < 49,
step size in range 1
SHRCGSR = fHRCGSR(HRCGTRIM+1) – fHRCG(HRCGTRIM),
TDHCLKSRx = X, Y, Z
48 < TDHCLKTRIMx < 32,
step size in range 2
HRCG frequency
temperature drift
dfHRCG/dT
MIN
TYP
MAX
150
230
360
130
230
350
100
230
340
fHRCG = 8 MHz, TDHREGEN = 0
±0.17
fHRCG = 16 MHz, TDHREGEN = 0
±0.16
fHRCG = 25 MHz, TDHREGEN = 0
±0.16
fHRCG = 8, 16, or 25 MHz, TDHREGEN = 1
dfHRCG/
dVDVCC
HRCG frequency voltage drift
tSETTLE
fHRCG = 8, 16, or 25 MHz, TDHREGEN = 0
TDHEN = 0 -> 1, TDHFW = 0
Settling time, fast wake-up
TDHEN = 0 -> 1, TDHFW = 1
kHz
%/°C
0
0
5
fHRCG = 8, 16, or 25 MHz, TDHREGEN = 1
Settling time
UNIT
0
3
5
9
1.5
%/V
µs
5.46 Timer_D, Trimmed Clock Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance during trimming
MIN
TYP
–0.5%
MAX
UNIT
+0.5%
fTRIM(64MHz)
TDHMx = 0, TDHREGEN = 0, TDHCLKCR = 0,
TDHxCTL1 = TDHxCTL1_64
TA = 25°C,
VCC = 1.8 V
63
64
65
MHz
fTRIM(128MHz)
TDHMx = 0, TDHREGEN = 0, TDHCLKCR = 1,
TDHxCTL1 = TDHxCTL1_128
TA = 25°C,
VCC = 2.0 V
126
128
130
MHz
fTRIM(200MHz)
TDHMx = 0, TDHREGEN = 0, TDHCLKCR = 1,
TDHxCTL1 = TDHxCTL1_200
TA = 25°C,
VCC = 2.4 V
197
200
203
MHz
fTRIM(256MHz)
TDHMx = 1, TDHREGEN = 0, TDHCLKCR = 1,
TDHxCTL1 = TDHxCTL1_256
TA = 25°C,
VCC = 2.2 V
250
256
262
MHz
TYP
MAX
UNIT
5.47 Timer_D, Frequency Multiplication Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
External frequency tolerance
0%
E(TDHREGEN = 1,64)
freference = 8 MHz, TDHMx = 0, TDHREGEN = 1,
TDHCLKCR = 0, TDHCLKRx = 0
TA = 25°C,
VCC = 1.8 V
–1%
+1%
E(TDHREGEN = 1,128)
freference = 16 MHz, TDHMx = 0, TDHREGEN = 1,
TDHCLKCR = 1, TDHCLKRx = 0
TA = 25°C,
VCC = 2.0 V
–1%
+1%
E(TDHREGEN = 1,200)
freference = 25 MHz, TDHMx = 0, TDHREGEN = 1,
TDHCLKCR = 1, TDHCLKRx = 0
TA = 25°C,
VCC = 2.4 V
–1%
+1%
E(TDHREGEN = 1,256)
freference = 16 MHz, TDHMx = 1, TDHREGEN = 1,
TDHCLKCR = 1, TDHCLKRx = 0
TA = 25°C,
VCC =2.2 V
–1%
+1%
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
47
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5.48 Timer_D, Input Capture and Output Compare Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tTD,cap
tTD0,cap,matching
tTD1,cap,matching
tTD01,cap,matching
TEST CONDITIONS
MIN
TYP
MAX
Timer_D input capture timing, minimum pulse duration to
trigger input capture event
fMAX = 262 MHz
4
Timer0_D input capture timing, matching between input
capture channels P1.6 to P1.7 and P2.0
fMAX = 262 MHz
1
2
Timer0_D input capture timing, matching between input
capture channels. P2.4 to P2.5 and P2.6
fMAX = 262 MHz
3
4
Timer1_D input capture timing, matching between input
capture channels P2.1 to P2.2 and P2.3
fMAX = 262 MHz
2
3
Timer1_D input capture timing, matching between input
capture channels. P2.7 to P3.0 and P3.1
fMAX = 262 MHz
2
4
Timer0_D and Timer1_D input capture timing, matching
between input capture channels. Timer0_D is the highresolution clock generator source.
fMAX = 262 MHz
4
8
LSB
Timer0_D output compare timing, matching between
Falling edges,
output capture compare channels for pins P1.6, P1.7, and
fMAX = 262 MHz
P2.0
Rising and falling edges,
fMAX = 262 MHz
Rising edges,
fMAX = 262 MHz
tTD1,comp,matching
tTD01,comp,matching
48
Timer1_D output compare timing, matching between
Falling edges,
output capture compare channels for pins P2.1, P2.2, and
fMAX = 262 MHz
P2.3
Rising and falling edges,
fMAX = 262 MHz
Timer0_D and Timer1_D output compare timing, matching
All edges,
between output compare channels. Timer0_D is the highfMAX = 262 MHz
resolution clock generator source.
Specifications
ns
LSB
Rising edges,
fMAX = 262 MHz
tTD0,comp,matching
UNIT
LSB
4
4
ns
8
4
4
ns
8
8
LSB
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
5.49 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
UNIT
3.6
V
IPGM
Supply current from DVCC during program
3
5
mA
IERASE
Supply current from DVCC during erase
2
6.5
mA
IMERASE, IBANK
Supply current from DVCC during mass erase or bank erase
2
6.5
mA
tCPT
Cumulative program time
See
(1)
16
104
Program and erase endurance
ms
cycles
tRetention
Data retention duration
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
tBlock,
TJ = 25°C
105
100
years
Block program time for last byte or word
See
(2)
55
73
µs
tMass Erase
Mass erase time
See
(2)
23
32
ms
tSeg
Segment erase time
See
(2)
23
32
ms
0
1
MHz
tBlock,
N
Erase
fMCLK,MGR
(1)
(2)
MCLK frequency in marginal read mode (FCLK4.MGR0 = 1 or
FCTL4.MGR1 = 1)
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the flash controller state machine.
5.50 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)
2.2 V, 3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
100
µs
fTCK
TCK input frequency, 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
VCC
MIN
TYP
15
2.2 V
0
5
3V
0
10
2.2 V, 3 V
45
60
80
MHz
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
49
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time (see Figure 6-1).
The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-1. Integrated CPU Registers
50
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
6.2
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 lists examples of the three types of instruction formats; Table 6-2 lists the address
modes.
Table 6-1. Instruction Word Formats
FORMAT
EXAMPLE
Dual operands, source-destination
ADD
Single operands, destination only
R4 + R5 → R5
R8
PC → (TOS), R8 → PC
CALL
Relative jump, un/conditional
OPERATION
R4,R5
JNE
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV & MEM, & TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
51
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.3
www.ti.com
Operating Modes
The MSP430 has one active mode and six software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up input from RST/NMI, P1, and P2
52
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
6.4
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1)
(Non)maskable
0FFFAh
61
Comp_B
CBIIFG, CBIFG (CBIV) (1)
Maskable
0FFF8h
60
Maskable
0FFF6h
59
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
TEC0
INTERRUPT FLAG
WDTIFG, KEYV (SYSRSTIV) (1)
(2)
(2)
(3)
TEC0FLTIFG, TEC0EXCLRIFG,
TEC0AXCLRIFG (1) (3)
TD0
(3)
Maskable
0FFF4h
58
TD0
TD0CCR1 CCIFG1, ... TD0CCR2 CCIFG2,
TD0IFG, TD0HFLIFG, TD0HFHIFG, TD0HLKIFG,
TD0HUNLKIFG (TD0IV) (1) (3)
Maskable
0FFF2h
57
Watchdog Timer_A Interval
Timer Mode
WDTIFG
Maskable
0FFF0h
56
Maskable
0FFEEh
55
Maskable
0FFECh
54
USCI_A0 Receive or Transmit
USCI_B0 Receive or Transmit
TD0CCR0 CCIFG0
UCA0RXIFG, UCA0TXIFG (UCA0IV)
I2C Status
(1) (3)
UCB0RXIFG, UCB0TXIFG,
Flags (UCB0IV)
(1) (3)
Interrupt
ADC10_A (MSP430F51x2 only)
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV) (1) (3)
Maskable
0FFEAh
53
TA0
TA0CCR0 CCIFG0 (3)
Maskable
0FFE8h
52
TA0
TA0CCR1 CCIFG1 ... TA0CCR2 CCIFG2,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1)
Maskable
0FFE4h
50
TEC1
TEC1FLTIFG, TEC1EXCLRIFG,
TEC1AXCLRIFG (1) (3)
Maskable
0FFE2
49
TD1
TD1CCR0 CCIFG0 (3)
Maskable
0FFE0h
48
TD1
TD1CCR1 CCIFG1 ... TD1CCR2 CCIFG2,
TD1IFG, TD1HFLIFG, TD1HFHIFG, TD1HLKIFG,
TD1HUNLKIFG (TD1IV) (1) (3)
Maskable
0FFDEh
47
(3)
Maskable
0FFDCh
46
(1) (3)
Maskable
0FFDAh
45
0FFD8h
44
I/O Port P1
I/O Port P2
P1IFG.0 to P1IFG.7 (P1IV) (1)
P2IFG.0 to P2IFG.7 (P2IV)
Reserved
(1)
(2)
(3)
(4)
(3)
Reserved
(4)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
Interrupt flags are in the module.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
53
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.5
www.ti.com
Memory Organization
Table 6-4 summarizes the memory map of all devices.
Table 6-4. Memory Organization
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
Size
RAM
MSP430F5172,
MSP430F5171
8KB
00FFFFh–00FF80h
00FFFFh–00E000h
16KB
00FFFFh–00FF80h
00FFFFh–00C000h
32KB
00FFFFh–00FF80h
00FFFFh–008000h
1KB
2KB
2KB
0023FFh–001C00h
0023FFh–001C00h
512 Byte
512 Byte
512 Byte
Info A
128B
0019FFh–001980h
128B
0019FFh–001980h
128B
0019FFh–001980h
Info B
128B
00197Fh–001900h
128B
00197Fh–001900h
128B
00197Fh–001900h
Info C
128B
0018FFh–001880h
128B
0018FFh–001880h
128B
0018FFh–001880h
Info D
128B
00187Fh–001800h
128B
00187Fh–001800h
128B
00187Fh–001800h
2K
2KB
2KB
BSL 3
512B
0017FFh–001600h
512B
0017FFh–001600h
512B
0017FFh–001600h
BSL 2
512B
0015FFh–001400h
512B
0015FFh–001400h
512B
0015FFh–001400h
BSL 1
512B
0013FFh–001200h
512B
0013FFh–001200h
512B
0013FFh–001200h
BSL 0
512B
0011FFh–001000h
512B
0011FFh–001000h
512B
0011FFh–001000h
Size
Flash
4KB
000FFFh–000000h
4KB
000FFFh–000000h
4KB
000FFFh–000000h
Size
Information memory
(Flash)
Size
Peripherals
6.6
MSP430F5152,
MSP430F5151
001FFFh–001C00h
Sector 0
Bootloader (BSL)
memory
MSP430F5132,
MSP430F5131
Bootloader (BSL)
The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the
device memory by the BSL is protected by user-defined password. A bootloader security key is provided
to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. For
complete description of the features of the BSL and its implementation, see MSP430 Programming With
the Bootloader (BSL). Table 6-5 lists the pins required for BSL access.
Table 6-5. BSL Functions
BSL FUNCTION
54
DESCRIPTION
40-PIN QFN RSB PACKAGE
38-PIN TSSOP DA PACKAGE
40-PIN DSBGA YFF PACKAGE
RST/NMI/SBWTDIO
Entry sequence signal
Entry sequence signal
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
Entry sequence signal
Entry sequence signal
Data transmit
P3.5 - 34
P3.7 - 36
P3.5 - 37
P3.5 - A3
P3.7 - B4
Data receive
P3.6 - 35
P3.6 - 38
P3.6 - A4
VCC
Power supply
Power supply
Power supply
VSS
Ground supply
Ground supply
Ground supply
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
6.7
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.
6.8
RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data is lost. Features of the RAM include:
• RAM has n sectors. The size of a sector can be found in Section 6.5.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
manged using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide.
6.9.1
Digital I/O
Up to three 8-bit I/O ports are implemented. Port PJ contains seven individual I/O pins, common to all
devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• All 8 bits of ports P1 and P2 support edge-selectable interrupt input.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise. P1 and P2 can also be accessed word-wise (PA).
• The input and output voltage levels of the pins supplied by DVIO (see Table 4-1) are defined by the
voltage supplied by DVIO (up to 5 V).
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
55
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.9.2
www.ti.com
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to Port P1,
Port P2, and Port P3 (see Table 6-6).
Table 6-6. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
1
2
3
4
5
6
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
PM_TD0.0
TD0 input capture channel 0
TD0 output compare channel 0
8
PM_TD0.1
TD0 input capture channel 1
TD0 output compare channel 1
9
PM_TD0.2
TD0 input capture channel 2
TD0 output compare channel 2
10
PM_TD1.0
TD1 input capture channel 0
TD1 output compare channel 0
11
PM_TD1.1
TD1 input capture channel 1
TD1 output compare channel 1
12
PM_TD1.2
TD1 input capture channel 2
TD1 output compare channel 2
PM_CLR1TD0.0
TD0 external clear input
PM_FLT1_2TD0.0
TD0 fault input channel 2
14
PM_FLT1_0TD0.1
TD0 fault input channel 0
TD0 output compare channel 1
15
PM_FLT1_1TD0.2
TD0 fault input channel 1
TD0 output compare channel 2
PM_CLR2TD1.0
TD1 external clear input (controlled by
module input enable)
PM_FLT2_1TD1.0
TD1 fault input channel 1 (controlled
by module input enable)
17
PM_FLT2_2TD1.1
TD1 fault input channel 2
TD1 output compare channel 1
18
PM_FLT2_0TD1.2
TD1 fault input channel 0
TD1 output compare channel 2
19
PM_TD0.0SMCLK
TD0 input capture channel 0
SMCLK output
20
PM_TA0CLKCBOUT
TA0 input clock
Comparator_B output
21
PM_TD0CLKMCLK
TD0 input clock
MCLK output
22
PM_TA0_0
TA0 input capture channel 0
TA0 output compare channel 0
23
PM_TA0_1
TA0 input capture channel 1
TA0 output compare channel 1
24
PM_TA0_2
TA0 input capture channel 2
TA0 output compare channel 2
25
PM_DMAE0SMCLK
DMAE0 input
SMCLK output
26
PM_DMAE1MCLK
DMAE1 input
MCLK output
27
PM_DMAE2SVM
DMAE2 input
SVM output
28
PM_TD0OUTH
TD0 3-state input
ADC10CLK
29
PM_TD1OUTH
TD1 3-state input
ACLK
30
Reserved
None
DVSS
31 (0FFh) (1)
PM_ANALOG
13
16
(1)
56
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
7
TD0 output compare channel 0
TD1 output compare channel 0
Disables the output driver and the input Schmitt-trigger to prevent parasitic
cross currents when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read out value of 31.
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-7 lists the default assignments for all pins that support port mapping.
Table 6-7. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCA0CLK
PM_UCB0STE
USCI_A0 clock input/output
(direction controlled by USCI)
USCI_B0 SPI slave transmit enable
(direction controlled by USCI)
P1.1/PM_UCA0TXD/
PM_UCA0SIMO/A1/CB1
PM_UCA0TXD
PM_UCA0SIMO
USCI_A0 UART TXD (Direction
controlled by USCI – output)
USCI_A0 SPI slave in master out
(direction controlled by USCI)
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A2/CB2
PM_UCA0RXD
PM_UCA0SOMI
USCI_A0 UART RXD (Direction
controlled by USCI – input)
USCI_A0 SPI slave out master in
(direction controlled by USCI)
P1.3/PM_UCB0CLK/
PM_UCA0STE/A3/CB3
PM_UCB0CLK
PM_UCA0STE
USCI_B0 clock input/output
(direction controlled by USCI)
USCI_A0 SPI slave transmit enable
(direction controlled by USCI)
P1.4/PM_UCB0SIMO/
PM_UCB0SDA/A4/CB4
PM_UCB0SIMO
PM_UCB0SDA
USCI_B0 SPI slave in master out
(direction controlled by USCI)
USCI_B0 I2C data (open drain and
direction controlled by USCI)
P1.5/PM_UCB0SOMI/
PM_UCB0SCL/A5/CB5
PM_UCB0SOMI
PM_UCB0SCL
USCI_B0 SPI slave out master in
(direction controlled by USCI)
USCI_B0 I2C clock (open drain and
direction controlled by USCI)
P1.6/PM_TD0.0
PM_TD0.0
TD0 input capture channel 0
TD0 output compare channel 0
P1.7/PM_TD0.1
PM_TD0.1
TD0 input capture channel 1
TD0 output compare channel 1
P2.0/PM_TD0.2
PM_TD0.2
TD0 input capture channel 2
TD0 output compare channel 2
P2.1/PM_TD1.0
PM_TD1.0
TD1 input capture channel 0
TD1 output compare channel 0
P2.2/PM_TD1.1
PM_TD1.1
TD1 input capture channel 1
TD1 output compare channel 1
P2.3/PM_TD1.2
PM_TD1.2
TD1 input capture channel 2
TD1 output compare channel 2
P2.4/PM_TEC0CLR/
PM_TEC0FLT2/PM_TD0.0
PM_CLR1TD0.0
PM_FLT1_2TD0.0
TD0 external clear input (controlled
by module input enable)
TD0 fault input channel 2
(controlled by module input enable)
TD0 output compare channel 0
P2.5/PM_TEC0FLT0/PM_TD0.1
PM_FLT1_0TD0.1
TD0 fault input channel 0
TD0 output compare channel 1
P2.6/PM_TEC0FLT1/PM_TD0.2
PM_FLT1_1TD0.2
TD0 fault input channel 1
TD0 output compare channel 2
P2.7/PM_TEC1CLR/
PM_TEC1FLT1/PM_TD1.0
PM_CLR2TD1.0
PM_FLT2_1TD1.0
TD1 external clear input (controlled
by module input enable)
TD1 fault input channel 1
(controlled by module input enable)
TD1 output compare channel 0
P3.0/PM_TEC1FLT2/
PM_TD1.1
PM_FLT2_2TD1.1
TD1 fault input channel 2
TD1 output compare channel 1
P3.1/PM_TEC1FLT0/
PM_TD1.2
PM_FLT2_0TD1.2
TD1 fault input channel 0
TD1 output compare channel 2
P3.2/PM_TD0.0/
PM_SMCLK/CB14
PM_TD0.0SMCLK
TD0 input capture channel 0
SMCLK output
P3.3/PM_TA0CLK/
PM_CBOUT/CB13
PM_TA0CLKCBOUT
TA0 input clock
Comparator_B output
P3.4/PM_TD0CLK/
PM_MCLK
PM_TD0CLKMCLK
TD0 input clock
MCLK output
P3.5/PM_TA0.2/
VEREF+/CB12
PM_TA3_2
TA0 input capture channel 0
TA0 output compare channel 0
P3.6/PM_TA0.1/A7
VEREF-/CB11
PM_TA3_1
TA0 input capture channel 1
TA0 output compare channel 1
P3.7/PM_TA0.0/
A6/CB10
PM_TA3_0
TA0 input capture channel 2
TA0 output compare channel 2
P1.0/PM_UCA0CLK/
PM_UCB0STE/A0/CB0
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
57
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.9.3
www.ti.com
Oscillator and System Clock
The clock system (Unified Clock System [UCS]) module includes support for a 32-kHz watch crystal
oscillator and high-frequency crystal oscillator, an internal very-low-power low-frequency oscillator (VLO),
an internal trimmed low-frequency oscillator (REFO), and an integrated internal digitally controlled
oscillator (DCO). The UCS module is designed to meet the requirements of both low system cost and low
power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in
conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the
watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than
5 µs. The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal or high-frequency crystal (XT1), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally-controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.9.4
Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level
and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (SVM, the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.9.5
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and
unsigned multiplication as well as signed and unsigned multiply and accumulate operations
6.9.6
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart
after a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be configured as an interval timer and
can generate interrupts at selected time intervals.
58
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
6.9.7
SLAS619P – AUGUST 2010 – REVISED MAY 2016
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
and power-up clear handling, NMI source selection and management, reset interrupt vector generators
(see Table 6-8), bootloader entry mechanisms, and configuration management (device descriptors). It also
includes a data exchange mechanism using JTAG that is called a JTAG mailbox and that can be used in
the application.
Table 6-8. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
INTERRUPT EVENT
OFFSET
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
PMMSWBOR (BOR)
06h
LPM5 wake-up (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SYSRSTIV, System Reset
WORD ADDRESS
SVMH_OVP (POR)
019Eh
12h
14h
WDT time-out (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
SYSSNIV, System NMI
SYSUNIV, User NMI
VMAIFG
Lowest
Highest
08h
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
Highest
10h
PMMSWPOR (POR)
DLYHIFG
PRIORITY
019Ah
Lowest
Highest
04h
ACCVIFG
06h
Reserved
08h to 1Eh
Lowest
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
59
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.9.8
www.ti.com
DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to wake to move data to or from a peripheral. Table 6-9 lists the triggers that can be assigned to
start a DMA transfer.
Table 6-9. DMA Trigger Assignments (1)
TRIGGER
(1)
60
CHANNEL
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TD0CCR0 CCIFG
TD0CCR0 CCIFG
TD0CCR0 CCIFG
4
TD0CCR2 CCIFG
TD0CCR2 CCIFG
TD0CCR2 CCIFG
5
TD1CCR0 CCIFG
TD1CCR0 CCIFG
TD1CCR0 CCIFG
6
TD1CCR2 CCIFG
TD1CCR2 CCIFG
TD1CCR2 CCIFG
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
Reserved
Reserved
Reserved
21
Reserved
Reserved
Reserved
22
Reserved
Reserved
Reserved
23
Reserved
Reserved
Reserved
24
ADC10IFG0
ADC10IFG0
ADC10IFG0
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
6.9.9
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module
contains two modules, A and B.
The USCI_Ax module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bx module provides support for SPI (3 or 4 pin) or I2C.
6.9.10 TA0
TA0 is a 16-bit timer/counter with three capture/compare registers (see Table 6-10). TA0 can support
multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-10. TA0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
P3.3 - G6
TA0CLK
TACLK
ACLK
ACLK
ACLK
RSB
(40-PIN
QFN)
DA
(38-PIN
TSSOP)
YFF
(40-PIN
DSBGA)
P3.3 - 30
P3.3 - 34
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
SMCLK
SMCLK
SMCLK
P3.3 - 30
P3.3 - 34
P3.3 - G6
TA0CLK
P3.7 - 36
–
P3.7 - G4
TA0.0
–
–
–
CBOUT
CCI0B
–
–
–
VSS
GND
–
–
–
VCC
P3.6 - 35
–
P3.6 - G3
–
–
–
–
–
–
–
P3.5 - 34
(1)
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
RSB
(40-PIN
QFN)
DA
(38-PIN
TSSOP)
YFF
(40-PIN
DSBGA)
–
–
–
–
–
–
–
–
–
TACLK
–
–
–
CCI0A
P3.7 - 36
–
P3.7 - G4
–
–
–
–
–
–
VCC
–
–
–
TA0.1
CCI1A
P3.6 - 35
P3.6 - 38
P3.6 - G3
ACLK
CCI1B
ADC10_A (1)
(internal)
ADC10SHS
x = 001b
ADC10_A (1)
(internal)
ADC10SHS
x = 001b
ADC10_A (1)
(internal)
ADC10SHS
x = 001b
–
VSS
GND
–
–
–
–
VCC
VCC
–
–
–
P3.5 - 37
P3.5 - F3
TA0.2
CCI2A
P3.5 - 34
P3.5 - 37
P3.5 - F3
–
–
–
VSS
CCI2B
–
–
–
–
–
–
VSS
GND
–
–
–
–
–
–
VCC
VCC
–
–
–
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
NA
TA0.0
TA0.1
TA0.2
The ADC10_A trigger is available on MSP430F51x2 devices.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
61
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.9.11 TD0
TD0 is a 16-bit timer/counter with three capture/compare registers supporting up to 256-MHz (4-ns)
resolution (see Table 6-11). TD0 can support multiple capture/compares, PWM outputs, and interval
timing. TD0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers. External fault inputs as well as a
external timer counter clear is supported along with interrupt flags from the TEC0 module.
Table 6-11. TD0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
P3.4 - G5
TD0CLK
ACLK
(internal)
SMCLK
(internal)
P3.4 - 31
–
RSB
(40-PIN
QFN)
DA
(38-PIN
TSSOP)
YFF
(40-PIN
DSBGA)
P3.4 - 31
–
ACLK
(internal)
ACLK
(internal)
SMCLK
(internal)
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
RSB
(40-PIN
QFN)
DA
(38-PIN
TSSOP)
YFF
(40-PIN
DSBGA)
TDCLK
–
–
–
ACLK
ACLK
–
–
–
SMCLK
(internal)
SMCLK
SMCLK
–
–
–
–
P3.4 - G5
TD0CLK
TDCLK
–
–
–
–
–
–
CLK0
–
–
–
P2.4 - 19
P2.4 - 23
P2.4 - B4
TEC0CLR
TECXCLR
–
–
–
P1.6 - 11 (1)
P1.6 - 15 (1)
P1.6 - A1 (1)
TD0.0
CCI0A
P1.6 - 11 (1)
P1.6 - 15 (1)
P1.6 - A1 (1)
P3.2 - 29
P3.2 - 33
P3.2 - F5
TD0.0
CCI0B
P2.4 - 19
P2.4 - 23
P2.4 - B4
GND
ADC10_A
(internal)
ADC10SHS
x = 010b (2)
ADC10_A
(internal)
ADC10SHS
x = 010b (2)
ADC10_A
(internal)
ADC10SHS
x = 010b (2)
–
–
–
–
VSS
Timer
CCR0
NA
TD0
NA
TD0
–
–
–
VCC
VCC
–
–
P2.5 - 20
P2.5 - 24
P2.5 - A6
TEC0FLT0
TECXFLT0
–
–
P1.7 - 12 (1)
P1.7 - 16 (1)
P1.7 - B2 (1)
TD0.1
CCI1A
P1.7 - 12 (1)
P1.7 - 16 (1)
P1.7 - B2 (1)
CBOUT
(internal)
CBOUT
(internal)
CBOUT
(internal)
TD0.1
CCI1B
PJ.6 - 28
PJ.6 - 32
PJ.6 - E5
–
–
–
VSS
GND
CCR1
–
–
–
VCC
VCC
TD1
TD1
P2.5 - 20
P2.5 - 24
P2.5 - A6
ADC10_A
(internal)
ADC10SHS
x = 011b (2)
ADC10_A
(internal)
ADC10SHS
x = 011b (2)
ADC10_A
(internal)
ADC10SHS
x = 011b (2)
P2.6 - 21
P2.6 - 20
P2.6 - B5
TEC0FLT1
TECXFLT1
–
–
P2.0 - 13 (1)
P2.0 - 17 (1)
P2.0 - B3 (1)
TD0.2
CCI2A
P2.0 - 13 (1)
P2.0 - 17 (1)
P2.0 - B3 (1)
ACLK
(internal)
ACLK
(internal)
ACLK
(internal)
TD0.2
CCI2B
P2.6 - 21
P2.6 - 25
P2.6 - B5
–
–
–
VSS
GND
–
–
–
–
–
–
VCC
VCC
–
–
–
P2.4 - 19
P2.4 - 23
P2.4 - B4
TEC0FLT2
TECXFLT2
–
–
–
(1)
(2)
62
CCR2
TD2
TD2
Pins P1.6 for TD0.0, P1.7 for TD0.1, and P2.0 for TD0.2 are optimized for matching.
The ADC10_A trigger is available on MSP430F51x2 devices.
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.9.12 TD1
TD1 is a 16-bit timer/counter with three capture/compare registers supporting up to 256-MHz (4-ns)
resolution (see Table 6-12). TD1 can support multiple capture/compares, PWM outputs, and interval
timing. TD1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers. External fault inputs as well as a
external timer counter clear is supported along with interrupt flags from the TEC0 module.
Table 6-12. TD1 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
PJ.6 - E5
TD1CLK
ACLK
(internal)
SMCLK
SMCLK
PJ.6 - 32
RSB
(40-PIN
QFN)
DA
(38-PIN
TSSOP)
YFF
(40-PIN
DSBGA)
PJ.6 - 28
PJ.6 - 32
ACLK
(internal)
ACLK
(internal)
SMCLK(inte
rnal)
PJ.6 - 28
–
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
RSB
(40-PIN
QFN)
DA
(38-PIN
TSSOP)
YFF
(40-PIN
DSBGA)
TDCLK
–
–
–
ACLK
ACLK
–
–
–
SMCLK
SMCLK
–
–
–
PJ.6 - E5
TD1CLK
TDCLK
–
–
–
–
–
from TD0
(internal)
CLK0
Timer
NA
NA
P2.7 - 22
P2.7 - 26
P2.7 - C5
TEC1CLR
TECxCLR
–
–
–
P2.1 - 14 (1)
P2.1 - 18 (1)
P2.1 - A2
TD1.0
CCI0A
P2.1 - 14 (1)
P2.1 - 18 (1)
P2.1 - A2 (1)
–
–
–
TD1.0
CCI0B
P2.7 - 22
P2.7 - 26
P2.7 - C5
–
–
–
VSS
GND
–
–
–
–
–
–
VCC
VCC
–
–
–
P3.1 - 24
P3.1 - 28
P3.1 - C6
TEC1FLT0
TECXFLT0
–
–
–
P2.2 - 15 (1)
P2.2 - 19 (1)
P2.2 - A3
TD1.1
CCI1A
P2.2 - 15 (1)
P2.2 - 19 (1)
P2.2 - A3 (1)
CBOUT
(internal)
CBOUT
(internal)
CBOUT
(internal)
TD1.1
CCI1B
P3.0 - 23
P3.0 - 27
P3.0 - B6
CCR0
CCR1
TD0
TD1
TD0
TD1
–
–
–
VSS
GND
–
–
–
–
–
–
VCC
VCC
–
–
–
P2.7 - 22
P2.7 - 26
P2.7 - C5
TEC1FLT1
TECXFLT1
–
–
–
P2.3 - 16 (1)
P2.3 - 20 (1)
P2.3 - C4
TD1.2
CCI2A
P2.3 - 16 (1)
P2.3 - 20 (1)
P2.3 - C4 (1)
ACLK
(internal)
ACLK
(internal)
ACLK
(internal)
TD1.2
CCI2B
P3.1 - 24
P3.1 - 28
P3.1 - C6
–
–
–
VSS
GND
–
–
–
–
–
–
VCC
VCC
–
–
–
P3.0 - 23
P3.0 - 27
P3.0 - B6
TEC1FLT2
TECXFLT2
–
–
–
(1)
CCR2
TD2
TD2
Pins P2.1 for TD1.0, P2.2 for TD1.1, and P2.3 for TD1.2 are optimized for matching.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
63
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.9.13 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.9.14 ADC10_A (MSP430F51x2 Only)
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator and a conversion result buffer. A window
comparator with lower and upper limits allows CPU-independent result monitoring with three window
comparator interrupt flags.
6.9.15 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.9.16 Reference (REF) Module Voltage Reference
The REF is responsible for generation of all critical reference voltages that can be used by the various
analog peripherals in the device.
6.9.17 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
64
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.9.18 Peripheral File Map
Table 6-13 lists the base address and offset range for the registers of all peripherals.
Table 6-13. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-14)
0100h
000h–01Fh
PMM (see Table 6-15)
0120h
000h–010h
Flash Control (see Table 6-16)
0140h
000h–00Fh
CRC16 (see Table 6-17)
0150h
000h–007h
RAM Control (see Table 6-18)
0158h
000h–001h
Watchdog (see Table 6-19)
015Ch
000h–001h
UCS (see Table 6-20)
0160h
000h–01Fh
SYS (see Table 6-21)
0180h
000h–01Fh
Shared Reference (see Table 6-22)
01B0h
000h–001h
Port Mapping Control (see Table 6-23)
01C0h
000h–007h
Port Mapping Port P1 (see Table 6-24)
01C8h
000h–007h
Port Mapping Port P2 (see Table 6-25)
01D0h
000h–007h
Port Mapping Port P3 (see Table 6-26)
01D8h
000h–007h
Port P1, P2 (see Table 6-27)
0200h
000h–01Fh
Port P3 (see Table 6-28)
0220h
000h–01Fh
Port PJ (see Table 6-29)
0320h
000h–01Fh
TA0 (see Table 6-30)
03C0h
000h–03Fh
32-Bit Hardware Multiplier (see Table 6-31)
04C0h
000h–02Fh
DMA General Control (see Table 6-32)
0500h
000h–00Fh
DMA Channel 0 (see Table 6-33)
0500h
010h–00Ah
DMA Channel 1 (see Table 6-34)
0500h
020h–00Ah
DMA Channel 2 (see Table 6-35)
0500h
030h–00Ah
USCI_A0 (see Table 6-36)
05C0h
000h–01Fh
USCI_B0 (see Table 6-36)
05E0h
000h–01Fh
ADC10_A (see Table 6-38)
(MSP430F51x2 only)
0740h
000h–01Fh
Comparator_B (see Table 6-39)
08C0h
000h–00Fh
TD0 (see Table 6-40)
0B00h
000h–03Fh
TEC0 (see Table 6-42)
0C00h
000h–007h
TD1 (see Table 6-41)
0B40h
000h–03Fh
TEC1 (see Table 6-43)
0C20h
000h–007h
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
65
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-14. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-15. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 6-16. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-17. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC result
CRC16INIRES
04h
Table 6-18. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-19. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-20. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
66
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-21. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-22. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 6-23. Port Mapping Control (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password
PMAPPWD
00h
Port mapping control
PMAPCTL
02h
Table 6-24. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1.0 mapping
P1MAP0
00h
Port P1.1 mapping
P1MAP1
01h
Port P1.2 mapping
P1MAP2
02h
Port P1.3 mapping
P1MAP3
03h
Port P1.4 mapping
P1MAP4
04h
Port P1.5 mapping
P1MAP5
05h
Port P1.6 mapping
P1MAP6
06h
Port P1.7 mapping
P1MAP7
07h
Table 6-25. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2.0 mapping
P2MAP0
00h
Port P2.1 mapping
P2MAP2
01h
Port P2.2 mapping
P2MAP2
02h
Port P2.3 mapping
P2MAP3
03h
Port P2.4 mapping
P2MAP4
04h
Port P2.5 mapping
P2MAP5
05h
Port P2.6 mapping
P2MAP6
06h
Port P2.7 mapping
P2MAP7
07h
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
67
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-26. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3.0 mapping
P3MAP0
00h
Port P3.1 mapping
P3MAP1
01h
Port P3.2 mapping
P3MAP2
02h
Port P3.3 mapping
P3MAP3
03h
Port P3.4 mapping
P3MAP4
04h
Port P3.5 mapping
P3MAP5
05h
Port P3.6 mapping
P3MAP6
06h
Port P3.7 mapping
P3MAP7
07h
Table 6-27. Port Registers Port P1, P2 (Base Addresses: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-28. Port Registers P3 (Base Addresses: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
68
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-29. Port Registers PJ (Base Addresses: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Port PJ selection
PJSEL
0Ah
Table 6-30. TA0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-31. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
69
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-32. DMA General Control (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 6-33. DMA Channel 0 (Base Address: 0510h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
Table 6-34. DMA Channel 1 (Base Address: 0520h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
Table 6-35. DMA Channel 2 (Base Address: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
70
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-36. USCI0_A Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA0CTL0
01h
USCI control 1
UCA0CTL1
00h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
Table 6-37. USCI0_B Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB0CTL0
00h
USCI synchronous control 1
UCB0CTL1
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Table 6-38. ADC10_A Registers (MSP430F51x2 Devices Only) (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A control 0
ADC10CTL0
00h
ADC10_A control 1
ADC10CTL1
02h
ADC10_A control 2
ADC10CTL2
04h
ADC10_A window comparator low threshold
ADC10LO
06h
ADC10_A window comparator high threshold
ADC10HI
08h
ADC10_A memory control register 0
ADC10MCTL0
0Ah
ADC10_A conversion memory register
ADC10MEM0
12h
ADC10_A interrupt enable
ADC10IE
1Ah
ADC10_A interrupt flags
ADC10IGH
1Ch
ADC10_A interrupt vector word
ADC10IV
1Eh
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
71
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-39. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comparator_B control 0
CBCTL0
00h
Comparator_B control 1
CBCTL1
02h
Comparator_B control 2
CBCTL2
04h
Comparator_B control 3
CBCTL3
06h
Comparator_B interrupt
CBINT
0Ch
Comparator_B interrupt vector word
CBIV
0Eh
Table 6-40. TD0 Registers (Base Address: 0B00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TD0 control 0
TD0CTL0
00h
TD0 control 1
TD0CTL1
02h
TD0 control 2
TD0CTL2
04h
TD0 counter
TD0R
06h
Capture/compare control 0
TD0CCTL0
08h
Capture/compare 0
TD0CCR0
0Ah
Capture/compare latch 0
TD0CL0
0Ch
Capture/compare control 1
TD0CCTL1
0Eh
Capture/compare 1
TD0CCR1
10h
Capture/compare latch 1
TD0CL1
12h
Capture/compare control 2
TD0CCTL2
14h
Capture/compare 2
TD0CCR2
16h
Capture/compare latch 2
TD0CL2
18h
TD0 high-resolution control 0
TD0HCTL0
38h
TD0 high-resolution control 1
TD0HCTL1
3Ah
TD0 high-resolution interrupt
TD0HINT
3Ch
TD0 interrupt vector
TD0IV
3Eh
Table 6-41. TD1 Registers (Base Address: 0B40h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TD1 control 0
TD1CTL0
00h
TD1 control 1
TD1CTL1
02h
TD1 control 2
TD1CTL2
04h
TD1 counter
TD1R
06h
Capture/compare control 0
TD1CCTL0
08h
Capture/compare 0
TD1CCR0
0Ah
Capture/compare latch 0
TD1CL0
0Ch
Capture/compare control 1
TD1CCTL1
0Eh
Capture/compare 1
TD1CCR1
10h
Capture/compare latch 1
TD1CL1
12h
Capture/compare control 2
TD1CCTL2
14h
Capture/compare 2
TD1CCR2
16h
Capture/compare latch 2
TD1CL2
18h
TD1 high-resolution control 0
TD1HCTL0
38h
TD1 high-resolution control 1
TD1HCTL1
3Ah
TD1 high-resolution interrupt
TD1HINT
3Ch
TD1 interrupt vector
TD1IV
3Eh
72
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-42. TEC0 Registers (Base Address: 0C00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Timer event control 0 external control 0
TEC0CTL0
00h
Timer event control 0 external control
TEC0CTL1
02h
Timer event control 0 external control
TEC0CTL2
04h
Timer event control 0 status
TEC0STA
06h
Timer event control 0 external interrupt
TEC0XINT
08h
Timer event control 0 external interrupt vector
TEC0IV
0Ah
Table 6-43. TEC1 Registers (Base Address: 0C20h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Timer event control 1 external control 0
TEC1CTL0
00h
Timer event control 1 external control
TEC1CTL1
02h
Timer event control 1 external control
TEC1CTL2
04h
Timer event control 1 status
TEC1STA
06h
Timer event control 1 external interrupt
TEC1XINT
08h
Timer event control 1 external interrupt vector
TEC1IV
0Ah
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
73
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10 Input/Output Diagrams
6.10.1 Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-44 summarizes the selection of the pin function.
Pad Logic
To ADC10
INCHx = x
Pad Logic
To Comparator_B
From Comparator_B
CBPD.y
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.0/PM_UCA0CLK/PM_UCB0STE/A0/CB0
P1.1/PM_UCA0TXD/PM_UCA0SIMO/A1/CB1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A2/CB2
P1.3/PM_UCB0CLK/PM_UCA0STE/A3/CB3
P1.4/PM_UCB0SIMO/PM_UCB0SDA/A4/CB4
P1.5/PM_UCB0SOMI/PM_UCB0SCL/A5/CB5
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Holder
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-2. Port P1 (P1.0 to P1.5) Diagram
74
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-44. Port P1 (P1.0 to P1.5) Pin Functions
PIN NAME (P1.x)
x
P1.0/
CONTROL BITS OR SIGNALS (1)
FUNCTION
P1.x (I/O)
PM_UCA0CLK/
PM_UCB0STE/
UCA0CLK/UCB0STE (2)
P1SEL.x
P1MAP.x
CBPD.y
0
X
0
0
1
default
0
X
1
31
INCHx = 0
X
0
A0/
A0 (4)
CB0
CB0
P1.1/
P1.x (I/O)
PM_UCA0TXD/
PM_UCA0SIMO/
(3)
P1DIR.x
I: 0; O: 1
PM_UCA0TXD/PM_UCA0SIMO
(2)
X
X
X
1 (y = 0)
I: 0; O: 1
0
X
0
0
1
default
0
1
A1/
A1 (4)
X
1
31
INCHx = 1
X
CB1
CB1
X
X
X
1 (y = 1)
P1.2/
P1.x (I/O)
I: 0; O: 1
0
X
0
0
1
default
0
X
1
31
INCHx = 2
X
PM_UCA0RXD/
PM_UCA0SOMI/
PM_UCA0RXD/PM_UCA0SOMI
(2)
2
A2/
A2 (4)
CB2
CB2
P1.3/
P1.x (I/O)
X
X
X
1 (y = 2)
I: 0; O: 1
0
X
0
UCB0CLK/UCA0STE (2)
0
1
default
0
A3/
A3 (4)
X
1
31
INCHx = 3
X
CB3
CB3
P1.4/
P1.x (I/O)
PM_UCB0CLK/
PM_UCA0STE/
PM_UCB0SIMO/
PM_UCB0SDA/
3
PM_UCB0SIMO/PM_UCB0SDA (2)
(5)
X
X
X
1 (y = 3)
I: 0; O: 1
0
X
0
0
1
default
0
4
A4/
A4 (4)
X
1
31
INCHx = 4
X
CB4
CB4
X
X
X
1 (y = 4)
P1.5/
P1.x (I/O)
I: 0; O: 1
0
X
0
0
1
default
0
PM_UCB0SOMI/
PM_UCB0SCL/
PM_UCB0SOMI/PM_UCB0SCL
(2) (5)
5
A5/
A5 (4)
X
1
31
INCHx = 5
X
CB5
CB5
X
X
X
1 (y = 5)
(1)
(2)
(3)
(4)
(5)
X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
MSP430F51x2 device only
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
75
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.2 Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-45 summarizes the selection of the pin function.
Pad Logic
P1REN.x
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVIO
1
1
Direction
0: Input
1: Output
P1.6/PM_TD0_0
P1.7/PM_TD0_1
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Figure 6-3. Port P1 (P1.6 and P1.7) Diagram
Table 6-45. Port P1 (P1.6 and P1.7) Pin Functions
PIN NAME (P1.x)
x
P1.6/
6
P1.7/
PM_TD0.1
76
7
CONTROL BITS OR SIGNALS (1)
P1DIR.x
P1SEL.x
P1MAP.x
I: 0; O: 1
0
X
TD0.CCI0A
0
1
default
TD0.TA0
1
1
default
P1.x (I/O)
I: 0; O: 1
0
X
TD0.CCI1A
0
1
default
TD0.TA1
1
1
default
P1.x (I/O)
PM_TD0.0
(1)
FUNCTION
X = Don't care
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.10.3 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-46 summarizes the selection of the pin function.
Pad Logic
P2REN.x
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVIO
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
To Port Mapping
P2.0/PM_TD0_2
P2.1/PM_TD1_0
P2.2/PM_TD1_1
P2.3/PM_TD1_2
P2.4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0_0
P2.5/PM_TEC0FLT0/PM_TD0_1
P2.6/PM_TEC0FLT1/PM_TD0_2
P2.7/PM_TEC1CLR/PM_TEC1FLT1/PM_TD1_0
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-4. Port P2 (P2.0 to P2.7) Diagram
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
77
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-46. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
x
CONTROL BITS OR SIGNALS
FUNCTION
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
0
1
default
TD0.TA2
1
1
default
P2.x (I/O)
I: 0; O: 1
0
X
0
1
default
TD1.TA0
1
1
default
P2.x (I/O)
I: 0; O: 1
0
X
0
1
default
TD1.TA1
1
1
default
P2.x (I/O)
I: 0; O: 1
0
0
TD1.CCI2A
0
1
default
TD1.TA2
1
1
default
P2.4/
P2.x (I/O)
I: 0; O: 1
0
X
PM_TEC0CLR/
TD0.TECEXTCLR, controlled by enable signals in the TEC0 module
0
1
default
TD0.TECXFLT2, controlled by enable signals in the TEC0 module
0
1
default
default
P2.0/
P2.x (I/O)
PM_TD0.2
0
P2.1/
PM_TD1.0
1
P2.2/
PM_TD1.1
2
P2.3/
PM_TD1.2
3
PM_TEC0FLT2/
4
TD0.CCI2A
TD1.CCI0A
TD1.CCI1A
P2MAP.x
PM_TD0.0
TD0.TA0
1
1
P2.5/
P2.x (I/O)
I: 0; O: 1
0
x
0
1
default
default
PM_TEC0FLT0/
5
TD0.TECXFLT0, controlled by enable signals in the TEC0 module
PM_TD0.1
TD0.TA1
1
1
P2.6/
P2.x (I/O)
I: 0; O: 1
0
X
TD0.TECXFLT1, controlled by enable signals in the TEC0 module
0
1
default
PM_TD0.2
TD0.TA2
1
1
default
P2.7/
P2.x (I/O)
I: 0; O: 1
0
X
PM_TEC1CLR/
TD1.TECEXTCLR, controlled by enable signals in the TEC1 module
0
1
default
TD1.TECXFLT1, controlled by enable signals in the TEC1 module
0
1
default
TD1.TA0
1
1
default
PM_TEC0FLT1/
PM_TEC1FLT1/
PM_TD1.0
78
6
7
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.10.4 Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-47 summarizes the selection of the pin function.
Pad Logic
P3REN.x
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVIO
1
1
Direction
0: Input
1: Output
P3.0/PM_TEC1FLT2/PM_TD1_1
P3.1/PM_TEC1FLT0/PM_TD1_2
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
To Port Mapping
D
Figure 6-5. Port P3 (P3.0 and P3.1) Diagram
Table 6-47. Port P3 (P3.0 and P3.1) Pin Functions
PIN NAME (P3.x)
x
P3.0/
P3.x (I/O)
PM_TEC1FLT2/
0
PM_TD1.1
P3.1/
PM_TEC1FLT0/
PM_TD1.2
FUNCTION
1
CONTROL BITS OR SIGNALS
P3DIR.x
P3SEL.x
P3MAP.x
I: 0; O: 1
0
X
TD1.TECXFLT2, controlled by enable signals in the TEC1 module
0
1
default
TD1.TA1
1
1
default
P3.x (I/O)
I: 0; O: 1
0
X
TD1.TECXFLT0, controlled by enable signals in the TEC1 module
0
1
default
TD1.TA2
1
1
default
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
79
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.5 Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-48 summarizes the selection of the pin function.
Pad Logic
To Comparator_B
From Comparator_B
CBPD.y
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.2/PM_TD0_0/PM_SMCLK/CB14
P3.3/PM_TA0CLK/PM_CBOUT/CB13
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Holder
EN
To Port Mapping
D
Figure 6-6. Port P3 (P3.2 and P3.3) Diagram
Table 6-48. Port P3 (P3.2 and P3.3) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
P3MAP.x
CBPD.y
P3.2/
P3.x (I/O)
I: 0; O: 1
0
X
0
PM_TD0.0/
TD0.CCI0A
0
1
default
0
SMCLK output
1
1
default
0
CB14
CB14
X
X
X
1 (y = 14)
P3.3/
P3.x (I/O)
I: 0; O: 1
0
X
0
PM_TA0CLK/
TA0.TA0CLK
0
1
default
0
CBOUT
1
1
default
0
CB13
X
X
X
1 (y = 13)
PM_SMCLK/
PM_CBOUT/
2
3
CB13
(1)
80
X = Don't care
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.10.6 Port P3 (P3.4) Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-49 summarizes the selection of the pin function.
Pad Logic
To DCO
CBPD.y
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.4/PM_TD0CLK/PM_MCLK
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Holder
EN
To Port Mapping
D
Figure 6-7. Port P3 (P3.4) Diagram
Table 6-49. Port P3 (P3.4) Pin Functions
PIN NAME (P3.x)
x
P3.4/
P3.x (I/O)
PM_TD0CLK/
PM_MCLK
(1)
FUNCTION
4
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
P3MAP.x
I: 0; O: 1
0
X
0
TD0 clock input
0
1
default
0
MCLK output
1
1
default
0
X = Don't care
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
81
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.7 Port P3 (P3.5) Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-50 summarizes the selection of the pin function.
Pad Logic
To ADC10 reference VREF-
To ADC10
INCHx = x
To Comparator_B
From Comparator_B
CBPD.y
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.5/PM_TA0_2/A8/VREF+/CB12
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Holder
EN
To Port Mapping
D
Figure 6-8. Port P3 (P3.5) Diagram
Table 6-50. Port P3 (P3.5) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
P3MAP.x
CBPD.y
P3.5/
P3.x (I/O)
I: 0; O: 1
0
X
0
PM_TA0.2/
TA0.CCI2A
0
1
default
0
TA0.TA2
1
1
default
0
X
VEREF+/
5
X
1
31
A8/
A8 (2)
X
1
INCHx=8
X
CB12
CB12
X
X
X
1 (y = 12)
(1)
(2)
82
VEREF+
(2)
X = Don't care
MSP430F51x2 devices only.
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.10.8 Port P3 (P3.6) Input/Output With Schmitt Trigger
Figure 6-9 shows the port diagram. Table 6-51 summarizes the selection of the pin function.
Pad Logic
To ADC10 reference VREF-
To ADC10
INCHx = x
To Comparator_B
From Comparator_B
CBPD.y
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.6/PM_TA0_1/A7/VREF-/CB11
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Holder
EN
To Port Mapping
D
Figure 6-9. Port P3 (P3.6) Diagram
Table 6-51. Port P3 (P3.6) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
P3MAP.x
CBPD.y
P3.6/
P3.x (I/O) (2)
I: 0; O: 1
0
X
0
PM_TA0.1/
TA0.CCR0
0
1
default
0
TA0.TA1
1
1
default
0
X
1
31
X
X
1
31
INCHx = 7
X
X
X
0
1 (y = 11)
VEREF-/
A7/
VEREFA7
CB11
(1)
(2)
(3)
6
(3)
(3)
CB11
X = Don't care
Default condition.
MSP430F51x2 devices only.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
83
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.9 Port P3 (P3.7) Input/Output With Schmitt Trigger
Figure 6-10 shows the port diagram. Table 6-52 summarizes the selection of the pin function.
Pad Logic
To ADC10
INCHx = x
Pad Logic
To Comparator_B
From Comparator_B
CBPD.y
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.7/PM_TA0_0/A6/CB10
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Holder
EN
To Port Mapping
D
Figure 6-10. Port P3 (P3.7) Diagram
Table 6-52. Port P3 (P3.7) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.2
P3MAP.x
CBPD.y
P3.7/
P3.x (I/O) (1)
I: 0; O: 1
0
X
0
PM_TA0.0/
TA0.CCR0
0
1
default
0
TA0.TA0
1
1
default
0
A6/
A6 (2)
X
1
31
INCHx = 6
X
CB10
CB10
X
X
0
1 (y = 10)
7
(1)
(2)
84
X = Don't care
MSP430F51x2 devices only.
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-11 shows the port diagram. Table 6-53 summarizes the selection of the pin function.
Pad Logic
To Comparator_B
From Comparator_B
CBPD.x
PJREN.x
PJDIR.x
0
DVCC
1
PJOUT.x
00
From JTAG
01
SMCLK
10
DVSS
0
DVCC
1
PJDS.0
0: Low drive
1: High drive
11
1
PJ.0/SMCLK/TDO/CB6
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
Figure 6-11. Port PJ (PJ.0) Diagram
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
85
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-12 shows the port diagram. Table 6-53 summarizes the selection of the pin function.
Pad Logic
To Comparator_B
From Comparator_B
CBPD.x
PJREN.x
PJDIR.x
DVSS
DVSS
0
DVCC
1
1
0
1
PJOUT.x
00
From JTAG
01
MCLK/ADC10CLK/ACLK
10
PJDS.x
0: Low drive
1: High drive
11
PJ.1/MCLK/TDI/TCLK/CB7
PJ.2/ADC10CLK/TMSCB8
PJ.3/ACLK/TCK/CB9
PJSEL.x
From JTAG
PJIN.x
EN
To JTAG
Bus
Holder
D
Figure 6-12. Port PJ (PJ.1 to PJ.3) Diagram
86
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-53. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.x (I/O) (2)
PJ.0/
SMCLK/
0
TDO/
CB6
0
1
X
X
X
0
1 (y = 6)
I: 0; O: 1
0
0
0
1
1
0
0
X
X
1
X
0
X
0
1 (y = 7)
I: 0; O: 1
0
0
0
1
1
0
0
X
X
1
X
(2)
TDI/TCLK (3)
(4)
(2)
PJ.x (I/O)
ADC10CLK/
ADC10CLK (See
TMS (3)
CB8
PJ.3/
PJ.x (I/O) (2)
ACLK/
ACLK
(1)
(2)
(3)
(4)
(5)
TCK
(5)
)
(4)
CB8
CB9
0
0
PJ.2/
TCK/
0
1
CB7
3
0
X
MCLK
2
I: 0; O: 1
1
PJ.x (I/O)
TMS/
CBPD.y
X
MCLK/
CB7
JTAG
MODE
TDO (3)
PJ.1/
1
PJSEL.x
SMCLK
CB6
TDI/TCLK/
PJDIR.x
(3) (4)
CB9
X
X
0
1 (y = 8)
I: 0; O: 1
0
0
0
1
1
0
0
X
X
1
X
X
X
0
1 (y = 9)
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
MSP430F51x2 device only.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
87
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
Figure 6-13 shows the port diagram. Table 6-54 summarizes the selection of the pin function.
Pad Logic
From XT1
PJREN.4
PJDIR.4
DVSS
0
DVCC
1
1
0
1
PJOUT.4
0
DVSS
1
PJSEL.5
PJDS.x
0: Low drive
1: High drive
XT1BYPASS
PJSEL.4
PJ.4/XOUT
PJIN.4
EN
Module X IN
Bus
Keeper
D
Figure 6-13. Port PJ (PJ.4) Diagram
88
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
Figure 6-14 shows the port diagram. Table 6-54 summarizes the selection of the pin function.
Pad Logic
To XT1
PJREN.5
PJDIR.5
DVSS
0
DVCC
1
1
0
1
PJOUT.5
0
Module X OUT
1
PJ.5/XIN
PJDS.0
0: Low drive
1: High drive
PJSEL.5
PJIN.5
Bus
Keeper
EN
Module X IN
D
Figure 6-14. Port PJ (PJ.5) Diagram
Table 6-54. Port PJ (PJ.4 and PJ.5) Pin Functions
PIN NAME (PJ.x)
PJ.4/
x
4
FUNCTION
PJ.4 (I/O)
XOUT
XOUT crystal mode (2)
PJ.5/
PJ.5 (I/O) (2)
XIN
5
XIN crystal mode
(3)
XIN bypass mode (3)
(1)
(2)
(3)
CONTROL BITS OR SIGNALS (1)
PJDIR.x
PJSEL.4
PJSEL.5
XT1BYPASS
I: 0; O: 1
0
0
X
1
X
1
X
1
0
I: 0; O: 1
X
0
x
X
X
1
0
X
X
1
1
X = Don't care
Setting PJSEL.5 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, PJ.4 can be used as
general-purpose I/O.
Setting PJSEL.5 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, PJ.5 is configured for crystal mode
or bypass mode.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
89
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
Figure 6-15 shows the port diagram. Table 6-55 summarizes the selection of the pin function.
Pad Logic
To Comparator_B
From Comparator_B
CBPD..x
PJREN.x
PJDIR.x
0
From Module
1
PJOUT.x
0
From Module
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
PJ.6/TD1CLK/TD0_1/CB15
PJDS.x
0: Low drive
1: High drive
PJSEL.x
PJIN.x
Bus
Holder
EN
To Port Mapping
D
Figure 6-15. Port PJ (PJ.6) Diagram
Table 6-55. Port PJ (PJ.6) Pin Functions
PIN NAME (PJ.x)
x
FUNCTION
PJ.6/
PJ.x (I/O)
TD1CLK/
TD1 clock input
6
TD0.1/
CB15
(1)
90
CONTROL BITS OR SIGNALS (1)
PJDIR.x
PJSEL.x
CBPD.y
I: 0; O: 1
0
0
0
1
0
TD0.TA1
1
1
0
CB15
X
X
1 (y = 15)
X = Don't care
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
6.11 Device Descriptors
Table 6-56 and Table 6-57 list the complete contents of the device descriptor tag-length-value (TLV)
structure for the MSP430F51x2 and MSP430F51x1 devices, respectively.
Table 6-56. MSP430F51x2 Device Descriptor Table (1)
VALUE
DESCRIPTION
Timer_D0
Calibration
Timer_D1
Calibration
(1)
F5172
F5152
F5132
RSB, YFF
DA
RSB
DA
RSB
DA
0x06
0x06
0x06
0x06
0x06
0x06
0x1A00
1
CRC length
0x1A01
1
0x06
0x06
0x06
0x06
0x06
0x06
CRC value
0x1A02
2
per unit
per unit
per unit
per unit
per unit
per unit
Device ID
0x1A04
1
0x30
0x30
0x2C
0x2C
0x28
0x28
Device ID
0x1A05
1
0x80
0x80
0x80
0x80
0x80
0x80
Hardware revision
0x1A06
1
0x30
030
0x30
0x30
0x30
0x30
Firmware revision
0x1A07
1
0x10
0x10
0x10
0x10
0x10
0x10
Die record tag
0x1A08
1
0x08
08
0x08
08
0x08
08
Die record length
0x1A09
1
0x0A
0A
0x0A
0A
0x0A
0A
Lot/wafer ID
0x1A0A
4
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
0x1A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
0x1A10
2
per unit
per unit
per unit
per unit
per unit
per unit
Test results
0x1A12
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC10 calibration tag
0x1A14
1
0x13
0x13
0x13
0x13
0x13
0x13
ADC10 calibration length
0x1A15
1
0x10
0x10
0x10
0x10
0x10
0x10
ADC gain factor
0x1A16
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC offset
0x1A18
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V reference
Temperature sensor 30°C
0x1A1A
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V reference
Temperature sensor 85°C
0x1A1C
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V reference
Temperature sensor 30°C
0x1A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V reference
Temperature sensor 85°C
0x1A20
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V reference
Temperature sensor 30°C
0x1A22
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V reference
Temperature sensor 85°C
0x1A24
2
per unit
per unit
per unit
per unit
per unit
per unit
0x12
Die Record
REF User
Calibration
SIZE
(bytes)
Info length
Info Block
ADC10
Calibration
ADDRESS
REF tag
0x1A26
1
0x12
0x12
0x12
0x12
0x12
REF length
0x1A27
1
0x06
0x06
0x06
0x06
0x06
0x06
REF 1.5-V reference
0x1A28
2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
REF 2.0-V reference
0x1A2A
2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
REF 2.5-V reference
0x1A2C
2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Timer_D tag
0x1A2E
1
0x15
0x15
0x15
0x15
0x15
0x15
Timer_D length
0x1A2F
1
0x08
0x08
0x08
0x08
0x08
0x08
Timer_D 64-MHz frequency
0x1A30
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 128-MHz frequency
0x1A32
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 200-MHz frequency
0x1A34
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 256-MHz frequency
0x1A36
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D tag
0x1A38
1
0x15
0x15
0x15
0x15
0x15
0x15
Timer_D length
0x1A39
1
0x08
0x08
0x08
0x08
0x08
0x08
Timer_D 64-MHz frequency
0x1A3A
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 128-MHz frequency
0x1A3C
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 200-MHz frequency
0x1A3E
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 256-MHz frequency
0x1A40
2
per unit
per unit
per unit
per unit
per unit
per unit
NA = Not applicable
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
91
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-56. MSP430F51x2 Device Descriptor Table(1) (continued)
VALUE
DESCRIPTION
Peripheral
Descriptor
92
ADDRESS
SIZE
(bytes)
F5172
F5152
F5132
RSB, YFF
DA
RSB
DA
RSB
DA
0x02
0x02
0x02
0x02
0x02
0x02
Peripheral descriptor tag
0x1A42
1
Peripheral descriptor length
0x1A43
1
0x53
0x53
0x53
0x53
0x53
0x53
BSL memory
0x1A44
2
0x8A08
0x8A08
0x8A08
0x8A08
0x8A08
0x8A08
Information memory
0x1A46
2
0x860C
0x860C
0x860C
0x860C
0x860C
0x860C
RAM
0x1A48
2
0x2A0E
0x2A0E
0x2A0E
0x2A0E
0x280E
0x280E
Main memory
0x1A4A
2
0x9240
0x9240
0x9060
0x9060
0x8E70
0x8E70
Delimiter
0x1A4C
1
0x00
0x00
0x00
0x00
0x00
0x00
Peripheral count
0x1A4D
1
0x1C
0x1C
0x1B
0x1B
0x1B
0x1B
MSP430CPUXV2
0x1A4E
2
0x2300
0x2300
0x2300
0x2300
0x2300
0x2300
SBW
0x1A50
2
0x0F00
0x0F00
0x0F00
0x0F00
0x0F00
0x0F00
EEM-S
0x1A52
2
0x0300
0x0300
0x0300
0x0300
0x0300
0x0300
TI BSL
0x1A54
2
0xFC00
0xFC00
0xFC00
0xFC00
0xFC00
0xFC00
SFR
0x1A56
2
0x4110
0x4110
0x4110
0x4110
0x4110
0x4110
PMM
0x1A58
2
0x3002
0x3002
0x3002
0x3002
0x3002
0x3002
FCTL
0x1A5A
2
0x3802
0x3802
0x3802
0x3802
0x3802
0x3802
CRC16
0x1A5C
2
0x3C01
0x3C01
0x3C01
0x3C01
0x3C01
0x3C01
CRC16_RB
0x1A5E
2
0x3D00
0x3D00
0x3D00
0x3D00
0x3D00
0x3D00
RAMCTL
0x1A60
2
0x4400
0x4400
0x4400
0x4400
0x4400
0x4400
WDT_A
0x1A62
2
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
UCS
0x1A64
2
0x4801
0x4801
0x4801
0x4801
0x4801
0x4801
SYS
0x1A66
2
0x4202
0x4202
0x4202
0x4202
0x4202
0x4202
Shared REF
0x1A68
2
0xA003
0xA003
0xA003
0xA003
0xA003
0xA003
Port Mapping
0x1A6A
2
0x1001
0x1001
0x1001
0x1001
0x1001
0x1001
Port 1/2
0x1A6C
2
0x5104
0x5104
0x5104
0x5104
0x5104
0x5104
Port 3/4
0x1A6E
2
0x5202
0x5202
0x5202
0x5202
0x5202
0x5202
Port J
0x1A70
2
0x5F10
0x5F10
0x5F10
0x5F10
0x5F10
0x5F10
TA0
0x1A72
2
0x610A
0x610A
0x610A
0x610A
0x610A
0x610A
MPY32
0x1A74
2
0x8510
0x8510
0x8510
0x8510
0x8510
0x8510
DMA with 3 channels
0x1A76
2
0x4704
0x4704
0x4704
0x4704
0x4704
0x4704
USCI_A0/B0
0x1A78
2
0x900C
0x900C
0x900C
0x900C
0x900C
0x900C
ADC10_A
0x1A7A
2
0xD318
0xD318
0xD318
0xD318
0xD318
0xD318
COMP_B
0x1A7C
2
0xA818
0xA818
0x1A919
0xA818
0x1A919
0xA818
TIMER_D0
0x1A7E
2
0xD624
0xD624
0xD624
0xD624
0xD624
0xD624
TIMER_D1
0x1A80
2
0x6D04
0x6D04
0x6D04
0x6D04
0x6D04
0x6D04
TEC_0
0x1A82
2
0x700C
0x700C
0x700C
0x700C
0x700C
0x700C
TEC_1
0x1A84
2
0x7002
0x7002
0x7002
0x7002
0x7002
0x7002
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-56. MSP430F51x2 Device Descriptor Table(1) (continued)
VALUE
DESCRIPTION
Interrupts
Empty
ADDRESS
SIZE
(bytes)
F5172
F5152
F5132
RSB, YFF
DA
RSB
DA
RSB
DA
COMP_B
0x1A86
1
0xA8
0xA8
0xA8
0xA8
0xA8
0xA8
TEC_0
0x1A87
1
0x6D
0x6D
0x6D
0x6D
0x6D
0x6D
TIMER_D0
0x1A88
1
0x62
0x62
0x62
0x62
0x62
0x62
TIMER_D0
0x1A89
1
0x63
0x63
0x63
0x63
0x63
0x63
WDTIFG
0x1A8A
1
0x40
0x40
0x40
0x40
0x40
0x40
USCI_A0
0x1A8B
1
0x90
0x90
0x90
0x90
0x90
0x90
USCI_B0
0x1A8C
1
0x91
0x91
0x91
0x91
0x91
0x91
ADC10_A
0x1A8D
1
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
TA0.CCIFG0
0x1A8E
1
0x60
0x60
0x60
0x60
0x60
0x60
TA0.CCIFG1..4
0x1A8F
1
0x61
0x61
0x61
0x61
0x61
0x61
DMA
0x1A90
1
0x46
0x46
0x46
0x46
0x46
0x46
TEC_1
0x1A91
1
0x6E
0x6E
0x6E
0x6E
0x6E
0x6E
TIMER_D1
0x1A92
1
0x64
0x64
0x64
0x64
0x64
0x64
TIMER_D1
0x1A93
1
0x65
0x65
0x65
0x65
0x65
0x65
Port P1
0x1A94
1
0x50
0x50
0x50
0x50
0x50
0x50
Port P2
0x1A95
1
0x51
0x51
0x51
0x51
0x51
0x51
Delimiter
0x1A96
1
0x00
0x00
0x00
0x00
0x00
0x00
Unused memory
0x1A97 0x1AB9
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Table 6-57. MSP430F51x1 Device Descriptor Table (1)
VALUE
DESCRIPTION
SIZE
(bytes)
F5171
F5151
F5131
RSB
DA
RSB
DA
RSB
DA
0x06
0x06
0x06
0x06
0x06
0x06
Info length
0x1A00
1
CRC length
0x1A01
1
0x06
0x06
0x06
0x06
0x06
0x06
CRC value
0x1A02
2
per unit
per unit
per unit
per unit
per unit
per unit
Device ID
0x1A04
1
0x2E
0x2E
0x2A
0x2A
0x26
0x26
Device ID
0x1A05
1
0x80
0x80
0x80
0x80
0x80
0x80
Hardware revision
0x1A06
1
0x30
0x30
0x30
0x30
0x30
0x30
Firmware revision
0x1A07
1
0x10
0x10
0x10
0x10
0x10
0x10
Die record tag
0x1A08
1
0x08
08
0x08
08
0x08
08
Die record length
0x1A09
1
0x0A
0A
0x0A
0A
0x0A
0A
Info Block
Die Record
(1)
ADDRESS
Lot/wafer ID
0x1A0A
4
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
0x1A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
0x1A10
2
per unit
per unit
per unit
per unit
per unit
per unit
Test results
0x1A12
2
per unit
per unit
per unit
per unit
per unit
per unit
NA = Not applicable
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
93
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-57. MSP430F51x1 Device Descriptor Table(1) (continued)
VALUE
DESCRIPTION
ADC10
Calibration
REF User
Calibration
Timer_D0
Calibration
Timer_D1
Calibration
94
ADDRESS
SIZE
(bytes)
F5171
F5151
F5131
RSB
DA
RSB
DA
RSB
DA
0x05
0x05
0x05
0x05
0x05
0x05
ADC10 calibration tag
0x1A14
1
ADC10 calibration length
0x1A15
1
0x10
0x10
0x10
0x10
0x10
0x10
ADC gain factor
0x1A16
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC offset
0x1A18
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V reference
Temperature sensor 30°C
0x1A1A
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V reference
Temperature sensor 85°C
0x1A1C
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V reference
Temperature sensor 30°C
0x1A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V reference
Temperature sensor 85°C
0x1A20
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V reference
Temperature sensor 30°C
0x1A22
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V reference
Temperature sensor 85°C
0x1A24
2
per unit
per unit
per unit
per unit
per unit
per unit
0x12
REF tag
0x1A26
1
0x12
0x12
0x12
0x12
0x12
REF length
0x1A27
1
0x06
0x06
0x06
0x06
0x06
0x06
REF 1.5-V reference
0x1A28
2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
REF 2.0-V reference
0x1A2A
2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
REF 2.5-V reference
0x1A2C
2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Timer_D tag
0x1A2E
1
0x15
0x15
0x15
0x15
0x15
0x15
Timer_D length
0x1A2F
1
0x08
0x08
0x08
0x08
0x08
0x08
Timer_D 64-MHz frequency
0x1A30
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 128-MHz frequency
0x1A32
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 200-MHz frequency
0x1A34
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 256-MHz frequency
0x1A36
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D tag
0x1A38
1
0x15
0x15
0x15
0x15
0x15
0x15
Timer_D length
0x1A39
1
0x08
0x08
0x08
0x08
0x08
0x08
Timer_D 64-MHz frequency
0x1A3A
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 128-MHz frequency
0x1A3C
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 200-MHz frequency
0x1A3E
2
per unit
per unit
per unit
per unit
per unit
per unit
Timer_D 256-MHz frequency
0x1A40
2
per unit
per unit
per unit
per unit
per unit
per unit
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Table 6-57. MSP430F51x1 Device Descriptor Table(1) (continued)
VALUE
DESCRIPTION
Peripheral
Descriptor
ADDRESS
SIZE
(bytes)
F5171
F5151
F5131
RSB
DA
RSB
DA
RSB
DA
0x02
0x02
0x02
0x02
0x02
0x02
Peripheral descriptor tag
0x1A42
1
Peripheral descriptor length
0x1A43
1
0x51
0x51
0x51
0x51
0x51
0x51
BSL memory
0x1A44
2
0x8A08
0x8A08
0x8A08
0x8A08
0x8A08
0x8A08
Information memory
0x1A46
2
0x860C
0x860C
0x860C
0x860C
0x860C
0x860C
RAM
0x1A48
2
0x2A0E
0x2A0E
0x2A0E
0x2A0E
0x280E
0x280E
Main memory
0x1A4A
2
0x9240
0x9240
0x9060
0x9060
0x8E70
0x8E70
Delimiter
0x1A4C
1
0x00
0x00
0x00
0x00
0x00
0x00
Peripheral count
0x1A4D
1
0x1B
0x1B
0x1B
0x1B
0x1B
0x1B
MSP430CPUXV2
0x1A4E
2
0x2300
0x2300
0x2300
0x2300
0x2300
0x2300
SBW
0x1A50
2
0x0F00
0x0F00
0x0F00
0x0F00
0x0F00
0x0F00
EEM-S
0x1A52
2
0x0300
0x0300
0x0300
0x0300
0x0300
0x0300
TI BSL
0x1A54
2
0xFC00
0xFC00
0xFC00
0xFC00
0xFC00
0xFC00
SFR
0x1A56
2
0x4110
0x4110
0x4110
0x4110
0x4110
0x4110
PMM
0x1A58
2
0x3002
0x3002
0x3002
0x3002
0x3002
0x3002
FCTL
0x1A5A
2
0x3802
0x3802
0x3802
0x3802
0x3802
0x3802
CRC16
0x1A5C
2
0x3C01
0x3C01
0x3C01
0x3C01
0x3C01
0x3C01
CRC16_RB
0x1A5E
2
0x3D00
0x3D00
0x3D00
0x3D00
0x3D00
0x3D00
RAMCTL
0x1A60
2
0x4400
0x4400
0x4400
0x4400
0x4400
0x4400
WDT_A
0x1A62
2
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
UCS
0x1A64
2
0x4801
0x4801
0x4801
0x4801
0x4801
0x4801
SYS
0x1A66
2
0x4202
0x4202
0x4202
0x4202
0x4202
0x4202
Shared REF
0x1A68
2
0xA003
0xA003
0xA003
0xA003
0xA003
0xA003
Port Mapping
0x1A6A
2
0x1001
0x1001
0x1001
0x1001
0x1001
0x1001
Port 1/2
0x1A6C
2
0x5104
0x5104
0x5104
0x5104
0x5104
0x5104
Port 3/4
0x1A6E
2
0x5202
0x5202
0x5202
0x5202
0x5202
0x5202
Port J
0x1A70
2
0x5F10
0x5F10
0x5F10
0x5F10
0x5F10
0x5F10
TA0
0x1A72
2
0x610A
0x610A
0x610A
0x610A
0x610A
0x610A
MPY32
0x1A74
2
0x8510
0x8510
0x8510
0x8510
0x8510
0x8510
DMA with 3 channels
0x1A76
2
0x4704
0x4704
0x4704
0x4704
0x4704
0x4704
USCI_A0/B0
0x1A78
2
0x900C
0x900C
0x900C
0x900C
0x900C
0x900C
COMP_B
0x1A7A
2
0xA830
0xA830
0xA830
0xA830
0xA830
0xA830
TIMER_D0
0x1A7C
2
0xD624
0xD624
0xD624
0xD624
0xD624
0xD624
TIMER_D1
0x1A7E
2
0x6D04
0x6D04
0x6D04
0x6D04
0x6D04
0x6D04
TEC_0
0x1A80
2
0x700C
0x700C
0x700C
0x700C
0x700C
0x700C
TEC_1
0x1A82
2
0x7002
0x7002
0x7002
0x7002
0x7002
0x7002
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
95
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Table 6-57. MSP430F51x1 Device Descriptor Table(1) (continued)
VALUE
DESCRIPTION
Interrupts
Empty
96
ADDRESS
SIZE
(bytes)
F5171
F5151
F5131
RSB
DA
RSB
DA
RSB
DA
COMP_B
0x1A83
1
0xA8
0xA8
0xA8
0xA8
0xA8
0xA8
TEC_0
0x1A84
1
0x6D
0x6D
0x6D
0x6D
0x6D
0x6D
TIMER_D0
0x1A85
1
0x62
0x62
0x62
0x62
0x62
0x62
TIMER_D0
0x1A86
1
0x63
0x63
0x63
0x63
0x63
0x63
WDTIFG
0x1A87
1
0x40
0x40
0x40
0x40
0x40
0x40
USCI_A0
0x1A88
1
0x90
0x90
0x90
0x90
0x90
0x90
USCI_B0
0x1A89
1
0x91
0x91
0x91
0x91
0x91
0x91
ADC10_A
0x1A8A
1
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
TA0.CCIFG0
0x1A8B
1
0x60
0x60
0x60
0x60
0x60
0x60
TA0.CCIFG1..4
0x1A8C
1
0x61
0x61
0x61
0x61
0x61
0x61
DMA
0x1A8D
1
0x46
0x46
0x46
0x46
0x46
0x46
TEC_1
0x1A8E
1
0x6E
0x6E
0x6E
0x6E
0x6E
0x6E
TIMER_D1
0x1A8F
1
0x64
0x64
0x64
0x64
0x64
0x64
TIMER_D1
0x1A90
1
0x65
0x65
0x65
0x65
0x65
0x65
Port P1
0x1A91
1
0x50
0x50
0x50
0x50
0x50
0x50
Port P2
0x1A92
1
0x51
0x51
0x51
0x51
0x51
0x51
Delimiter
0x1A93
1
0x00
0x00
0x00
0x00
0x00
0x00
Unused Memory
0x1A94–
0x1AB9
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
7 Device and Documentation Support
7.1
Getting Started and Next Steps
For more information on the MSP430 family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend
for reading the complete device name for any family member.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
97
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz with LCD
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz with LCD
0 = Low-Voltage Series
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
98
Device and Documentation Support
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
7.3
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at Development Kits and Software for
Low-Power MCUs.
Table 7-1 lists the debug features of these MCUs. See the Code Composer Studio for MSP430 User's
Guide for details on the available features.
Table 7-1. Hardware Debug Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
Design Kits and Evaluation Modules
MSP430 40-Pin Target Development Board for MSP430F5x MCUs The MSP-TS430RSB40 is a standalone 40-pin ZIF socket target board that is used to program and debug the MSP430 MCU
in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
MSP430 40-Pin Package Board and USB Programmer The MSP-FET430U40 is a bundle featuring a
standalone 40-pin ZIF socket target board which is used to program and debug the MSP430
MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol and
the MSP-FET Flash Emulation Tool.
Software
MSP430F51x2, MSP430F51x1 Code Examples C Code examples are available for every MSP device
that configures each of the integrated peripherals for various application needs.
MSPWare™ Software MSPWare software is a collection of code examples, data sheets, and other
design resources for all MSP devices delivered in a convenient package. In addition to
providing a complete collection of existing MSP design resources, MSPWare software also
includes a high-level API called MSP Driver Library. This library makes it easy to program
MSP hardware. MSPWare software is available as a component of CCS or as a stand-alone
package.
MSP Driver Library Driver Library's abstracted API keeps you above the bits and bytes of the MSP430
hardware by providing easy-to-use function calls. Thorough documentation is delivered
through a helpful API Guide, which includes details on each function call and the recognized
parameters. Developers can use Driver Library functions to write complete projects with
minimal overhead.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the application’s energy profile and
helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully utilize the unique ultra-low power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp
out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
99
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
IEC60730 Software Package The IEC60730 MSP430 software package was developed to be useful in
assisting customers in complying with IEC 60730-1:2010 (Automatic Electrical Controls for
Household and Similar Use – Part 1: General Requirements) for up to Class B products,
which includes home appliances, arc detectors, power converters, power tools, e-bikes, and
many others. The IEC60730 MSP430 software package can be embedded in customer
applications running on MSP430s to help simplify the customer’s certification efforts of
functional safety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low power and low cost
microcontroller space, TI brings you MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating point math library of scalar functions brings you up to 26x better
performance. Mathlib is easy to integrate into your designs. This library is free and is
integrated in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in
depth look at the math library and relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features. The intuitive IDE provides a single user interface taking you through each step of
the application development flow. Familiar utilities and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a
compelling feature-rich development environment for embedded developers. When using
CCS with an MSP MCU, a unique and powerful set of plugins and embedded software
utilities are made available to fully leverage the MSP microcontroller.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) files directly to
the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU). Creating MCU software usually requires downloading the
resulting binary program to the MSP device for validation and debugging. The MSP-FET
provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the
computer's USB interface and the MSP UART. This affords the MSP programmer a
convenient method for communicating serially between the MSP and a terminal running on
the computer. It also supports loading programs (often called firmware) to the MSP target
using the BSL (bootloader) through the UART and I2C communication protocols.
100
Device and Documentation Support
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
SLAS619P – AUGUST 2010 – REVISED MAY 2016
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an
expansion board, called the Gang Splitter, that implements the interconnections between the
MSP Gang Programmer and multiple target devices. Eight cables are provided that connect
the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The
programming can be done with a PC or as a stand-alone device. A PC-side graphical user
interface is also available and is DLL-based.
7.4
Documentation Support
The following documents describe the MSP430F51x2 and MSP430F51x1 devices. Copies of these
documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for example, MSP430F5172). In the upper right corner, click the "Alert me" button.
This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430F5172 Device Erratasheet Describes the known exceptions to the functional specifications for all
silicon revisions of the device.
MSP430F5152 Device Erratasheet Describes the known exceptions to the functional specifications for all
silicon revisions of the device.
MSP430F5132 Device Erratasheet Describes the known exceptions to the functional specifications for all
silicon revisions of the device.
MSP430F5171 Device Erratasheet Describes the known exceptions to the functional specifications for all
silicon revisions of the device.
MSP430F5151 Device Erratasheet Describes the known exceptions to the functional specifications for all
silicon revisions of the device.
MSP430F5131 Device Erratasheet Describes the known exceptions to the functional specifications for all
silicon revisions of the device.
User's Guides
MSP430x5xx and MSP430x6xx Family User's Guide Detailed
peripherals available in this device family.
information
on
the
modules
and
Code Composer Studio v6.1 for MSP430 User's Guide This manual describes the use of TI Code
Composer Studio IDE v6.1 (CCS v6.1) with the MSP430 ultra-low-power microcontrollers.
This document applies only for the Windows version of the Code Composer Studio IDE. The
Linux version is similar and, therefore, is not described separately.
IAR Embedded Workbench Version 3+ for MSP430 User's Guide This manual describes the use of
IAR Embedded Workbench (EW430) with the MSP430 ultra-low-power microcontrollers.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
101
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
MSP430 Programming With the Bootloader (BSL) The MSP430 bootloader (BSL, formerly known as
the bootstrap loader) allows users to communicate with embedded memory in the MSP430
microcontroller during the prototyping phase, final production, and in service. Both the
programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming Via the JTAG Interface This document describes the functions that are required
to erase, program, and verify the memory module of the MSP430 flash-based and FRAMbased microcontroller families using the JTAG communication port. In addition, it describes
how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
7.5
Related Links
Table 7-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-2. Related Links
102
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F5172
Click here
Click here
Click here
Click here
Click here
MSP430F5152
Click here
Click here
Click here
Click here
Click here
MSP430F5132
Click here
Click here
Click here
Click here
Click here
MSP430F5171
Click here
Click here
Click here
Click here
Click here
MSP430F5151
Click here
Click here
Click here
Click here
Click here
MSP430F5131
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
www.ti.com
7.6
SLAS619P – AUGUST 2010 – REVISED MAY 2016
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.7
Trademarks
MSP430, MSPWare, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of Texas
Instruments.
All other trademarks are the property of their respective owners.
7.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
Copyright © 2010–2016, Texas Instruments Incorporated
103
MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
104
Mechanical, Packaging, and Orderable Information
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5172 MSP430F5152 MSP430F5132 MSP430F5171 MSP430F5151 MSP430F5131
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430F5131IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5131
MSP430F5131IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5131
MSP430F5131IRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5131
MSP430F5131IRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5131
MSP430F5131IYFFR
ACTIVE
DSBGA
YFF
40
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5131
MSP430F5131IYFFT
ACTIVE
DSBGA
YFF
40
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5131
MSP430F5132IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5132
MSP430F5132IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5132
MSP430F5132IRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5132
MSP430F5132IRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5132
MSP430F5132IYFFR
ACTIVE
DSBGA
YFF
40
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5132
MSP430F5132IYFFT
ACTIVE
DSBGA
YFF
40
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5132
MSP430F5151IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5151
MSP430F5151IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5151
MSP430F5151IRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5151
MSP430F5151IRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5151
MSP430F5151IYFFR
ACTIVE
DSBGA
YFF
40
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5151
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Jul-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430F5151IYFFT
ACTIVE
DSBGA
YFF
40
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5151
MSP430F5152IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5152
MSP430F5152IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5152
MSP430F5152IRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5152
MSP430F5152IRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5152
MSP430F5152IYFFR
ACTIVE
DSBGA
YFF
40
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5152
MSP430F5152IYFFT
ACTIVE
DSBGA
YFF
40
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5152
MSP430F5171IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5171
MSP430F5171IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5171
MSP430F5171IRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5171
MSP430F5171IRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5171
MSP430F5171IYFFR
ACTIVE
DSBGA
YFF
40
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5171
MSP430F5171IYFFT
ACTIVE
DSBGA
YFF
40
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5171
MSP430F5172IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5172
MSP430F5172IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430F5172
MSP430F5172IRSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5172
MSP430F5172IRSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430
F5172
MSP430F5172IYFFR
ACTIVE
DSBGA
YFF
40
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430F5172
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Jul-2015
Status
(1)
MSP430F5172IYFFT
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YFF
40
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
M430F5172
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F5131IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430F5131IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5131IRSBT
WQFN
RSB
40
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5131IYFFR
DSBGA
YFF
40
3000
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5131IYFFT
DSBGA
YFF
40
250
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5132IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430F5132IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5132IRSBT
WQFN
RSB
40
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5132IYFFR
DSBGA
YFF
40
3000
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5132IYFFT
DSBGA
YFF
40
250
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5151IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430F5151IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5151IRSBT
WQFN
RSB
40
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5151IYFFR
DSBGA
YFF
40
3000
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5151IYFFT
DSBGA
YFF
40
250
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5152IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430F5152IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5152IRSBT
WQFN
RSB
40
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
MSP430F5152IYFFR
DSBGA
YFF
40
3000
180.0
8.4
MSP430F5152IYFFT
DSBGA
YFF
40
250
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.86
3.16
0.69
4.0
8.0
Q1
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5171IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430F5171IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5171IRSBT
WQFN
RSB
40
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5171IYFFR
DSBGA
YFF
40
3000
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5171IYFFT
DSBGA
YFF
40
250
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5172IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430F5172IRSBR
WQFN
RSB
40
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5172IRSBT
WQFN
RSB
40
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
MSP430F5172IYFFR
DSBGA
YFF
40
3000
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
MSP430F5172IYFFT
DSBGA
YFF
40
250
180.0
8.4
2.86
3.16
0.69
4.0
8.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F5131IDAR
TSSOP
DA
38
2000
367.0
367.0
45.0
MSP430F5131IRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
MSP430F5131IRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
MSP430F5131IYFFR
DSBGA
YFF
40
3000
182.0
182.0
20.0
MSP430F5131IYFFT
DSBGA
YFF
40
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F5132IDAR
TSSOP
DA
38
2000
367.0
367.0
45.0
MSP430F5132IRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
MSP430F5132IRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
MSP430F5132IYFFR
DSBGA
YFF
40
3000
182.0
182.0
20.0
MSP430F5132IYFFT
DSBGA
YFF
40
250
182.0
182.0
20.0
MSP430F5151IDAR
TSSOP
DA
38
2000
367.0
367.0
45.0
MSP430F5151IRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
MSP430F5151IRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
MSP430F5151IYFFR
DSBGA
YFF
40
3000
182.0
182.0
20.0
MSP430F5151IYFFT
DSBGA
YFF
40
250
182.0
182.0
20.0
MSP430F5152IDAR
TSSOP
DA
38
2000
367.0
367.0
45.0
MSP430F5152IRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
MSP430F5152IRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
MSP430F5152IYFFR
DSBGA
YFF
40
3000
182.0
182.0
20.0
MSP430F5152IYFFT
DSBGA
YFF
40
250
182.0
182.0
20.0
MSP430F5171IDAR
TSSOP
DA
38
2000
367.0
367.0
45.0
MSP430F5171IRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
MSP430F5171IRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
MSP430F5171IYFFR
DSBGA
YFF
40
3000
182.0
182.0
20.0
MSP430F5171IYFFT
DSBGA
YFF
40
250
182.0
182.0
20.0
MSP430F5172IDAR
TSSOP
DA
38
2000
367.0
367.0
45.0
MSP430F5172IRSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
MSP430F5172IRSBT
WQFN
RSB
40
250
210.0
185.0
35.0
MSP430F5172IYFFR
DSBGA
YFF
40
3000
182.0
182.0
20.0
MSP430F5172IYFFT
DSBGA
YFF
40
250
182.0
182.0
20.0
Pack Materials-Page 3
D: Max = 3.09 mm, Min = 3.03 mm
E: Max = 2.79 mm, Min = 2.73 mm
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated