LINER LTC4269CDKD-2-TRPBF Ieee 802.3at high power pd and synchronous forward controller with aux support Datasheet

LTC4269-2
IEEE 802.3at High Power PD
and Synchronous Forward
Controller with AUX Support
Description
Features
n
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25.5W IEEE 802.3at Compliant (Type-2) PD
PoE+ 2-Event Classification
IEEE 802.3at High Power Available Indicator
Integrated State-of-the-Art Synchronous Forward
Controller
– Isolated Power Supply Efficiency >94%
Flexible Auxiliary Power Interface
Superior EMI Performance
Robust 100V 0.7Ω (Typ) Integrated Hot Swap™
MOSFET
Integrated Signature Resistor, Programmable Class
Current, UVLO, OVLO and Thermal Protection
Short-Circuit Protection with Auto-Restart
Programmable Switching Frequency from
100kHz to 500kHz
Thermally Enhanced 7mm × 4mm DFN Package
The LTC®4269-2 is an integrated Powered Device (PD)
interface and power supply controller featuring 2-event
classification signaling, flexible auxiliary power options, and a power supply controller suitable for synchronously rectified forward supplies. These features
make the LTC4269-2 ideally suited for an IEEE802.3at
PD application.
The PD controller features a 100V MOSFET that isolates
the power supply during detection and classification, and
provides 100mA inrush current limit. Also included are
power good outputs, an undervoltage/overvoltage lockout and thermal protection. The current mode forward
controller allows for synchronous rectification, resulting
in an extremely high efficiency, green product. Soft-start
for controlled output voltage start-up and fault recovery is
included. Programmable frequency over 100kHz to 500kHz
allows flexibility in efficiency vs size and low EMI.
Applications
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IP Phones with Large Color Screens
Dual Radio 802.11n Access Points
PTZ Security Cameras
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap, ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
Typical Application
PoE-Based Self-Driven Synchronous Forward Power Supply
1mH
•
10µH
+
54V FROM
DATA PAIR
~ +
~ –
54V FROM
SPARE PAIR
~ +
~ –
10µF
2.2µF
33k
237k
+
10µF
30.9Ω
SOUT
OUT
OC
LTC4269-2
COMP
FB
VREF
T2P VNEG PGND GND BLANK DELAY ROSC SS_MAXDC
VCC
1.5k
33k
50mΩ
220µF
82k
332k
158k
158k
4.7nF
2k
11.3k
10nF
22k
1.2k
22.1k
0.1µF
TO
MICROCONTROLLER
5.1Ω
5V
5A
10k
ISENSE
RCLASS
SHDN
VPORTN
+
0.1µF
133Ω
SD_VSEC PWRGD VIN
VPORTP
•
4.7nF
VCC
10.0k
0.1µF
6.8µH
•
0.22µF
TLV431
3.65k
42692 TA01
42692fb
LTC4269-2
Absolute Maximum Ratings
(Notes 1, 2)
Pins with Respect to VPORTN
VPORTP Voltage......................................... –0.3V to 100V
VNEG Voltage.......................................... –0.3V to VPORTP
VNEG Pull-Up Current...................................................1A
SHDN........................................................ –0.3V to 100V
RCLASS, Voltage............................................ –0.3V to 7V
RCLASS Source Current...........................................50mA
PWRGD Voltage (Note 3)
Low Impedance Source..... VNEG – 0.3V to VNEG + 11V
Sink Current..........................................................5mA
PWRGD, T2P Voltage................................ –0.3V to 100V
PWRGD, T2P Sink Current......................................10mA
Pin Configuration
TOP VIEW
SHDN 1
T2P 2
RCLASS 3
NC 4
VPORTN 5
VPORTN 6
NC 7
NC 8
COMP 9
FB 10
ROSC 11
SYNC 12
SS_MAXDC 13
VREF 14
SD_VSEC 15
GND 16
Pins with Respect to GND
VIN (Note 4)................................................. –0.3V to 25V
SYNC, SS_MAXDC, SD_VSEC,
ISENSE, OC..................................................... –0.3V to 6V
COMP, BLANK, DELAY............................... –0.3V to 3.5V
FB ................................................................. –0.3V to 3V
ROSC Current......................................................... –50µA
VREF Source Current...............................................10mA
33
32 VPORTP
31 NC
30 NC
29 PWRGD
28 PWRGD
27 VNEG
26 VNEG
25 NC
24 SOUT
23 VIN
22 OUT
21 PGND
20 DELAY
19 OC
18 ISENSE
17 BLANK
DKD PACKAGE
32-LEAD (7mm s 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 2°C/W
EXPOSED PAD (PIN 33) MUST BE SOLDERED TO
HEAT SINKING PLANE THAT IS CONNECTED TO GND
Operating Ambient Temperature Range
LTC4269C-2.............................................. 0°C to 70°C
LTC4269I-2...........................................–40°C to 85°C
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4269CDKD-2#PBF
LTC4269CDKD-2#TRPBF
42692
32-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC4269IDKD-2#PBF
LTC4269IDKD-2#TRPBF
42692
32-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4269CDKD-2
LTC4269CDKD-2#TR
42692
32-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC4269IDKD-2
LTC4269IDKD-2#TR
42692
32-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
42692fb
LTC4269-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
60
9.8
21.0
37.2
V
V
V
V
V
V
Interface Controller (Note 5)
Operating Input Voltage
Signature Range
Classification Range
On Voltage
Undervoltage Lockout
Overvoltage Lockout
At VPORTP (Note 6)
l
l
l
l
1.5
12.5
30.0
ON/UVLO Hysteresis Window
l
Signature/Class Hysteresis Window
l
1.4
State Machine Reset for 2-Event Classification
l
2.57
Supply Current at 57V
Measured at VPORTP Pin
Class O Current
71.0
4.1
V
V
5.40
V
l
1.35
mA
VPORTP = 17.5V, No RCLASS Resistor
l
0.40
mA
Signature Resistance
1.5V ≤ VPORTP ≤ 9.8V (Note 7)
l
26.00
kΩ
Invalid Signature Resistance, SHDN Invoked
1.5V ≤ VPORTP ≤ 9.8V, VSHDN = 3V (Note 7)
l
11
kΩ
Invalid Signature Resistance During Mark Event
(Notes 7, 8)
l
11
kΩ
Class Accuracy
10mA < ICLASS < 40mA, 12.5V < VPORTP < 21V
(Notes 9, 10)
l
±3.5
%
Classification Stability Time
VPORTP Pin Step to 17.5V, RCLASS = 30.9Ω,
ICLASS within 3.5% of Ideal Value (Notes 9, 10)
l
1
ms
Inrush Current
VPORTP = 54V, VNEG = 3V
l
100
180
mA
Power FET On-Resistance
Tested at 600mA into VNEG, VPORTP = 54V
l
0.7
1.0
Ω
Power FET Leakage Current at VNEG
VPORTP = SHDN = VNEG = 57V
l
1
µA
Reset Threshold
Supply Current
Signature
23.25
Classification
Normal Operation
60
Digital Interface
SHDN Input High Level Voltage
l
SHDN Input Low Level Voltage
l
3
V
0.45
100
V
SHDN Input Resistance
VPORTP = 9.8V, SHDN = 9.65V
l
kΩ
PWRGD, T2P Output Low Voltage
Tested at 1mA, VPORTP = 57V, For T2P, Must
Complete 2-Event Classification to See Active Low
l
0.15
V
PWRGD, T2P Leakage Current
Pin Voltage Pulled 57V, VPORTP = VPORTN = 0V
l
1
µA
PWRGDP Output Low Voltage
Tested at 0.5mA, VPORTP = 52V, VNEG = 4V, Output
Voltage is with Respect to VNEG
l
0.4
V
PWRGDP Clamp Voltage
Tested at 2mA, VNEG = 0V, Voltage is with Respect
to VNEG
l
16.5
V
PWRGDP Leakage Current
VPWRGD = 11V, VNEG = 0V, Voltage is with Respect
to VNEG
l
1
µA
Operational Input Voltage
IVREF = 0µA
l
VIN Quiescent Current
IVREF = 0µA, ISENSE = OC = Open
VIN Start-Up Current
FB = 0V, SS_MAXDC = 0V (Notes 12, 13)
VIN Shutdown Current
SD_VSEC = 0V (Notes 12, 13)
SD_VSEC Threshold
10V < SD < 25V
12.0
PWM Controller (Note 11)
VIN(OFF)
25
V
5.2
6.5
mA
l
460
700
µA
l
240
350
µA
1.32
1.379
V
1.261
42692fb
LTC4269-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
SD_VSEC(ON) Current
SD_VSEC = SD_VSEC Threshold +100mV
SD_VSEC(OFF) Current
SD_VSEC = SD_VSEC Threshold – 100mV
MIN
TYP
MAX
0
8.3
UNITS
µA
10
11.7
µA
VIN(ON)
l
14.25
15.75
V
VIN(OFF)
l
8.75
9.25
V
VIN(HYST)
l
3.75
5.5
7.0
V
l
2.425
2.5
2.575
V
VREF
Output Voltage
IVREF = 0
Line Regulation
IVREF = 0, 10V < VIN < 25V
1
10
mV
Load Regulation
0mA < IVREF < 2.5mA
1
10
mV
Oscillator
Frequency, fOSC
ROSC = 178k, FB = 1V, SS_MAXDC = 1.84V
165
200
240
kHz
fOSC(MIN)
ROSC = 365k, FB = 1V
80
100
120
kHz
fOSC(MAX)
ROSC = 64.9k, COMP = 2.5V, SD_VSEC = 2.64V
440
500
560
kHz
l
SYNC Input Resistance
SYNC Switching Threshold
18
FB = 1V
1.5
kΩ
2.2
SYNC Frequency/fOSC
FB = 1V (Note 14)
1.25
1.5
fOSC Line Regulation
ROSC = 178k; 10V < VIN < 25V, SS_MAXDC = 1.84V
0.05
0.33
VROSC
ROSC Pin Voltage
1
V
%/V
V
Error Amplifier
FB Reference Voltage
10V < VIN < 25V, VOL + 0.2V < COMP < VOH – 0.2
FB Input Bias Current
FB = FB Reference Voltage
Open-Loop Voltage Gain
VOL + 0.2V < COMP < VOH – 0.2
Unity-Gain Bandwidth
(Note 15)
COMP Source Current
FB = 1V, COMP = 1.6V
COMP Sink Current
COMP = 1.6V
COMP Current (Disabled)
FB = VREF , COMP = 1.6V
18
23
COMP High Level VOH
FB = 1V, ICOMP = –250µA
2.7
3.2
V
COMP Active Threshold
FB = 1V, SOUT Duty Cycle > 0%
0.7
0.8
V
COMP Low Level VOL
ICOMP = 250µA
l
1.201
65
1.226
1.250
-75
-200
V
nA
85
dB
3
MHz
–4
–9
mA
4
10
mA
28
µA
0.15
0.4
V
220
243
mV
Current Sense
ISENSE Maximum Threshold
COMP = 2.5V, FB =1V
197
ISENSE Input Current (Duty Cycle = 0%)
COMP = 2.5V, FB = 1V (Note 12)
–8
µA
ISENSE Input Current (Duty Cycle = 80%)
COMP = 2.5V, FB = 1V (Note 12)
–35
µA
OC Threshold
COMP = 2.5V, FB = 1V
107
116
mV
OC Input Current
(OC = 100mV)
–50
–100
nA
Default Blanking Time
COMP = 2.5V, FB = 1V, RBLANK = 40k (Note 16)
180
ns
Adjustable Blanking Time
COMP = 2.5V, FB = 1V, RBLANK = 120k
540
ns
1
V
98
VBLANK
SOUT Driver
SOUT Clamp Voltage
IGATE = 0µA, COMP = 2.5V, FB = 1V
SOUT Low Level
IGATE = 25mA
10.54
12
13.5
V
0.5
0.75
V
42692fb
LTC4269-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
SOUT High Level
IGATE = –25mA, VIN = 12V COMP = 2.5V, FB = 1V
MIN
10
V
SOUT Active Pull-Off in Shutdown
VIN = 5V, SD_VSEC = 0V, SOUT = 1V
1
mA
SOUT to OUT (Rise) DELAY (tDELAY)
COMP = 2.5V, FB = 1V (Note 16)
RDELAY = 120k
VDELAY
TYP
MAX
UNITS
40
120
ns
ns
0.9
V
OUT Driver
OUT Rise Time
FB = 1V, CL = 1nF (Notes 15, 16)
50
ns
OUT Fall Time
FB = 1V, CL = 1nF (Notes 15, 16)
30
ns
OUT Clamp Voltage
IGATE = 0µA, COMP = 2.5V, FB = 1V
OUT Low Level
IGATE = 20mA
IGATE = 200mA
OUT High Level
IGATE = –20mA, VIN = 12V COMP = 2.5V, FB = 1V
IGATE = –200mA, VIN = 12V COMP = 2.5V, FB = 1V
OUT Active Pull-Off in Shutdown
VIN = 5V, SD_VSEC = 0V, OUT = 1V
20
OUT Max Duty Cycle
COMP = 2.5V, FB = 1V, RDELAY = 10k (fOSC = 200kHz),
VIN = 10V, SD_VSEC = 1.4V, SS_MAXDC = VREF
83
90
OUT Max Duty Cycle Clamp
COMP = 2.5V, FB = 1V, RDELAY = 10k (fOSC = 200kHz),
VIN = 10V
SD_VSEC = 1.32V, SS_MAXDC = 1.84V
SD_VSEC = 2.64V, SS_MAXDC = 1.84V
63.5
25
72
33
11.5
13
14.5
V
0.45
1.25
0.75
1.8
V
V
9.9
9.75
V
V
mA
%
80.5
41
%
%
Soft-Start
SS_MAXDC Low Level: VOL
ISS_MAXDC = 150µA, OC = 1V
0.2
V
SS_MAXDC Soft-Start Reset Threshold
Measured on SS_MAXDC
0.45
V
SS_MAXDC Active Threshold
FB + 1V, DC > 0%
0.8
V
SS_MAXDC Input Current
(Soft-Start Pull-Down: IDIS)
SS_MAXDC = 1V, SD_VSEC = 1.4V, OC = 1V
800
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: PWRGD voltage clamps at 14V with respect to VNEG.
Note 4: In applications where the VIN pin is supplied via an external RC
network from a system VIN > 25V, an external Zener with clamp voltage
VIN ON(MAX) < VZ < 25V should be connected from the VIN pin to GND.
Note 5: All voltages are with respect to VPORTN pin unless otherwise noted.
Note 6: Input voltage specifications are defined with respect to LTC4269-2
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 7: Signature resistance is measured via the ∆V/∆I method with the
minimum ∆V of 1V. The LTC4269-2 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 8: An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See the Applications Information section.
Note 9: Class accuracy is respect to the ideal current defined as
1.237/RCLASS and does not include variations in RCLASS resistance.
Note 10: This parameter is assured by design and wafer level testing.
Note 11: Voltages are with respect to GND unless otherwise specified.
Tested with COMP open, VFB = 1.4V, RROSC = 178k, VSYNC = 0V, VSS(MAXDC)
set to VREF (but electrically isolated), CVREF = 0.1µF, VSD_VSEC = 2V, RBLANK
= 121k, RDELAY = 121k, VISENSE = 0V, VOC = 0V, COUT = 1nF, VIN = 15V,
SOUT open, unless otherwise specified.
Note 12: Guaranteed by correlation to static test.
Note 13: VIN start-up current is measured at VIN = VIN(ON) – 0.25V and
scaled by × 1.18 (to correlate to worst-case VIN start-up current at VIN(ON).
Note 14: Maximum recommended SYNC frequency = 500kHz.
Note 15: Guaranteed but not tested.
Note 16: Timing for R = 40k derived from measurement with R = 240k.
42692fb
LTC4269-2
Typical Performance Characteristics
Input Current vs Input Voltage
25k Detection Range
TA = 25°C
VPORTP CURRENT (mA)
VPORTP CURRENT (mA)
0.3
0.2
10.5
CLASS 3
20
CLASS 2
10
0
0
4
6
VPORTP VOLTAGE (V)
8
10
CLASS 0
0
50
20
30
40
10
VPORTP VOLTAGE RISING (V)
9.5
60
Class Operation vs Time
1.0
25
CLASS
CURRENT
10mA/DIV
24
IEEE LOWER LIMIT
TIME (10µs/DIV)
9
10
0.2
–50
42692 G05
Active High PWRGD Output Low
Voltage vs Current
1.0
FB Voltage vs Temperature
TA = 25°C
VPORTP – VNEG = 4V
1.24
0.2
FB VOLTAGE (V)
PWRGD (V)
0.4
0.6
0.4
10
42692 G07
0
1.23
1.22
1.21
0.2
8
100
1.25
0.8
6
4
CURRENT (mA)
0
25
50
75
–25
JUNCTION TEMPERATURE (°C)
42692 G06
0.6
2
0.6
42692 G04
TA = 25°C
0
0.8
0.4
23
PWRGD, T2P Output Low Voltage
vs Current
VPWRGD – VPORTN (V)
VT2P – VPORTN (V)
TA = 25°C
LTC4269-2 + 2 DIODES
0
22
On-Resistance vs Temperature
RESISTANCE (Ω)
SIGNATURE RESISTANCE (kΩ)
VPORTP
INPUT
VOLTAGE
10V/DIV
26
0.8
20
18
16
VPORTP VOLTAGE (V)
1.2
RESISTANCE = $V = V2 – V1
$I I2 – I1
27 DIODES: HD01
TA = 25°C
IEEE UPPER LIMIT
7
5
8
6
VPORTP VOLTAGE (V)
14
12
42692 G03
28
3
4
–40°C
42692 G02
Signature Resistance
vs Input Voltage
22
V1: 1
V2: 2
85°C
10.0
CLASS 1
42692 G01
LTC4269-2 ONLY
CLASS 1 OPERATION
CLASS 4
30
0.1
2
11.0
TA = 25°C
40
0.4
0
Input Current vs Input Voltage
Input Current vs Input Voltage
50
VPORTP CURRENT (mA)
0.5
0
0.5
1
1.5
CURRENT (mA)
2
42692 G08
1.20
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
42692 G09
42692fb
LTC4269-2
Typical Performance Characteristics
Switching Frequency
vs Temperature
VIN Shutdown Current
vs Temperature
500
215
200
185
170
400
350
300
250
200
150
50
25
0
75
TEMPERATURE (°C)
–25
100
–25
50
25
0
75
TEMPERATURE (°C)
42692 G10
300
100
200
–50
125
5.0
4.5
4.0
100
1.32
1.27
–25
50
25
0
75
TEMPERATURE (°C)
100
10
5
0
–50
125
1.6
12.5
RISENSE = 0k
COMP SOURCE CURRENT (mA)
VIN TURN ON VOLTAGE
1.2
COMP (V)
14
1.0
0.8
0.6
0.4
8
–25
50
25
0
75
TEMPERATURE (°C)
100
125
COMP Source Current
vs Temperature
1.4
VIN TURN OFF VOLTAGE
0mA PIN CURRENT AFTER
PART TURN ON
42692 G15
COMP Active Threshold
vs Temperature
18
125
PIN CURRENT BEFORE
PART TURN ON
42692 G14
VIN Turn On/Off Voltage
vs Temperature
10
100
SD_VSEC Pin Current
vs Temperature
1.37
1.22
–50
125
12
50
25
0
75
TEMPERATURE (°C)
15
42692 G13
16
–25
42692 G12
SD_VSEC PIN CURRENT (µA)
SD_VSEC TURN ON THRESHOLD (V)
IQ (mA)
5.5
6
–50
350
1.42
6.0
50
25
0
75
TEMPERATURE (°C)
400
SD_VSEC Turn On Threshold
vs Temperature
OC = OPEN
–25
450
42692 G11
IQ (VIN) vs Temperature
3.5
–50
500
250
100
–50
125
SD_VSEC = 1.4V
550
VIN STARTUP CURRENT (µA)
230
155
–50
VIN (V)
600
VIN = 15V
450 SD_VSEC = 0V
VIN SHUTDOWN CURRENT (µA)
SWITCHING FREQUENCY (kHz)
245
6.5
VIN Start-Up Current
vs Temperature
FB = 1V
COMP = 1.6V
10.0
7.5
CURRENT OUT OF PIN
0.2
–25
50
25
0
75
TEMPERATURE (°C)
100
125
42692 G16
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
42692 G17
5.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
42692 G18
42692fb
LTC4269-2
Typical Performance Characteristics
COMP Sink Current
vs Temperature
50
10.0
7.5
5.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
240
FB = VREF
COMP = 1.6V
40
30
20
10
0
–50
125
–25
50
0
75
25
TEMPERATURE (°C)
ISENSE PIN CURRENT (µA)
ISENSE MAX THRESHOLD (mV)
40
230
220
210
50
25
0
75
TEMPERATURE (°C)
100
20
10
0
100
125
42692 G25
RSLOPE = 0Ω
RSLOPE = 470Ω
185
TA = 25°C
COMP = 2.5V
0
RSLOPE = 1k
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
42692 G24
400
200
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
BLANK Duration vs RBLANK
TA = 25°C
800
RBLANK = 120k
600
3.0
2.5
195
1000
600
400
200
RBLANK = 40k
50
25
0
75
TEMPERATURE (°C)
2.0
1.5
COMP (V)
205
175
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
BLANK (ns)
BLANK DURATION (ns)
OC THRESHOLD (mV)
90
1.0
0.5
215
Blank Duration vs Temperature
100
0
42692 G21
800
PRECISION OVERCURRENT THRESHOLD
INDEPENDENT OF DUTY CYCLE
–25
40
42692 G23
OC (Overcurrent) Threshold
vs Temperature
80
–50
80
225
30
0
125
110
OC THRESHOLD
ISENSE Maximum Threshold
vs Duty Cycle (Programming
Slope Compensation)
TA = 25°C
42692 G22
120
120
ISENSE Pin Current (Out of Pin)
vs Duty Cycle
COMP = 2.5V
RISENSE = 0k
–25
160
0
125
ISENSE MAX THRESHOLD (mV)
ISENSE Maximum Threshold
vs Temperature
200
–50
100
200
TA = 25°C
RISENSE = 0k
42692 G20
42692 G19
240
ISENSE Maximum Threshold
vs COMP
ISENSE MAX THRESHOLD (mV)
FB = 1.4V
COMP = 1.6V
COMP PIN CURRENT (µA)
COMP SINK CURRENT (mA)
12.5
(Disabled) COMP Pin Current
vs Temperature
100
125
42692 G26
0
0
20
40
60 80 100 120 140 160
RBLANK (k)
42692 G27
42692fb
LTC4269-2
Typical Performance Characteristics
tDELAY: SOUT Rise to OUT Rise
vs Temperature
240
200
tDELAY: SOUT Rise to OUT Rise
vs RDELAY
OUT Rise/Fall Time vs OUT Load
Capacitance
125
TA = 25°C
160
tDELAY (ns)
RDELAY = 120k
tDELAY (ns)
OUT RISE/FALL TIME (ns)
150
100
80
50
TA = 25°C
100
tr
75
tf
50
25
RDELAY = 40k
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
0
125
0
40
80
160
RDELAY (k)
TA = 25°C
SS_MAXDC = 2.5V
SD_VSEC = 1.4V
200
300
fOSC (kHz)
400
OUT : Max Duty Cycle CLAMP
vs SD_VSEC
60
50
40
30
10
TA = 25°C
SS_MAXDC = 1.84V
fOSC = 200kHz
RDELAY = 10k
0
1.32
500
1.65
1.98
SD_VSEC (V)
2.64
2.31
42692 G31
TA = 25°C
fOSC = 200kHz
80 R
DELAY = 10k
SD_VSEC = 1.32V
70
60
50
SD_VSEC = 1.98V
40
SD_VSEC = 2.64V
30
20
1.60
1.84
SS_MAXDC (V)
2.08
42692 G33
42692 G32
SS_MAXDC Setting vs fOSC
(for OUT DC = 72%)
SS_MAXDC Reset and Active
Thresholds vs Temperature
2.32
1.2
TA = 25°C
SD_VSEC = 1.32V
2.20 RDELAY = 10k
1.0
2.08
1.96
1.84
1.72
1.60
100
90
70
20
5000
OUT : Max Duty Cycle CLAMP
vs SS_MAXDC
80
SS_MAXDC (mV)
70
100
2000
1000
3000
4000
OUT LOAD CAPACITANCE (pF)
42692 G30
OUT MAX DUTY CYCLE CLAMP (%)
OUT MAX DUTY CYCLE CLAMP (%)
90
80
SS_MAXDC (V)
OUT DUTY CYCLE (%)
OUT : Max Duty Cycle vs fOSC
90
0
42692 G29
42692 G28
100
0
240
200
120
ACTIVE THRESHOLD
0.8
0.6
0.4
RESET THRESHOLD
0.2
200
300
fOSC (kHz)
400
500
42692 G34
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
42692 G35
42692fb
LTC4269-2
Pin Functions
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4269-2
operation and corrupt the signature resistance. If unused,
tie SHDN to VPORTN.
SYNC (Pin 12): Used to synchronize the internal oscillator
to an external signal. It is directly logic compatible and
can be driven with any signal between 10% and 90% duty
cycle. If unused, the pin should be connected to GND.
T2P (Pin 2): Type-2 PSE Indicator, Open-Drain. Low
impedance indicates the presence of a Type-2 PSE.
SS_MAXDC (Pin 13): The external resistor divider from
VREF sets the maximum duty cycle clamp (SS_MAXDC =
1.84V, SD_VSEC = 1.32V gives 72% duty cycle). Capacitor
on SS_MAXDC pin in combination with external resistor
divider sets soft-start timing.
RCLASS (Pin 3): Class Select Input. Connect a resistor
between RCLASS and VPORTN to set the classification load
current.
VPORTN (Pins 5, 6): Power Input. Tie to the PD input through
the diode bridge. Pins 5 and 6 must be electrically tied
together at the package.
NC (Pins 4, 7, 8, 25, 30, 31): No Connect.
COMP (Pin 9): Output Pin of the Error Amplifier. The error
amplifier is an op amp, allowing various compensation
networks to be connected between the COMP pin and
FB pin for optimum transient response in a nonisolated
supply. The voltage on this pin corresponds to the peak
current of the external FET. Full operating voltage range is
between 0.8V and 2.5V corresponding to 0mV to 220mV
at the ISENSE pin. For applications using the 100mV OC
pin for overcurrent detection, typical operating range for
the COMP pin is 0.8V to 1.6V. For isolated applications
where COMP is controlled by an opto-coupler, the COMP
pin output drive can be disabled with FB = VREF , reducing
the COMP pin current to (COMP – 0.7)/40k.
FB (Pin 10): In a nonisolated supply, FB monitors the output
voltage via an external resistor divider and is compared
with an internal 1.23V reference by the error amplifier. FB
connected to VREF disables error amplifier output.
ROSC (Pin11): A resistor to GND programs the operating
frequency of the IC between 100kHz and 500kHz. Nominal
voltage on the ROSC pin is 1.0V.
VREF (Pin 14): The output of an internal 2.5V reference
which supplies internal control circuitry. Capable of sourcing up to 2.5mA drive for external use. Bypass to GND
with a 0.1µF ceramic capacitor.
SD_VSEC (Pin 15): The SD_VSEC pin, when pulled below
its accurate 1.32V threshold, is used to turn off the IC and
reduce current drain from VIN. The SD_VSEC pin is connected to system input voltage through a resistor divider to
define undervoltage lockout (UVLO) for the power supply
and to provide a volt-second clamp on the OUT pin. An
11µA pin current hysteresis allows external programming
of UVLO hysteresis.
GND (Pin 16): Analog Ground. Tie to VNEG.
BLANK (Pin 17): A resistor to GND adjusts the extended
blanking period of the overcurrent and current sense
amplifier outputs during FET turn-on—to prevent false
current limit trip. Increasing the resistor value increases
the blanking period.
ISENSE (Pin 18): The Current Sense Input for the Control
Loop. Connect this pin to the sense resistor in the source
of the external power MOSFET. A resistor in series with
the ISENSE pin programs slope compensation.
42692fb
10
LTC4269-2
Pin Functions
OC (Pin 19): OC is an accurate 107mV threshold, independent of duty cycle, for overcurrent detection and trigger of
soft-start. Connect this pin directly to the sense resistor
in the source of the external power MOSFET.
VNEG (Pins 26, 27): Power Output. Connects the PoE
return line to the power supply through the internal Hot
Swap power MOSFET. Pins 26 and 27 must be electrically
tied together at the package.
DELAY (Pin 20): A resistor to GND adjusts the delay period
between SOUT rising edge and OUT rising edge. Used to
maximize efficiency in forward converter applications by
adjusting the timing. Increasing the resistor value increases
the delay period.
PWRGD (Pin 28): Active High Power Good Output, Open
Collector. Signals that the internal Hot Swap MOSFET is
on. High Impedance indicates power is good. PWRGD is
referenced to VNEG and is low impedance during inrush
and in the event of thermal overload. PWRGD is clamped
14V above VNEG.
PGND (Pin 21): Power Ground. Carries the gate driver’s
return current. Tie to VNEG.
OUT (Pin 22): Drives the gate of an N-channel MOSFET
between 0V and VIN with a maximum limit of 13V on
OUT pin set by an internal clamp. Active pull-off exists in
shutdown (see electrical specification).
VIN (Pin 23): Input Supply for the Power Supply Controller. It
must be closely decoupled to GND. An internal undervoltage
lockout threshold exists for VIN at approximately 14.25V
on and 8.75V off.
PWRGD (Pin 29): Active Low Power Good Output, Open
Drain. Signals that the internal Hot Swap MOSFET is
on. Low Impedance indicates power is good. PWRGD
is referenced to VPORTN and is high impedance during
inrush and in the event of thermal overload. PWRGD has
no internal clamps.
VPORTP (Pin 32): Input Voltage Positive Rail. This pin is
connected to the PD’s positive rail.
Exposed Pad (Pin 33): Tie to GND and PCB heat sink.
SOUT (Pin 24): Switched Output in Phase with OUT Pin.
Provides sync signal for control of secondary-side FETs
in forward converter applications requiring highly efficient
synchronous rectification. SOUT is actively clamped to
12V. Active pull-off exists in shutdown (see electrical
specification). Can also be used to drive the active clamp
FET of an active clamp forward supply.
42692fb
11
LTC4269-2
Block DiagramS
SHDN 1
+
REF
32 VPORTP
CLASSIFICATION
CURRENT LOAD
T2P 2
–
EN
25k
16k
RCLASS 3
29 PWRGD
CONTROL
CIRCUITS
28 PWRGD
27 VNEG
VPORTN 5
26 VNEG
BOLD LINE INDICATES
HIGH CURRENT PATH
VPORTN 6
42692 BD1
VIN
VREF
SS_MAXDC
23
14
13
START-UP
INPUT CURRENT (ISTART)
VINON
VINOFF
–
0.45V
+
2.5V
+
VREF
>90%
SOFT-START CONTROL
–
R
SOURCE
2.5mA
Q
–
S
+
p50mA
1.23V
–
IHYST
10µA SD_VSEC = 1.32V
0µA SD_VSEC > 1.32V
–
ADAPTIVE
MAXIMUM
DUTY CYCLE
CLAMP
24 SOUT
12V
+
+
(TYPICAL 200kHz)
SD_VSEC 15
OSC
1.32V
ROSC 11
(100 TO 500)kHz
S
(LINEAR)
SLOPE COMP
8µA 0% DC
35µA 80% DC
RAMP
Q
ON
DELAY
DRIVER
p1A
R
21 PGND
SYNC 12
1.23V
+
BLANK
(VOLTAGE)
ERROR AMPLIFIER
SENSE
–CURRENT+
0mV TO 220mV
EXPOSED PAD 33
10
9
16
FB
COMP
GND
13V
OVER
–CURRENT+
–
22 OUT
107mV
20
17
DELAY BLANK
19 OC
18 ISENSE
42692 BD2
42692fb
12
LTC4269-2
Applications Information
OVERVIEW
50
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
VPORTP (V)
40
ON
CLASSIFICATION
DETECTION V2
DETECTION V1
VPORTP – VNEG (V)
50
dV = INRUSH
dt
C1
40
30
UVLO
ON
20
UVLO
T = RLOAD C1
10
TIME
VPORTP – PWRGD (V)
–10
POWER
BAD
–20
POWER
GOOD
PWRGD
TRACKS
VPORTP
–30
–40
PWRGD – VNEG (V)
–50
POWER
BAD
PWRGD
TRACKS
VPORTP
PWRGD TRACKS
VPORTN
20
POWER
BAD
10
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
PD CURRENT
INRUSH
LOAD, ILOAD
CLASSIFICATION
ICLASS
TIME
DETECTION I2
DETECTION I1
I1 =
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I2 =
25kΩ
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
INRUSH = 100mA
ILOAD =
VPORTP
RLOAD
LTC4269-2
IIN
The LTC4269-2 has several modes of operation depending on the input voltage applied between the VPORTP and
VPORTN pins. Figure 1 presents an illustration of voltage
TIME
TIME
The IEEE 802.3at standard also establishes a new method
of acquiring power classification from a PD and communicating the presence of a Type 2 PSE. A Type 2 PSE has the
option of acquiring PD power classification by performing
2-event classification (Layer 1) or by communicating with
the PD over the data line (Layer 2). In turn, a Type 2 PD
must be able to recognize both layers of communications
and identify a Type 2 PSE.
MODES OF OPERATION
UVLO
20
10
The IEE802.3at standard establishes a higher power
allocation for Power over Ethernet while maintaining
backwards compatibility with the existing IEEE 802.3af
systems. Power Sourcing Equipment (PSE) and Powered
Devices are distinguished as Type 1 complying with the
IEEE 802.3af power levels, or Type 2 complying with the
IEEE 802.3at power levels. The maximum available power
of a Type 2 PD is 25.5W.
The LTC4269-2 is specifically designed to support a PD
that must operate under the IEEE 802.3at standard. In
particular, the LTC4269-2 provides the T2P indicator bit
which recognizes 2-event classification. This indicator
bit may be used to alert the LTC4269-2 output load that
a Type 2 PSE is present. With an internal signature resistor, classification circuitry, inrush control, and thermal
shutdown, the LTC4269-2 is a complete PD interface
solution capable of supporting in the next generation PD
applications. In addition to the PD front end, the LTC4269-2
also incorporates a high efficiency synchronous forward
controller that minimizes component sizes while maximizing output power.
30
PSE
RLOAD
RCLASS VPORTP
PWRGD
RCLASS
C1
PWRGD
VPORTN
VNEG
42692 F01
Figure 1. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
42692fb
13
LTC4269-2
Applications Information
and current waveforms the LTC4269-2 may encounter with
the various modes of operation summarized in Table 1.
voltage ranges. Note that the Electrical Specifications are
referenced with respect to the LTC4269-2 package pins.
Table 1. LTC4269-2 Modes of Operation as a Function
of Input Voltage
DETECTION
VPORTP – VPORTN (V) LTC4269-2 MODES OF OPERATION
0V to 1.4V
Inactive (Reset after 1st Classification Event)
1.5V to 9.8V
25k Signature Resistor Detection Before 1st
Classification Event
(Mark, 11k Signature Corrupt After 1st
Classification Event)
(5.4V to 9.8V)
During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltages V1 and V2 and the corresponding PD current. The
PSE calculates the signature resistance using the ∆V/∆I
measurement technique.
12.5V to On/UVLO
Classification Load Current Active
On/UVLO to 60V
Inrush and Power Applied to PD Load
>71V
Overvoltage Lockout, Classification and Hot Swap
are Disabled.
On/UVLO includes hysteresis. Rising input threshold: 37.2V max.
Falling input threshold: 30.0V min.
These modes satisfy the requirements defined in the
IEEE 802.3af/at specification.
INPUT DIODE BRIDGE
In the IEEE 802.3af/at standard, the modes of operation
reference the input voltage at the PD’s RJ45 connector.
Since the PD must handle power received in either polarity
from either the data or the spare pair, input diode bridges
BR1 and BR2 are connected between the RJ45 connector
and the LTC4269-2 (Figure 2).
The input diode bridge introduces a voltage drop that affects the range for each mode of operation. The LTC4269-2
compensates for these voltage drops so that a PD built
with the LTC4269-2 meets the IEEE 802.3af/at-established
RJ45
1
2
3
POWERED
DEVICE (PD)
INPUT
6
4
TX+
8
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4269-2 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/at specifications, and
alerts the PSE not to apply power. Invoking the SHDN pin
T1
BR1
TX–
RX+
TO PHY
RX–
VPORTP
SPARE+
5
7
The LTC4269-2 presents its precision, temperature-compensated 25k resistor between the VPORTP and VPORTN
pins, alerting the PSE that a PD is present and requests
power to be applied. The LTC4269-2 signature resistor
also compensates for the additional series resistance
introduced by the input diode bridge. Thus a PD built with
the LTC4269-2 conforms to the IEEE 802.3af/at detection
specifications.
BR2
0.1µF
100V
D3
LTC4269-2
VPORTN
SPARE–
42692 F02
Figure 2. PD Front End Using Diode Bridge on Main and Spare Inputs
42692fb
14
LTC4269-2
Applications Information
LTC4269-2
TO
PSE
Layer 2 communications takes place directly between the
PSE and the PD, the LTC4269-2 concerns itself only with
recognizing 2-event classification.
VPORTP
14k
25k SIGNATURE
RESISTOR
SHDN
VPORTN
42692 F03
In 2-event classification, a Type 2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
SIGNATURE DISABLE
50
Figure 3. 25k Signature Resistor with Disable
Table 2. Summary of Power Classifications and LTC4269-2
RCLASS Resistor Selection
USAGE
Type 1
Type 1
Type 1
Type 1
Type 2
LTC4269‑2
RCLASS
RESISTOR
(Ω, 1%)
Open
124
69.8
45.3
30.9
2ND MARK
1ST MARK
PD CURRENT
LOAD, ILOAD
1ST CLASS
2ND CLASS
40mA
TIME
DETECTION I1
DETECTION I2
50
40
30
2ND MARK
1ST MARK
dV = INRUSH
dt
C1
UVLO
ON
20
UVLO
T = RLOAD C1
10
TIME
TIME
–10
–20
–30
–40
TRACKS
VPORTN
–50
INRUSH = 100mA RCLASS = 30.9Ω
V
ILOAD = PORTP
RLOAD
LTC4269-2
2-EVENT CLASSIFICATION AND THE T2P PIN
A Type 2 PSE may declare the availability of high power by
performing a 2-event classification (Layer 1) or by communicating over the high speed data line (Layer 2). A Type
2 PD must recognize both layers of communication. Since
UVLO
INRUSH
VPORTP – VNEG (V)
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4269-2 asserts a load current representing the
PD power classification. The classification load current
is programmed with a resistor RCLASS that is chosen
from Table 2.
ON
20
10
VPORTP – T2P (V)
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power classification. Class 0 is included in the IEEE specification for
PDs that don’t support classification. Class 1-3 partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE 802.3at (see Table 2).
CLASS
0
1
2
3
4
1ST CLASS
2ND CLASS
30
DETECTION V1
DETECTION V2
CLASSIFICATION
MAXIMUM
NOMINAL
POWER LEVELS CLASSIFICATION
AT INPUT OF PD LOAD CURRENT
(W)
(mA)
0.44 to 12.95
<0.4
0.44 to 3.84
10.5
3.84 to 6.49
18.5
6.49 to 12.95
28
12.95 to 25.5
40
VPORTP (V)
also ceases operation for classification and turns off the
internal Hot Swap FET. If this feature is not used, connect
SHDN to VPORTN.
40
IIN
PSE
RCLASS VPORTP
RCLASS
RLOAD
C1
T2P
VPORTN
VNEG
42692 F04
Figure 4. VNEG, T2P and PD Current as a
Result of 2-Event Classification
42692fb
15
LTC4269-2
Applications Information
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4269-2 presents a Class 4 load current. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Classification and 2nd mark event occurrence. This alerts the
LTC4269-2 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4269-2 charges
up the reservoir capacitor C1 with a controlled inrush
current. When C1 is fully charged, and the LTC4269-2
declares power good, the T2P pin presents an active low
signal, or low impedance output with respect to VPORTN.
The T2P output becomes inactive when the LTC4269-2
input voltage falls below the PoE undervoltage lockout
threshold.
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE 802.3at working group, Linear
noted that it is possible for a Type 2 PD to receive a false
indication of a 2-event classification if a PSE port is precharged to a voltage above the detection voltage range
before the first detection cycle. The IEEE working group
modified the standard to prevent this possibility by requiring a Type 2 PD to corrupt the signature resistance during
the mark event, alerting the PSE not to apply power. The
LTC4269-2 conforms to this standard by internally corrupting the signature resistance. This also discharges the
port before the PSE begins the next detection cycle.
PD STABILITY DURING CLASSIFICATION
Classification presents a challenging stability problem due
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
The LTC4269-2 prevents this oscillation by introducing a
voltage hysteresis window between the detection and classification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
The LTC4269-2 also maintains a positive I-V slope throughout the classification range up to the on voltage. In the
event a PSE overshoots beyond the classification voltage
range, the available load current aids in returning the PD
back into the classification voltage range. (The PD input
may otherwise be “trapped” by a reverse-biased diode
bridge and the voltage held by the 0.1µF capacitor.)
INRUSH CURRENT
Once the PSE detects and optionally classifies the PD, the
PSE then applies power to the PD. When the LTC4269‑2 port
voltage rises above the on voltage threshold, LTC4269‑2
connects VNEG to VPORTN through the internal power
MOSFET.
To control the power-on surge currents in the system, the
LTC4269-2 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
The LTC4269-2 keeps the PD inrush current below the
PSE current limit to provide a well-controlled power-up
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4269-2 interoperability
with any PSE.
PoE UNDERVOLTAGE LOCKOUT
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD operation when the port voltage is too low. In addition, this
specification allows PD designs to incorporate an on-off
hysteresis window to prevent start-up oscillations.
The LTC4269-2 features a PoE undervoltage lockout
(UVLO) hysteresis window (See Figure 5) that conforms
with the IEEE 802.3af/at specification and accommodates
the voltage drop in the cable and input diode bridge at the
onset of the inrush current.
Once C1 is fully charged, the LTC4269-2 turns on its internal MOSFET and passes power to the PD. The LTC4269-2
42692fb
16
LTC4269-2
Applications Information
LTC4269-2
LTC4269-2
TO
PSE
VPORTP
C1
5µF
MIN
+
OVLO
ON
UVLO
TSD
PD
LOAD
UNDERVOLTAGE
OVERVOLTAGE
LOCKOUT
CIRCUIT
VPORTN
29 PWRGD
CONTROL
CIRCUIT
28 PWRGD
VNEG
LTC4269-2
VPORTP – VPORTN POWER MOSFET
0V TO ON*
OFF
>ON*
ON
<UVLO*
OFF
>OVLO
OFF
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD 36.1V
UVLO THRESHOLD 30.7V
OVLO THRESHOLD 71.0V
42692 F05
CURRENT-LIMITED
TURN ON
Figure 5. LTC4269-2 Undervoltage and Overvoltage Lockout
VPORTN 5
27 VNEG
26 VNEG
VPORTN 6
BOLD LINE INDICATES HIGH CURRENT PATH
42692 F06
INRUSH COMPLETE
ON < VPORTP < OVLO
AND NOT IN THERMAL SHUTDOWN
POWER
NOT
GOOD
POWER
GOOD
continues to power the PD load as long as the port voltage does not fall below the UVLO threshold. When the
LTC4269-2 port voltage falls below the UVLO threshold,
the PD is disconnected, and classification mode resumes.
C1 discharges through the LTC4269-2 circuitry.
Figure 6. LTC4269-2 Power Good Functional and State Diagram
COMPLEMENTARY POWER GOOD
When power good is declared and active, the PWRGD pin
is low impedance with respect to VPORTN.
When LTC4269-2 fully charges the load capacitor (C1),
power good is declared and the LTC4269-2 load can safely
begin operation. The LTC4269-2 provides complementary
power good signals that remain active during normal
operation and are deasserted when the port voltage falls
below the PoE UVLO threshold, when the voltage exceeds
the overvoltage lockout (OVLO) threshold, or in the event
of a thermal shutdown. See Figure 6.
The PWRGD pin features an open-collector output referenced to VNEG which can interface directly with the SD_VSEC
pin. When power good is declared and active, the PWRGD
pin is high impedance with respect to VNEG. An internal
14V clamp limits the PWRGD pin voltage. Connecting
the PWRGD pin to the SD_VSEC pin prevents the DC/DC
converter from commencing operation before the PDI
interface completely charges the reservoir capacitor, C1.
The active low PWRGD pin connects to an internal, opendrain MOSFET referenced to VPORTN and can interface
directly to the shutdown pin of a DC/DC converter product.
VPORTP < UVLO
VPORTP > OVLO
OR THERMAL SHUTDOWN
PWRGD PIN WHEN SHDN IS INVOKED
In PD applications where an auxiliary power supply invokes
the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to
the “RUN” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
OVERVOLTAGE LOCKOUT
The LTC4269-2 includes an Overvoltage Lockout (OVLO)
feature (Figure 5) which protects the LTC4269-2 and its
load from an overvoltage event. If the input voltage exceeds the OVLO threshold, the LTC4269-2 discontinues
PD operation. Normal operations resume when the input
voltage falls below the OVLO threshold and when C1 is
charged up.
42692fb
17
LTC4269-2
Applications Information
THERMAL PROTECTION
The IEEE 802.3af/at specification requires a PD to withstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
During classification, excessive heating may occur if the
PSE exceeds the 75ms probing time limit. At turn-on, when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
The LTC4269-2 includes a thermal protection feature which
protects the LTC4269-2 from excessive heating. If the
LTC4269-2 junction temperature exceeds the overtemperature threshold, the LTC4269-2 discontinues PD operations.
Normal operation resumes when the junction temperature
falls below the overtemperature threshold and when C1 is
charged up and power good becomes inactive.
The increased current levels in a Type 2 PD over a Type 1
increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
provide correct impedance matching and to avoid radiated
and conducted emissions. Transformer vendors such as
Bel Fuse, Coilcraft, Halo, Pulse and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
16799 Schoenborn Street
North Hills, CA 91343
Tel: 818-892-0761
www.pca.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
Coilcraft Inc.
Halo Electronics
PCA Electronics
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Pulse Engineering
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
isolation transformer must also include a center tap on
the RJ45 connector side (see Figure 7).
Tyco Electronics
RJ45
Input Diode Bridge
1
2
3
6
4
TX+
14 T1 1
12
3
TX–
13
2
RX+
10
5
11
4
9
6
RX–
8
TO PHY
COILCRAFT ETH1-230LD
SPARE+
5
7
BR1
HD01
SPARE–
BR2
HD01
VPORTP
C14
D3
0.1µF SMAJ58A
100V
TVS
LTC4269-2
VPORTN VNEG
42692 F07
Figure 7. PD Front End with Isolation Transformer, Diode
Bridges, Capacitors and a Transient Voltage Suppressor (TVS)
C1
Figure 2 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4269-2 supports the use of either silicon or
Schottky input diode bridges. However, there are trade-offs
in the choice of diode bridges.
An input diode bridge must be rated above the maximum
current the PD application will encounter at the temperature the PD will operate. Diode bridge vendors typically
call out the operating current at room temperature, but
derate the maximum current with increasing temperature.
Consult the diode bridge vendors for the operating current
de-rating curve.
42692fb
18
LTC4269-2
Applications Information
A silicon diode bridge can consume over 4% of the available
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
A Schottky bridge may not be suitable for some high
temperature PD applications. The leakage current has
a temperature and voltage dependency that can reduce
the perceived signature resistance. In addition, the IEEE
802.3af/at specification mandates the leakage back-feeding
through the unused bridge cannot generate more than 2.8V
across a 100k resistor when a PD is powered with 57V.
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically derated. The larger package may not be acceptable in some space-limited environments.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profile. Figure 7 shows how the reconnect the two diode
bridges. Consult the diode bridge vendors for the de-rating
curve when only one of four diodes is in operation.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement. Place this capacitor
as close to the LTC4269-2 as possible.
Transient Voltage Suppressor
The LTC4269-2 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4269-2, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4269-2 as close
to the LTC4269-2 as possible as shown in Figure 7.
Classification Resistor (RCLASS)
The RCLASS resistor sets the classification load current,
corresponding to the PD power classification. Select the
value of RCLASS from Table 2 and connect the resistor
between the RCLASS and VPORTN pins as shown in Figure 4,
or float the RCLASS pin if the classification load current is
not required. The resistor tolerance must be 1% or better
to avoid degrading the overall accuracy of the classification circuit.
Load Capacitor
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5µF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store significant energy when fully
charged. The PD design must ensure that this energy is not
inadvertently dissipated in the LTC4269-2. For example,
if the VPORTP pin shorts to VPORTN while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-2.
T2P Interface
When a 2-event classification sequence successfully
completes, the LTC4269-2 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-2 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an optoisolater to communicate across the
42692fb
19
LTC4269-2
Applications Information
VPORTP
LTC4269-2
TO
PSE
–54V
VPORTN
These options come with various trade-offs and design
considerations. Contact Linear Technology applications
support for detailed information on implementing custom
auxiliary power sources.
V+
RP
TO PD’s
MICROPROCESSOR
T2P
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
V+
VPORTP
LTC4269-2
TO
PSE
RP
T2P
–54V
VPORTN
TO PD’s
MICROPROCESSOR
VNEG
42692 F08
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
Under the IEEE 802.3at standard, a PD must operate
under 12.95W in accordance with IEEE 802.3at standard
until it recognizes a Type 2 PSE. Initializing PD operation
in 12.95W mode eliminates interoperability issue in case
a Type 2 PD connects to a Type 1 PSE. Once the PD recognizes a Type 2 PSE, the IEEE 802.3at standard requires
the PD to wait 80ms in 12.95W operation before 25.5W
operation can commence.
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
Figure 8. T2P Interface Examples
DC/DC converter isolation barrier. The pull-up resistor RP
is sized according to the requirements of the opto-isolator operating current, the pull-down capability of the T2P
pin, and the choice of V+. V+ for example can come from
the PoE supply rail (which the LTC4269-2 VPORTP is tied
to), or from the voltage source that supplies power to
the DC/DC converter. Option 1 has the advantage of not
drawing power unless T2P is declared active.
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to VPORTN . If unused, connect
SHDN directly to VPORTN.
Exposed Pad
The LTC4269-2 uses a thermally enhanced DFN12 package
that includes an Exposed Pad. The Exposed Pad should
be electrically connected to the GND pin’s PCB copper
plane. This plane should be large enough to serve as the
heat sink for the LTC4269-2.
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter. Auxiliary
power can be injected into the PD at several locations with
priority chosen between PoE or auxiliary power sources.
20
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically draw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05µF. If one of these conditions
is not met, the PSE may disconnect power to the PD.
Isolation
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors, and any
auxiliary power connection. For PDs, there are two common methods to meet the isolation requirement. If there
are any user-accessible connections to the PD, then an
isolated DC/DC converter is necessary to meet the isolation
requirements. If user connections can be avoided, then it
is possible to meet the safety requirement by completely
enclosing the PD in an insulated housing.
Switcher Controller Operation
The LTC4269-2 has a current mode synchronous PWM
controller optimized for control of a forward converter
topology. The LTC4269-2 is ideal for power systems
where very high efficiency and reliability, low complexity
and cost are required in a small space. Key features of the
LTC4269-2 include an adaptive maximum duty cycle clamp.
42692fb
LTC4269-2
Applications Information
An additional output signal is included for synchronous
rectifier control or active clamp control. A precision 107mV
threshold senses overcurrent conditions and triggers softstart for low stress short-circuit protection and control.
The key functions of the LTC4269-2 PWM controller are
shown in the Block Diagrams.
Part Start-Up
In normal operation, the SD_VSEC pin must exceed 1.32V
and the VIN pin must exceed 14.25V to allow the part
to turn on. This combination of pin voltages allows the
2.5V VREF pin to become active, supplying the LTC4269-2
control circuitry and providing up to 2.5mA external drive.
SD_VSEC threshold can be used for externally programming
the power supply undervoltage lockout (UVLO) threshold
on the input voltage to the forward converter. Hysteresis
on the UVLO threshold can also be programmed since
the SD_VSEC pin draws 11µA just before part turn-on and
0µA after part turn-on.
With the LTC4269-2 turned on, the VIN pin can drop as
low as 8.75V before part shutdown occurs. This VIN pin
hysteresis (5.5V) combined with low 460µA start-up input
current allows low power start-up using a resistor/capacitor network from power supply input voltage to supply
the VIN pin (Figure 10). The VIN capacitor value is chosen
to prevent VIN falling below its turn-off threshold before
a bias winding in the converter takes over supply to the
VIN pin.
Output Drivers
The LTC4269-2 has two outputs, SOUT and OUT. The OUT
pin provides a ±1A peak MOSFET gate drive clamped to
13V. The SOUT pin has a ±50mA peak drive clamped to
12V and provides sync signal timing for synchronous
rectification control or active clamp control.
For SOUT and OUT turn-on, a PWM latch is set at the
start of each main oscillator cycle. OUT turn-on is delayed
from SOUT turn-on by a time, tDELAY (Figure 14). tDELAY
is programmed using a resistor from the DELAY pin to
GND and is used to set the timing control of the secondary
synchronous rectifiers for optimum efficiency.
SOUT and OUT turn off at the same time each cycle by
one of three methods:
(1) MOSFET peak current sense at ISENSE pin
(2) Adaptive maximum duty cycle clamp reached during
load/line transients
(3) Maximum duty cycle reset of the PWM latch
During any of the following conditions—low VIN, low
SD_VSEC or overcurrent detection at the OC pin—a softstart event is latched and both SOUT and OUT turn off
immediately (Figure 11).
Leading Edge Blanking
To prevent MOSFET switching noise causing premature
turn-off of SOUT or OUT, programmable leading edge
blanking exists. This means both the current sense comparator and overcurrent comparator outputs are ignored
during MOSFET turn-on and for an extended period after
the OUT leading edge (Figure 12). The extended blanking
period is programmable by adjusting a resistor from the
BLANK pin to GND.
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
For forward converter applications, a maximum switch
duty cycle clamp which adapts to transformer input voltage is necessary for reliable control of the MOSFET. This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. Instantaneous
load changes can cause the converter loop to demand
maximum duty cycle. If the maximum duty cycle of the
switch is too great, the transformer reset voltage can exceed the voltage rating of the primary-side MOSFETs with
catastrophic damage. Many converters solve this problem
by limiting the operational duty cycle of the MOSFET to
50% or less—or by using a fixed (non-adaptive) maximum
duty cycle clamp with very large voltage rated MOSFETs.
The LTC4269-2 provides a volt-second clamp to allow
MOSFET duty cycles well above 50%. This gives greater
power utilization for the MOSFETs, rectifiers and transformer resulting in less space for a given power output.
In addition, the volt-second clamp can allow a reduced
voltage rating on the MOSFET resulting in lower RDS(ON)
for greater efficiency. The volt-second clamp defines a
maximum duty cycle ‘guard rail’ which falls when power
supply input voltage increases.
42692fb
21
LTC4269-2
Applications Information
An increase of voltage at the SD_VSEC pin causes the
maximum duty cycle clamp to decrease. If SD_VSEC is
resistively divided down from power supply input voltage, a volt-second clamp is realized. To adjust the initial
maximum duty cycle clamp, the SS_MAXDC pin voltage
is programmed by a resistor divider from the 2.5V VREF
pin to GND. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
Soft-Start
The LTC4269-2 provides true PWM soft-start by using the
SS_MAXDC pin to control soft-start timing. The proportional relationship between SS_MAXDC voltage and switch
maximum duty cycle clamp allows the SS_MAXDC pin
to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
A soft-start event is triggered whenever VIN is too low,
SD_VSEC is too low (power supply UVLO), or a 107mV
overcurrent threshold at OC pin is exceeded. Whenever a
soft-start event is triggered, switching at SOUT and OUT
is stopped immediately.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below its reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to GND on the
SS_MAXDC pin in combination with a resistor divider from
VREF , defines the soft-start timing.
Current Mode Topology (ISENSE Pin)
The LTC4269-2 current mode topology eases frequency
compensation requirements because the output inductor does not contribute to phase delay in the regulator
loop. This current mode technique means that the error
amplifier (nonisolated applications) or the opto-coupler
(isolated applications) commands current (rather than voltage) to be delivered to the output. This makes frequency
compensation easier and provides faster loop response
to output load transients.
A resistor divider from the application’s output voltage generates a voltage at the inverting FB input of the LTC4269-2
error amplifier (or to the input of an external opto-coupler)
and is compared to an accurate reference (1.23V for
LTC4269-2). The error amplifier output (COMP) defines the
input threshold (ISENSE) of the current sense comparator.
COMP voltages between 0.8V (active threshold) and 2.5V
define a maximum ISENSE threshold from 0mV to 220mV.
By connecting ISENSE to a sense resistor in series with the
source of an external power MOSFET, the MOSFET peak
current trip point (turn off) can be controlled by COMP
level and hence by the output voltage. An increase in output
load current causing the output voltage to fall, will cause
COMP to rise, increasing ISENSE threshold, increasing the
current delivered to the output. For isolated applications,
the error amplifier COMP output can be disabled to allow
the opto-coupler to take control. Setting FB = VREF disables
the error amplifier COMP output, reducing pin current to
(COMP – 0.7)/40k.
Slope Compensation
The current mode architecture requires slope compensation
to be added to the current sensing loop to prevent subharmonic oscillations which can occur for duty cycles above
50%. Unlike most current mode converters which have a
slope compensation ramp that is fixed internally, placing a
constraint on inductor value and operating frequency, the
LTC4269-2 has externally adjustable slope compensation.
Slope compensation can be programmed by inserting an
external resistor (RSLOPE) in series with the ISENSE pin. The
LTC4269-2 has a linear slope compensation ramp which
sources current out of the ISENSE pin of approximately 8µA
at 0% duty cycle to 35µA at 80% duty cycle.
Overcurrent Detection and Soft-Start (OC Pin)
An added feature to the LTC4269-2 is a precise 107mV
sense threshold at the OC pin used to detect overcurrent
conditions in the converter and set a soft-start latch. The
OC pin is connected directly to the source of the primaryside MOSFET to monitor peak current in the MOSFET (Figure 13). The 107mV threshold is constant over the entire
duty cycle range of the converter because it is unaffected
by the slope compensation added to the ISENSE pin.
42692fb
22
LTC4269-2
Applications Information
Synchronizing
A SYNC pin allows the LTC4269-2 oscillator to be synchronized to an external clock. The SYNC pin can be driven
from a logic-level output, requiring less than 0.8V for a
logic-level low and greater than 2.2V for a logic-level high.
Duty cycle should run between 10% and 90%. To avoid
loss of slope compensation during synchronization, the free
running oscillator frequency, fOSC, should be programmed
to 80% of the external clock frequency (fSYNC). The RSLOPE
resistor chosen for nonsynchronized operation should be
increased by 1.25x (= fSYNC/fOSC).
Shutdown and Programming the Power Supply
Undervoltage Lockout
The LTC4269-2 has an accurate 1.32V shutdown threshold
at the SD_VSEC pin. This threshold can be used in conjunction with a resistor divider to define the power supply
undervoltage lockout threshold (UVLO) of the power supply
input voltage (VS) (Figure 9). A pin current hysteresis (11µA
before part turn-on, 0µA after part turn-on) allows power
supply UVLO hysteresis to be programmed. Calculation of
the on/off thresholds for the power supply input voltage
can be made as follows:
POWER SUPPLY
INPUT VOLTAGE (VS)
R1
LTC4269-2
SD_VSEC
–
11µA
R2
PWRGD
+
1.32V
42692 F09
Figure 9. Programming Power Supply
Undervoltage Lockout (UVLO)
POWER SUPPLY
INPUT VOLTAGE (VS)
FROM AUXILIARY WINDING
RSTART
VIN
LTC4269-2
D1*
–
1.32V
+
CSTART
VS(OFF) Threshold = 1.32[1 + (R1/R2)]
VS(ON) Threshold = VS(OFF) + (11µA • R1)
Connect the PWRGD pin to the resistive divider network
at the SD_VSEC pin to prevent the DC/DC converter from
starting before the PD interface completely charges the
reservoir capacitor, C1 (Figure 9).
The SD_VSEC pin must not be left open since there must
be an external source current >11µA to lift the pin past its
1.32V threshold for part turn-on.
Micropower Start-Up: Selection of Start-Up Resistor
and Capacitor for VIN
The LTC4269-2 uses turn-on voltage hysteresis at the VIN
pin and low start-up current to allow micropower start-up
(Figure 10). The LTC4269-2 monitors VIN pin voltage to
allow the part to turn-on at 14.25V and the part to turnoff at 8.75V. Low start-up current (460µA) allows a large
resistor to be connected between the power supply input
supply and VIN. Once the part is turned on, input current
42692 F10
*FOR VS > 25V, ZENER D1 RECOMMENDED
(VIN ON(MAX) < VZ < 25V)
Figure 10. Low Power Start-Up
increases to drive the IC (5.2mA) and the output drivers
(IDRIVE). A large enough capacitor is chosen at the VIN pin
to prevent VIN falling below its turn-off threshold before
a bias winding in the converter takes over supply to VIN.
This technique allows a simple resistor/capacitor for
start-up which draws low power from the system supply
to the converter.
For system input voltages exceeding the absolute maximum
rating of the LTC4269-2 VIN pin, an external Zener should
be connected from the VIN pin to GND. This covers the
condition where VIN charges past VIN(ON) but the part does
not turn on because SD_VSEC < 1.32V. In this condition,
VIN will continue to charge towards system VIN, possibly
exceeding the rating for the VIN pin. The Zener voltage
should obey VIN(ONMAX) < VZ < 25V.
42692fb
23
LTC4269-2
Applications Information
Programming Oscillator Frequency
The oscillator frequency (fOSC) of the LTC4269-2 is programmed using an external resistor, ROSC, connected
between the ROSC pin and GND. Figure 11 shows typical
fOSC vs ROSC resistor values. The LTC4269-2 free-running oscillator frequency is programmable in the range
of 100kHz to 500kHz.
Stray capacitance and potential noise pickup on the ROSC
pin should be minimized by placing the ROSC resistor as
close as possible to the ROSC pin and keeping the area of
the ROSC node as small as possible. The ground side of
the ROSC resistor should be returned directly to the (analog
ground) GND pin. ROSC can be calculated by:
ROSC = 9.125k [(4100k/fOSC) – 1]
times can vary depending on MOSFET type. For this reason
the LTC4269-2 performs true ‘leading edge blanking’ by
automatically blanking OC and ISENSE comparator outputs
until OUT rises to within 0.5V of VIN or reaches its clamp
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to GND. Typical durations for this
portion of the blanking period are from 45ns at RBLANK
= 10k to 540ns at RBLANK = 120k. Blanking duration can
be approximated as:
Blanking (extended) = [45(RBLANK/10k)]ns
(See graph in the Typical Performance Characteristics
section).
Programming Leading Edge Blank Time
Programming Current Limit (OC Pin)
For PWM controllers driving external MOSFETs, noise
can be generated at the source of the MOSFET during
gate rise time and some time thereafter. This noise can
potentially exceed the OC and ISENSE pin thresholds of the
LTC4269-2 to cause premature turn-off of SOUT and OUT
pins in addition to false trigger of soft-start. The LTC4269‑2
provides a programmable leading edge blanking of the
OC and ISENSE comparator outputs to avoid false current
sensing during MOSFET switching.
The LTC4269-2 uses a precise 107mV sense threshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
duty cycle because it is not affected by slope compensation programmed at the ISENSE pin. The OC pin monitors
the peak current in the primary MOSFET by sensing the
voltage across a sense resistor (RS) in the source of the
MOSFET. The overcurrent limit for the converter can be
programmed by:
Blanking is provided in two phases (Figure 12): The first
phase automatically blanks during gate rise time. Gate rise
Overcurrent limit = (107mV/RS)(NP/NS) – (½)(IRIPPLE)
(AUTOMATIC)
LEADING
EDGE
BLANKING
500
450
(PROGRAMMABLE)
EXTENDED
BLANKING
CURRENT
SENSE
DELAY
10k < RBLANK b 240k
100ns
FREQUENCY (kHz)
400
350
OUT
300
RBLANK
(MIN)
250
= 10k
200
150
100
50
BLANKING
100
150
200 250
ROSC (kΩ)
300
350
42692 F12
400
42692 F11
Figure 11. Oscillator Frequency, fOSC, vs ROSC
0
Xns
X + 45ns
[X + 45(RBLANK/10k)]ns
Figure 12. Leading Edge Blank Timing
42692fb
24
LTC4269-2
Applications Information
where:
RS = sense resistor in source of primary MOSFET
IRIPPLE = IP-P ripple current in the output inductor L1
NS = number of transformer secondary turns
NP = number of transformer primary turns
Programming Slope Compensation
The LTC4269-2 uses a current mode architecture to provide
fast response to load transients and to ease frequency
compensation requirements. Current mode switching
regulators which operate with duty cycles above 50%
and have continuous inductor current must add slope
compensation to their current sensing loop to prevent
subharmonic oscillations. (For more information on slope
compensation, see Application Note 19.) The LTC4269-2
has programmable slope compensation to allow a wide
range of inductor values, to reduce susceptibility to PCB
generated noise and to optimize loop bandwidth. The
LTC4269-2 programs slope compensation by inserting a
resistor, RSLOPE, in series with the ISENSE pin (Figure 13).
The LTC4269-2 generates a current at the ISENSE pin which
is linear from 0% duty cycle to the maximum duty cycle
of the OUT pin. A simple calculation of ISENSE • RSLOPE
gives an added ramp to the voltage at the ISENSE pin for
programmable slope compensation. (See both graphs
ISENSE Pin Current vs Duty Cycle and ISENSE Maximum
Threshold vs Duty Cycle in the Typical Performance
Characteristics section.)
CURRENT SLOPE = 35µA • DC
LTC4269-2
OUT
OC
ISENSE
VSOURCE
RSLOPE
RS
V(ISENSE) = VSOURCE + (ISENSE • RSLOPE)
ISENSE = 8µA + 35DC µA
DC = DUTY CYCLE
FOR SYNC OPERATION
ISENSE(SYNC) = 8µA + (k • 35DC)µA
k = fOSC/fSYNC
42692 F13
Figure 13. Programming Slope Compensation
Programming Synchronous Rectifier Timing:
SOUT to OUT delay (‘tDELAY’)
The LTC4269-2 has an additional output SOUT which provides a ±50mA peak drive clamped to 12V. In applications
requiring synchronous rectification for high efficiency,
the LTC4269-2 SOUT provides a sync signal for secondary side control of the synchronous rectifier MOSFETs
(Figure 14). Timing delays through the converter can
cause non-optimum control timing for the synchronous
rectifier MOSFETs. The LTC4269-2 provides a programmable delay (tDELAY, Figure 14) between SOUT rising
edge and OUT rising edge to optimize timing control for
the synchronous rectifier MOSFETs to achieve maximum
efficiency gains. A resistor RDELAY connected from the
DELAY pin to GND sets the value of tDELAY. Typical values
for tDELAY range from 10ns with RDELAY = 10k to 160ns
with RDELAY = 160k (see graph in the Typical Performance
Characteristics section).
tDELAY
SOUT
OUT
LTC4269-2
DELAY
42692 F14
RDELAY
Figure 14. Programming SOUT and OUT Delay: tDELAY
Programming Maximum Duty Cycle Clamp
For forward converter applications, a maximum switch
duty cycle clamp which adapts to transformer input voltage is necessary for reliable control of the MOSFETs. This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. The LTC4269-2
SD_VSEC and SS_MAXDC pins provide a capacitor-less,
programmable volt-second clamp solution using simple
resistor ratios (Figure 15).
An increase of voltage at the SD_VSEC pin causes the
maximum duty cycle clamp to decrease. Deriving SD_VSEC
from a resistor divider connected to system input voltage
42692fb
25
LTC4269-2
Applications Information
POWER SUPPLY
INPUT VOLTAGE
R1
ADAPTIVE
DUTY CYCLE
CLAMP INPUT
LTC4269-2
SD_VSEC
R2
RT*
SS_MAXDC
Example calculation for (2):
VREF
RB
(3) The maximum duty cycle clamp calculated in (2)
should be programmed to be 10% greater than the
maximum operational duty cycle calculated in (1).
Simple adjustment of maximum duty cycle can be
achieved by adjusting SS_MAXDC.
42692 F15
MAX DUTY CYCLE
CLAMP ADJUST INPUT
*MINIMUM ALLOWABLE RT IS 10k TO
GUARANTEE SOFT-START PULL-OFF
Figure 15. Programming Maximum Duty Cycle Clamp
creates the volt-second clamp. The maximum duty cycle
clamp can be adjusted by programming voltage on the
SS_MAXDC pin using a resistor divider from VREF . An
increase of voltage at the SS_MAXDC pin causes the
maximum duty cycle clamp to increase.
To program the volt-second clamp, the following steps
should be taken:
(1) The maximum operational duty cycle of the converter
should be calculated for the given application.
(2) An initial value for the maximum duty cycle clamp
should be calculated using the equation below with a
first pass guess for SS_MAXDC.
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
SD_VSEC pin = 1.32V.
Max Duty Cycle Clamp (OUT Pin) =
k • 0.522(SS_MAXDC(DC)/SD_VSEC) – (tDELAY • fOSC)
where:
SS_MAXDC(DC) = VREF(RB/(RT + RB)
For RT = 35.7k, RB = 100k, VREF = 2.5V,
RDELAY = 40k, fOSC = 200kHz and SD_VSEC = 1.32V,
this gives SS_MAXDC(DC) = 1.84V, tDELAY = 40ns
and k = 1
Maximum Duty Cycle Clamp
= 1 • 0.522(1.84/1.32) – (40ns • 200kHz)
= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)
Note 1: To achieve the same maximum duty cycle clamp at
100kHz as calculated for 200kHz, the SS_MAXDC voltage
should be reprogrammed by,
SS_MAXDC(DC) (100kHz)
= SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz)
= 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)
Note 2 : To achieve the same maximum duty cycle clamp
while synchronizing to an external clock at the SYNC pin,
the SS_MAXDC voltage should be reprogrammed as,
SS_MAXDC (DC) (fsync)
= SS_MAXDC (DC) (200kHz) • [(fosc/fsync) +
0.09(fosc/200kHz)0.6]
For SS_MAXDC (DC) (200kHz) = 1.84V for 72%
duty cycle
SS_MAXDC (DC) (fsync = 250kHz) for 72%
duty cycle
= 1.84 • [(200kHz/250kHz) + 0.09(1)0.6]
= 1.638V
SD_VSEC = 1.32V at minimum system input voltage
Programming Soft-Start Timing
tDELAY = programmed delay between SOUT and OUT
The LTC4269-2 has built-in soft-start capability to provide
low stress controlled start-up from a list of fault conditions that can occur in the application (see Figures 16
and 17). The LTC4269-2 provides true PWM soft-start by
k = 1.11 – 5.5e–7 • (fOSC)
42692fb
26
LTC4269-2
Applications Information
tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY
SOUT
OUT
SS_MAXDC
FAULTS TRIGGERING SOFT-START
VIN < 8.75V
OR
SD_VSEC < 1.32V (UVLO)
OR
OC > 107mV (OVERCURRENT)
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
0.2V
SOFT-START LATCH RESET:
SOFT-START
LATCH SET
VIN > 14.25V
(> 8.75V IF LATCH SET BY OC)
AND
SD_VSEC > 1.32V
AND
OC < 107mV
AND
SS_MAXDC < 0.45V 42692 F16
A soft-start event is triggered for the following faults:
(1) VIN < 8.75V, or
(2) SD_VSEC < 1.32V (UVLO), or
(3) OC > 107mV (overcurrent condition)
When a soft-start event is triggered, switching at SOUT
and OUT is stopped immediately. A soft-start latch is set
and SS_MAXDC pin is discharged. The SS_MAXDC pin can
only recharge when the soft-start latch has been reset.
Figure 16. Timing Diagram
SS_MAXDC
SOFT-START
EVENT TRIGGERED
using the SS_MAXDC pin to control soft-start timing. The
proportional relationship between SS_MAXDC voltage and
switch maximum duty cycle clamp allows the SS_MAXDC
pin to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
A capacitor CSS on the SS_MAXDC pin and the resistor
divider from VREF used to program maximum switch duty
cycle clamp, determine soft-start timing (Figure 18).
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
TIMING (A): SOFT START FAULT REMOVED
BEFORE SS_MAXDC FALLS TO 0.45V
Note: A soft-start event caused by (1) or (2) above, also
causes VREF to be disabled and to fall to GND.
Soft-start latch reset requires all of the following:
(A) VIN > 14.25V*, and
SS_MAXDC
(B) SD_VSEC > 1.32V, and
(C) OC < 107mV, and
0.8V (ACTIVE THRESHOLD)
42692 F17
0.45V (RESET THRESHOLD)
0.2V
TIMING (B): SOFT-START FAULT REMOVED
AFTER SS_MAXDC FALLS PAST 0.45V
SS_MAXDC(DC)
SS_MAXDC
RT
CSS
RB
LTC4269-2
RCHARGE
VREF
*VIN > 8.75V is okay for latch reset if the latch was only
set by overcurrent condition in (3) above.
SS_MAXDC Discharge Timing
Figure 17. Soft-Start Timing
LTC4269-2
(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)
SS_MAXDC
CSS
SS_MAXDC CHARGING MODEL
SS_MAXDC(DC) = VREF [RB/(RT + RB)]
RCHARGE = [RT • RB/(RT + RB)]
Figure 18. Programming Soft-Start Timing
42692 F18
It can be seen in Figure 17 that two types of discharge
can occur for the SS_MAXDC pin. In timing (A) the fault
that caused the soft-start event has been removed before SS_MAXDC falls to 0.45V. This means the soft-start
latch will be reset when SS_MAXDC falls to 0.45V and
SS_MAXDC will begin charging. In timing (B), the fault that
caused the soft-start event is not removed until some time
after SS_MAXDC has fallen past 0.45V. The SS_MAXDC
pin continues to discharge to 0.2V and remains low until
all faults are removed.
42692fb
27
LTC4269-2
Applications Information
The time for SS_MAXDC to fall to a given voltage can be
approximated as:
SS_MAXDC(tFALL)=
(CSS/IDIS) • [SS_MAXDC(DC) – VSS(MIN)]
where:
IDIS = net discharge current on CSS
CSS = capacitor value at SS_MAXDC pin
SS_MAXDC(DC) = programmed DC voltage
VSS(MIN) = minimum SS_MAXDC voltage before
recharge
IDIS ≅ 8e–4 + (VREF – VSS(MIN))[(1/2RB) – (1/RT)]
For faults arising from (1) and (2):
VREF = 100mV.
For a fault arising from (3):
VREF = 2.5V.
SS_MAXDC(DC) = VREF[RB/(RT + RB)]
VSS(MIN) = SS_MAXDC reset threshold = 0.45V
(if fault removed before tFALL)
Example
For an overcurrent fault (OC > 100mV), VREF = 2.5V,
RT = 35.7k, RB = 100k, CSS = 0.1µF and assume
VSS(MIN) = 0.45V,
IDIS ≅ 8e–4 + (2.5 – 0.45)[(½ • 100k) – (1/35.7k)]
= 8e–4 + (2.05)(–0.23e–4) = 7.5e–4
The calculation of charging time for the SS_MAXDC pin
between any two voltage levels can be approximated as
an RC charging waveform using the model shown in
Figure 16.
The ability to predict SS_MAXDC rise time between any two
voltages allows prediction of several key timing periods:
(1) No Switching Period (time from SS_MAXDC(DC) to
VSS(MIN) + time from VSS(MIN) to VSS(ACTIVE))
(2) Converter Output Rise Time (time from VSS(ACTIVE) to
VSS(REG); VSS(REG) is the level of SS_MAXDC where
maximum duty cycle clamp equals the natural duty
cycle of the switch)
(3) Time For Maximum Duty Cycle Clamp within X% of
Target Value
The time for SS_MAXDC to charge to a given voltage VSS
is found by re-arranging:
VSS(t) = SS_MAXDC(DC) (1 – e(–t/RC))
to give,
t = RC • (–1) • ln(1 – VSS/SS_MAXDC(DC))
where,
VSS = SS_MAXDC voltage at time t
SS_MAXDC(DC) = programmed DC voltage setting
maximum duty cycle clamp = VREF(RB/(RT + RB)
R = RCHARGE (Figure 16) = RT • RB/(RT + RB)
C = CSS (Figure 16)
SS_MAXDC(DC) = 1.84V
Example (1) No Switching Period
SS_MAXDC(tFALL)
= (1e–7/7.5e–4) • (1.84 – 0.45)=1.85e–4s
The period of no switching for the converter, when a softstart event has occurred, depends on how far SS_MAXDC
can fall before recharging occurs and how long a fault exists. It will be assumed that a fault triggering soft-start is
removed before SS_MAXDC can reach its reset threshold
(0.45V).
If the OC fault is not removed before 185µs then SS_MAXDC
will continue to fall past 0.45V towards a new VSS(MIN).
The typical VOL for SS_MAXDC at 150µA is 0.2V.
SS_MAXDC Charge Timing
No Switching Period = tDISCHARGE + tCHARGE
When all faults are removed and the SS_MAXDC pin
has fallen to its reset threshold of 0.45V or lower, the
SS_MAXDC pin will be released and allowed to charge.
tDISCHARGE = discharge time from SS_MAXDC(DC) to
0.45V
SS_MAXDC will rise until it settles at its programmed DC
voltage—setting the maximum switch duty cycle clamp.
tCHARGE = charge time from 0.45V to VSS(ACTIVE)
tDISCHARGE was already calculated earlier as 185µs.
42692fb
28
LTC4269-2
Applications Information
tCHARGE is calculated by assuming the following:
VREF = 2.5V, RT = 35.7k, RB = 100k, CSS = 0.1µF and
VSS(MIN) = 0.45V.
tCHARGE = t(VSS = 0.8V) – t(VSS = 0.45V)
Step 1:
SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V
RCHARGE = (35.7k • 100k/135.7k) = 26.3k
Step 2:
t(VSS = 0.45V) is calculated from:
t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))
= 2.63e4 • 1e–7 • (–1) • ln(1 – 0.45/1.84)
= 2.63e–3 • (–1) • ln(0.755) = 7.3e–4 s
Step 3:
t(VSS = 0.8V) is calculated from:
t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS–MAXDC(DC))
= 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84)
= 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s
From Step 1 and Step 2
tCHARGE
= (1.5 – 0.73)e–3 s = 7.7e–4 s
The total time of no switching for the converter due to a
soft-start event
= tDISCHARGE + tCHARGE = 1.85e–4 + 7.7e–4 = 9.55e–4 s
Example (2) Converter Output Rise Time
The rise time for the converter output to reach regulation
can be closely approximated as the time between the start
of switching (SS_MAXDC = VSS(ACTIVE)) and the time where
converter duty cycle is in regulation (DC(REG)) and no
longer controlled by SS_MAXDC (SS_MAXDC = VSS(REG)).
Converter output rise time can be expressed as:
Output Rise Time = t(VSS(REG)) – t(VSS(ACTIVE))
Step 1: Determine converter duty cycle DC(REG) for output
in regulation.
The natural duty cycle DC(REG) of the converter depends
on several factors. For this example it is assumed that
DC(REG) = 60% for power supply input voltage near the
power supply UVLO. This gives SD_VSEC = 1.32V.
Also assume that the maximum duty cycle clamp programmed for this condition is 72% for SS_MAXDC(DC)
= 1.84V, fOSC = 200kHz and RDELAY = 40k.
Step 2: Calculate VSS(REG)
To calculate the level of SS_MAXDC (VSS(REG)) that no
longer clamps the natural duty cycle of the converter, the
equation for maximum duty cycle clamp must be used
(see previous section Programming Maximum Duty Cycle
Clamp).
The point where the maximum duty cycle clamp meets
DC(REG) during soft-start is given by:
DC(REG) = Max Duty Cycle Clamp
0.6 = k • 0.522(SS_MAXDC(DC)/SD_VSEC) – (tDELAY
• fOSC)
For SD_VSEC = 1.32V, fOSC = 200kHz and
RDELAY = 40k
This gives k = 1 and tDELAY = 40ns.
Rearranging the above equation to solve for SS_MAXDC
= VSS(REG)
= [0.6 + (tDELAY • fOSC)(SD_VSEC)]/(k • 0.522)
= [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522)
= (0.608)(1.32)/0.522 = 1.537V
Step 3: Calculate t(VSS(REG)) – t(VSS(ACTIVE))
Recall the time for SS_MAXDC to charge to a given voltage VSS is given by:
t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))
(Figure 16 gives the model for SS_MAXDC charging)
For RT = 35.7k, RB = 100k, RCHARGE = 26.3k
For CSS = 0.1µF, this gives t(VSS(ACTIVE))
= t(VSS(0.8V)) = 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84)
= 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s
t(VSS(REG)) = t(VSS(1.537V)) = 26.3k • 0.1µF • –1 •
ln(1 – 1.66/1.84) = 2.63e–3 • (–1) • ln(0.146) = 5e–3 s
The rise time for the converter output:
= t(VSS(REG)) – t(VSS(ACTIVE)) = (5 – 1.5)e–3 s
= 3.5e–3 s
42692fb
29
LTC4269-2
Applications Information
Example (3) Time For Maximum Duty Cycle Clamp to
Reach Within X% of Target Value
A maximum duty cycle clamp of 72% was calculated previously in the section ‘Programming Maximum Duty Cycle
Clamp’. The programmed value used for SS_MAXDC(DC)
was 1.84V.
The time for SS_MAXDC to charge from its minimum value
VSS(MIN) to within X% of SS_MAXDC(DC) is given by:
t(SS_MAXDC charge time within X% of target)
= t[(1 – (X/100) • SS_MAXDC(DC)] – t(VSS(MIN))
From previous calculations, t(0.45) = 7.3e–4s.
Using previous values for RT , RB and CSS,
t(1.803) = 2.63e–4 • 1e–7 • (–1) • ln(1 – 1.803/1.84)
= 2.63e–3 • (–1) • ln(0.02) = 1.03e–2 s
Hence the time for SS_MAXDC to charge from its minimum reset threshold of 0.45V to within 2% of its target
value is given by:
t(1.803) – t(0.45) = 1.03e–2 – 7.3e–4 = 9.57e–3s
For X = 2 and VSS(MIN) = 0.45V, t(0.98 • 1.84) – t(0.45)
= t(1.803) – t(0.45)
42692fb
30
54V FROM
SPARE PAIR
54V FROM
DATA PAIR
B1100 s 8 PLCS
48V
AUXILIARY
POWER
BAS21
S1B
10k
+
24k
10µF
100V
10µH
DO1608C-103
SMAJ58A
BSS63LT1
0.1µF
100V
107k
36V
PDZ36B
VPORTP
30.9Ω
2.2µF
100V
65
70
75
80
85
90
95
T2P VNEG
VPORTN
RCLASS
SHDN
VPORTP
33k
GND
82k
BLANK
BAS516
0.1µF
158k
0.5
1
1.5
2
2.5
3
LOAD (A)
3.5
4
COMP
FB
VREF
ISENSE
OC
10k
332k
5
42692 TA02b
4.5
42V
50V
57V
100pF
SS_MAXDC
OUT
BAS516
ROSC DELAY
LTC4269-2
SOUT
10µF
16V
133Ω
18V
PDZ18B
Efficiency vs Load Current
PGND
+
VCC
SD_VSEC PWRGD VIN
10.0k
237k
EFFICIENCY (%)
1mH
DO1608C-105 BAS516
158k
33k
1.5k
22k
FDS2582
IRF6217
4.7nF
250V
•
0.22µF
22.1k
50mΩ
•
•
5.1Ω
1nF
PS2801-1-L
51k
0.1µF VPORTP
5V
20k
10nF
4.7nF
TLV431A
2k
5.1Ω
1nF
6.8µH
PG0702.682
3.65k
11.3k
+
2692 TA02
T2P
TO MICROCONTROLLER
1.2k
VCC
5.1Ω FDS8880
PS2801-1-L
BC857BF
2.2nF
2kV
FDS8880
PA2431NL
PoE-Based Self-Driven Synchronous Forward Power Supply
220µF
6.3V
PSLV0J227M(12)A
5V
5A
LTC4269-2
TYPICAL APPLICATION
42692fb
31
LTC4269-2
Package Description
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 p 0.05
4.50 p 0.05
6.43 p0.05
2.65 p0.05
3.10 p 0.05
PACKAGE
OUTLINE
0.20 p 0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 p0.10
17
R = 0.115
TYP
32
R = 0.05
TYP
0.40 p 0.10
6.43 p0.10
4.00 p0.10
2.65 p0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
0.75 p0.05
0.40 BSC
BOTTOM VIEW—EXPOSED PAD
0.200 REF
0.20 p 0.05
1
6.00 REF
(DKD32) QFN 0707 REV A
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
42692fb
32
LTC4269-2
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
04/10
Connected PWRGD Pin to SD_VSEC Pin in Typical Applications Circuits.
PAGE NUMBER
Added Text Clarifying Connecting PWRGD Pin to SD_VSEC Pin in Shutdown and Programming the Power Supply
Undervoltage Lockout Section of Applications Information.
1, 23, 31
23
42692fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC4269-2
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42692fb
34 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0409 REV B • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2009