FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13732-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90860A Series
MB90F867A (S) , MB90867A (S)
■ DESCRIPTION
The MB90860A-series is Fujitsu 16-bit general-purpose microcontroller which enhances each kind of timers and
communication macros. With the new 0.35 µm CMOS technology, Fujitsu now offers 128 Kbytes on-chip FLASHROM program memory. An internal voltage booster removes the necessity for a second programming voltage.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ PACKAGES
100-pin Plastic QFP
100-pin Plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90860A Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied PLL clock).
• 16 Mbyte CPU memory space
• 24-bit internal addressing
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
(Continued)
2
MB90860A Series
(Continued)
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
• UART (LIN/SCI) : 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface* : 2 channels
• Up to 400 kbit/s transfer rate
• DTP/External interrupt : 16 channels, CAN wakeup : 2 channels
• Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
• Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
• ROM security function
• Protects the content of ROM (MASK ROM device only)
• Flash security function
• Protects the content of Flash (Flash device only)
• External bus interface
• Clock monitor function
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C standard Specification as defined by
Philips.
3
MB90860A Series
■ PRODUCT LINEUP
Part Number
MB90F867A (S) , MB90867A (S)
MB90V340(S)
Parameter
F2MC-16LX CPU
CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
ROM
Boot-block,Flash memory
128 Kbytes
RAM
Emulator-specific
power supply*1
External
30 Kbytes
6 Kbytes
Yes
Technology
0.35 µm CMOS with on-chip voltage regulator for internal
power supply + Flash memory with
On-chip charge pump for programming voltage
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
5 V ± 10%
−40 °C to +105 °C
QFP-100, LQFP-100
PGA-299
4 channels
5 channels
Temperature range
Package
UART
I2C (400 Kbit/s)
A/D
Converter
0.35 µm CMOS with
on-chip voltage regulator
for internal power supply
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2 channel
24 input channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
16-bit
I/O Timer
(2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer match output compare registers.
(8 channels (16-bit) / A pair of compare registers can be used to generate an output signal.
16 channels (8-bit) )
16-bit Input Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
(Continued)
4
MB90860A Series
(Continued)
Part Number
MB90F867A (S) , MB90867A (S)
MB90V340(S)
Parameter
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
8/16-bit
Sixteen 8-bit reload registers for L pulse width
Programmable Pulse Sixteen 8-bit reload registers for H pulse width
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
(8 channels)
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN Interface
External Interrupt
(16 channels)
D/A converter
3 channels
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded inteligent I/O services (EI2OS) and DMA
2 channels
Up to100 kHz
Subclock for low
power operation
devices with ‘S’-suffix
: without subclock
devices without ‘S’-suffix : with subclock
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
Flash
Memory
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90860A Series
■ PIN ASSIGNMENTS
• MB90F867A (S) , MB90867A (S)
RST
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6/INT9R
P43/IN7
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
P56/AN14
P33/WRH
P34/HRQ/OUT4
P31/RD/IN5
P32/WRL/WR/INT10R
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
42
QFP - 100
90
41
91
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/NT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
MD0
MD1
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA 1
PA0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
(TOP VIEW)
(FPT-100P-M06)
* : MB90F867A, MB90867A : X0A, X1A
MB90F867AS, MB90867AS : P40, P41
(Continued)
6
MB90860A Series
(Continued)
RST
MD0
MD1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6//INT9R
P43/IN7
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P33/WRH
P34/HRQ/OUT4
P31/RD/IN5
P32/WRL/WR/INT10R
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
LQFP - 100
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/NT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
P00/AD00/INT8
PA 1
PA0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
(TOP VIEW)
(FPT-100P-M05)
* : MB90F867A, MB90867A : X0A, X1A
MB90F867AS, MB90867AS : P40, P41
7
MB90860A Series
■ PIN DESCRIPTION
Pin No.
LQFP100*2 QFP100*1
Pin name
90
92
X1
91
93
X0
52
54
RST
Circuit
type
A
E
77 to 84
84
G
INT8 to INT15
External interrupt request input pins for INT8 to INT15.
85
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
G
AD08
I/O pin for bit 8 of the external address/data bus.
This function is enabled when the external bus is enabled.
TIN1
Event input pin for the reload timer 1
P11
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
86
87
G
AD09
I/O pin for bit 9 of the external address/data bus.
This function is enabled when the external bus is enabled.
TOT1
Output pin for the reload timer 1
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
AD10
N
SIN3
Sub external interrupt request input pin for INT11
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P13
88
G
AD11
I/O pin for bit 11 of the external address/data bus.
This function is enabled when the external bus is enabled.
SOT3
Serial data output pin for UART3
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P14
87
I/O pin for bit 10 of the external address/data bus.
This function is enabled when the external bus is enabled.
Serial data input pin for UART3
INT11R
86
Reset input
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
P12
85
Oscillation input
AD00 to AD07
P10
83
Oscillation output
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P00 to P07
75 to 82
Function
89
G
AD12
I/O pin for bit 12 of the external address/data bus.
This function is enabled when the external bus is enabled.
SCK3
Clock I/O pin for UART3
(Continued)
8
MB90860A Series
Pin No.
LQFP100*
2
QFP100*
1
Pin name
Circuit
type
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P15
92
93
94
G
AD13
I/O pin for bit 13 of the external address/data bus.
This function is enabled when the external bus is enabled.
SIN4
Serial data input pin for UART4 (MB90V340 only)
P16
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
95
G
AD14
I/O pin for bit 14 of the external address/data bus.
This function is enabled when the external bus is enabled.
SOT4
Serial data output pin for UART4 (MB90V340 only)
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P17
94
96
G
AD15
I/O pin for bit 15 of the external address/data bus. This function
is enabled when the external bus is enabled.
SCK4
Clock I/O pin for UART4 (MB90V340 only)
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
P20 to P23
95 to 98
97 to 100
G
A16 to A19
PPG9,PPGB,
PPGD,PPGF
1 to 4
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
G
A20 to A23
Output pins for A20 to A23 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A20 to A23).
IN0 to IN3
Data sample input pins for input captures ICU0 to ICU3
General purpose I/O.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
P30
3
Output pins for A16 to A19 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
Output pins for PPGs
P24 to P27
99 to 2
Function
5
G
ALE
Address latch enable output pin. This function is enabled when
the external bus is enabled.
IN4
Data sample input pin for input capture ICU4
(Continued)
9
MB90860A Series
Pin No.
2
LQFP100* QFP100*
1
Pin name
Circuit
type
General purpose I/O.The register can be set to select whether to
use a pull-up resistor.This function is enabled in single-chip
mode.
P31
4
5
6
7
G
RD
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
IN5
Data sample input pin for input capture ICU5
P32
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the WR/WRL pin output disabled.
WRL / WR
Write strobe output pin for the data bus. This function is enabled
when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in
16-bit access while WR is used to write-strobe 8 bits of the data
bus in 8-bit access.
G
RX2
RX input pin for CAN2 Interface (MB90V340 only)
INT10R
Sub external interrupt request input pin for INT10
General purpose I/O. The register can be set to select whether to
use a pull-up resistor.This function is enabled either in single-chip
mode or with the WRH pin output disabled.
P33
6
7
WRH
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the
external bus 16-bit mode is selected, and when the WRH output
pin is enabled.
TX2
TX Output pin for CAN2 (MB90V340 only)
P34
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the hold function disabled.
8
G
9
G
HRQ
Hold request input pin. This function is enabled when both the external bus and the hold function are enabled.
OUT4
Waveform output pin for output compare OCU4
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the hold function disabled.
P35
8
10
G
HAK
OUT5
11
Hold acknowledge output pin. This function is enabled when both
the external bus and the hold function are enabled.
Waveform output pin for output compare OCU5
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the external ready function disabled.
P36
9
Function
G
RDY
Ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
OUT6
Waveform output pin for output compare OCU6
(Continued)
10
MB90860A Series
Pin No.
LQFP100*
2
QFP100*
1
Pin name
Circuit
type
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled either in
single-chip mode or with the CLK output disabled.
P37
10
12
G
CLK
OUT7
11 to 12
13 to 14
18
P40 , P41
F
General purpose I/O (devices with S-suffix)
X0A , X1A
B
Oscillator input pins for sub-clock (devices without S-suffix)
IN6
RX1
General purpose I/O
F
INT9R
18
19
20
IN7
F
TX Output pin for CAN1 (MB90V340 (S) only)
P44
General purpose I/O
SDA0
H
SCL0
22
21
23
P46
SDA1
P47
SCL1
General purpose I/O
H
23
24
25
AN8
H
H
O
Serial clock I/O pin for I2C 1
Analog input pin for the A/D converter
P51
General purpose I/O
AN9
I
AN10
AN11
TIN3
Analog input pin for the A/D converter
Serial data output pin for UART2
General purpose I/O
I
Analog input pin for the A/D converter
Clock I/O pin for UART2
P53
27
General purpose I/O
Serial data input pin for UART2
SCK2
25
Serial data I/O pin for I2C 1
SIN2
P52
26
General purpose I/O
General purpose I/O
SOT2
24
Serial clock I/O pin for I2C 0
Input for the 16-bit I/O Timer 1
P50
22
Serial data I/O pin for I2C 0
Input for the 16-bit I/O Timer 0
FRCK1
20
Data sample input pin for input capture ICU7
TX1
P45
21
RX input pin for CAN1 (MB90V340 (S) only)
General purpose I/O
FRCK0
19
Data sample input pin for input capture ICU6
Sub external interrupt request input pin for INT10
P43
17
CLK output pin. This function is enabled when both the
external bus and CLK output are enabled.
Waveform output pin for output compare OCU7
P42
16
Function
General purpose I/O
I
Analog input pin for the A/D converter
Event input pin for the reload timer 3
(Continued)
11
MB90860A Series
Pin No.
LQFP100*
2
QFP100*
1
Pin name
Circuit
type
P54
26
28
AN12
General purpose I/O
I
TOT3
27
29
P55
AN13
30, 31
AN14 to AN15
I
J
43 to 48,
53, 54
45 to 50,
55, 56
AN0 to AN7
I
Output pins for PPGs
P70 to P77
General purpose I/O
AN16 to AN23
I
TIN0
ADTG
General purpose I/O
F
TOT0
CKOT
F
SIN0
TIN2
M
SOT0
F
SCK0
General purpose I/O
F
INT15R
60
62
61
63
P85
SIN1
P86
SOT1
Serial data output pin for UART0
Output pin for the reload timer 2
P84
61
Event input pin for the reload timers 2
General purpose I/O
TOT2
59
Serial data input pin for UART0
Sub external interrupt request input pin for INT14
P83
60
Output pin for the clock monitor
General purpose I/O
INT14R
58
Output pin for the reload timer 0
Sub external interrupt request input pin for INT13
P82
59
Trigger input pin for the A/D converter
General purpose I/O
INT13R
57
Event input pin for the reload timers 0
Sub external interrupt request input pin for INT12
P81
58
Analog input pins for the A/D converter (devices with C-suffix)
External interrupt request input pins for INT0 to INT7
INT12R
56
Analog input pins for the A/D converter
PPG0, 2, 4, 6,
8, A, C, E
P80
57
Analog input pin for the A/D converter
General purpose I/O
INT0 to INT7
55
Analog input pin for the A/D converter
D/A converter analog output pins (MB90V340 only)
P60 to P67
36 to 43
General purpose I/O
General purpose I/O
DA00 to DA01
34 to 41
Analog input pin for the A/D converter
Output pin for the reload timer 3
P56 to P57
28, 29
Function
Clock I/O pin for UART0
Sub external interrupt request input pin for INT15
M
F
General purpose I/O
Serial data input pin for UART1
General purpose I/O
Serial data output pin for UART1
(Continued)
12
MB90860A Series
(Continued)
Pin No.
2
1
LQFP100*
QFP100*
62
64
65 to 68
67 to 70
Pin name
P87
SCK1
P90 to P93
PPG1, 3, 5, 7
Circuit
type
F
F
P94 to P97
69 to 72
71 to 74
OUT0 to
OUT3
75
RX0
F
Clock I/O pin for UART1
General purpose I/O
Output pins for PPGs
Waveform output pins for output compares OCU0 to OCU3.
This function is enabled when the OCU enables waveform
output.
General purpose I/O
F
INT8R
PA1
General purpose I/O
General purpose I/O
PA0
73
Function
RX input pin for CAN0 (MB90V340 (s) only)
Sub external interrupt request input pin for INT8
76
30
32
AVCC
K
Vcc power input pin for analog circuits
31
33
AVRH
L
Reference voltage input for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or
equal to AVRH is applied to AVCC.
32
34
AVRL
K
Lower reference voltage input for the A/D Converter
33
35
AVSS
K
Vss power input pin for analog circuits
50, 51
52, 53
MD1, MD0
C
Input pins for specifying the operating mode. The pins must be
directly connected to Vcc or Vss
49
51
MD2
D
Input pin for specifying the operating mode. The pins must be
directly connected to Vcc or Vss.
13
63
88
15
65
90
VCC
Power (3.5 V to 5.5 V) input pins
14
42
64
89
16
44
66
91
VSS
Power (0V) input pins
15
17
C
K
This is the power supply stabilization capacitor pin. It should be
connected to a higher than or equal to 0.1 µF ceramic capacitor.
TX0
F
General purpose I/O
74
TX Output pin for CAN0 (MB90V340 (s) only)
*1 : FPT-100P-M06
*2 : FPT-100P-M05
13
MB90860A Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1
A
Remarks
Xout
Oscillation circuit
• High-speed oscillation feedback
resistor = approx. 1 MΩ
X0
Standby control signal
X1A
B
Xout
Oscillation circuit
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
X0A
Standby control signal
Mask ROM and EVA device:
• CMOS Hysteresis input pin
C
R
Hysteresis
inputs
R
Hysteresis
inputs
D
Pull-down
Resistor
Flash device:
• CMOS input pin
Mask ROM and EVA device:
• CMOS Hysteresis input pin
• Pull-down resistor valule: approx. 50 kΩ
Flash device:
• CMOS input pin
• No Pull-down
CMOS Hysteresis input pin
• Pull-up resistor valule: approx. 50 kΩ
E
Pull-up
Resistor
R
Hysteresis
inputs
(Continued)
14
MB90860A Series
Type
Circuit
Remarks
Pout
Nout
F
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
pull-up control
Pout
Nout
G
R
Hysteresis inputs
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
• Programmalble pullup resistor: 50 kΩ
approx.
Automotive inputs
TTL input
Standby control for
input shutdown
Pout
Nout
H
• CMOS level output(IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
15
MB90860A Series
Type
Circuit
Remarks
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standbytime input shutdown function)
• Automotive input (With the standby-time input shutdown function)
• A/D analog input
Pout
Nout
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• D/A analg output
• CMOS hysteresis inputs (With the standbytime input shutdown function)
• Automotive input (With the standby-time input shutdown function)
• A/D analog input
Pout
Nout
R
J
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Analog output
• Power supply input protection circuit
K
ANE
L
AVR
• A/D converter reference voltage power
supply input pin, with the protection circuit
• Flash devices do not have a protection circuit against VCC for pin AVRH
ANE
(Continued)
16
MB90860A Series
(Continued)
Type
Circuit
Pout
Nout
M
Remarks
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
R
CMOS inputs
Automotive inputs
Standby control for
input shutdown
pull-up control
Pout
Nout
N
R
CMOS inputs
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
Programmable pullup registor:50 kΩ
approx.
Automotive inputs
TTL input
Standby control for
input shutdown
Pout
Nout
R
O
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• A/D analog input
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
17
MB90860A Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on(External-bus mode)
• Flash security Function
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90860A Series
X0
Open
X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
18
MB90860A Series
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90860A
Series
Vcc
Vss
Vss
Vcc
7. Pull-up/down resistors
The MB90860A Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
19
MB90860A Series
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
VDD5
VDD3
Port0 to Port3
Port0 to 3 outputs
might be unstable
Port0 to 3 outputs = Hi-Z
15. Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01H is written in the security byte, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
MB90F867A (S)
20
Flash memory size
Address for security byte
Embedded 1 Mbit Flash Memory
FE0001H
MB90860A Series
■ BLOCK DIAGRAMS
MB90V340(S)
X0,X1
X0A,X1A*
RST
Clock
Controller
16LX
CPU
IO Timer 0
RAM 30 K
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
DA01, DA00
Input
Capture
8 ch
IN7 to IN0
Output
Compare
8 ch
OUT7 to OUT0
Prescaler
5 ch
IO Timer 1
UART
5 ch
CAN
Controller
3 ch
16-bit Reload
Timer 4 ch
FRCK1
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
10-bit ADC
24 ch
AD15 to AD00
10-bit
DAC
2 ch
FMC-16 Bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
FRCK0
A23 to A16
ALE
RD
External
Bus
Interface
WRL
WRH
HRQ
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
HAK
8/16-bit
PPG
16 ch
I2C
Interface
2 ch
DMAC
RDY
CLK
External
Interrupt
Clock
Monitor
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
CKOT
* : Only for MB90V340 ( without ‘S’ Suffix )
21
MB90860A Series
MB90F867A (S) , MB90867A (S)
X0,X1
X0A,X1A*
RST
Clock
Controller
16LX
CPU
IO Timer 0
RAM
6K
ROM/Flash
128 K
Prescaler
4 ch
AVCC
AVSS
AN15 to AN0
AN23 to AN16
AVRH
AVRL
ADTG
PPGF to PPG0
Input
Capture
8 ch
IN7 to IN0
Output
Compare
8 ch
OUT7 to OUT0
IO Timer 1
FRCK1
UART
4 ch
16-bit Reload
Timer 4 ch
TIN3 to TIN0
TOT3 to TOT0
10-bit ADC
16/24 ch
AD15 to AD00
FMC-16 Bus
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
FRCK0
A23 to A16
ALE
RD
External
Bus
Interface
8/16-bit
PPG
16 ch
WRL
WRH
HRQ
HAK
RDY
SDA1, SDA0
SCL1, SCL0
CLK
I2C
Interface
2 ch
External
Interrupt
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DMAC
Clock
Monitor
* : Only for devices without ‘S’ Suffix
22
CKOT
MB90860A Series
■ MEMORY MAP
MB90867A (S)
MB90F867A (S)
MB90V340 (S)
FFFFFFH
FFFFFFH
ROM(FF bank)
ROM(FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM(FE bank)
ROM(FE bank)
FE0000H
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
008000H
007FFFH
007900H
0078FFH
ROM
(Image of FF bank)
00FFFFH
008000H
007FFFH
Peripheral
ROM
(Image of FF bank)
Peripheral
007900H
RAM 30 K
0018FFH
RAM 6 K
000100H
000100H
0000EFH
000000H
Peripheral
0000EFH
000000H
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
23
MB90860A Series
■ I/O MAP
Address
Register
Abbreviation
Access
Resource name
Initial value
00H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXX
01H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXX
02H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXX
03H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXX
04H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXX
05H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXX
06H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXX
07H
Port 7 Data Register
PDR7
R/W
Port 7
XXXXXXXX
08H
Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXX
09H
Port 9 Data Register
PDR9
R/W
Port 9
XXXXXXXX
0AH
Port A Data Register
PDRA
R/W
Port A
XXXXXXXX
0BH
Port 5 Analog Input Enable Register
ADER5
R/W
Port 5, A/D
11111111
0CH
Port 6 Analog Input Enable Register
ADER6
R/W
Port 6, A/D
11111111
0DH
Port 7 Analog Input Enable Register
ADER7
R/W
Port 7, A/D
11111111
0EH
Input Level Select Register 0
ILSR0
R/W
Ports
00000000
0FH
Input Level Select Register 1
ILSR1
R/W
Ports
00000000
10H
Port 0 Direction Register
DDR0
R/W
Port 0
00000000
11H
Port 1 Direction Register
DDR1
R/W
Port 1
00000000
12H
Port 2 Direction Register
DDR2
R/W
Port 2
00000000
13H
Port 3 Direction Register
DDR3
R/W
Port 3
00000000
14H
Port 4 Direction Register
DDR4
R/W
Port 4
00000000
15H
Port 5 Direction Register
DDR5
R/W
Port 5
00000000
16H
Port 6 Direction Register
DDR6
R/W
Port 6
00000000
17H
Port 7 Direction Register
DDR7
R/W
Port 7
00000000
18H
Port 8 Direction Register
DDR8
R/W
Port 8
00000000
19H
Port 9 Direction Register
DDR9
R/W
Port 9
00000000
1AH
Port A Direction Register
DDRA
R/W
Port A
00000100
1BH
Reserved
1CH
Port 0 Pullup Control Register
PUCR0
R/W
Port 0
00000000
1DH
Port 1 Pullup Control Register
PUCR1
R/W
Port 1
00000000
1EH
Port 2 Pullup Control Register
PUCR2
R/W
Port 2
00000000
1FH
Port 3 Pullup Control Register
PUCR3
R/W
Port 3
00000000
(Continued)
24
MB90860A Series
Address
Register
Abbreviation
Access
Resource name
Initial value
20H
Serial Mode Register 0
SMR0
W, R/W
00000000
21H
Serial Control Register 0
SCR0
W, R/W
00000000
22H
Reception/Transmission Data Register 0
RDR0/
TDR0
R/W
00000000
23H
Serial Status Register 0
SSR0
R, R/W
24H
Extended Communication Control Reg. 0
ECCR0
R, W,
R/W
25H
Extended Status/Control Register 0
ESCR0
R/W
00000100
26H
Baud Rate Generator Register 00
BGR00
R/W
00000000
27H
Baud Rate Generator Register 01
BGR01
R/W
00000000
28H
Serial Mode Register 1
SMR1
W, R/W
00000000
29H
Serial Control Register 1
SCR1
W, R/W
00000000
2AH
Reception/Transmission Data Register 1
RDR1/
TDR1
R/W
00000000
2BH
Serial Status Register 1
SSR1
R, R/W
2CH
Extended Communication Control Reg. 1
ECCR1
R, W,
R/W
2DH
Extended Status Control Register 1
ESCR1
R/W
00000100
2EH
Baud Rate Generator Register 10
BGR10
R/W
00000000
2FH
Baud Rate Generator Register 11
BGR11
R/W
00000000
30H
PPG 0 Operation Mode Control Register
PPGC0
W, R/W
0X000XX1
31H
PPG 1 Operation Mode Control Register
PPGC1
W, R/W
32H
PPG 01 Clock Select Register
PPG01
R/W
000000X0
0X000XX1
UART0
00001000
000000XX
UART1
00001000
000000XX
16-bit PPG 0/1
0X000001
Reserved
33H
34H
PPG 2 Operation Mode Control Register
PPGC2
W, R/W
35H
PPG 3 Operation Mode Control Register
PPGC3
W, R/W
36H
PPG 23 Clock Select Register
PPG23
R/W
000000X0
0X000XX1
0X000001
Reserved
37H
38H
PPG 4 Operation Mode Control Register
PPGC4
W, R/W
39H
PPG 5 Operation Mode Control Register
PPGC5
W, R/W
3AH
PPG 4 and PPG 5 Clock Select Register
PPG45
R/W
3BH
Program Address Detection Control
Status Register 1
PACSR1
R/W
3CH
PPG 6 Operation Mode Control Register
PPGC6
W, R/W
3DH
PPG 7 Operation Mode Control Register
PPGC7
W, R/W
3EH
PPG 67 Clock Select Register
PPG67
R/W
3FH
16-bit PPG 2/3
16-bit PPG 4/5
0X000001
000000X0
Address Match
Detection 1
00000000
0X000XX1
16-bit PPG 6/7
0X000001
000000X0
Reserved
(Continued)
25
MB90860A Series
Address
Register
Abbreviation
Access
Resource name
Initial value
40H
PPG 8 Operation Mode Control Register
PPGC8
W, R/W
41H
PPG 9 Operation Mode Control Register
PPGC9
W, R/W
42H
PPG 89 Clock Select Register
PPG89
R/W
000000X0
0X000XX1
43H
0X000XX1
16-bit PPG 8/9
0X000001
Reserved
44H
PPG A Operation Mode Control Register
PPGCA
W, R/W
45H
PPG B Operation Mode Control Register
PPGCB
W, R/W
46H
PPG AB Clock Select Register
PPGAB
R/W
000000X0
0X000XX1
16-bit PPG A/B
0X000001
Reserved
47H
48H
PPG C Operation Mode Control Register
PPGCC
W, R/W
49H
PPG D Operation Mode Control Register
PPGCD
W, R/W
4AH
PPG CD Clock Select Register
PPGCD
R/W
000000X0
0X000XX1
4BH
16-bit PPG C/D
0X000001
Reserved
4CH
PPG E Operation Mode Control Register
PPGCE
W, R/W
4DH
PPG F Operation Mode Control Register
PPGCF
W, R/W
4EH
PPG EF Clock Select Register
PPGEF
R/W
4FH
16-bit PPG E/F
0X000001
000000X0
Reserved
50H
Input Capture Control Status Register 0/1
ICS01
R/W
51H
Input Capture Edge Register 0/1
ICE01
R/W, R
52H
Input Capture Control Status Register 2/3
ICS23
R/W
53H
Input Capture Edge Register 2/3
ICE23
R
54H
Input Capture Control Status Register 4/5
ICS45
R/W
55H
Input Capture Edge Register 4/5
ICE45
R
56H
Input Capture Control Status Register 6/7
ICS67
R/W
57H
Input Capture Edge Register 6/7
ICE67
R/W, R
58H
Output Compare Control Status Register 0
OCS0
R/W
59H
Output Compare Control Status Register 1
OCS1
R/W
5AH
Output Compare Control Status Register 2
OCS2
R/W
5BH
Output Compare Control Status Register 3
OCS3
R/W
5CH
Output Compare Control Status Register 4
OCS4
R/W
5DH
Output Compare Control Status Register 5
OCS5
R/W
5EH
Output Compare Control Status Register 6
OCS6
R/W
5FH
Output Compare Control Status Register 7
OCS7
R/W
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
00000000
XXX0X0XX
00000000
XXXXXXXX
00000000
XXXXXXXX
00000000
XXX000XX
0000XX00
0XX00000
0000XX00
0XX00000
0000XX00
0XX00000
0000XX00
0XX00000
(Continued)
26
MB90860A Series
Address
Register
Abbreviation
Access
Resource name
Initial value
60H
Timer Control Status Register 0
TMCSR0
R/W
61H
Timer Control Status Register 0
TMCSR0
R/W
62H
Timer Control Status Register 1
TMCSR1
R/W
63H
Timer Control Status Register 1
TMCSR1
R/W
64H
Timer Control Status Register 2
TMCSR2
R/W
65H
Timer Control Status Register 2
TMCSR2
R/W
66H
Timer Control Status Register 3
TMCSR3
R/W
67H
Timer Control Status Register 3
TMCSR3
R/W
68H
A/D Control Status Register 0
ADCS0
R/W
000XXXX0
69H
A/D Control Status Register 1
ADCS1
R/W
0000000X
6AH
A/D Data Register 0
ADCR0
R
6BH
A/D Data Register 1
ADCR1
R
6CH
ADC Setting Register 0
ADSR0
R/W
00000000
6DH
ADC Setting Register 1
ADSR1
R/W
00000000
6EH
6FH
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
A/D Converter
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXXXX00
Reserved
ROM Mirroring Register
ROMM
W
70H to 8FH
Reserved
90H to 9AH
Reserved
ROM Mirror
XXXXXXX1
9BH
DMA Descriptor Channel Specification
Register
DCSR
R/W
9CH
DMA Status Register L
DSRL
R/W
9DH
DMA Status Register H
DSRH
R/W
9EH
Program Address Detection Control
Status Register 0
PACSR0
R/W
Address Match
Detection 0
00000000
9FH
Delayed Interrupt/Release
DIRR
R/W
Delayed Interrupt
XXXXXXX0
A0H
Low-power Mode Control Register
LPMCR
W, R/W
Low Power
Controller
00011000
A1H
Clock Selection Register
CKSCR
R, R/W
Low Power
Controller
11111100
DMA
00000000
A2H, A3H
00000000
DMA
00000000
00000000
Reserved
A4H
DMA Stop Status Register
DSSR
R/W
A5H
Automatic Ready Function Select Reg.
ARSR
W
0011XX00
External Memory
Access
A6H
External Address Output Control Reg.
HACR
W
A7H
Bus Control Signal Selection Register
ECSR
W
A8H
Watchdog Control Register
WDTC
R, W
Watchdog Timer
XXXXX111
A9H
Timebase Timer Control Register
TBTC
W, R/W
Time Base Timer
1XX00100
00000000
0000000X
(Continued)
27
MB90860A Series
Address
AAH
Register
Watch Timer Control Register
ABH
Abbreviation
Access
Resource name
Initial value
WTC
R, R/W
Watch Timer
1X001000
Reserved
ACH
DMA Enable Register L
DERL
R/W
ADH
DMA Enable Register H
DERH
R/W
AEH
Flash Control Status Register
(FlashDevices only.
Otherwise reserved)
FMCS
R, R/W
AFH
DMA
Flash Memory
00000000
00000000
000X0000
Reserved
B0H
Interrupt Control Register 00
ICR00
W, R/W
00000111
B1H
Interrupt Control Register 01
ICR01
W, R/W
00000111
B2H
Interrupt Control Register 02
ICR02
W, R/W
00000111
B3H
Interrupt Control Register 03
ICR03
W, R/W
00000111
B4H
Interrupt Control Register 04
ICR04
W, R/W
00000111
B5H
Interrupt Control Register 05
ICR05
W, R/W
00000111
B6H
Interrupt Control Register 06
ICR06
W, R/W
00000111
B7H
Interrupt Control Register 07
ICR07
W, R/W
B8H
Interrupt Control Register 08
ICR08
W, R/W
B9H
Interrupt Control Register 09
ICR09
W, R/W
00000111
BAH
Interrupt Control Register 10
ICR10
W, R/W
00000111
BBH
Interrupt Control Register 11
ICR11
W, R/W
00000111
BCH
Interrupt Control Register 12
ICR12
W, R/W
00000111
BDH
Interrupt Control Register 13
ICR13
W, R/W
00000111
BEH
Interrupt Control Register 14
ICR14
W, R/W
00000111
BFH
Interrupt Control Register 15
ICR15
W, R/W
00000111
C0H
D/A Converter Data 0
DAT0
R/W
XXXXXXXX
C1H
D/A Converter Data 1
DAT1
R/W
C2H
D/A Control 0
DACR0
R/W
C3H
D/A Control 1
DACR1
R/W
XXXXXXX0
00000000
C4H, C5H
Interrupt Controller
D/A Converter
00000111
00000111
XXXXXXXX
XXXXXXX0
Reserved
C6H
External Interrupt Request Enable
Register 0
ENIR0
R/W
C7H
External Interrupt Request Register 0
EIRR0
R/W
C8H
External Interrupt Level Register 0
ELVR0
R/W
00000000
C9H
External Interrupt Level Register 0
ELVR0
R/W
00000000
External Interrupt 0
XXXXXXXX
(Continued)
28
MB90860A Series
Address
Register
Abbreviation
Access
Resource name
Initial value
CAH
External Interrupt Request Enable
Register 1
ENIR1
R/W
00000000
CBH
External Interrupt Request Register 1
EIRR1
R/W
XXXXXXXX
CCH
External Interrupt Level Register 1
ELVR1
R/W
CDH
External Interrupt Level Register 1
ELVR1
R/W
00000000
CEH
External Interrupt Source Select
Register
EISSR
R/W
00000000
CFH
PLL/Subclock Control Register
PSCCR
W
D0H
DMA Buffer Address Pointer L
BAPL
R/W
XXXXXXXX
D1H
DMA Buffer Address Pointer M
BAPM
R/W
XXXXXXXX
D2H
DMA Buffer Address Pointer H
BAPH
R/W
XXXXXXXX
D3H
DMA Control Register
DMACS
R/W
D4H
I/O Register Address Pointer L
IOAL
R/W
D5H
I/O Register Address Pointer H
IOAH
R/W
XXXXXXXX
D6H
Data Counter L
DCTL
R/W
XXXXXXXX
D7H
Data Counter H
DCTH
R/W
XXXXXXXX
D8H
Serial Mode Register 2
SMR2
W, R/W
00000000
D9H
Serial Control Register 2
SCR2
W, R/W
00000000
DAH
Reception/Transmission Data
Register 2
RDR2/
TDR2
R/W
00000000
DBH
Serial Status Register 2
SSR2
R, R/W
DCH
Extended Communication Control
Register 2
ECCR2
R, W,
R/W
DDH
Extended Status/Control Register 2
ESCR2
R/W
00000100
DEH
Baud Rate Reload Register 20
BGR20
R/W
00000000
DFH
Baud Rate Reload Register 21
BGR21
R/W
00000000
E0H to EFH
Reserved
F0H to FFH
External
External Interrupt 1
PLL
DMA
UART2
00000000
XXXX0000
XXXXXXXX
XXXXXXXX
00001000
000000XX
(Continued)
29
MB90860A Series
Address
Register
Abbreviation
Access
Resource name
Initial value
7900H
Reload Register L0
PRLL0
R/W
7901H
Reload Register H0
PRLH0
R/W
7902H
Reload Register L1
PRLL1
R/W
7903H
Reload Register H1
PRLH1
R/W
XXXXXXXX
7904H
Reload Register L2
PRLL2
R/W
XXXXXXXX
7905H
Reload Register H2
PRLH2
R/W
7906H
Reload Register L3
PRLL3
R/W
7907H
Reload Register H3
PRLH3
R/W
XXXXXXXX
7908H
Reload Register L4
PRLL4
R/W
XXXXXXXX
7909H
Reload Register H4
PRLH4
R/W
790AH
Reload Register L5
PRLL5
R/W
790BH
Reload Register H5
PRLH5
R/W
XXXXXXXX
790CH
Reload Register L6
PRLL6
R/W
XXXXXXXX
790DH
Reload Register H6
PRLH6
R/W
790EH
Reload Register L7
PRLL7
R/W
790FH
Reload Register H7
PRLH7
R/W
XXXXXXXX
7910H
Reload Register L8
PRLL8
R/W
XXXXXXXX
7911H
Reload Register H8
PRLH8
R/W
7912H
Reload Register L9
PRLL9
R/W
7913H
Reload Register H9
PRLH9
R/W
XXXXXXXX
7914H
Reload Register LA
PRLLA
R/W
XXXXXXXX
7915H
Reload Register HA
PRLHA
R/W
7916H
Reload Register LB
PRLLB
R/W
7917H
Reload Register HB
PRLHB
R/W
XXXXXXXX
7918H
Reload Register LC
PRLLC
R/W
XXXXXXXX
7919H
Reload Register HC
PRLHC
R/W
791AH
Reload Register LD
PRLLD
R/W
791BH
Reload Register HD
PRLHD
R/W
XXXXXXXX
791CH
Reload Register LE
PRLLE
R/W
XXXXXXXX
791DH
Reload Register HE
PRLHE
R/W
791EH
Reload Register LF
PRLLF
R/W
791FH
Reload Register HF
PRLHF
R/W
XXXXXXXX
7920H
Input Capture Data Register 0
IPCP0
R
XXXXXXXX
7921H
Input Capture Data Register 0
IPCP0
R
7922H
Input Capture Data Register 1
IPCP1
R
7923H
Input Capture Data Register 1
IPCP1
R
XXXXXXXX
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
16-bit PPG 6/7
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
30
MB90860A Series
Address
Register
Abbreviation
Access
Resource name
Initial value
7924H
Input Capture Data Register 2
IPCP2
R
7925H
Input Capture Data Register 2
IPCP2
R
7926H
Input Capture Data Register 3
IPCP3
R
7927H
Input Capture Data Register 3
IPCP3
R
XXXXXXXX
7928H
Input Capture Data Register 4
IPCP4
R
XXXXXXXX
7929H
Input Capture Data Register 4
IPCP4
R
792AH
Input Capture Data Register 5
IPCP5
R
792BH
Input Capture Data Register 5
IPCP5
R
XXXXXXXX
792CH
Input Capture Data Register 6
IPCP6
R
XXXXXXXX
792DH
Input Capture Data Register 6
IPCP6
R
792EH
Input Capture Data Register 7
IPCP7
R
792FH
Input Capture Data Register 7
IPCP7
R
XXXXXXXX
7930H
Output Compare Register 0
OCCP0
R/W
XXXXXXXX
7931H
Output Compare Register 0
OCCP0
R/W
7932H
Output Compare Register 1
OCCP1
R/W
7933H
Output Compare Register 1
OCCP1
R/W
XXXXXXXX
7934H
Output Compare Register 2
OCCP2
R/W
XXXXXXXX
7935H
Output Compare Register 2
OCCP2
R/W
7936H
Output Compare Register 3
OCCP3
R/W
7937H
Output Compare Register 3
OCCP3
R/W
XXXXXXXX
7938H
Output Compare Register 4
OCCP4
R/W
XXXXXXXX
7939H
Output Compare Register 4
OCCP4
R/W
793AH
Output Compare Register 5
OCCP5
R/W
793BH
Output Compare Register 5
OCCP5
R/W
XXXXXXXX
793CH
Output Compare Register 6
OCCP6
R/W
XXXXXXXX
793DH
Output Compare Register 6
OCCP6
R/W
793EH
Output Compare Register 7
OCCP7
R/W
793FH
Output Compare Register 7
OCCP7
R/W
XXXXXXXX
7940H
Data Register 0
TCDT0
R/W
00000000
7941H
Data Register 0
TCDT0
R/W
7942H
Control Status Register 0
TCCSL0
R/W
7943H
Control Status Register 0
TCCSH0
R/W
0XXXXXXX
7944H
Data Register 1
TCDT1
R/W
00000000
7945H
Data Register 1
TCDT1
R/W
7946H
Control Status Register 1
TCCSL1
R/W
7947H
Control Status Register 1
TCCSH1
R/W
XXXXXXXX
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
I/O Timer 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
00000000
0XXXXXXX
(Continued)
31
MB90860A Series
Address
7948H
7949H
794AH
794BH
794CH
794DH
794EH
794FH
Register
Abbreviation
Access
Resource name
Initial value
16-bit Reload
Timer 0
XXXXXXXX
16-bit Reload
Timer 1
XXXXXXXX
16-bit Reload
Timer 2
XXXXXXXX
16-bit Reload
Timer 3
XXXXXXXX
Timer Register 0/Reload Register 0
TMR0/
TMRLR0
R/W
Timer Register 1/Reload Register 1
TMR1/
TMRLR1
R/W
Timer Register 2/Reload Register 2
TMR2/
TMRLR2
R/W
Timer Register 3/Reload Register 3
TMR3/
TMRLR3
R/W
R/W
R/W
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
7950H
Serial Mode Register 3
SMR3
W, R/W
00000000
7951H
Serial Control Register 3
SCR3
W, R/W
00000000
7952H
Reception/Transmission Data Register 3
RDR3/
TDR3
R/W
00000000
7953H
Serial Status Register 3
SSR3
R, R/W
7954H
Extended Communication Control Reg. 3
ECCR3
R, W,
R/W
7955H
Extended Status/Control Register 3
ESCR3
R/W
00000100
7956H
Baud Rate Reload Register 30
BGR30
R/W
00000000
7957H
Baud Rate Reload Register 31
BGR31
R/W
00000000
7958H
Serial Mode Register 4
SMR4
W, R/W
00000000
7959H
Serial Control Register 4
SCR4
W, R/W
00000000
795AH
Reception/Transmission Data Register 4
RDR4/
TDR4
R/W
00000000
795BH
Serial Status Register 4
SSR4
R, R/W
795CH
Extended Communication Control Reg. 4
ECCR4
R, W,
R/W
795DH
Extended Status/Control Register 4
ESCR4
R/W
00000100
795EH
Baud Rate Reload Register 40
BGR40
R/W
00000000
795FH
Baud Rate Reload Register 41
BGR41
R/W
00000000
7960H to
796BH
796CH
796DH to
796FH
UART3
00001000
000000XX
UART4
00001000
000000XX
Reserved
Clock Output Enable Register
CLKR
R/W
Clock Monitor
XXXX0000
Reserved
(Continued)
32
MB90860A Series
Address
7970H
7971H
7972H
7973H
7974H
7975H
7976H
7977H
7978H
Register
I2C Bus Status Register 0
2
I C Bus Control Register 0
I2C 10-bit Slave Address Register 0
I2C 10-bit Slave Address Mask Register 0
Access
IBSR0
R
00000000
IBCR0
W, R/W
00000000
ITBAL0
R/W
00000000
ITBAH0
R/W
00000000
ITMKL0
R/W
Resource name
I2C Interface 0
Initial value
11111111
ITMKH0
R/W
00111111
2
ISBA0
R/W
00000000
2
ISMK0
R/W
01111111
2
IDAR0
R/W
00000000
I C 7-bit Slave Address Register 0
I C 7-bit Slave Address Mask Register 0
I C Data Register 0
7979H,
797AH
797BH
Abbreviation
Reserved
I2C Clock Control Register 0
797CH to
797FH
ICCR0
R/W
I2C Interface 0
00011111
Reserved
7980H
I2C Bus Status Register 1
IBSR1
R
00000000
7981H
I2C Bus Control Register 1
IBCR1
W, R/W
00000000
ITBAL1
R/W
00000000
ITBAH1
R/W
7982H
7983H
7984H
7985H
I2C 10-bit Slave Address Register 1
I2C 10-bit Slave Address Mask Register 1
2
00000000
2
I C Interface 1
ITMKL1
R/W
11111111
ITMKH1
R/W
00111111
7986H
I C 7-bit Slave Address Register 1
ISBA1
R/W
00000000
7987H
I2C 7-bit Slave Address Mask Register 1
ISMK1
R/W
01111111
7988H
I2C Data Register 1
IDAR1
R/W
00000000
7989H,
798AH
798BH
Reserved
I2C Clock Control Register 1
798CH to
79C1H
79C2H
79C3H to
79DFH
ICCR1
R/W
I2C Interface 1
00011111
R, R/W
Clock Modulator
0001X000
Reserved
Clock Modulator Control Register
CMCR
Reserved
(Continued)
33
MB90860A Series
(Continued)
Address
Register
Abbreviation
Access
79E0H
Program Address Detection Register 0
PADR0
R/W
XXXXXXXX
79E1H
Program Address Detection Register 0
PADR0
R/W
XXXXXXXX
79E2H
Program Address Detection Register 0
PADR0
R/W
XXXXXXXX
79E3H
Program Address Detection Register 1
PADR1
R/W
Resource name
Initial value
XXXXXXXX
Address Match
Detection 0
79E4H
Program Address Detection Register 1
PADR1
R/W
79E5H
Program Address Detection Register 1
PADR1
R/W
XXXXXXXX
79E6H
Program Address Detection Register 2
PADR2
R/W
XXXXXXXX
79E7H
Program Address Detection Register 2
PADR2
R/W
XXXXXXXX
79E8H
Program Address Detection Register 2
PADR2
R/W
XXXXXXXX
79E9H to
79EFH
XXXXXXXX
Reserved
79F0H
Program Address Detection Register 3
PADR3
R/W
XXXXXXXX
79F1H
Program Address Detection Register 3
PADR3
R/W
XXXXXXXX
79F2H
Program Address Detection Register 3
PADR3
R/W
XXXXXXXX
79F3H
Program Address Detection Register 4
PADR4
R/W
XXXXXXXX
Address Match
Detection 1
79F4H
Program Address Detection Register 4
PADR4
R/W
79F5H
Program Address Detection Register 4
PADR4
R/W
XXXXXXXX
79F6H
Program Address Detection Register 5
PADR5
R/W
XXXXXXXX
79F7H
Program Address Detection Register 5
PADR5
R/W
XXXXXXXX
79F8H
Program Address Detection Register 5
PADR5
R/W
XXXXXXXX
79F9H to
7FFFH
XXXXXXXX
Reserved
Notes : • Initial value of “X” represents unknown value.
• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary
functions of the MCU. A read access to these reserved addresses results reading “X” and any write
access should not be performed.
34
MB90860A Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
EI2OS
clear
DMA ch
number
Reset
N
INT9 instruction
Interrupt cause
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
#08
FFFFDCH
N
#09
FFFFD8H
Exception
N
#10
FFFFD4H
(Reserved)
N
#11
FFFFD0H
(Reserved)
N
#12
FFFFCCH
ICR00
0000B0H
Input Capture 6
Y1
#13
FFFFC8H
Input Capture 7
Y1
#14
FFFFC4H
ICR01
0000B1H
I2C0
N
#15
FFFFC0H
(Reserved)
N
#16
FFFFBCH
ICR02
0000B2H
16-bit Reload Timer 0
Y1
0
#17
FFFFB8H
16-bit Reload Timer 1
Y1
1
#18
FFFFB4H
ICR03
0000B3H
16-bit Reload Timer 2
Y1
2
#19
FFFFB0H
16-bit Reload Timer 3
Y1
#20
FFFFACH
ICR04
0000B4H
PPG 0/1/4/5
N
#21
FFFFA8H
PPG 2/3/6/7
N
#22
FFFFA4H
ICR05
0000B5H
PPG 8/9/C/D
N
#23
FFFFA0H
PPG A/B/E/F
N
#24
FFFF9CH
ICR06
0000B6H
Time Base Timer
N
#25
FFFF98H
External Interrupt 0 to 3, 8 to 11
Y1
3
#26
FFFF94H
ICR07
0000B7H
Watch Timer
N
#27
FFFF90H
External Interrupt 4 to 7, 12 to 15
Y1
4
#28
FFFF8CH
ICR08
0000B8H
A/D Converter
Y1
5
#29
FFFF88H
I/O Timer 0 / I/O Timer 1
N
#30
FFFF84H
ICR09
0000B9H
Input Capture 4/5 / I2C1
Y1
6
#31
FFFF80H
Output Compare 0/1/4/5
Y1
7
#32
FFFF7CH
ICR10
0000BAH
Input Capture 0 to 3
Y1
8
#33
FFFF78H
Output Compare 2/3/6/7
Y1
9
#34
FFFF74H
ICR11
0000BBH
UART 0 RX
Y2
10
#35
FFFF70H
UART 0 TX
Y1
11
#36
FFFF6CH
ICR12
0000BCH
UART 1 RX / UART 3 RX
Y2
12
#37
FFFF68H
UART 1 TX / UART 3 TX
Y1
13
#38
FFFF64H
ICR13
0000BDH
(Continued)
35
MB90860A Series
(Continued)
EI2OS
clear
DMA ch
number
UART 2 RX / UART 4 RX
Y2
UART 2 TX / UART 4 TX
Interrupt cause
Interrupt vector
Number
Address
14
#39
FFFF60H
Y1
15
#40
FFFF5CH
Flash Memory
N
#41
FFFF58H
Delayed interrupt
N
#42
FFFF54H
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
36
MB90860A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0 V)
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC *1
AVRH,
AVRL
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
Input voltage
VI
VSS − 0.3
VSS + 6.0
V
*2
Output voltage
VO
VSS − 0.3
VSS + 6.0
V
*2
ICLAMP
−4.0
+4.0
mA
*4
Σ|ICLAMP|
40
mA
*4
IOL
15
mA
*3
“L” level average output current
IOLAV
4
mA
*3
“L” level maximum overall output current
ΣIOL
100
mA
*3
“L” level average overall output current
ΣIOLAV
50
mA
*3
IOH
−15
mA
*3
“H” level average output current
IOHAV
−4
mA
*3
“H” level maximum overall output current
ΣIOH
−100
mA
*3
“H” level average overall output current
ΣIOHAV
−50
mA
*3
Power consumption
PD
340
mW MB90F867A
Operating temperature
TA
−40
+105
°C
TSTG
−55
+150
°C
Power supply voltage
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“H” level maximum output current
Storage temperature
(Continued)
37
MB90860A Series
(Continued)
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating.
*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB90860A Series
2. Recommended Conditions
Parameter
Power supply voltage
Symbol
VCC,
AVCC
(VSS = AVSS = 0 V)
Value
Unit
Remarks
Min
Typ
Max
4.0
5.0
5.5
V
Under normal operation
3.5
5.0
5.5
V
Under normal operation, when not
using the A/D converter and not
Flash programming.
4.5
5.0
5.5
V
When External bus is used.
3.0
5.5
V
Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of better AC characteristics.
Capacitor at the VCC should be
greater than this capacitor.
Smooth capacitor
CS
0.1
1.0
µF
Operating temperature
TA
−40
+105
°C
C
CS
C Pin Connection Diagram
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
39
MB90860A Series
3. DC Characteristics
Parameter
Input H
voltage
(At VCC =
5 V ± 10%)
Input L
voltage
(At VCC =
5 V ± 10%)
Symbol
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Pin
Condition
Value
Min
Typ
Max
Unit
Remarks
VIHS
0.8 VCC
VCC + 0.3
V
Port inputs if CMOS
hysteresis input levels
are selected (except
UART SIN input pins
and I2C input pins)
VIHA
0.8 VCC
VCC + 0.3
V
Port inputs if
AUTOMOTIVE input
levels are selected
VIHT
2.0
VCC + 0.3
V
Port inputs if TTL input
levels are selected
VIHS
0.7 VCC
VCC + 0.3
V
UART SIN inputs if
CMOS input levels are
selected
VIHI
0.7 VCC
VCC + 0.3
V
I2C Port inputs if CMOS
hysteresis input levels
are selected
VIHR
0.8 VCC
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHM
VCC − 0.3
VCC + 0.3
V
MD input pin
VILS
VSS − 0.3
0.2 VCC
V
Port inputs if CMOS
hysteresis input levels
are selected (except
UART SIN input pins
and I2C input pins)
VILA
VSS − 0.3
0.5 VCC
V
Port inputs if
AUTOMOTIVE input
levels are selected
VILT
VSS − 0.3
0.8
V
Port inputs if TTL
input levels are selected
VILS
VSS − 0.3
0.3 VCC
V
UART SIN inputs if
CMOS input levels are
selected
VILI
VSS − 0.3
0.3 VCC
V
I2C Port inputs if CMOS
hysteresis input levels
are selected
VILR
VSS − 0.3
0.2 VCC
V
RST input pin (CMOS
hysteresis)
VILM
VSS − 0.3
VSS + 0.3
V
MD input pin
Output H
voltage
VOH
Normal
outputs
VCC = 4.5 V,
VCC − 0.5
IOH = −4.0 mA
V
Output H
voltage
VOHI
I2C current VCC = 4.5 V,
VCC − 0.5
outputs
IOH = −3.0 mA
V
Output L
voltage
VOL
Normal
outputs
VCC = 4.5 V,
IOL = 4.0 mA
0.4
V
Output L
voltage
VOLI
I2C current VCC = 4.5 V,
outputs
IOL = 3.0 mA
0.4
V
(Continued)
40
MB90860A Series
(Continued)
(TA = −40 °C to +105, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Parameter
Symbol
Input leak current
IIL
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-down
resistance
RDOWN
MD2
Pin
Input capacity
Value
Unit
Remarks
Min
Typ
Max
−1
1
µA
25
50
100
kΩ
25
50
100
kΩ
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
55
70
mA MB90F867A
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing FLASH memory.
70
85
mA MB90F867A
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing FLASH memory.
75
90
mA MB90F867A
ICCS
VCC = 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
25
35
mA MB90F867A
ICTS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
0.3
0.8
mA MB90F867A
ICTSPLL6
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency = 4 MHz
4
7
mA MB90F867A
ICCL
VCC = 5.0V
Internal frequency: 8 kHz,
At sub operation
TA = +25°C
170
360
µA MB90F867A
ICCLS
VCC = 5.0V
Internal frequency: 8 kHz,
At sub sleep
TA = +25°C
20
50
µA MB90F867A
ICCT
VCC = 5.0V
Internal frequency: 8 kHz,
At watch mode
TA = +25°C
10
35
µA MB90F867A
ICCH
VCC = 5.0 V,
At Stop mode,
TA = +25°C
7
25
µA MB90F867A
5
15
pF
ICC
Power supply
current*
Condition
CIN
VCC
VCC = 5.5 V, VSS < VI < VCC
Other than C, AVCC, AVSS,
AVRH, AVRL, VCC, VSS,
Except Flash
devices
* : Current values are tentative. They are subject to change without notice according to improvements in the
characteristics. The power supply current is measured with an external clock.
41
MB90860A Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Parameter
Symbol
Value
Pin
Unit
Remarks
Min
Typ
Max
X0, X1
3
16
MHz
When using an oscillation
circuit
X0
3
24
MHz
When using an external
clock*
X0A, X1A
—
32.768
100
kHz
X0, X1
62.5
333
ns
When using an oscillation
circuit
X0
41.67
333
ns
When using an external
clock
tCYLL
X0A, X1A
10
30.5
—
µs
PWH, PWL
X0
10
ns
PWHL, PWLL
X0A
5
15.2
µs
Duty ratio is about 30% to
70%.
Input clock rise and fall time
tCR, tCF
X0
5
ns
When using external clock
Internal operating clock
frequency (machine clock)
fCP
1.5
24
MHz
When using main clock
fCPL
8.192
50
kHz
When using sub clock
tCP
41.67
666
ns
When using main clock
tCPL
20
122.1
µs
When using sub clock
fC
Clock frequency
fCL
tCYL
Clock cycle time
Input clock pulse width
Internal operating clock
cycle time (machine clock)
* : Whem selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCF
Clock Timing
42
tCR
MB90860A Series
• Guaranteed PLL operation range
Guaranteed operation range
Power supply voltage VCC (V)
Guaranteed PLLL operation range (CS2=1)
5.5
Guaranteed A/D converter
operation range
4.5
3.5
Guaranteed PLL operation range (CS=0)
1.5
4
8
Machine clock fCP (MHz)
20
24
Guaranteed operation range of MB90860A Series
Machine clock fCP (MHz)
CS2 (bit0 in PSCCR reigster) = 0
×4
×3
(CS=11) (CS=10)
Guaranteed operation frequency range*2
×2
(CS=01)
×1
(CS=00)
20
16
×1/2
(PLL off)
12
8
4.0
1.5
3 4
8
12
External clock fC (MHz)
1
CS2 (bit0 in PSCCR reigster) = 1
Machine clock fCP (MHz)
24
×6
×4
(CS=10) (CS=01)
16
20
24
Guaranteed operation frequency range*2
×2
(CS=00)
16
×1/2
(PLL off)
12
8
4.0
1.5
3 4
8
12
External clock fC (MHz)
16
24
1
*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 20 MHz.
*2 : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.
External clock frequency and Machine clock frequency
43
MB90860A Series
(2) Reset Standby Input
Parameter
Reset input
time
Symbol
tRSTL
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Pin
RST
Value
Unit
Remarks
Min
Max
500
ns
Under normal operation
Oscillation time of oscillator*
+ 100 µs
ns
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
100
µs
In Time Timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal operation
clock
100 ms
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
44
MB90860A Series
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Condition
Value
Unit
Min
Max
0.05
30
ms
1
ms
Remarks
Due to repetitive operation
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
VSS
Holds RAM data
45
MB90860A Series
(4) Bus Timing (Read)
Parameter
46
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
SymPin
Condition
Unit Remarks
bol
Min
Max
ALE pulse width
tLHLL
ALE
tCP/2 − 10
ns
Valid address ⇒ ALE ↓ time
tAVLL
ALE, A23 to
A16, AD15
to AD00
tCP/2 − 15
ns
ALE ↓ ⇒ Address valid time
tLLAX
ALE, AD15
to AD00
tCP/2 − 15
ns
Valid address ⇒ RD ↓ time
tAVRL
A23 toA16,
AD15 to
AD00, RD
tCP − 15
ns
Valid address ⇒ Valid data
input
tAVDV
A23 to A16,
AD15 to
AD00
5 tCP/2 − 40
ns
RD pulse width
tRLRH
RD
3 tCP/2 − 20
ns
RD ↓ ⇒ Valid data input
tRLDV
RD, AD15 to
AD00
3 tCP/2 − 50
ns
RD ↑ ⇒ Data hold time
tRHDX
RD, AD15 to
AD00
0
ns
RD ↓ ⇒ ALE ↑ time
tRHLH
RD, ALE
tCP/2 − 15
ns
RD ↑ ⇒ Address valid time
tRHAX
RD, A23 to
A16
tCP/2 − 10
ns
Valid address ⇒ CLK ↑ time
tAVCH
A23 to A16,
AD15 to
AD00, CLK
tCP/2 − 15
ns
RD ↓ ⇒ CLK ↑ time
tRLCH
RD, CLK
tCP/2 − 15
ns
ALE ↓ ⇒ RD ↓ time
tLLRL
ALE, RD
tCP/2 − 15
ns
MB90860A Series
tRLCH
tAVCH
2.4 V
CLK
2.4 V
tLLAX
tAVLL
ALE
2.4 V
tRHLH
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
AD15 to AD00
2.4 V
0.8 V
2.4 V
Address
0.8 V
VIH
VIL
VIH
Read data
VIL
47
MB90860A Series
(5) Bus Timing (Write)
Parameter
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
Symbol
Pin
Condition
Unit Remarks
Min
Max
Valid address ⇒ WR ↓ time
tAVWL
A23 to A16,
AD15 to AD00,
WR
WR pulse width
tWLWH
Valid data output ⇒ WR ↑
time
tCP−15
ns
WR
3 tCP/2 − 20
ns
tDVWH
AD15 to AD00,
WR
3 tCP/2 − 20
ns
WR ↑ ⇒ Data hold time
tWHDX
AD15 to AD00,
WR
15
ns
WR ↑ ⇒ Address valid time
tWHAX
A23 to A16,
WR
tCP/2 − 10
ns
WR ↑ ⇒ ALE ↑ time
tWHLH
WR, ALE
tCP/2 − 15
ns
WR ↓ ⇒ CLK ↑ time
tWLCH
WR, CLK
tCP/2 − 15
ns
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
2.4 V
0.8 V
48
2.4 V
2.4 V
Address
0.8 V
tWHDX
Write data
0.8 V
MB90860A Series
(6) Ready Input Timing
Parameter
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
SymTest
Pin
Units Remarks
bol
Condition
Min
Max
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
45
ns
0
ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
RDY
When WAIT is not used.
RDY
When WAIT is used.
tRYHS
tRYHH
VIH
VIH
VIL
49
MB90860A Series
(7) Hold Timing
Parameter
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
Symbol
Pin
Condition
Units
Remarks
Min
Max
Pin floating ⇒ HAK ↓
time
tXHAL
HAK ↑ time ⇒ Pin valid
time
tHAHV
HAK
30
tCP
ns
tCP
2 tCP
ns
HAK
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4V
HAK
0.8V
tHAHV
tXHAL
Each pin
2.4V
0.8V
50
High-Z
2.4V
0.8V
MB90860A Series
(8) UART0/1/2/3/4
Parameter
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Condition
Unit Remarks
Min
Max
Symbol
Pin
Serial clock cycle time
tSCYC
SCK0 to SCK4
8 tCP
ns
SCK ↓ → SOT delay time
tSLOV
−80
+80
ns
Valid SIN → SCK ↑
tIVSH
100
ns
SCK ↑ → Valid SIN hold time
tSHIX
SCK0 to SCK4,
SOT0 to SOT4 Internal clock
operation output
SCK0 to SCK4, pins are
SIN0 to SIN4 CL = 80 pF + 1 TTL.
SCK0 to SCK4,
SIN0 to SIN4
60
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK4
4 tCP
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK4
4 tCP
ns
SCK ↓ → SOT delay time
tSLOV
150
ns
Valid SIN → SCK ↑
tIVSH
60
ns
SCK ↑ → Valid SIN hold time
tSHIX
60
ns
SCK0 to SCK4, External clock
SOT0 to SOT4 operation output
pins are
SCK0 to SCK4,
CL = 80 pF + 1 TTL.
SIN0 to SIN4
SCK0 to SCK4,
SIN0 to SIN4
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine cycle (Unit : ns)
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
tSHIX
VIH
VIH
VIL
VIL
Internal Shift Clock Mode
51
MB90860A Series
tSLSH
tSHSL
VIH
VIH
SCK
VIL
VIL
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
VIH
VIH
VIL
VIL
External Shift Clock Mode
(9) Trigger Input Timing
Parameter
Input pulse width
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Condition
Unit
Remarks
Min
Max
Symbol
Pin
tTRGH
tTRGL
INT0 to INT15,
INT0R to INT15R,
ADTG
52
5 tCP
ns
VIH
VIH
INT0 to INT15,
INT0R to INT15R,
ADTG
VIL
VIL
tTRGH
tTRGL
MB90860A Series
(10) Timer Related Resource Input Timing
Parameter
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Condition
Unit
Remarks
Min
Max
Symbol
Pin
tTIWH
TIN0 to TIN3
IN0 to IN7
Input pulse width
tTIWL
4 tCP
ns
VIH
VIH
TIN0 to TIN3,
IN0 to IN7
VIL
VIL
tTIWH
tTIWL
(11) Timer Related Resource Output Timing
(TA = –40° to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)
Value
Condition
Unit
Remarks
Min
Max
Parameter
Symbol
Pin
CLK ↑ ⇒ TOUT change time
tTO
TOT0 to TOT3,
PPG0 to PPGF
CLK
30
ns
2.4 V
2.4 V
TOT0 to TOT3,
PPG0 to PPGF
0.8 V
tTO
53
MB90860A Series
(12) I2C Timing
(TA = –40°C to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)
Standard-mode Fast-mode*4
Unit
Symbol Condition
Min
Max
Min
Max
Parameter
SCL clock frequency
fSCL
0
100
0
400
kHz
tHDSTA
4.0
0.6
µs
“L” width of the SCL clock
tLOW
4.7
1.3
µs
“H” width of the SCL clock
tHIGH
4.0
0.6
µs
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
4.7
0.6
µs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
µs
Data set-up time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL ↑ → SDA ↑
tSUSTO
4.0
0.6
µs
tBUS
4.7
1.3
µs
Hold time (repeated) START condition
SDA ↓ → SCL ↓
Bus free time between a STOP and START
condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tSUDAT
tLOW
tBUS
tHDSTA
SCL
tHDSTA
54
tHDDAT
tHIGH
tSUSTA
tSUSTO
MB90860A Series
5. A/D Converter
(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Resolution
Total error
Value
Unit
Min
Typ
Max
10
bit
±3.0
LSB
Nonlinearity error
±2.5
LSB
Differential
nonlinearity error
±1.9
LSB
Zero reading
voltage
VOT
AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB
Full scale reading
voltage
VFST
AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
Compare time
Sampling time
Analog port input
current
IAIN
AN0 to AN23
Analog input
voltage range
VAIN
Reference
voltage range
Power supply
current
Reference
voltage current
Offset between
input channels
1.0
16,500
µs
∞
µs
−0.3
+0.3
µA
AN0 to AN23
AVRL
AVRH
V
AVRH
AVRL + 2.7
AVCC
V
AVRL
0
AVRH − 2.7
V
IA
AVCC
3.5
7.5
mA
IAH
AVCC
5
µA
IR
AVRH
600
900
µA
IRH
AVRH
5
µA
AN0 to AN23
4
LSB
2.0
0.5
1.2
Remarks
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
*
*
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH − AVRL becomes smaller.
55
MB90860A Series
6. Definition of A/D Converter Terms
Resolution
Non linearity
error
Differential
linearity error
Total error
Zero reading
voltage
Full scale
reading voltage
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
: Input voltage which results in the minimum conversion value.
: Input voltage which results in the maximum conversion value.
Total error
3FF
3FE
Actual conversion
characteristics
1.5 LSB
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
003
002
Actual conversion
characteristics
Ideal characteristics
001
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
VOT (Ideal value) = AVRL + 0.5 LSB [V]
Total error of digital output “N” =
[LSB]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
56
MB90860A Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FD
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004
Actual conversion
characteristics
003
Digital output
3FE
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002
Ideal characteristics
Actual conversion
characteristics
N−2
001
VOT (actual measurement value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
57
MB90860A Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
if the output inpedance exceeds 1.5 kΩ, set a longer sampling time or add an external capacitor compensate
the output inpedance. About setting of sampling time, please refer to hardware manual of MB90860A series.
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
• Analog input circuit model
Analog input
R
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R =: 2.52 kΩ, C =: 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R =: 13.6 kΩ, C =: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics
Parameter
Conditions
Sector erase time
Chip erase time
TA = +25 °C
VCC = 5.0 V
Word (16 bit width)
programming time
Value
Unit
Remarks
Min
Typ
Max
1
15
s
Excludes programming
prior to erasure
9
s
Excludes programming
prior to erasure
16
3,600
µs
Except for the over head
time of the system
Programs/Erase cycle
10,000
cycle
Flash Data Retention
Time
Average
TA = +85 °C
20
Year
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
58
MB90860A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F867APF
MB90F867ASPF
MB90867APF
100-pin Plastic QFP
(FPT-100P-M06)
MB90867ASPF
MB90F867APFV
MB90F867ASPFV
MB90867APFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90867ASPFV
MB90V340
MB90V340S
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
59
MB90860A Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness including plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
60
MB90860A Series
(Continued)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin Plastic LQFP
(FPT-100P-M05)
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
61
MB90860A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0405
FUJITSU LIMITED Printed in Japan