Freescale MC9S12KL64CPU Microcontroller Datasheet

MC9S12K Family
Device User Guide
Covers MC9S12KT256, MC9S12KG256,
MC9S12KG128, MC9S12KL128, MC9S12KC128,
MC9S12KG64, MC9S12KL64, MC9S12KC64
and MC9S12KG32
HCS12
Microcontrollers
9S12KT256DGV1/D
V01.09
9 SEP 2004
freescale.com
Device User Guide — 9S12KT256DGV1/D V01.09
Revision History
Version Revision
Number
Date
2
Author
Description of Changes
01.00
16 JUL 02
Original Version.
01.01
22 NOV 02
Change load cap value on VDD and VDDPLL.
Correct expanded bus timing from 20MHz to 25 MHz.
01.02
15 JAN 03
Move ATD interrupt vector from $ffd0 to $ffd2.
Change PWeh and tDSW parameter in external bus timing.
01.03
13 JUN 03
Expand to a K-Family SoC Guide and include 9S12KT256.
01.04
18 JUN 03
Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.
01.05
14 NOV 03
Changed to a Device User Guide and added Document number.
Updated Table A-17 Oscillator Characteristics.
Replaced XCLKS with PE7 for Clock Selection diagrams.
Added CTRL to Table 2-1 Signal Properties.
Replaced Burst programming with Row Programming in NVM
electricals.
Changed Digital logic to Internal Logic.
Added LRAE bootloader information.
Changed PWEL, PWEH, tDSW, tACCE, tNAD, tNAV, tRWV, tLSV, tNOV,
tP0V and tP1V in the external bus timing.
Added voltage regulator characteristics.
01.06
10 FEB 04
Updated Table A-7 3.3V I/O Characteristics.
01.07
13 MAY 04
Updated Table A-16 NVM Timing Characteristics.
Corrected A.6.1.2 Row Programming time tbwpgm equation
01.08
20 JUL 04
Expanded K-family to include 9S12KC128, 9S12KC64, 9S12KL128
and 9S12KL64.
01.09
9 SEP 04
Updated osciilator start up time and supply current characteristics.
Added ATDCTL0 and ATDCTL1 register bits to Sec 1.7.
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MC9S12KG(L)(C)128(64)(32) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MC9S12KT(G)256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.1
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.2
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.3
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.4
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.5
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.6
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 61
2.3.7
PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]. . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.8
PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.9
PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 61
2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 62
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.14 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.16 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.17 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.18 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Freescale Semiconductor
3
Device User Guide — 9S12KT256DGV1/D V01.09
2.3.20
2.3.21
2.3.22
2.3.23
2.3.24
2.3.25
2.3.26
2.3.27
2.3.28
2.3.29
2.3.30
2.3.31
2.3.32
2.3.33
2.3.34
2.3.35
2.3.36
2.3.37
2.3.38
2.3.39
2.3.40
2.3.41
2.3.42
2.3.43
2.3.44
2.3.45
2.3.46
2.3.47
2.3.48
2.3.49
2.3.50
2.3.51
2.3.52
2.3.53
2.3.54
2.3.55
4
PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . 65
PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . 65
PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 66
PM7 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PM6 / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . 66
PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . 66
PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . 67
PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . 67
PM1 / TXCAN0 — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PM0 / RXCAN0 — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . 67
PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . 67
PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . 68
PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 68
PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 68
PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 68
PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
2.3.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4.1
VDDX,VSSX — Power Supply Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.2
VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage Regulator
70
2.4.3
VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic . . . . . . . . . 70
2.4.4
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 70
2.4.5
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.6
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 70
Section 3 System Clock Description
Section 4 Modes of Operation
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.1
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.1
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Section 6 HCS12 Core Block Description
6.1
6.2
6.3
6.4
CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 78
HCS12 Debug (DBG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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5
Device User Guide — 9S12KT256DGV1/D V01.09
6.5
6.6
HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 79
HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . 79
Section 7 Analog to Digital Converter (ATD) Block Description
Section 8 Clock Reset Generator (CRG) Block Description
8.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Section 9 EEPROM Block Description
Section 10 Flash EEPROM Block Description
Section 11 IIC Block Description
Section 12 MSCAN Block Description
Section 13 OSC Block Description
Section 14 Port Integration Module (PIM) Block Description
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Serial Communications Interface (SCI) Block Description
Section 17 Serial Peripheral Interface (SPI) Block Description
Section 18 Timer (TIM) Block Description
Section 19 Voltage Regulator (VREG) Block Description
19.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
19.1.1 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.1
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.2
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.3
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
A.1.4
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
A.1.5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
A.1.6
ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A.1.7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A.1.8
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87
A.1.9
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.2 Voltage Regulator (VREG_3V3) Operating Characteristics . . . . . . . . . . . . . . . . . . . 94
A.3 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4.1
Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4.2
Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
A.5 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.5.1
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.5.2
Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
A.5.3
ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.6 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A.6.1
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A.6.2
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.7 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.7.1
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.7.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
A.7.3
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.8 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.9.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.9.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
A.10 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
A.10.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix B Package Information
B.1
B.2
B.3
80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
100-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
8
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
List of Figures
Figure 0-1
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 3-1
Figure A-1
Figure A-2
Figure A-3
Figure A-4
Figure A-5
Figure A-6
Figure A-7
Figure A-8
Figure A-9
Figure B-1
Figure B-2
Figure B-3
Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MC9S12KG(L)(C)128(64)(32) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 19
MC9S12KT(G)256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MC9S12KT256 and MC9S12KG256 Memory Map . . . . . . . . . . . . . . . . . . . . 23
MC9S12KG128, MC9S12KL128 and MC9S12KC128 Memory Map . . . . . . 24
MC9S12KG64, MC9S12KL64 and MC9S12KC64 Memory Map . . . . . . . . . 25
MC9S12KG32 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin assignments for 112 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Pin assignments for 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Pin assignments for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Loop Controlled Pierce Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . 62
Full Swing Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . 63
External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 95
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 122
100-pin LQFP Mechanical Dimensions (case no. 983) . . . . . . . . . . . . . . . 123
112-pin LQFP Mechanical Dimensions (case no. 987) . . . . . . . . . . . . . . . 124
Freescale Semiconductor
9
Device User Guide — 9S12KT256DGV1/D V01.09
10
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
List of Tables
Table 0-1
Table 0-2
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 2-1
Table 2-2
Table 2-3
Table 4-1
Table 4-2
Table 4-3
Table 5-1
Table 5-2
Table A-1
Table A-2
Table A-3
Table A-4
Table A-5
Table A-6
Table A-7
Table A-8
Table A-9
Table A-10
Table A-11
Table A-12
Table A-13
Table A-14
Table A-15
Table A-16
Table A-17
Table A-18
List of MC9S12K-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MC9S12KT(G)256 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MC9S12KG(L)(C)128(64)(32) Device Memory Map . . . . . . . . . . . . . . . . . . . . 22
Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 43
Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clock selection based on PE7 during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 86
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5V ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5V ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.3V ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-19
Table A-20
Table A-21
Table A-22
Table A-23
Table A-24
12
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Preface
The Device User Guide provides information about the MC9S12K-Family devices made up of standard
HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A
complete set of device manuals also includes all the individual Block Guides of the implemented modules.
In a effort to reduce redundancy all module specific information is located only in the respective Block
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
Table 0-1 shows a feature overview of the MC9S12K-Family members.
Table 0-1 List of MC9S12K-Family members
Flash RAM EEPROM
Device
Temp Options1 Package CAN SCI SPI IIC A/D2 PWM2 TIM2 I/O3
256K
12K
4K
MC9S12KT256
C, V, M
256K
12K
4K
MC9S12KG256
C, V, M
128K
8K
2K
MC9S12KG128
C, V, M
64K
4K
1K
MC9S12KG64
C, V, M
32K
2K
1K
MC9S12KG32
C, V, M
128K
6K
2K
MC9S12KL128
C, V, M
64K
128K
64K
4K
6K
4K
1K
None
None
MC9S12KL64
MC9S12KC128
MC9S12KC64
C, V, M
C, V, M
C, V, M
112 LQFP
3
2
3
1
16
8
8
91
112 LQFP
2
2
3
1
16
8
8
91
80 QFP
2
2
3
1
8
7
8
59
112 LQFP
2
2
3
1
16
8
8
91
100 LQFP
2
2
2
1
13
7
8
79
80 QFP
2
2
2
1
8
7
8
59
112 LQFP
2
2
2
1
16
8
8
91
80 QFP
2
2
2
1
8
7
8
59
80 QFP
2
2
2
1
8
7
8
59
112 LQFP
1
1
2
1
16
8
8
91
100 LQFP
1
1
2
1
13
7
8
79
80 QFP
1
1
2
1
8
7
8
59
112 LQFP
1
1
2
1
16
8
8
91
80 QFP
1
1
2
1
8
7
8
59
112 LQFP
1
1
2
1
16
8
8
91
100 LQFP
1
1
2
1
13
7
8
79
80 QFP
1
1
2
1
8
7
8
59
112 LQFP
1
1
2
1
16
8
8
91
80 QFP
1
1
2
1
8
7
8
59
NOTES:
1. C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
2. Number of channels
3. I/O is the sum of ports capable to act as digital input or output.
Freescale Semiconductor
13
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 0-1 shows the part number coding based on the package and temperature options for the
MC9S12K-Family.
MC9S12 KT256
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
C FU
Package Option
Temperature Option
Device Title
Controller Family
Package Options
PV = 112LQFP
PU = 100LQFP
FU = 80QFP
Figure 0-1 Order Part number Coding
Table 0-2 shows names and versions of the referenced documents throughout the Device User Guide.
Table 0-2 Document References
User Guide
Version
Document Order Number
CPU12 Reference Manual
V02
S12CPUV2/D
HCS12 Background Debug (BDM) Block Guide
V04
S12BDMV4/D
HCS12 Debug (DBG) Block Guide
V01
S12DBGV1/D
HCS12 Interrupt (INT) Block Guide
V01
S12INTV1/D
HCS12 Multiplexed Expanded Bus Interface (MEBI) Block Guide
V03
S12MEBIV3/D
HCS12 Module Mapping Control (MMC) Block Guide
V04
S12MMCV4/D
Analog to Digital Converter: 10-Bit, 16 Channels (ATD_10B16C) Block Guide
V03
S12ATD10B16CV3/D1
Analog to Digital Converter: 10-Bit, 8 Channels (ATD_10B8C) Block Guide
V03
S12ATD10B8CV3/D2
Clock and Reset Generator (CRG) Block Guide
V04
S12CRGV4/D
2K Byte EEPROM (EETS2K) Block Guide
V01
S12EETS2KV1/D(1)
4K Byte EEPROM (EETS4K) Block Guide
V02
S12EETS4KV2/D(2)
128K Byte Flash with Error Code Correction (FTS128K1ECC) Block Guide
V01
FTS128K1ECCV1/D(1)
256K Byte Flash with Error Code Correction (FTS256K2ECC) Block Guide
V01
FTS256K2ECCV1/D(2)
Inter IC Bus (IIC) Block Guide
V02
S12IICV2/D
Motorola Scalable CAN (MSCAN) Block Guide
V02
S12MSCANV2/D
Oscillator Loop Control Pierce (OSC_LCP) Block Guide
V01
S12OSCLCPV1/D
Port Integration Module(1) (PIM_9KG128) Block Guide
V01
S12KG128PIMV1/D
Port Integration Module(2) (PIM_9KT256) Block Guide
V01
S12KT256PIMV1/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide
V01
S12PWM8B6CV1/D
Serial Communications Interface (SCI) Block Guide
V02
S12SCIV2/D
Serial Peripheral Interface (SPI) Block Guide
V03
S12SPIV3/D
Timer: 16-Bit, 8 Channels (TIM_16B8C) Block Guide
V01
S12TIM16B8CV1/D
Voltage Regulator (VREG_3V3) Block Guide
V01
S12VREG3V3V1/D
NOTES:
1. Block Guide for MC9S12K-Family except MC9S12KT256 and MC9S12KG256.
2. Block Guide for MC9S12KT256 and MC9S12KG256 only.
14
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Section 1 Introduction
1.1 Overview
The MC9S12K-Family is a 112/100/80 pin 16-bit Flash-based microcontroller family targeted for high
reliability systems. Members of the MC9S12K-Family have an increased performance in reliability over
the life of the product due to a built-in Error Checking and Correction Code (ECC) in the Flash memory.
The program and erase operations automatically generate six parity bits per word making ECC transparent
to the user.
All members of the MC9S12K-Family are comprised of standard on-chip peripherals including a 16-bit
central processing unit (CPU12), up to 256K bytes of Flash EEPROM, up to 4K bytes of EEPROM, up to
12K bytes of RAM, up to two asynchronous serial communications interface (SCI), up to three serial
peripheral interface (SPI), IIC-bus, an 8-channel IC/OC timer, 16-channel or two 8-channel 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), up to three CAN 2.0 A,
B software compatible modules, 29 discrete digital I/O channels (Port A, Port B, Port E and Port K), and
20 discrete digital I/O lines with interrupt and wakeup capability. The MC9S12K-Family has full 16-bit
data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
•
HCS12 Core
–
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
•
–
MEBI (Multiplexed External Bus Interface)
–
MMC (Memory Map and Interface)
–
INT (Interrupt Controller)
–
DBG (Debugger)
–
BDM (Background Debug Mode)
Oscillator
–
4Mhz to 16Mhz frequency range
–
Pierce with amplitude loop control
–
Clock monitor
Freescale Semiconductor
15
Device User Guide — 9S12KT256DGV1/D V01.09
•
•
Clock and Reset Generator (CRG)
–
Phase-locked loop clock frequency multiplier
–
Self Clock mode in absence of external clock
–
COP watchdog
–
Real Time interrupt (RTI)
Memory
–
32K, 64K, 128K or 256K Byte Flash EEPROM
i. Internal program/erase voltage generation
ii. Security and Block Protect bits
iii. Hamming Error Correction Coding (ECC)
–
1K, 2K or 4K Byte EEPROM
–
2K, 4K, 6K, 8K or 12K Byte static RAM
Single-cycle misaligned word accesses without wait states
•
•
•
•
16
Analog-to-Digital Converter(s) (ADC)
–
One 16-channel module with 10-bit resolution except for MC9S12KT256 and MC9S12KG256
–
Two 8-channel module with 10-bit resolution for MC9S12KT256 and MC9S12KG256
–
External conversion trigger capability
8-channel Timer (TIM)
–
Programmable input capture or output compare channels
–
Simple PWM mode
–
Counter Modulo Reset
–
External Event Counting
–
Gated Time Accumulation
8-channel Pulse Width Modulator (PWM)
–
Programmable period and duty cycle per channel
–
8-bit 8-channel or 16-bit 4-channel
–
Edge and center aligned PWM signals
–
Emergency shutdown input
Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules
–
Five receive and three transmit buffers
–
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
–
Four separate interrupt channels for Rx, Tx, error and wake-up
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
•
•
•
•
–
Low-pass filter wake-up function
–
Loop-back for self test operation
Serial interfaces
–
Two asynchronous serial communication interface (SCI)
–
Three synchronous serial peripheral interface (SPI)
–
Inter-IC Bus (IIC)
Internal 2.5V Regulator
–
Input voltage range from 3.15V to 5.5V
–
Low power mode capability
–
Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)
20 key wake up inputs
–
Rising or falling edge triggered interrupt capability
–
Digital filter to prevent short pulses from triggering interrupts
–
Programmable pull ups and pull downs
Operating frequency for ambient temperatures (TA -40°C to 125°C)
–
•
50MHz equivalent to 25MHz Bus Speed
112-Pin LQFP, 100-Pin LQFP, or 80-Pin QFP package
–
I/O lines with 3.3V/5V input and drive capability
–
3.3V/5V A/D converter inputs
1.3 Modes of Operation
•
•
•
Normal modes
–
Normal Single-Chip Mode
–
Normal Expanded Wide Mode
–
Normal Expanded Narrow Mode
–
Emulation Expanded Wide Mode
–
Emulation Expanded Narrow Mode
Special Operating Modes
–
Special Single-Chip Mode with active Background Debug Mode
–
Special Test Mode (Motorola use only)
–
Special Peripheral Mode (Motorola use only)
Each of the above modes of operation can be configured for three Low power submodes
Freescale Semiconductor
17
Device User Guide — 9S12KT256DGV1/D V01.09
•
18
–
Stop Mode
–
Pseudo Stop Mode
–
Wait Mode
Secure operation, preventing the unauthorized read and write of the memory contents.
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1.4 MC9S12KG(L)(C)128(64)(32) Block Diagram
SPI0
Multiplexed Address/Data Bus
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
Internal Logic 2.5V
VDD1,2
VSS1,2
CAN4
RxCAN
TxCAN
PWM
OSC/PLL 2.5V
VDDPLL
VSSPLL
Voltage Regulator 3.3V/5V A/D Converter 3.3V/5V
VDDR
Voltage Reference
VSSR
RxCAN
TxCAN
IIC
I/O Driver 3.3V/5V
VDDX
VSSX
CAN0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PTB
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
DDRB
PTA
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Multiplexed
Narrow Bus
DDRA
VDDA
VSSA
MISO
MOSI
SCK
SS
SPI1
SPI2
SDA
SCL
KWJ0
KWJ1
KWJ6
KWJ7
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
DDRK
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
Signals shown in Bold are not available on n the 80 Pin Package
SCI1
TEST
Multiplexed
Wide Bus
RXD
TXD
RXD
TXD
SCI0
PAD
System
Integration
Module
(SIM)
TIM
PTK
Breakpoints
Debugger
PTT
PTE
DDRE
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
NOACC/XCLKS
DDRT
CRG
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PTS
PLL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
DDRS
CPU12
PTM
Periodic Interrupt
COP Watchdog
Clock Monitor
OSC
DDRM
XTAL
EXTAL
VSSPLL
VDDPLL
XFC
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PTJ
Single-wire BDM
BKGD
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
DDRJ
PPAGE
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PTP
Voltage Regulator
DDRP
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
VRH
VRL
VDDA
VSSA
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
Module to
Port Routing
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
8K Byte RAM
PAD
2K Byte EEPROM
VRH
VRL
VDDA
VSSA
PTH
ATD
DDRH
128K Byte Flash EEPROM
Figure 1-1 MC9S12KG(L)(C)128(64)(32) Block Diagram
Freescale Semiconductor
19
Device User Guide — 9S12KT256DGV1/D V01.09
RXD
TXD
RXD
TXD
SCI0
SCI1
TEST
SPI0
Multiplexed Address/Data Bus
MISO
MOSI
SCK
SS
RxCAN
TxCAN
RxCAN
CAN1
TxCAN
RxCAN
CAN4
TxCAN
CAN0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
PTB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
IIC
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Multiplexed
Narrow Bus
DDRB
PTA
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
Multiplexed
Wide Bus
DDRA
Internal Logic 2.5V
VDD1,2
VSS1,2
I/O Driver 3.3V/5V
VDDX
VSSX
PWM
OSC/PLL 2.5V
VDDPLL
VSSPLL
Voltage Regulator 3.3V/5V A/D Converter 3.3V/5V
VDDR
Voltage Reference
VSSR
VDDA
VSSA
SPI1
SPI2
SDA
SCL
KWJ0
KWJ1
KWJ6
KWJ7
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
DDRK
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
Signals shown in Bold are not available on n the 80 Pin Package
System
Integration
Module
(SIM)
TIM
AD1
Breakpoints
Debugger
PTK
PTE
DDRE
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
NOACC/XCLKS
PTT
CRG
DDRT
PLL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PTS
CPU12
DDRS
Periodic Interrupt
COP Watchdog
Clock Monitor
OSC
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PTM
XTAL
EXTAL
VSSPLL
VDDPLL
XFC
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
DDRM
Single-wire BDM
BKGD
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PTJ
PPAGE
VRH
VRL
VDDA
VSSA
DDRJ
Voltage Regulator
VRH
VRL
VDDA
VSSA
PTP
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
ATD1
DDRP
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
12K Byte RAM
VRH
VRL
VDDA
VSSA
PTH
4K Byte EEPROM
VRH
VRL
VDDA
VSSA
DDRH
ATD0
Module to
Port Routing
256K Byte Flash EEPROM
AD0
1.5 MC9S12KT(G)256 Block Diagram
Figure 1-2 MC9S12KT(G)256 Block Diagram
20
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1.6 Device Memory Map
Table 1-1 shows the device register map of the MC9S12KT256 and MC9S12KG256 after reset. Table
1-2 shows the device register map of the MC9S12KG128(64)(32), MC9S12KL128(64) and
MC9S12KC128(64) after reset.
Table 1-1 MC9S12KT(G)256 Device Memory Map
Address
Module
Size
$000 - $017
CORE (Ports A, B, E, Modes, Inits, Test)
$018
Reserved
1
$019
Voltage Regulator (VREG)
1
$01A - $01B
Device ID register (PARTID)
2
$01C - $01F
CORE (MEMSIZ, IRQ, HPRIO)
$020 - $02F
CORE (DBG)
$030 - $033
CORE (PPAGE, Port K)
$034 - $03F
Clock and Reset Generator (PLL, RTI, COP)
12
$040 - $06F
Standard Timer 16-bit 8 channels (TIM)
48
$070 - $07F
Reserved
16
$080 - $09F
Analog to Digital Converter 10-bit 8 channels (ATD0)
32
$0A0 - $0C7
Reserved
40
$0C8 - $0CF
Serial Communications Interface 0 (SCI0)
8
$0D0 - $0D7
Serial Communications Interface 1 (SCI1)
8
$0D8 - $0DF
Serial Peripheral Interface 0 (SPI0)
8
$0E0 - $0E7
Inter Integrated Circuit Bus (IIC)
8
$0E8 - $0EF
Reserved
8
$0F0 - $0F7
Serial Peripheral Interface 1 (SPI1)
8
$0F8 - $0FF
Serial Peripheral Interface 2 (SPI2)
$100- $10F
Flash Control Register
16
$110- $11B
EEPROM Control Register
12
$11C - $11F
Reserved
$120 - $13F
Analog to Digital Converter 10-bit 8 channels (ATD1)
32
$140 - $17F
Motorola Scalable Controller Area Network 0 (CAN0)
64
$180 - $1BF
Motorola Scalable Controller Area Network 1 (CAN1)
$1C0 - $23F
Reserved
$240 - $27F
Port Integration Module (PIM)
64
$280 - $2BF
Motorola Scalable Controller Area Network 4 (CAN4)
64
$2C0 - $2E7
Pulse Width Modulator 8-bit 8 channels (PWM)
$2E8 - $3FF
Reserved
Freescale Semiconductor
24
4
16
4
8
4
64
128
40
280
21
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-2 MC9S12KG(L)(C)128(64)(32) Device Memory Map
Address
22
Module
Size
$000 - $017
CORE (Ports A, B, E, Modes, Inits, Test)
24
$018
Reserved
1
$019
Voltage Regulator (VREG)
1
$01A - $01B
Device ID register (PARTID)
2
$01C - $01F
CORE (MEMSIZ, IRQ, HPRIO)
4
$020 - $02F
CORE (DBG)
$030 - $033
CORE (PPAGE, Port K)
$034 - $03F
Clock and Reset Generator (PLL, RTI, COP)
12
$040 - $06F
Standard Timer 16-bit 8 channels (TIM)
48
$070 - $07F
Reserved
16
$080 - $0AF
Analog to Digital Converter 10-bit 16 channels (ATD)
48
$0B0 - $0C7
Reserved
24
$0C8 - $0CF
Serial Communications Interface 0 (SCI0)
8
$0D0 - $0D7
Serial Communications Interface 1 (SCI1)
8
$0D8 - $0DF
Serial Peripheral Interface 0 (SPI0)
8
$0E0 - $0E7
Inter Integrated Circuit Bus (IIC)
8
$0E8 - $0EF
Reserved
8
$0F0 - $0F7
Serial Peripheral Interface 1 (SPI1)
8
$0F8 - $0FF
Serial Peripheral Interface 2 (SPI2)
8
$100- $10F
Flash Control Register
16
$110- $11B
EEPROM Control Register
12
$11C - $13F
Reserved
36
$140 - $17F
Motorola Scalable Controller Area Network 0 (CAN0)
64
$180 - $23F
Reserved
$240 - $27F
Port Integration Module (PIM)
64
$280 - $2BF
Motorola Scalable Controller Area Network 4 (CAN4)
64
$2C0 - $2E7
Pulse Width Modulator 8-bit 8 channels (PWM)
40
$2E8 - $3FF
Reserved
16
4
192
280
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-4 illustrates the full user configurable device memory map of MC9S12KT256 and
MC9S12KG256.
$0000
1K Register Space
$0000
$0400
$03FF
Mappable to any 2K Boundary
$0000
4K Bytes EEPROM
$1000
$0FFF
Mappable to any 4K Boundary
$1000
12K Bytes RAM
$3FFF
Mappable to any 16K Boundary
and alignable to top or bottom
$4000
0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM
$0000 - $0FFF: 4K EEPROM (1K hidden behind Register Space)
Figure 1-3 MC9S12KT256 and MC9S12KG256 Memory Map
Freescale Semiconductor
23
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-4 illustrates the full user configurable device memory map of MC9S12KG128, MC9S12KL128
and MC9S12KC128.
$0000
$0400
$0800
$1000
$2000
$0000
1K Register Space
$03FF
Mappable to any 2K Boundary
$0800
2K Bytes EEPROM
$0FFF
Mappable to any 2K Boundary
$2000
8K Bytes RAM
$3FFF
Mappable to any 8K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
eight * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (1K RAM hidden behind Register Space)
$0000 - $07FF: 2K EEPROM (not visible)
Figure 1-4 MC9S12KG128, MC9S12KL128 and MC9S12KC128 Memory Map
24
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-5 illustrates the full user configurable device memory map of MC9S12KG64, MC9S12KL64
and MC9S12KC64.
$0000
1K Register Space
$03FF
Mappable to any 2K Boundary
$0800
$0000
$0400
$0800
$1000
$0FFF
1K Bytes EEPROM
Mappable to any 2K Boundary
(1K mapped two times in 2K space)
$3000
$3000
4K Bytes RAM
$3FFF
Mappable to any 4K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
four * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (1K RAM hidden behind Register Space)
$0000 - $03FF: 1K EEPROM (not visible)
Figure 1-5 MC9S12KG64, MC9S12KL64 and MC9S12KC64 Memory Map
Freescale Semiconductor
25
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-6 illustrates the full user configurable device memory map of MC9S12KG32.
$0000
$0000
$0400
$0800
$1000
$3800
1K Register Space
$03FF
Mappable to any 2K Boundary
$0800
$0FFF
1K Bytes EEPROM
Mappable to any 2K Boundary
(1K mapped two times in 2K space)
$3800
2K Bytes RAM
$3FFF
Mappable to any 2K Boundary
$4000
$8000
$8000
EXT
32K Fixed Flash EEPROM
$FFFF
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $07FF: 2K RAM (1K RAM hidden behind Register Space)
$0000 - $03FF: 1K EEPROM (not visible)
Figure 1-6 MC9S12KG32 Memory Map
26
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1.7 Detailed Register Map
The following tables show the detailed register map of the MC9S12K-Family.
$0000 - $000F
Address
Name
$0000
PORTA
$0001
PORTB
$0002
DDRA
$0003
DDRB
$0004
Reserved
$0005
Reserved
$0006
Reserved
$0007
Reserved
$0008
PORTE
$0009
DDRE
$000A
PEAR
$000B
MODE
$000C
PUCR
$000D
RDRIV
$000E
EBICTL
$000F
Reserved
$0010 - $0014
Address
Name
$0010
INITRM
$0011
INITRG
Freescale Semiconductor
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
NOACCE
Write:
Read:
MODC
Write:
Read:
PUPKE
Write:
Read:
RDPK
Write:
Read:
0
Write:
Read:
0
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
Bit 1
Bit 0
6
5
4
3
Bit 2
0
0
PIPOE
NECLK
LSTRE
RDWE
0
0
EMK
EME
PUPBE
PUPAE
RDPB
RDPA
0
MODB
MODA
0
0
0
0
0
0
0
0
0
IVIS
0
0
0
0
0
0
0
0
0
0
0
0
0
PUPEE
RDPE
ESTR
0
MMC map 1 of 4 (HCS12 Module Mapping Control)
Bit 7
Read:
RAM15
Write:
Read:
0
Write:
Bit 6
Bit 5
Bit 4
Bit 3
RAM14
RAM13
RAM12
RAM11
REG14
REG13
REG12
REG11
Bit 2
0
Bit 1
0
0
0
Bit 0
RAMHAL
0
27
Device User Guide — 9S12KT256DGV1/D V01.09
$0010 - $0014
Address
MMC map 1 of 4 (HCS12 Module Mapping Control)
Name
$0012
INITEE
$0013
MISC
$0014
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
$0015 - $0016
Address
ITCR
$0016
ITEST
Read:
Write:
Read:
Write:
$0017 - $0017
Address
$0017
Read:
Write:
$0018 - $0018
Address
$0018
Read:
Write:
$0019 - $0019
Address
$0019
Read:
Write:
$001A - $001B
Address
28
PARTIDH
$001B
PARTIDL
EE15
EE14
EE13
EE12
EE11
0
0
0
0
0
0
0
0
Bit 2
0
Bit 1
0
Bit 0
EEON
EXSTR1 EXSTR0 ROMHM ROMON
0
0
0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WRINT
ADR3
ADR2
ADR1
ADR0
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
LVDS
Bit 1
Bit 0
LVIE
LVIF
Miscellaneous Peripherals (Device Guide)
Name
$001A
Bit 3
VREG3V3 (Voltage Regulator)
Name
VREGCTRL
Bit 4
Miscellaneous Peripherals (Device Guide)
Name
Reserved
Bit 5
MMC map 2 of 4 (HCS12 Module Mapping Control)
Name
Reserved
Bit 6
INT map 1 of 2 (HCS12 Interrupt)
Name
$0015
Bit 7
Read:
Write:
Read:
Write:
Bit 7
ID15
Bit 6
ID14
Bit 5
ID13
Bit 4
ID12
Bit 3
ID11
Bit 2
ID10
Bit 1
ID9
Bit 0
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$001C - $001D
Guide)
Address
Name
$001C
MEMSIZ0
$001D
MEMSIZ1
MMC map 3 of 4 (HCS12 Module Mapping Control, Device
Bit 7
Bit 6
Bit 5
Bit 4
Read: reg_sw0
0
eep_sw1 eep_sw0
Write:
Read: rom_sw1 rom_sw0
0
0
Write:
$001E - $001E
Address
$001E
Read:
Write:
$001F - $001F
Address
$001F
Read:
Write:
$0020 - $002F
Addres
s
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
-
DBGSC
DBGTBH
DBGTBL
DBGCNT
DBGCCX
DBGCCH
DBGCCL
-
DBGC2
BKPCT0
DBGC3
BKPCT1
DBGCAX
BKP0X
DBGCAH
BKP0H
Freescale Semiconductor
0
pag_sw1 pag_sw0
Bit 7
Bit 6
IRQE
IRQEN
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
DBG (including BKP) map 1of 1 (HCS12 Debug)
Name
DBGC1
0
INT map 2 of 2 (HCS12 Interrupt)
Name
HPRIO
Bit 2
Bit 1
Bit 0
ram_sw2 ram_sw1 ram_sw0
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Name
INTCR
Bit 3
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ARM
TRGSEL
BEGIN
DBGBRK
BF
CF
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBF
0
read
DBGEN
write
AF
read
write
read Bit 15
write
read
write
read
write
read
write
read
write
read
write
Bit 2
Bit 1
0
CAPMOD
TRG
CNT
PAGSEL
EXTCMP
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
RWCEN
RWC
RWBEN
RWB
9
Bit 8
read
BKABEN
FULL
BDM
TAGAB BKCEN
TAGC
write
read
BKAMBH BKAMBL BKBMBH BKBMBL RWAEN
RWA
write
read
PAGSEL
EXTCMP
write
read
write
Bit 0
Bit 15
14
13
12
11
10
29
Device User Guide — 9S12KT256DGV1/D V01.09
$0020 - $002F
Addres
s
$002C
$002D
$002E
$002F
DBG (including BKP) map 1of 1 (HCS12 Debug)
Name
DBGCAL
BKP0L
DBGCBX
BKP1X
DBGCBH
BKP1H
DBGCBL
BKP1L
read
write
read
write
read
write
read
write
$0030 - $0031
Address
PPAGE
$0031
Reserved
Read:
Write:
Read:
Write:
$0032 - $0033
Address
PORTK
$0033
DDRK
$0034 - $003F
30
Address
Name
$0034
SYNR
$0035
REFDV
$0036
CTFLG
TEST ONLY
$0037
CRGFLG
$0038
CRGINT
$0039
CLKSEL
$003A
PLLCTL
$003B
RTICTL
$003C
COPCTL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
PAGSEL
EXTCMP
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
0
Bit 6
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
0
0
0
0
0
0
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Name
$0032
Bit 6
MMC map 4 of 4 (HCS12 Module Mapping Control)
Name
$0030
Bit 7
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
CRG (Clock and Reset Generator)
Bit 7
Read:
0
Write:
Read:
0
Write:
Read: TOUT7
Write:
Read:
RTIF
Write:
Read:
RTIE
Write:
Read:
PLLSEL
Write:
Read:
CME
Write:
Read:
0
Write:
Read:
WCOP
Write:
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
0
0
0
TOUT6
TOUT5
TOUT4
PROF
0
PSTP
0
0
LOCKIF
LOCKIE
SYSWAI ROAWAI
REFDV3 REFDV2 REFDV1 REFDV0
TOUT3
TOUT2
LOCK
TRACK
0
0
PLLWAI
CWAI
RTIWAI
COPWAI
PRE
PCE
SCME
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
PLLON
AUTO
ACQ
RTR6
RTR5
RTR4
RTR3
0
0
0
RSBCK
TOUT1
SCMIF
SCMIE
TOUT0
SCM
0
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0034 - $003F
Address
$003D
$003E
$003F
Name
FORBYP
TEST ONLY
CTCTL
TEST ONLY
ARMCOP
CRG (Clock and Reset Generator)
Bit 7
Bit 6
Read:
RTIBYP COPBYP
Write:
Read: TCTL7
TCTL6
Write:
Read:
0
0
Write:
Bit 7
6
$0040 - $006F
Address
TIOS
$0041
CFORC
$0042
OC7M
$0043
OC7D
$0044
TCNT (hi)
$0045
TCNT (lo)
$0046
TSCR1
$0047
TTOV
$0048
TCTL1
$0049
TCTL2
$004A
TCTL3
$004B
TCTL4
$004C
TIE
$004D
TSCR2
$004E
TFLG1
$004F
TFLG2
$0050
TC0 (hi)
$0051
TC0 (lo)
$0052
TC1 (hi)
$0053
TC1 (lo)
Freescale Semiconductor
Bit 4
PLLBYP
Bit 3
0
Bit 2
0
Bit 1
FCM
Bit 0
0
TCTL5
TCTL4
TCLT3
TCTL2
TCTL1
TCTL0
0
5
0
4
0
3
0
2
0
1
0
Bit 0
TIM (Timer 16 Bit 8 Channels)
Name
$0040
Bit 5
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
FOC7
0
FOC6
0
FOC5
0
FOC4
0
FOC3
0
FOC2
0
FOC1
0
FOC0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TEN
TSWAI
TSFRZ
TFFCA
0
0
0
0
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
TCRE
PR2
PR1
PR0
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TOI
C7F
TOF
31
Device User Guide — 9S12KT256DGV1/D V01.09
$0040 - $006F
Address
32
TIM (Timer 16 Bit 8 Channels)
Name
$0054
TC2 (hi)
$0055
TC2 (lo)
$0056
TC3 (hi)
$0057
TC3 (lo)
$0058
TC4 (hi)
$0059
TC4 (lo)
$005A
TC5 (hi)
$005B
TC5 (lo)
$005C
TC6 (hi)
$005D
TC6 (lo)
$005E
TC7 (hi)
$005F
TC7 (lo)
$0060
PACTL
$0061
PAFLG
$0062
PACNT (hi)
$0063
PACNT (lo)
$0064
Reserved
$0065
Reserved
$0066
Reserved
$0067
Reserved
$0068
Reserved
$0069
Reserved
$006A
Reserved
$006B
Reserved
$006C
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
0
PAOVF
PAIF
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0040 - $006F
Address
TIM (Timer 16 Bit 8 Channels)
Name
$006D
Reserved
$006E
Reserved
$006F
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
$0070 - $007F
Address
$0070
- $007F
$0080 - $00AF
Address
Name
$0080
ATDCTL0
$0081
ATDCTL1
$0082
ATDCTL2
$0083
ATDCTL3
$0084
ATDCTL4
$0085
ATDCTL5
$0086
ATDSTAT0
$0087
Reserved
$0088
ATDTEST0
$0089
ATDTEST1
$008A
ATDSTAT0
$008B
ATDSTAT1
$008C
ATDDIEN1
$008D
ATDDIEN0
$008E
PORTAD1
$008F
PORTAD0
Freescale Semiconductor
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved space
Name
Reserved
Bit 7
0
Read:
Write:
Bit 7
0
Bit 6
0
ATD (Analog to Digital Converter 10 Bit 16 Channel)1
Bit 7
Read:
0
Write:
Read:
ETRIGSEL
Write:
Read:
ADPU
Write:
Read:
0
Write:
Read:
SRES8
Write:
Read:
DJM
Write:
Read:
SCF
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read: CCF15
Write:
Read: CCF7
Write:
Read:
IEN15
Write:
Read:
IEN7
Write:
Read: PTAD15
Write:
Read: PTAD7
Write:
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
WRAP3
WRAP2
WRAP1
WRAP0
0
0
0
ETRIGCH3
ETRIGCH2
ETRIGCH1
ETRIGCH0
AFFC
AWAI
ETRIG
ASCIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DSGN
SCAN
MULT
CC
CB
CA
ETORF
FIFOR
0
CC2
CC1
CC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCF14
CCF13
CCF12
CCF11
CCF10
CCF9
CCF8
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
IEN14
IEN13
IEN12
IEN11
IEN10
IEN9
IEN8
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
PTAD14
PTAD13
PTAD12
PTAD11
PTAD10
PTAD9
PTAD8
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0
ETRIGLE ETRIGP
0
ASCIF
SC
33
Device User Guide — 9S12KT256DGV1/D V01.09
ATD (Analog to Digital Converter 10 Bit 16 Channel)1
$0080 - $00AF
Address
34
Name
$0090
ATDDR0H
$0091
ATDDR0L
$0092
ATDDR1H
$0093
ATDDR1L
$0094
ATDDR2H
$0095
ATDDR2L
$0096
ATDDR3H
$0097
ATDDR3L
$0098
ATDDR4H
$0099
ATDDR4L
$009A
ATDDR5H
$009B
ATDDR5L
$009C
ATDDR6H
$009D
ATDDR6L
$009E
ATDDR7H
$009F
ATDDR7L
$00A0
ATDDR8H
$00A1
ATDDR8L
$00A2
ATDDR9H
$00A3
ATDDR9L
$00A4
ATDDR10H
$00A5
ATDDR10L
$00A6
ATDDR11H
$00A7
ATDDR11L
$00A8
ATDDR12H
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit15
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
ATD (Analog to Digital Converter 10 Bit 16 Channel)1
$0080 - $00AF
Address
Name
$00A9
ATDDR12L
$00AA
ATDDR13H
$00AB
ATDDR13L
$00AC
ATDDR14H
$00AD
ATDDR14L
$00AE
ATDDR15H
$00AF
ATDDR15L
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit7
Bit 6
Bit6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit 1
0
Bit 0
0
NOTES:
1. Registers only available on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64)
Reserved space1
$00B0 - $00C7
Address
$00B0
- $00C7
Name
Reserved
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
NOTES:
1. Reserved space for MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64)
$0080 - $009F
Address
Name
$0080
ATD0CTL0
$0081
ATD0CTL1
$0082
ATD0CTL2
$0083
ATD0CTL3
$0084
ATD0CTL4
$0085
ATD0CTL5
$0086
ATD0STAT0
$0087
Reserved
$0088
ATD0TEST0
$0089
ATD0TEST1
Freescale Semiconductor
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)1
Bit 7
Read:
0
Write:
Read:
ETRIGSEL
Write:
Read:
ADPU
Write:
Read:
0
Write:
Read:
SRES8
Write:
Read:
DJM
Write:
Read:
SCF
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
0
0
0
0
AFFC
AWAI
S8C
S4C
S2C
SMP1
SMP0
PRS4
DSGN
SCAN
MULT
ETORF
FIFOR
0
0
0
0
0
Bit 2
Bit 1
Bit 0
WRAP2
WRAP1
WRAP0
ETRIGCH2
ETRIGCH1
ETRIGCH0
ETRIG
ASCIE
S1C
FIFO
FRZ1
FRZ0
PRS3
PRS2
PRS1
PRS0
CC
CB
CA
0
CC2
CC1
CC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ETRIGLE ETRIGP
0
0
0
ASCIF
SC
35
Device User Guide — 9S12KT256DGV1/D V01.09
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)1
$0080 - $009F
Address
Name
$008A
Reserved
$008B
ATD0STAT1
$008C
Reserved
$008D
ATD0DIEN
$008E
Reserved
$008F
PORTAD0
$0090
ATD0DR0H
$0091
ATD0DR0L
$0092
ATD0DR1H
$0093
ATD0DR1L
$0094
ATD0DR2H
$0095
ATD0DR2L
$0096
ATD0DR3H
$0097
ATD0DR3L
$0098
ATD0DR4H
$0099
ATD0DR4L
$009A
ATD0DR5H
$009B
ATD0DR5L
$009C
ATD0DR6H
$009D
ATD0DR6L
$009E
ATD0DR7H
$009F
ATD0DR7L
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
0
0
0
0
0
0
0
0
IEN7
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
0
0
0
0
0
0
0
0
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
NOTES:
1. Registers only available on MC9S12KT256 and MC9S12KG256
36
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Reserved space1
$00A0 - $00C7
Address
$00A0
- $00C7
Name
Reserved
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
NOTES:
1. Reserved space for MC9S12KT256 and MC9S12KG256
$00C8 - $00CF
Address
Name
$00C8
SCI0BDH
$00C9
SCI0BDL
$00CA
SCI0CR1
$00CB
SCI0CR2
$00CC
SCI0SR1
$00CD
SCI0SR2
$00CE
SCI0DRH
$00CF
SCI0DRL
$00D0 - $00D7
Address
Name
$00D0
SCI1BDH
$00D1
SCI1BDL
$00D2
SCI1CR1
$00D3
SCI1CR2
$00D4
SCI1SR1
$00D5
SCI1SR2
$00D6
SCI1DRH
$00D7
SCI1DRL
Freescale Semiconductor
SCI0 (Asynchronous Serial Interface)
Bit 7
Bit 6
Read:
0
0
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Read:
0
0
Write:
Read:
R8
T8
Write:
Read:
R7
R6
Write:
T7
T6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
0
0
0
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
RAF
SCI1 (Asynchronous Serial Interface)
Bit 7
Bit 6
Read:
0
0
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Read:
0
0
Write:
Read:
R8
T8
Write:
Read:
R7
R6
Write:
T7
T6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
0
0
0
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
RAF
37
Device User Guide — 9S12KT256DGV1/D V01.09
$00D8 - $00DF
Address
SPI0 (Serial Peripheral Interface)
Name
$00D8
SPI0CR1
$00D9
SPI0CR2
$00DA
SPI0BR
$00DB
SPI0SR
$00DC
Reserved
$00DD
SPI0DR
$00DE
Reserved
$00DF
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00E0 - $00E7
Address
IBAD
$00E1
IBFD
$00E2
IBCR
$00E3
IBSR
$00E4
IBDR
$00E5
Reserved
$00E6
Reserved
$00E7
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00E8 - $00EF
Address
$00E8
- $00EF
38
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODFEN BIDIROE
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
IBEN
IBIE
MS/SL
TX/RX
TXAK
0
TCF
IAAS
IBB
0
0
RSTA
SRW
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
IBAL
IBIF
IBSWAI
RXAK
Reserved space
Name
Reserved
Bit 6
IIC (Inter IC Bus)
Name
$00E0
Bit 7
Read:
Write:
Bit 7
0
Bit 6
0
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$00F0 - $00F7
Address
SPI1 (Serial Peripheral Interface)
Name
$00F0
SPI1CR1
$00F1
SPI1CR2
$00F2
SPI1BR
$00F3
SPI1SR
$00F4
Reserved
$00F5
SPI1DR
$00F6
Reserved
$00F7
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00F8 - $00FF
Address
SPI2CR1
$00F9
SPI2CR2
$00FA
SPI2BR
$00FB
SPI2SR
$00FC
Reserved
$00FD
SPI2DR
$00FE
Reserved
$00FF
Reserved
$0100 - $010F
Address
Name
$0100
FCLKDIV
$0101
FSEC
$0102
FTSTMOD
$0103
FCNFG
Freescale Semiconductor
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODFEN BIDIROE
0
0
SPI2 (Serial Peripheral Interface)
Name
$00F8
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
RNV5
RNV4
RNV3
RNV2
WRALL1
FDFD
0
MODFEN BIDIROE
0
0
Flash Control Register
Bit 7
Bit 6
Read: FDIVLD
PRDIV8
Write:
Read:
KEYEN
Write:
Read:
0
0
Write:
Read:
CBEIE
CCIE
Write:
0
KEYACC
0
DFDIE
SEC
0
0
0
0
0
BKSEL(1)
39
Device User Guide — 9S12KT256DGV1/D V01.09
$0100 - $010F
Address
Name
$0104
FPROT
$0105
FSTAT
$0106
FCMD
$0107
FCTL2
$0108
FADDRHI
$0109
FADDRLO
$010A
FDATAHI
$010B
FDATALO
$010C
Reserved
$010D
Reserved
$010E
Reserved
$010F
Reserved
Flash Control Register
Bit 7
Read:
FPOPEN
Write:
Read:
CBEIF
Write:
Read:
0
Write:
Read:
NV7
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Bit 6
RNV6
CCIF
Bit 5
Bit 4
FPHDIS
PVIOL
Bit 3
FPHS
ACCERR
Bit 2
Bit 1
FPLDIS
DFDIF
Bit 0
FPLS
BLANK
0
0
NV2
NV1
NV0
CMDB
NV6
NV5
NV4
NV3
FADDRHI
FADDRLO
FDATAHI
FDATALO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTES:
1. Bit only available on MC9S12KT256 and MC9S12KG256.
2. Register only available on MC9S12KT256 and MC9S12KG256.
$0110 - $011B
Address
40
Name
$0110
ECLKDIV
$0111
Reserved
$0112
Reserved for
Factory Test
$0113
ECNFG
$0114
EPROT
$0115
ESTAT
$0116
ECMD
$0117
Reserved for
Factory Test
$0118
EADDRHI
EEPROM Control Register
Bit 7
Bit 6
Read: EDIVLD
PRDIV8
Write:
Read:
0
0
Write:
Read:
0
0
Write:
Read:
CBEIE
CCIE
Write:
Read:
NV6
EPOPEN
Write:
Read:
CCIF
CBEIF
Write:
Read:
0
CMDB6
Write:
Read:
0
0
Write:
Read:
0
0
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDIV5
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NV5
NV4
EPDIS
EP2
EP1
EP0
PVIOL
ACCERR
0
0
0
0
0
0
0
0
0
0
0
CMDB5
BLANK
CMDB2
0
CMDB0
0
0
0
10
9
Bit 8
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0110 - $011B
Address
EEPROM Control Register
Name
$0119
EADDRLO
$011A
EDATAHI
$011B
EDATALO
Read:
Write:
Read:
Write:
Read:
Write:
$011C - $011F
Address
$011C
- $011F
$0120 - $013F
Address
Name
$0120
ATD1CTL0
$0121
ATD1CTL1
$0122
ATD1CTL2
$0123
ATD1CTL3
$0124
ATD1CTL4
$0125
ATD1CTL5
$0126
ATD1STAT0
$0127
Reserved
$0128
ATD1TEST0
$0129
ATD1TEST1
$012A
Reserved
$012B
ATD1STAT1
$012C
Reserved
$012D
ATD1DIEN
$012E
Reserved
$012F
PORTAD1
Freescale Semiconductor
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved space
Name
Reserved
Bit 7
Read:
Write:
Bit 7
0
Bit 6
0
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)1
Bit 7
Read:
0
Write:
Read:
ETRIGSEL
Write:
Read:
ADPU
Write:
Read:
0
Write:
Read:
SRES8
Write:
Read:
DJM
Write:
Read:
SCF
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read: CCF7
Write:
Read:
0
Write:
Read:
IEN7
Write:
Read:
0
Write:
Read: PTAD7
Write:
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
WRAP2
WRAP1
WRAP0
0
0
0
0
ETRIGCH2
ETRIGCH1
ETRIGCH0
AFFC
AWAI
ETRIG
ASCIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DSGN
SCAN
MULT
CC
CB
CA
ETORF
FIFOR
0
CC2
CC1
CC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
0
0
0
0
0
0
0
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
0
0
0
0
0
0
0
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0
ETRIGLE ETRIGP
0
0
0
ASCIF
SC
41
Device User Guide — 9S12KT256DGV1/D V01.09
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)1
$0120 - $013F
Address
Name
$0130
ATD1DR0H
$0131
ATD1DR0L
$0132
ATD1DR1H
$0133
ATD1DR1L
$0134
ATD1DR2H
$0135
ATD1DR2L
$0136
ATD1DR3H
$0137
ATD1DR3L
$0138
ATD1DR4H
$0139
ATD1DR4L
$013A
ATD1DR5H
$013B
ATD1DR5L
$013C
ATD1DR6H
$013D
ATD1DR6L
$013E
ATD1DR7H
$013F
ATD1DR7L
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit15
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
NOTES:
1. Registers only available on MC9S12KT256 and MC9S12KG256. Reserved space for MC9S12KG128(64)(32),
MC9S12KL128(64) and MC9S12KC128(64).
$0140 - $017F
Address
42
Name
$0140
CAN0CTL0
$0141
CAN0CTL1
$0142
CAN0BTR0
$0143
CAN0BTR1
$0144
CAN0RFLG
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
RXACT
SYNCH
RXFRM
CSWAI
TIME
WUPE
SLPRQ INITRQ
Write:
Read:
0
SLPAK
INITAK
CANE CLKSRC LOOPB LISTEN
WUPM
Write:
Read:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Write:
Read:
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read:
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
Write:
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0140 - $017F
Address
Name
$0145
CAN0RIER
$0146
CAN0TFLG
$0147
CAN0TIER
$0148
CAN0TARQ
$0149
CAN0TAAK
$014A
CAN0TBSEL
$014B
CAN0IDAC
$014C
Reserved
$014D
Reserved
$014E
CAN0RXERR
$014F
CAN0TXERR
$0150 $0153
$0154 $0157
$0158 $015B
$015C $015F
$0160 $016F
$0170 $017F
CAN0IDAR0 CAN0IDAR3
CAN0IDMR0 CAN0IDMR3
CAN0IDAR4 CAN0IDAR7
CAN0IDMR4 CAN0IDMR7
CAN0RXFG
CAN0TXFG
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Read:
WUPIE
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
Write:
Read:
0
0
0
0
0
TXE2
TXE1
Write:
Read:
0
0
0
0
0
TXEIE2 TXEIE1
Write:
Read:
0
0
0
0
0
ABTRQ2 ABTRQ1
Write:
Read:
0
0
0
0
0
ABTAK2 ABTAK1
Write:
Read:
0
0
0
0
0
TX2
TX1
Write:
Read:
0
0
0
IDHIT2
IDHIT1
IDAM1
IDAM0
Write:
Read:
0
0
0
0
0
0
0
Write:
Read:
0
0
0
0
0
0
0
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
Write:
Read:
FOREGROUND RECEIVE BUFFER see (Table 1-3)
Write:
Read:
FOREGROUND TRANSMIT BUFFER see (Table 1-3)
Write:
Bit 0
RXFIE
TXE0
TXEIE0
ABTRQ0
ABTAK0
TX0
IDHIT0
0
0
RXERR0
TXERR0
AC0
AM0
AC0
AM0
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$xxx0
$xxx1
$xxx2
$xxx3
Name
Extended ID
Standard ID
CANxRIDR0
Extended ID
Standard ID
CANxRIDR1
Extended ID
Standard ID
CANxRIDR2
Extended ID
Standard ID
CANxRIDR3
Freescale Semiconductor
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
43
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
$xxx4- CANxRDSR0 - Read:
$xxxB
CANxRDSR7 Write:
Read:
$xxxC
CANRxDLR
Write:
Read:
$xxxD
Reserved
Write:
Read:
$xxxE
CANxRTSRH
Write:
Read:
$xxxF
CANxRTSRL
Write:
Extended ID Read:
CANxTIDR0 Write:
$xx10
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR1 Write:
$xx10
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR2 Write:
$xx12
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR3 Write:
$xx13
Standard ID Read:
Write:
$xx14- CANxTDSR0 - Read:
$xx1B
CANxTDSR7 Write:
Read:
$xx1C
CANxTDLR
Write:
Read:
$xx1D
CONxTTBPR
Write:
Read:
$xx1E
CANxTTSRH
Write:
Read:
$xx1F
CANxTTSRL
Write:
$0180 - $01BF
Address
44
Name
$0180
CAN1CTL0
$0181
CAN1CTL1
$0182
CAN1BTR0
$0183
CAN1BTR1
Bit 7
DB7
Bit 6
DB6
Bit 5
DB5
Bit 4
DB4
Bit 3
DB3
Bit 2
DB2
Bit 1
DB1
Bit 0
DB0
DLC3
DLC2
DLC1
DLC0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID20
ID19
ID18
SRR=1
IDE=1
ID17
ID16
ID15
ID2
ID1
ID0
RTR
IDE=0
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
CAN1 (Motorola Scalable CAN - MSCAN)1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
RXACT
SYNCH
RXFRM
CSWAI
TIME
WUPE
SLPRQ INITRQ
Write:
Read:
0
SLPAK
INITAK
CANE CLKSRC LOOPB LISTEN
WUPM
Write:
Read:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Write:
Read:
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0180 - $01BF
Address
$0184
$0185
$0186
$0187
$0188
$0189
$018A
$018B
$018C
$018D
$018E
$018F
$0190
$0191
$0192
$0193
$0194
$0195
$0196
$0197
$0198
$0199
$019A
$019B
$019C
Name
CAN1 (Motorola Scalable CAN - MSCAN)1
Bit 7
Bit 6
Bit 5
Read:
RSTAT1
CAN1RFLG
WUPIF
CSCIF
Write:
Read:
CAN1RIER
WUPIE
CSCIE RSTATE1
Write:
Read:
0
0
0
CAN1TFLG
Write:
Read:
0
0
0
CAN1TIER
Write:
Read:
0
0
0
CAN1TARQ
Write:
Read:
0
0
0
CAN1TAAK
Write:
Read:
0
0
0
CAN1TBSEL
Write:
Read:
0
0
CAN1IDAC
IDAM1
Write:
Read:
0
0
0
Reserved
Write:
Read:
0
0
0
Reserved
Write:
Read: RXERR7 RXERR6 RXERR5
CAN1RXERR
Write:
Read: TXERR7 TXERR6 TXERR5
CAN1TXERR
Write:
Read:
CAN1IDAR0
AC7
AC6
AC5
Write:
Read:
CAN1IDAR1
AC7
AC6
AC5
Write:
Read:
CAN1IDAR2
AC7
AC6
AC5
Write:
Read:
CAN1IDAR3
AC7
AC6
AC5
Write:
Read:
CAN1IDMR0
AM7
AM6
AM5
Write:
Read:
CAN1IDMR1
AM7
AM6
AM5
Write:
Read:
CAN1IDMR2
AM7
AM6
AM5
Write:
Read:
CAN1IDMR3
AM7
AM6
AM5
Write:
Read:
CAN1IDAR4
AC7
AC6
AC5
Write:
Read:
CAN1IDAR5
AC7
AC6
AC5
Write:
Read:
CAN1IDAR6
AC7
AC6
AC5
Write:
Read:
CAN1IDAR7
AC7
AC6
AC5
Write:
Read:
CAN1IDMR4
AM7
AM6
AM5
Write:
Freescale Semiconductor
Bit 4
RSTAT0
Bit 3
TSTAT1
Bit 2
TSTAT0
Bit 1
Bit 0
OVRIF
RXF
OVRIE
RXFIE
TXE2
TXE1
TXE0
TXEIE2
TXEIE1
TXEIE0
RSTATE0 TSTATE1 TSTATE0
0
0
0
0
0
0
0
0
0
0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2
ABTAK1
ABTAK0
TX2
TX1
TX0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
0
0
0
IDAM0
RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
AC4
AC3
AC2
AC1
AC0
AC4
AC3
AC2
AC1
AC0
AC4
AC3
AC2
AC1
AC0
AC4
AC3
AC2
AC1
AC0
AM4
AM3
AM2
AM1
AM0
AM4
AM3
AM2
AM1
AM0
AM4
AM3
AM2
AM1
AM0
AM4
AM3
AM2
AM1
AM0
AC4
AC3
AC2
AC1
AC0
AC4
AC3
AC2
AC1
AC0
AC4
AC3
AC2
AC1
AC0
AC4
AC3
AC2
AC1
AC0
AM4
AM3
AM2
AM1
AM0
45
Device User Guide — 9S12KT256DGV1/D V01.09
CAN1 (Motorola Scalable CAN - MSCAN)1
$0180 - $01BF
Address
Name
$019D
CAN1IDMR5
$019E
CAN1IDMR6
$019F
CAN1IDMR7
$01A0 $01AF
$01B0 $01BF
CAN1RXFG
CAN1TXFG
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
FOREGROUND RECEIVE BUFFER see (Table 1-3)
FOREGROUND TRANSMIT BUFFER see (Table 1-3)
NOTES:
1. Registers only available on MC9S12KT256. Reserved space for MC9S12KG256(128)(64)(32), MC9S12KL128(64)
and MC9S12KC128(64).
$01C0 - $023F
Address
$01C0
- $023F
Reserved space
Name
Reserved
Read:
Write:
$0240 - $027F
Address
46
PTT
$0241
PTIT
$0242
DDRT
$0243
RDRT
$0244
PERT
$0245
PPST
$0246
Reserved
$0247
Reserved
$0248
PTS
$0249
PTIS
$024A
DDRS
$024B
RDRS
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
PIM (Port Integration Module)
Name
$0240
Bit 7
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT7
DDRT7
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
DDRS7
DDRS7
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0240 - $027F
Address
PIM (Port Integration Module)
Name
$024C
PERS
$024D
PPSS
$024E
WOMS
$024F
Reserved
$0250
PTM
$0251
PTIM
$0252
DDRM
$0253
RDRM
$0254
PERM
$0255
PPSM
$0256
WOMM
$0257
MODRR
$0258
PTP
$0259
PTIP
$025A
DDRP
$025B
RDRP
$025C
PERP
$025D
PPSP
$025E
PIEP
$025F
PIFP
$0260
PTH
$0261
PTIH
$0262
DDRH
$0263
RDRH
$0264
PERH
Freescale Semiconductor
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
DDRM7
DDRM7
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
RDRM7
RDRM6
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
0
MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
DDRP7
DDRP7
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSS0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
DDRH7
DDRH7
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
47
Device User Guide — 9S12KT256DGV1/D V01.09
$0240 - $027F
Address
Name
$0265
PPSH
$0266
PIEH
$0267
PIFH
$0268
PTJ
$0269
PTIJ
$026A
DDRJ
$026B
RDRJ
$026C
PERJ
$026D
PPSJ
$026E
PIEJ
$026F
PIFJ
$0270 $027F
Reserved
$0280 - $02BF
Address
$0280
$0281
$0282
$0283
$0284
$0285
$0286
$0287
$0288
$0289
$028A
48
PIM (Port Integration Module)
Bit 7
Read:
PPSH7
Write:
Read:
PIEH7
Write:
Read:
PIFH7
Write:
Read:
PTJ7
Write:
Read: PTIJ7
Write:
Read:
DDRJ7
Write:
Read:
RDRJ7
Write:
Read:
PERJ7
Write:
Read:
PPSJ7
Write:
Read:
PIEJ7
Write:
Read:
PIFJ7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
0
0
0
0
PTJ1
PTJ0
0
0
0
0
PTIJ1
PTIJ0
0
0
0
0
DDRJ1
DDRJ0
0
0
0
0
RDRJ1
RDRJ0
0
0
0
0
PERJ1
PERJ0
0
0
0
0
PPSJ1
PPSJ0
0
0
0
0
PIEJ1
PIEJ0
0
0
0
0
PIFJ1
PIFJ0
PTJ6
PTIJ6
DDRJ7
RDRJ6
PERJ6
PPSJ6
PIEJ6
PIFJ6
Read:
CAN4 (Motorola Scalable CAN - MSCAN)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
RXACT
SYNCH
CAN4CTL0
RXFRM
CSWAI
TIME
WUPE
SLPRQ INITRQ
Write:
Read:
0
SLPAK
INITAK
CAN4CTL1
CANE CLKSRC LOOPB LISTEN
WUPM
Write:
Read:
CAN4BTR0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Write:
Read:
CAN4BTR1
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read:
RSTAT1 RSTAT0 TSTAT1 TSTAT0
CAN4RFLG
WUPIF
CSCIF
OVRIF
RXF
Write:
Read:
CAN4RIER
WUPIE
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
RXFIE
Write:
Read:
0
0
0
0
0
CAN4TFLG
TXE2
TXE1
TXE0
Write:
Read:
0
0
0
0
0
CAN4TIER
TXEIE2 TXEIE1 TXEIE0
Write:
Read:
0
0
0
0
0
CAN4TARQ
ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read:
0
0
0
0
0
ABTAK2 ABTAK1 ABTAK0
CAN4TAAK
Write:
Read:
0
0
0
0
0
CAN4TBSEL
TX2
TX1
TX0
Write:
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$0280 - $02BF
Address
$028B
$028C
$028D
$028E
$028F
$0290
$0291
$0292
$0293
$0294
$0295
$0296
$0297
$0298
$0299
$029A
$029B
$029C
$029D
$029E
$029F
$02A0 $02AF
$02B0 $02BF
CAN4 (Motorola Scalable CAN - MSCAN)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
0
0
0
IDHIT2
IDHIT1
IDHIT0
CAN4IDAC
IDAM1
IDAM0
Write:
Read:
0
0
0
0
0
0
0
0
Reserved
Write:
Read:
0
0
0
0
0
0
0
0
Reserved
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CAN4RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
CAN4TXERR
Write:
Read:
CAN4IDAR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDAR1
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDAR2
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDAR3
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDMR0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDMR1
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDMR2
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDMR3
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDAR4
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDAR5
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDAR6
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDAR7
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
CAN4IDMR4
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDMR5
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDMR6
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
CAN4IDMR7
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
FOREGROUND RECEIVE BUFFER see (Table 1-3)
CAN4RXFG
Write:
Read:
CAN4TXFG
FOREGROUND TRANSMIT BUFFER see (Table 1-3)
Write:
Freescale Semiconductor
49
Device User Guide — 9S12KT256DGV1/D V01.09
$02C0 - $02E7
Address
$02C0
$02C1
$02C2
$02C3
$02C4
$02C5
$02C6
$02C7
$02C8
$02C9
$02CA
$02CB
$02CC
$02CD
$02CE
$02CF
$02D0
$02D1
$02D2
$02D3
$02D4
$02D5
$02D6
$02D7
$02D8
50
Name
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7
Read:
PWME
PWME7
Write:
Read:
PWMPOL
PPOL7
Write:
Read:
PWMCLK
PCLK7
Write:
Read:
0
PWMPRCLK
Write:
Read:
PWMCAE
CAE7
Write:
Read:
PWMCTL
CON67
Write:
Read:
0
PWMTST
Test Only
Write:
Read:
0
PWMPRSC
Write:
Read:
PWMSCLA
Bit 7
Write:
Read:
PWMSCLB
Bit 7
Write:
Read:
0
PWMSCNTA
Write:
Read:
0
PWMSCNTB
Write:
Read:
Bit 7
PWMCNT0
Write:
0
Read:
Bit 7
PWMCNT1
Write:
0
Read:
Bit 7
PWMCNT2
Write:
0
Read:
Bit 7
PWMCNT3
Write:
0
Read:
Bit 7
PWMCNT4
Write:
0
Read:
Bit 7
PWMCNT5
Write:
0
Read:
Bit 7
PWMCNT6
Write:
0
Read:
Bit 7
PWMCNT7
Write:
0
Read:
PWMPER0
Bit 7
Write:
Read:
PWMPER1
Bit 7
Write:
Read:
PWMPER2
Bit 7
Write:
Read:
PWMPER3
Bit 7
Write:
Read:
PWMPER4
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
PCLK6
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
CON45
CON23
CON01
PSWAI
PFRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$02C0 - $02E7
Address
Name
$02D9
PWMPER5
$02DA
PWMPER6
$02DB
PWMPER7
$02DC
PWMDTY0
$02DD
PWMDTY1
$02DE
PWMDTY2
$02DF
PWMDTY3
$02E0
PWMDTY4
$02E1
PWMDTY5
$02E2
PWMDTY6
$02E3
PWMDTY7
$02E4
PWMSDN
$02E5
Reserved
$02E6
Reserved
$02E7
Reserved
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
PWMIF
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
$02E8 - $03FF
Address
$02E8
- $03FF
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
PWMIE
0
PWMRS
PWMLVL
TRT
0
0
0
PWM7IN
0
0
PWM7IN PWM7E
L
NA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved space
Name
Reserved
Bit 6
Read:
Write:
Bit 7
0
Bit 6
0
1.8 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset. The read-only value is a unique part ID for each revision of the chip. Table 1-4 Assigned Part
ID Numbers shows the assigned part ID number.
Freescale Semiconductor
51
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-4 Assigned Part ID Numbers
Device
Mask Set Number
MC9S12KT256
MC9S12KG128
0L33V
0L74N
Part ID1
$7000
$7100
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-5 shows the read-only values of these registers. Refer to HCS12 Module
Mapping and Control (MMC) Block Guide for further details.
Table 1-5 Memory size registers
Device
MC9S12KT256
MC9S12KT256
MC9S12KG128
MC9S12KG128
52
Register name
MEMSIZ0
MEMSIZ1
MEMSIZ0
MEMSIZ1
Value
$25
$81
$13
$80
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Section 2 Signal Description
2.1 Device Pinout
The MC9S12K-Family and its derivatives are available in a 112-pin low profile quad flat pack (LQFP), a
100-pin low profile quad flat pack (LQFP), and a 80-pin quad flat pack (QFP). Most pins perform two or
more functions, as described in the Signal Descriptions. Figure 2-1, Figure 2-2 and Figure 2-3 show
the pin assignments for different packages.
Freescale Semiconductor
53
MC9S12K-Family
112LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VRH
VDDA
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
SS2/KWH7/PH7
SCK2/KWH6/PH6
MOSI2/KWH5/PH5
MISO2/KWH4/PH4
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP6/KWP6/PWM6/SS2
PP7/KWP7/PWM7/SCK2
PK7/ECS
VDDX
VSSX
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN4
PM7/TXCAN4
VSSA
VRL
Device User Guide — 9S12KT256DGV1/D V01.09
Signals shown in Bold are not available on the 80 Pin Package
Signals shown in Italic are only available in MC9S12KT256
Figure 2-1 Pin assignments for 112 LQFP
54
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MC9S12K-Family
100LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
KWH5/PH5
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
KWJ1/PJ1
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP6/KWP6/PWM6/SS2
PP7/KWP7/PWM7/SCK2
VDDX
VSSX
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
Device User Guide — 9S12KT256DGV1/D V01.09
Signals shown in Bold are not available on the 80 Pin Package
Signals shown in Italic are only available in MC9S12KT256
Figure 2-2 Pin assignments for 100 LQFP
Freescale Semiconductor
55
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MC9S12K-Family
80 QFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PWM3/KWP3/PP3
PWM2/KWP2/PP2
PWM1/KWP1/PP1
PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP7/KWP7/PWM7SCK2
VDDX
VSSX
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
Device User Guide — 9S12KT256DGV1/D V01.09
Signals shown in Italic are only available in MC9S12KT256
Figure 2-3 Pin assignments for 80 QFP
56
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
2.2 Signal Properties Summary
(Table 2-1) summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package. (Table 2-2) summarizes the power and ground pins.
Table 2-1 Signal Properties
Pin Name Pin Name Powered
Function 3 Function 4
by
Internal Pull
Resistor
Reset
CTRL
State
Pin Name
Function 1
Pin Name
Function 2
EXTAL
—
—
—
VDDPLL
NA
NA
XTAL
—
—
—
VDDPLL
NA
NA
RESET
—
—
—
VDDR
None
None
Description
Oscillator Pins
External Reset
TEST
—
—
—
NA
NA
NA
Test Input
VREGEN
—
—
—
VDDX
NA
NA
Voltage Regulator Enable Input
XFC
—
—
—
VDDPLL
NA
NA
PLL Loop Filter
VDDR
Always
Up
Up
Background Debug, Tag High, Mode
Input
BKGD
PAD[15:8]
TAGHI
AN[15:8]
MODC
AN1[7:0]1
—
—
VDDA
None
None
Port AD Input, Analog Inputs of ATD
in MC9S12KG128(64)(32),
MC9S12KL128(64) and
MC9S12KC128(64); Analog Inputs of
ATD1 in MC9S12KT256 and
MC9S12KG256
None
Port AD Input, Analog Inputs of ATD in
MC9S12KG128(64)(32),
MC9S12KL128(64) and
MC9S12KC128(64); Analog Inputs of
ATD0 in MC9S12KT256 and
MC9S12KG256
PAD[7:0]
AN[7:0]
AN0[7:0]1
—
VDDA
None
PA[7:0]
ADDR[15:8]/
DATA[15:8]
—
—
VDDR
PUCR
Disabled Port A I/O, Multiplexed Address/Data
PB[7:0]
ADDR[7:0]/
DATA[7:0]
—
—
VDDR
PUCR
Disabled Port B I/O, Multiplexed Address/Data
PE7
NOACC
XCLKS
—
VDDR
PUCR
PE6
IPIPE1
MODB
—
VDDR
While RESET
pin is low:
Down
Port E I/O, Pipe Status, Mode Input
PE5
IPIPE0
MODA
—
VDDR
While RESET
pin is low:
Down
Port E I/O, Pipe Status, Mode Input
PE4
ECLK
—
—
VDDR
PUCR
Up
Port E I/O, Bus Clock Output
PE3
LSTRB
TAGLO
—
VDDR
PUCR
Up
Port E I/O, Byte Strobe, Tag Low
PE2
R/W
—
—
VDDR
PUCR
Up
Port E I/O, R/W in expanded modes
PE1
IRQ
—
—
VDDR
PE0
XIRQ
—
—
VDDR
PH7
KWH7
SS2
—
VDDR
Freescale Semiconductor
Up
Always Up
PERH/
PPSH
Port E I/O, Access, Clock Select
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
Disabled Port H I/O, Interrupt, SS of SPI2
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Pin Name Pin Name Powered
Function 3 Function 4
by
Internal Pull
Resistor
Reset
CTRL
State
Pin Name
Function 1
Pin Name
Function 2
PH6
KWH6
SCK2
—
VDDR
PERH/
PPSH
Disabled
PH5
KWH5
MOSI2
—
VDDR
PERH/
PPSH
Disabled
PH4
KWH4
MISO2
—
VDDR
PERH/
PPSH
Disabled
PH3
KWH3
SS1
—
VDDR
PERH/
PPSH
Disabled
PH2
KWH2
SCK1
—
VDDR
PERH/
PPSH
Disabled
PH1
KWH1
MOSI1
—
VDDR
PERH/
PPSH
Disabled
PH0
KWH0
MISO1
—
VDDR
PERH/
PPSH
Disabled
PJ7
KWJ7
TXCAN4
SCL
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, TX of CAN4,
SCL of IIC
PJ6
KWJ6
RXCAN4
SDA
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, RX of CAN4,
SDA of IIC
PJ[1:0]
KWJ[1:0]
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupts
PK7
ECS
ROMCTL
—
VDDX
PUCR
Up
Port K I/O, Emulation Chip Select,
ROM On Enable
PK[5:0]
XADDR[19:14]
—
—
VDDX
PUCR
Up
Port K I/O, Extended Addresses
Disabled Port M I/O, CAN4 TX
Description
Port H I/O, Interrupt, SCK of SPI2
Port H I/O, Interrupt, MOSI of SPI2
Port H I/O, Interrupt, MISO of SPI2
Port H I/O, Interrupt, SS of SPI1
Port H I/O, Interrupt, SCK of SPI1
Port H I/O, Interrupt, MOSI of SPI1
Port H I/O, Interrupt, MISO of SPI1
PM7
TXCAN4
—
—
VDDX
PERM/
PPSM
PM6
RXCAN4
—
—
VDDX
PERM/
PPSM
Disabled Port M I/O, CAN4 RX
PM5
TXCAN0
TXCAN4
SCK0
VDDX
PERM/
PPSM
Disabled
Port M I/O, CAN0 TX, CAN4 TX,
SPI0 SCK
PM4
RXCAN0
RXCAN4
MOSI0
VDDX
PERM/
PPSM
Disabled
Port M I/O, CAN0 RX, CAN4 RX,
SPI0 MOSI
PM3
TXCAN11
TXCAN0
SS0
VDDX
PERM/
PPSM
Disabled
Port M I/O, CAN1 TX, CAN0 TX, SPI0
SS
PM2
RXCAN11
RXCAN0
MISO0
VDDX
PERM/
PPSM
Disabled
Port M I/O, CAN1 RX, CAN0 RX, SPI0
MISO
PM1
TXCAN0
—
—
VDDX
PERM/
PPSM
Disabled Port M I/O, CAN0 TX
PM0
RXCAN0
—
—
VDDX
PERM/
PPSM
Disabled Port M I/O, CAN0 RX
PP7
KWP7
PWM7
SCK2
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 7,
SCK of SPI2
PP6
KWP6
PWM6
SS2
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 6,
SPI2 SS
PP5
KWP5
PWM5
MOSI2
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 5,
SPI2 MOSI
PP4
KWP4
PWM4
MISO2
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 4,
SPI2 MISO
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Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Pin Name Pin Name Powered
Function 3 Function 4
by
Internal Pull
Resistor
Reset
CTRL
State
Pin Name
Function 1
Pin Name
Function 2
PP3
KWP3
PWM3
SS1
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 3,
SPI1 SS
PP2
KWP2
PWM2
SCK1
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 2,
SPI1 SCK
PP1
KWP1
PWM1
MOSI1
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 1,
SPI1 MOSI
PP0
KWP0
PWM0
MISO1
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, PWM Channel 0,
SPI1 MISO
PS7
SS0
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SPI0 SS
PS6
SCK0
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SPI0 SCK
PS5
MOSI0
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SPI0 MOSI
PS4
MISO0
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SPI0 MISO
PS3
TXD1
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SCI1TXD
PS2
RXD1
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SCI1RXD
PS1
TXD0
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SCI0 TXD
PS0
RXD0
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SCI0 RXD
PT[7:0]
IOC[7:0]
—
—
VDDX
Up or
Down
Description
Disabled Port T I/O, Timer channels
NOTES:
1. Only available on MC9S12KT256.
Table 2-2 Power and Ground
Mnemonic
Nominal
Voltage
VDD1
VDD2
2.5 V
VSS1
VSS2
0V
VDDR
3.3/5.0 V
VSSR
0V
VDDX
3.3/5.0 V
VSSX
0V
VDDA
3.3/5.0 V
VSSA
0V
VRH
3.3/5.0 V
Reference voltage high for the ATD converter.
VRL
0V
Reference voltage low for the ATD converter.
Freescale Semiconductor
Description
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and
bypass the internal voltage regulator.
External power and ground, supply to pin drivers and internal voltage
regulator.
External power and ground, supply to pin drivers.
Operating voltage and ground for the analog-to-digital converter and
the reference for the internal voltage regulator, allows the supply
voltage to the A/D to be bypassed independently.
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Device User Guide — 9S12KT256DGV1/D V01.09
NOTE:
Mnemonic
Nominal
Voltage
VDDPLL
2.5 V
VSSPLL
0V
Description
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
All VSS pins must be connected together in the application. Because fast signal
transitions place high, short-duration current demands on the power supply, use
bypass capacitors with high-frequency characteristics and place them as close to
the MCU as possible. Bypass requirements depend on MCU pin load.
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
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2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
R
MCU
CP
CS
VDDPLL
VDDPLL
Figure 2-4 PLL Loop Filter Connections
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]
PAD15 - PAD8 are general purpose input pins and analog inputs of the single analog to digital converter
with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD15 PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels
(ATD1) on MC9S12KT256 and MC9S12KG256.
2.3.8 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD7 - PAD0 are general purpose input pins and analog inputs of the single analog to digital converter
with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD7 PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels
(ATD0) on MC9S12KT256 and MC9S12KG256.
2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
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2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop
Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock
circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the
EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic
high a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an
input with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop
Controlled Pierce oscillator circuit on EXTAL and XTAL.
Table 2-3 Clock selection based on PE7 during reset
PE7
Description
1
Loop Controlled Pierce Oscillator selected
0
Full Swing Pierce Oscillator or external clock selected
EXTAL
C7
MCU
Crystal or
ceramic resonator
XTAL
C8
VSSPLL
Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1)
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Device User Guide — 9S12KT256DGV1/D V01.09
EXTAL
C7
MCU
Crystal or
ceramic resonator
RB
RS
XTAL
*
C8
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
MCU
XTAL
not connected
Figure 2-7 External Clock Connections (PE7=0)
2.3.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1.
2.3.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0.
2.3.14 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
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2.3.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.16 PE2 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.17 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
2 (SPI2).
2.3.20 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
2 (SPI2).
2.3.21 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.22 PH4 / KWH4 / MISO2 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
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2.3.23 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
1 (SPI1).
2.3.24 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).
2.3.25 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.26 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.27 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
2.3.28 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
2.3.29 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.30 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). During MCU expanded modes of operation, this pin is used to
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.For all other modes the reset state of the ROMON bit is as
follows:
special single : ROMCTL = 1
normal single : ROMCTL = 1
emulation expanded wide : ROMCTL = 0
emulation expanded narrow : ROMCTL = 0
special test : ROMCTL = 0
peripheral test : ROMCTL = 1
2.3.31 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.32 PM7 / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.33 PM6 / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.34 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as
the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as
the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial
Peripheral Interface 0 (SPI0).
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2.3.36 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial
Peripheral Interface 0 (SPI0).
2.3.38 PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.39 PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.40 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.41 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.42 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 2 (SPI2).
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2.3.43 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.45 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.46 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
2.3.47 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
2.3.48 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.49 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
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2.3.50 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
2.3.53 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.54 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.55 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Timer (TIM).
2.4 Power Supply Pins
MC9S12K-Family power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application.
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2.4.1 VDDX,VSSX — Power Supply Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage
Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
NOTE:
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
HCS12 CORE
Core Clock
BDM
CPU
MEBI
MMC
INT
DBG
Flash
RAM
EEPROM
TIM
EXTAL
ATD
OSC
CRG
Bus Clock
PWM
SCI0, SCI1
Oscillator Clock
XTAL
SPI0, SPI1, SPI2
CAN0, CAN1, CAN4
IIC
PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12K-Family. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset ((Table 4-1)). The MODC, MODB, and MODA bits in the MODE register show the current
operating mode and provide limited mode switching during operation. The states of the MODC, MODB,
and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal
allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is
visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the
ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
ROMON
Bit
0
0
0
X
1
0
0
1
0
1
1
0
0
1
0
X
0
0
1
1
0
X
1
0
0
1
1
X
1
0
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 MEBI Block Guide.
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Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
Description
1
Loop Controlled Pierce Oscillator selected
0
Full Swing Pierce Oscillator or external clock selected
Table 4-3 Voltage Regulator VREGEN
VREGEN
Description
1
Internal Voltage Regulator enabled
0
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
Protection of the contents of FLASH,
•
Protection of the contents of EEPROM,
•
Operation in single-chip mode,
•
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
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4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
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4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. Both local masking and CCR masking are included as listed in Table 5-1. System resets can
be generated through external control of the RESET pin, through the clock and reset generator module
CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG
and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
5.2.1 Vector Table
(Table 5-1) lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Interrupt Source
CCR
Mask
Local Enable
HPRIO Value
to Elevate
$FFFE, $FFFF
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register
to determine reset source)
None
None
–
$FFFC, $FFFD
Clock Monitor fail reset
None
PLLCTL (CME, FCME)
–
$FFFA, $FFFB
COP failure reset
None
COP rate select
–
$FFF8, $FFF9
Unimplemented instruction trap
None
None
–
$FFF6, $FFF7
SWI
None
None
–
$FFF4, $FFF5
XIRQ
X-Bit
None
–
$FFF2, $FFF3
IRQ
I-Bit
IRQCR (IRQEN)
$F2
$FFF0, $FFF1
Real Time Interrupt
I-Bit
CRGINT (RTIE)
$F0
$FFEE, $FFEF
Standard Timer channel 0
I-Bit
TIE (C0I)
$EE
$FFEC, $FFED
Standard Timer channel 1
I-Bit
TIE (C1I)
$EC
$FFEA, $FFEB
Standard Timer channel 2
I-Bit
TIE (C2I)
$EA
$FFE8, $FFE9
Standard Timer channel 3
I-Bit
TIE (C3I)
$E8
$FFE6, $FFE7
Standard Timer channel 4
I-Bit
TIE (C4I)
$E6
$FFE4, $FFE5
Standard Timer channel 5
I-Bit
TIE (C5I)
$E4
$FFE2, $FFE3
Standard Timer channel 6
I-Bit
TIE (C6I)
$E2
$FFE0, $FFE1
Standard Timer channel 7
I-Bit
TIE (C7I)
$E0
$FFDE, $FFDF
Standard Timer overflow
I-Bit
TSCR2 (TOI)
$DE
$FFDC, $FFDD
Pulse accumulator overflow
I-Bit
PACTL (PAOVI)
$DC
$FFDA, $FFDB
Pulse accumulator input edge
I-Bit
PACTL (PAI)
$DA
$FFD8, $FFD9
SPI0
I-Bit
SPICR1 (SPIE, SPTIE)
$D8
$D6
Vector Address
$FFD6, $FFD7
SCI0
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD4, $FFD5
SCI1
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
$D4
$FFD2, $FFD3
ATD0
I-Bit
ATDCTL2 (ASCIE)
$D2
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$FFD0, $FFD1
ATD1
I-Bit
ATDCTL2 (ASCIE)1
$D0
$CE
$CC
$FFCE, $FFCF
Port J
I-Bit
PIEJ
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
$FFCC, $FFCD
Port H
I-Bit
PIEH (PIEH7-0)
$FFCA, $FFCB
Reserved
$FFC8, $FFC9
$FFC6, $FFC7
I-Bit
$CA
Reserved
I-Bit
$C8
CRG PLL lock
I-Bit
CRGINT (LOCKIE)
$C6
$FFC4, $FFC5
CRG Self Clock Mode
I-Bit
CRGINT (SCMIE)
$C4
$FFC2, $FFC3
FLASH Double Fault Detect
I-Bit
FCNFG (DFDIE)
$C2
$FFC0, $FFC1
IIC Bus
I-Bit
IBCR (IBIE)
$C0
$FFBE, $FFBF
SPI1
I-Bit
SPICR1 (SPIE, SPTIE)
$BE
$FFBC, $FFBD
SPI2
I-Bit
SPICR1 (SPIE, SPTIE)
$BC
$FFBA, $FFBB
EEPROM command
I-Bit
ECNFG (CCIE, CBEIE)
$BA
$FFB8, $FFB9
FLASH command
I-Bit
FCNFG (CCIE, CBEIE)
$B8
$FFB6, $FFB7
CAN0 wake-up
I-Bit
CAN0RIER (WUPIE)
$B6
$FFB4, $FFB5
CAN0 errors
I-Bit
CAN0RIER (CSCIE, OVRIE)
$B4
$FFB2, $FFB3
CAN0 receive
I-Bit
CAN0RIER (RXFIE)
$B2
$FFB0, $FFB1
CAN0 transmit
I-Bit
CAN0TIER (TXEIE2 - TXEIE0)
$FFAE, $FFAF
CAN1 wake-up
I-Bit
$FFAC, $FFAD
CAN1 errors
I-Bit
$FFAA, $FFAB
CAN1 receive
$FFA8, $FFA9
CAN1 transmit
CAN1RIER
CAN1RIER (CSCIE, OVRIE)1
I-Bit
I-Bit
(WUPIE)1
CAN1RIER
(RXFIE)1
CAN1TIER (TXEIE2 -
TXEIE0)1
$B0
$AE
$AC
$AA
$A8
$FFA6, $FFA7
I-Bit
$A6
$FFA4, $FFA5
I-Bit
$A4
$FFA2, $FFA3
I-Bit
$A2
$FFA0, $FFA1
I-Bit
Reserved
$FF9E, $FF9F
Reserved
I-Bit
$A0
$9E
$FF9C, $FF9D
I-Bit
$9C
$FF9A, $FF9B
I-Bit
$9A
$FF98, $FF99
I-Bit
$98
$FF96, $FF97
CAN4 wake-up
I-Bit
CAN4RIER (WUPIE)
$96
$FF94, $FF95
CAN4 errors
I-Bit
CAN4RIER (CSCIE, OVRIE)
$94
$FF92, $FF93
CAN4 receive
I-Bit
CAN4RIER (RXFIE)
$92
$FF90, $FF91
CAN4 transmit
I-Bit
CAN4TIER (TXEIE2 - TXEIE0)
$90
$FF8E, $FF8F
Port P
I-Bit
PIEP (PIEP7-0)
$8E
$FF8C, $FF8D
PWM Emergency Shutdown
I-Bit
PWMSDN (PWMIE)
$8C
$FF8A, $FF8B
VREG Low Voltage Interrupt
I-Bit
CTRL0 (LVIE)
$8A
$FF80 to $FF89
Reserved
NOTES:
1. Interrupt vector is only available on MC9S12KT256. Otherwise it is reserved.
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5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2.
Table 5-2 Reset Summary
Reset
Priority
Source
Vector
Power-on Reset
1
CRG Module
$FFFE, $FFFF
External Reset
1
RESET pin
$FFFE, $FFFF
Low Voltage Reset
1
VREG Module
$FFFE, $FFFF
Clock Monitor Reset
2
CRG Module
$FFFC, $FFFD
COP Watchdog Reset
3
CRG Module
$FFFA, $FFFB
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode
dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
Refer to Table 1-2(Table 1-2) for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit.
When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods.
So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module.
When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
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6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface
module.
6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). When the ATD_10B16C Block
Guide refers to freeze mode this is equivalent to active BDM mode.
Consult the ATD_10B8C Block Guide for further information about the A/D Converter module for the
MC9S12KT256 and MC9S12KG256. When the ATD_10B8C Block Guide refers to freeze mode this is
equivalent to active BDM mode.
Section 8 Clock Reset Generator (CRG) Block Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block Guide for voltage level specifications.
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Section 9 EEPROM Block Description
Consult the EETS2K Block Guide for information about the EEPROM module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the EETS4K Block Guide for information about the EEPROM module for the MC9S12KT256
and MC9S12KG256.
Section 10 Flash EEPROM Block Description
Consult the FTS128K1ECC Block Guide for information about the flash module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the FTS256K2ECC Block Guide for information about the flash module for the MC9S12KT256
and MC9S12KG256.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into
the flash memory of this device during manufacture. This LRAE program will provide greater
programming flexibility to the end users by allowing the device to be programmed directly using SCI after
it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not
required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its
implementation, please see the S12 LREA Application Note (AN2546/D) .
It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE
programmed in the Flash . Exact details of the changeover (ie blank to programmed) for each product will
be communicated in advance via GPCN and will be traceable by the customer via datecode marking on
the device.
Please contact Motorola SPS Sales if you have any additional questions.
Section 11 IIC Block Description
Consult the IIC Block Guide for information about the Inter-IC Bus module.
Section 12 MSCAN Block Description
There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12KT256. There
are only two MSCAN modules (CAN4 and CAN0) implemented on the MC9S12KG128(64)(32). There
is only one MSCAN module (CAN0) implemented on the MC9S12KL128(64) and MC9S12KC128(64).
Consult the MSCAN Block Guide for information about the Motorola Scalable CAN Module.
Section 13 OSC Block Description
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Consult the OSC_LCP Block Guide for information about the Oscillator module.
Section 14 Port Integration Module (PIM) Block Description
Consult the PIM_9KG128 Block Guide for information about the Port Integration Module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the PIM_9KT256 Block Guide for information about the Port Integration Module for the
MC9S12KT256 and MC9S12KG256.
Section 15 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator Module. When
the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 16 Serial Communications Interface (SCI) Block
Description
There are two Serial Communications Interface modules (SCI1 and SCI0). Consult the SCI Block Guide
for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block
Description
There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12K-Family.
Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 18 Timer (TIM) Block Description
Consult the TIM_16B8C Block Guide for information about the Timer module. When the TIM_16B8C
Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG_3V3 Block Guide for information about the dual output linear voltage regulator.
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19.1 Device-specific information
19.1.1 VDD1, VDD2, VSS1, VSS2
In all package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the
device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together
internally. VSS1 and VSS2 are connected together internally. This allows systems to employ better supply
routing and further decoupling.
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Appendix A Electrical Characteristics
A.1 General
NOTE:
The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
This supplement contains the most accurate electrical information for the MC9S12K-Family of
microcontrollers available at the time of publication. The information should be considered
PRELIMINARY and is subject to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE:
This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T:
Those parameters are achieved by design characterization on a small sample size from typical
devices. All values shown in the typical column are within this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12K-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator,
PLL and internal logic.
The VDDA, VSSA pair supplies the A/D converter.
The VDDX, VSSX pair supplies the I/O pins
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The VDDR, VSSR pair supplies the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic.
VDDPLL, VSSPLL supply the oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDD1 and VDD2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the
sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used
for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is
used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 3.3V/5V I/O pins
Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This
group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The
internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for
the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2 Analog Reference
This group of pins is comprised of the VRH and VRL pins.
A.1.3.3 Oscillator
The pins EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by
VDDPLL.
A.1.3.4 PLL
The pin XFC dedicated to the oscillator have a nominal 2.5V level. It is supplied by VDDPLL.
A.1.3.5 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
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Device User Guide — 9S12KT256DGV1/D V01.09
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings
Num
Rating
Symbol
Min
Max
Unit
1
I/O, Regulator and Analog Supply Voltage
VDD5
-0.3
6.5
V
2
Internal Logic Supply Voltage1
VDD
-0.3
3.0
V
3
PLL Supply Voltage (1)
VDDPLL
-0.3
3.0
V
4
Voltage difference VDDX to VDDR and VDDA
∆VDDX
-0.3
0.3
V
5
Voltage difference VSSX to VSSR and VSSA
∆VSSX
-0.3
0.3
V
6
Digital I/O Input Voltage
VIN
-0.3
6.5
V
7
Analog Reference
VRH, VRL
-0.3
6.5
V
8
XFC, EXTAL, XTAL inputs
VILV
-0.3
3.0
V
9
TEST input
VTEST
-0.3
10.0
V
10
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 2
ID
-25
+25
mA
11
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL3
IDL
-25
+25
mA
12
Instantaneous Maximum Current
Single pin limit for TEST4
IDT
-0.25
0
mA
13
Operating Temperature Range (packaged)
TA
– 40
125
°C
14
Operating Temperature Range (junction)
TJ
– 40
140
°C
15
Storage Temperature Range
Tstg
– 65
155
°C
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
3. These pins are internally clamped to VSSPLL and VDDPLL
4. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ohm
Storage Capacitance
C
100
pF
Number of Pulse per pin
positive
negative
-
3
3
Series Resistance
R1
0
Ohm
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
-
3
3
Minimum input voltage limit
-2.5
V
Maximum input voltage limit
7.5
V
Latch-up
Table A-3 ESD and Latch-Up Protection Characteristics
Num
C
1
C
2
Rating
Symbol
Min
Max
Unit
Human Body Model (HBM)
VHBM
2000
-
V
C
Machine Model (MM)
VMM
200
-
V
3
C
Charge Device Model (CDM)
VCDM
500
-
V
4
C
Latch-up Current at 125°C
positive
negative
ILAT
+100
-100
-
mA
5
C
Latch-up Current at 27°C
positive
negative
ILAT
+200
-200
-
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
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Device User Guide — 9S12KT256DGV1/D V01.09
NOTE:
Instead of specifying ambient temperature all parameters are specified for the more
meaningful silicon junction temperature. For power dissipation calculations refer
to Section A.1.8 Power Dissipation and Thermal Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
Typ
Max
Unit
I/O, Regulator and Analog Supply Voltage
VDD5
3.15
3.3/5
5.5
V
Internal Logic Supply Voltage1
VDD
2.35
2.5
2.75
V
PLL Supply Voltage (1)
VDDPLL
2.35
2.5
2.75
V
Voltage Difference VDDX to VDDA
∆VDDX
-0.1
0
0.1
V
Voltage Difference VSSX to VSSR and VSSA
∆VSSX
-0.1
0
0.1
V
Oscillator
fosc
0.5
-
16
MHz
Bus Frequency
fbus
0.5
-
25
MHz
Operating Junction Temperature Range
TJ
-40
-
100
°C
Operating Ambient Temperature Range 2
TA
-40
27
85
°C
Operating Junction Temperature Range
TJ
-40
-
120
°C
Operating Ambient Temperature Range (2)
TA
-40
27
105
°C
Operating Junction Temperature Range
TJ
-40
-
140
°C
Operating Ambient Temperature Range (2)
TA
-40
27
125
°C
MC9S12K-FamilyC/MC9S12KT256C
MC9S12K-FamilyV/MC9S12KT256V
MC9S12K-FamilyM/MC9S12KT256M
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
T J = T A + ( P D • Θ JA )
T J = Junction Temperature, [°C ]
T A = Ambient Temperature, [°C ]
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P D = Total Chip Power Dissipation, [W]
Θ JA = Package Thermal Resistance, [°C/W]
The total power dissipation can be calculated from:
P D = P INT + P IO
P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA
2
P IO =
R DSON ⋅ I IO
i
i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For RDSON is valid:
V OL
R DSON = ------------ ;for outputs driven low
I OL
respectively
V DD5 – V OH
R DSON = ------------------------------------ ;for outputs driven high
I OH
2. Internal voltage regulator enabled
P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA
IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
2
P IO =
R DSON ⋅ I IO
i
i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-5 Thermal Package Characteristics1
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
T Thermal Resistance LQFP112, single sided PCB2
θJA
-
-
54
o
2
T
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
θJA
-
-
41
oC/W
3
T Thermal Resistance QFP 80, single sided PCB
θJA
-
-
51
o
C/W
4
T
θJA
-
-
41
o
C/W
Thermal Resistance QFP 80, double sided PCB with
2 internal planes
C/W
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable,
e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
1
P
2
P
3
C Input Hysteresis
4
P
5
P
Rating
Symbol
Min
Typ
Max
Unit
Input High Voltage
VIH
0.65*VDD5
-
VDD5 + 0.3
V
Input Low Voltage
VIL
VSS5 - 0.3
-
0.35*VDD5
V
Input Leakage Current (pins in high impedance input
mode)
Vin = VDD5 or VSS5
Output High Voltage (pins in output mode)
Partial Drive IOH = –2.0mA
VHYS
250
mV
Iin
–2.5
-
2.5
µA
VOH
VDD5 – 0.8
-
-
V
VOL
-
-
0.8
V
Full Drive IOH = –10.0mA
6
P
Output Low Voltage (pins in output mode)
Partial Drive IOL = +2.0mA
Full Drive IOL = +10.0mA
7
P
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
-
-
–130
µA
8
P
Internal Pull Up Device Current,
tested at VIH Min.
IPUH
-10
-
-
µA
9
P
Internal Pull Down Device Current,
tested at VIH Min.
IPDH
-
-
130
µA
10
P
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
10
-
-
µA
11
D Input Capacitance
7
-
pF
12
T
Injection current1
Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
-
2.5
25
mA
13
P
Port H, J, P Interrupt Input Pulse filtered2
tpign
3
µs
14
P
Port H, J, P Interrupt Input Pulse passed(2)
tpval
Cin
-2.5
-25
10
µs
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-7 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Input High Voltage
VIH
0.65*VDD5
-
VDD5 + 0.3
V
2
P Input Low Voltage
VIL
VSS5 - 0.3
-
0.35*VDD5
V
3
C Input Hysteresis
4
Input Leakage Current (pins in high impedance input
P mode)
Vin = VDD5 or VSS5
VHYS
250
mV
Iin
–1
-
1
µA
5
Output High Voltage (pins in output mode)
P Partial Drive IOH = –0.75mA
Full Drive IOH = –4.5mA
VOH
VDD5 – 0.4
-
-
V
6
Output Low Voltage (pins in output mode)
P Partial Drive IOL = +0.9mA
Full Drive IOL = +5.5mA
VOL
-
-
0.4
V
7
Internal Pull Up Device Current,
P tested at V Max.
IL
IPUL
-
-
–60
µA
8
Internal Pull Up Device Current,
P tested at V Min.
IH
IPUH
-6
-
-
µA
9
Internal Pull Down Device Current,
P tested at V Min.
IH
IPDH
-
-
60
µA
10
Internal Pull Down Device Current,
P tested at V Max.
IL
IPDL
6
-
-
µA
11
D Input Capacitance
Cin
7
-
pF
12
Injection current1
T Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
-
2.5
25
mA
13
P Port P, J Interrupt Input Pulse filtered2
tPULSE
3
µs
14
P Port P, J Interrupt Input Pulse passed(2)
tPULSE
-2.5
-25
10
µs
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
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Device User Guide — 9S12KT256DGV1/D V01.09
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
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Table A-8 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
Rating
Symbol
Min
Typ
Max
1
Run supply currents
Single Chip, Internal regulator enabled
IDD5
65
IDDW
40
5
Unit
mA
Wait Supply current
All modules enabled
only RTI enabled1
2
3
4
Pseudo Stop Current (RTI and COP enabled)1,2
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Pseudo Stop Current (RTI and COP disabled)1,2
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
IDDPS
IDDPS
90
130
155
180
250
295
470
520
1000
40
80
105
130
200
245
420
470
800
mA
350
1200
µA
2400
5000
200
1000
µA
2000
5000
Stop Current2
5
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
IDDS
20
60
85
110
180
225
400
450
600
100
800
µA
1800
5000
NOTES:
1. PLL off
2. All those low power dissipation levels TJ = TA can be assumed.
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A.2 Voltage Regulator (VREG_3V3) Operating Characteristics
This section describes the characteristics of the on chip voltage regulator.
Table A-9 VREG_3V3 - Operating Conditions
Num
C
Symbol
Min
Typical
Max
Unit
1
P
Input Voltages
VVDDR,A
3.15
—
5.5
V
2
P
Regulator Current
Reduced Power Mode
Shutdown Mode
IREG
—
—
20
12
50
40
µA
µA
P
Output Voltage Core
Full Performance Mode
Reduced Power Mode
Shutdown Mode1
VDD
2.35
1.7
—
2.5
2.5
—
2.75
2.75
—
V
V
V
4
P
Output Voltage PLL
Full Performance Mode
Reduced Power Mode2
Shutdown Mode(1)
VDDPLL
2.35
1.7
—
2.5
2.5
—
2.75
2.75
—
V
V
V
5
P
Low Voltage Interrupt3
Assert Level
Deassert Level
VLVIA
VLVID
4.1
4.25
4.37
4.52
4.66
4.77
V
V
5
P
Low Voltage Reset4
Assert Level
Deassert Level
VLVRA
VLVRD
2.25
—
—
—
—
2.55
V
V
7
C
Power-on Reset5
Assert Level
Deassert Level
VPORA
VPORD
0.97
—
-----
—
2.05
V
V
3
Characteristic
NOTES:
1. High Impedance Output
2. Current IDDPLL = 500µA
3. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
low supply voltage.
4. Monitors VDD, active only in Full Performance Mode. VLVRA and VPORD must overlap
5. Monitors VDD. Active in all modes.
NOTE:
94
The electrical characteristics given in this section are preliminary and
should be used as a guide only. Values in this section cannot be
guaranteed by Motorola and are subject to change without notice.
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
A.3 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage
reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1.
Figure A-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
V
VDDA
VLVID
VLVIA
VDD
VLVRD
VLVRA
VPORD
t
LVI
LVI enabled
LVI disabled due to LVR
POR
LVR
A.4 Output Loads
A.4.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no
external DC loads.
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A.4.2 Capacitive Loads
The capacitive loads are specified in Table A-10. Ceramic capacitors with X7R dielectricum are required.
Table A-10 Voltage Regulator - Capacitive Loads
Num
Characteristic
1
VDD external capacitive load
2
VDDPLL external capacitive load
96
Symbol
Min
Typical
Max
Unit
CDDext
200
440
12000
nF
CDDPLLext
90
220
5000
nF
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
A.5 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.5.1 ATD Operating Characteristics
The Table A-11 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table A-11 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
VRL
VRH
VSSA
VDDA/2
VRH-VRL
4.75
fATDCLK
Typ
Max
Unit
VDDA/2
VDDA
V
V
5.25
V
0.5
2.0
MHz
NCONV10
TCONV10
TCONV10
14
7
3.5
28
14
7
Cycles
µs
µs
NCONV8
TCONV8
12
6
26
13
Cycles
µs
Reference Potential
1
D
Low
High
2
C Differential Reference Voltage1
3
D ATD Clock Frequency
5.0
ATD 10-Bit Conversion Period
4
D
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
Conv, Time at 4.0MHz3 ATD Clock fATDCLK
ATD 8-Bit Conversion Period
Clock Cycles(1)
Conv, Time at 2.0MHz ATD Clock fATDCLK
5
D
6
D Stop Recovery Time (VDDA=5.0 Volts)
tSR
20
µs
7
P Reference Supply current (two ATD modules)
IREF
0.750
mA
8
P Reference Supply current (one ATD module)
IREF
0.375
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
3. Reduced accuracy see Table A-14 and Table A-15.
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Table A-12 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Rating
Symbol
Min
VRL
VRH
VSSA
VDDA/2
Typ
Max
Unit
VDDA/2
VDDA
V
V
3.6
V
Reference Potential
1
D
Low
High
2
C Differential Reference Voltage
VRH-VRL
3.0
3
D ATD Clock Frequency
fATDCLK
0.5
2.0
MHz
TCONV10
14
7
3.5
28
14
7
Cycles
µs
µs
NCONV8
TCONV8
12
6
26
13
Cycles
µs
3.3
ATD 10-Bit Conversion Period
4
D
Clock Cycles1 NCONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK T
Conv, Time at 4.0MHz2 ATD Clock fATDCLK
CONV10
ATD 8-Bit Conversion Period
Clock Cycles(1)
Conv, Time at 2.0MHz ATD Clock fATDCLK
5
D
6
D Recovery Time (VDDA=3.3 Volts)
tREC
20
µs
7
P
Reference Supply current (two ATD modules)
IREF
0.500
mA
8
P
Reference Supply current (one ATD module)
IREF
0.250
mA
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2. Reduced accuracy see Table A-14 and Table A-15.
A.5.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.5.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
A.5.2.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN).
A.5.2.3 Current injection
There are two cases to consider.
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1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less
than VRL unless the current is higher than specified as disruptive conditions.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-13 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
Rating
Symbol
Min
Typ
Max
Unit
RS
-
-
1
KΩ
10
22
pF
2.5
mA
1
Max input Source Resistance
2
Total Input Capacitance
Non Sampling
Sampling
3
Disruptive Analog Input Current
INA
4
Coupling Ratio positive current injection
Kp
10-4
A/A
5
Coupling Ratio negative current injection
Kn
10-2
A/A
CINN
CINS
-2.5
A.5.3 ATD accuracy
Table A-14 and Table A-15 specify the ATD conversion performance excluding any errors due to
current injection, input capacitance and source resistance.
Table A-14 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num
C
Rating
Symbol
Min
Typ
Max
1
P 10-Bit Resolution
LSB
2
P 10-Bit Differential Nonlinearity
DNL
–1
3
P 10-Bit Integral Nonlinearity
INL
–2.5
4
P 10-Bit Absolute Error1
AE
-3
5
C 10-Bit Absolute Error at fATDCLK= 4MHz
AE
±7.0
Counts
6
P 8-Bit Resolution
LSB
20
mV
7
P 8-Bit Differential Nonlinearity
DNL
–0.5
8
P 8-Bit Integral Nonlinearity
INL
–1.0
9
P 8-Bit Absolute Error(1)
AE
-1.5
Freescale Semiconductor
5
Unit
mV
1
Counts
±1.5
2.5
Counts
±2.0
3
Counts
0.5
Counts
±0.5
1.0
Counts
±1.0
1.5
Counts
99
Device User Guide — 9S12KT256DGV1/D V01.09
NOTES:
1. These values include quantization error which is inherently 1/2 count for any A/D converter.
Table A-15 3.3V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz
Num C
Rating
Symbol
Min
Typ
Max
3.25
Unit
1
P 10-Bit Resolution
LSB
mV
2
P 10-Bit Differential Nonlinearity
DNL
–1.5
3
P 10-Bit Integral Nonlinearity
INL
–3.5
4
P 10-Bit Absolute Error1
AE
-5
5
C 10-Bit Absolute Error at fATDCLK= 4MHz
AE
±7.0
Counts
6
P 8-Bit Resolution
LSB
13
mV
7
P 8-Bit Differential Nonlinearity
DNL
–0.5
8
P 8-Bit Integral Nonlinearity
INL
–1.5
9
P 8-Bit Absolute Error(1)
AE
-2.0
1.5
Counts
±1.5
3.5
Counts
±2.5
5
Counts
0.5
Counts
±0.1
1.5
Counts
±1.5
2.0
Counts
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-2.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
∑
i=1
100
Vn – V0
DNL ( i ) = -------------------- – n
1LSB
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
DNL
10-Bit Absolute Error Boundary
LSB
Vi-1
Vi
$3FF
8-Bit Absolute Error Boundary
$3FE
$3FD
$3FC
$FF
$3FB
$3FA
$3F9
$3F8
$FE
$3F7
$3F6
$3F4
8-Bit Resolution
10-Bit Resolution
$3F5
$FD
$3F3
9
Ideal Transfer Curve
8
2
7
10-Bit Transfer Curve
6
5
4
1
3
8-Bit Transfer Curve
2
1
0
5
10
15
20
25
30
35
40
50
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-2 ATD Accuracy Definitions
NOTE:Figure A-2 shows only definitions, for specification values refer to Table A-14 and Table
A-15 .
Freescale Semiconductor
101
Device User Guide — 9S12KT256DGV1/D V01.09
A.6 NVM, Flash and EEPROM
NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.6.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in Table A-16 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.6.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1
1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP
f bus
A.6.1.2 Row Programming
Flash programming where up to 64 words in a row can be programmed consecutively by keeping the
command pipeline filled. The time to program a consecutive word can be calculated as:
1
1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f NVMOP
f bus
The time to program a whole row is:
t brpgm = t swpgm + 63 ⋅ t bwpgm
Row programming is more than 2 times faster than single word programming.
A.6.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
102
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1
t era ≈ 4000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.6.1.4 Mass Erase
Erasing a NVM block takes:
1
t mass ≈ 20000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.6.1.5 Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t check ≈ location ⋅ t cyc + 10 ⋅ t cyc
Table A-16 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
50 1
MHz
1
D External Oscillator Clock
fNVMOSC
0.5
2
D Bus frequency for Programming or Erase Operations
fNVMBUS
1
3
D Operating Frequency
fNVMOP
150
200
kHz
4
P Single Word Programming Time
tswpgm
46 2
74.5 3
µs
5
D Flash Burst Programming consecutive word 4
tbwpgm
20.4 (2)
31 (3)
µs
6
D Flash Burst Programming Time for 64 Words (4)
tbrpgm
1331.2 (2)
2027.5 (3)
µs
7
P Sector Erase Time
tera
20 5
26.7 (3)
ms
8
P Mass Erase Time
tmass
100 (5)
133 (3)
ms
9
D Blank Check Time Flash per block
tcheck
11 6
65546 7
tcyc
10
D Blank Check Time EEPROM per block
tcheck
11 (6)
2058(7)
tcyc
MHz
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus.
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.
Refer to formula in Sections Section A.6.1.1 Single Word Programming- Section A.6.1.4 Mass Erase for guidance.
4. Burst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
Freescale Semiconductor
103
Device User Guide — 9S12KT256DGV1/D V01.09
A.6.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE:
All values shown in Table A-17 are target values and subject to further extensive
characterization.
Table A-17 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Data Retention at an average junction temperature of
TJavg = 70°C
tNVMRET
15
nFLPE
1000
Typ
Max
Unit
1
C
2
C Flash number of Program/Erase cycles
3
C
EEPROM number of Program/Erase cycles
(–40°C ≤ TJ ≤ 0°C)
nEEPE
10,000
Cycles
4
C
EEPROM number of Program/Erase cycles
(0°C < TJ ≤ 140°C)
nEEPE
100,000
Cycles
104
Years
10,000
Cycles
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
A.7 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.7.1 Startup
Table A-18 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-18 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
2.07
V
1
T POR release level
VPORR
2
T POR assert level
VPORA
0.97
V
3
D Reset input pulse width, minimum input time
PWRSTL
2
tosc
4
D Startup from Reset
nRST
192
5
D Interrupt pulse width, IRQ edge-sensitive mode
PWIRQ
20
6
D Wait recovery startup time
tWRS
196
nosc
ns
14
tcyc
A.7.1.1 POR
The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.
A.7.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.7.1.3 External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.7.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
Freescale Semiconductor
105
Device User Guide — 9S12KT256DGV1/D V01.09
A.7.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.
A.7.2 Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Full swing Pierce
oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is
asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA
Table A-19 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1a
C Crystal oscillator range (loop controlled Pierce)
fOSC
4.0
16
MHz
1b
C Crystal oscillator range (full swing Pierce) 1,2
fOSC
0.5
40
MHz
2
P Startup Current
iOSC
100
3
C Oscillator start-up time (loop controlled Pierce)
tUPOSC
4
D Clock Quality check time-out
tCQOUT
0.45
5
P Clock Monitor Failure Assert Frequency
fCMFA
50
6
P External square wave input frequency 2
fEXT
0.5
7
D External square wave pulse width low
tEXTL
9.5
ns
8
D External square wave pulse width high
tEXTH
9.5
ns
9
D External square wave rise time
tEXTR
1
ns
10
D External square wave fall time
tEXTF
1
ns
11
D Input Capacitance (EXTAL, XTAL pins)
12
P EXTAL Pin Input High Voltage
VIH,EXTAL
T EXTAL Pin Input High Voltage
VIH,EXTAL
VDDPLL + 0.3
V
P EXTAL Pin Input Low Voltage
VIL,EXTAL
0.3*VDDPLL
V
T EXTAL Pin Input Low Voltage
VIL,EXTAL
13
14
C EXTAL Pin Input Hysteresis
µA
33
CIN
100
504
ms
2.5
s
200
KHz
50
MHz
7
pF
0.7*VDDPLL
V
VSSPLL - 0.3
VHYS,EXTAL
V
250
mV
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
106
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
2. Only valid if full swing Pierce oscillator/external clock mode is selected
3. fOSC = 4MHz, C = 22pF.
4. Maximum value is for extreme cases using high Q, low frequency crystals
A.7.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.7.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp
VDDPLL
Cs
fosc
fref
1
refdv+1
R
Phase
∆
fcmp
XFC Pin
VCO
KΦ
KV
fvco
Detector
Loop Divider
1
synr+1
1
2
Figure A-3 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table A-20.
The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used
for fOSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
KV = K1 ⋅ e
( f 1 – f vco )
----------------------K 1 ⋅ 1V
= – 100 ⋅ e
( 60 – 50 )
-----------------------– 100
= -90.48MHz/V
The phase detector relationship is given by:
Freescale Semiconductor
107
Device User Guide — 9S12KT256DGV1/D V01.09
K Φ = – i ch ⋅ K V
= 316.7Hz/Ω
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f ref
f ref
1
f C < ------------------------------------------ ------ → f C < -------------- ;( ζ = 0.9 )
4 ⋅ 10
2 10

π⋅ ζ+ 1+ζ
fC < 25kHz


And finally the frequency relationship is defined as
f VCO
n = ------------- = 2 ⋅ ( synr + 1 )
f ref
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC=10kHz:
2 ⋅ π ⋅ n ⋅ fC
R = ----------------------------- = 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
KΦ
The capacitance Cs can now be calculated as:
2
0.516
2⋅ζ
C s = ---------------------- ≈ --------------- ;( ζ = 0.9 ) = 5.19nF =~ 4.7nF
π ⋅ fC ⋅ R fC ⋅ R
The capacitance Cp should be chosen in the range of:
C s ⁄ 20 ≤ C p ≤ C s ⁄ 10
Cp = 470pF
A.7.3.2 Jitter Information
NOTE:
This section is under construction
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
108
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1
0
2
3
N-1
N
tmin1
tnom
tmax1
tminN
tmaxN
Figure A-4 Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
t max ( N )
t min ( N ) 

J ( N ) = max  1 – --------------------- , 1 – --------------------- 
N ⋅ t nom
N ⋅ t nom 

NOTE:
From the evaluation data a formula for tmax= f(N), resp. tmin = f(N) should be
derived.
Assuming no long term drift of the reference clock, the following will hold
lim J ( N ) = 0
N→∞
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Freescale Semiconductor
109
Device User Guide — 9S12KT256DGV1/D V01.09
Table A-20 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Self Clock Mode frequency
fSCM
1
5.5
MHz
2
D VCO locking range
fVCO
8
50
MHz
3
D
∆trk
3%
4%1
—
4
D Lock Detection
∆Lock
0%
1.5%(1)
—
5
D Un-Lock Detection
∆unl
0.5%
2.5%(1)
—
6
D
∆unt
6%
8%(1)
—
7
C PLLON Total Stabilization delay2
tstab
0.5
ms
8
D PLLON Acquisition mode stabilization delay(2)
tacq
0.3
ms
9
D PLLON Tracking mode stabilization delay(2)
tal
0.2
ms
10
D Fitting parameter VCO loop gain
K1
-100
MHz/V
11
D Fitting parameter VCO loop frequency
f1
60
MHz
12
D Charge pump current acquisition mode
ich
-38.5
µA
13
D Charge pump current tracking mode
ich
-3.5
µA
14
C Jitter fit parameter 1(2)
j1
1.1
%
15
C Jitter fit parameter 2(2)
j2
0.13
%
Lock Detector transition from Acquisition to Tracking
mode
Lock Detector transition from Tracking to Acquisition
mode
NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.
110
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
A.8 MSCAN
Table A-21 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
1
P MSCAN Wake-up dominant pulse filtered
tWUP
2
P MSCAN Wake-up dominant pulse pass
tWUP
Freescale Semiconductor
Min
5
Typ
Max
Unit
2
µs
µs
111
Device User Guide — 9S12KT256DGV1/D V01.09
A.9 SPI
A.9.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-22.
SS1
(OUTPUT)
2
1
SCK
(CPOL = 0)
(OUTPUT)
3
11
4
4
12
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
9
MOSI
(OUTPUT)
BIT 6 . . . 1
LSB IN
9
MSB OUT2
BIT 6 . . . 1
10
LSB OUT
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5 SPI Master Timing (CPHA = 0)
112
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
SS1
(OUTPUT)
1
2
12
11
11
12
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
LSB IN
10
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA =1)
Table A-22 SPI Master Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num
C
1
P
1
Rating
Symbol
Min
Operating Frequency
fop
P
SCK Period
2
D
3
Max
Unit
DC
1/4
fbus
tsck
4
2048
tbus
Enable Lead Time
tlead
1/2
—
tsck
D
Enable Lag Time
tlag
1/2
4
D
Clock (SCK) High or Low Time
twsck
tbus − 30
5
D
Data Setup Time (Inputs)
tsu
25
ns
6
D
Data Hold Time (Inputs)
thi
0
ns
9
D
Data Valid (after SCK Edge)
tv
10
D
Data Hold Time (Outputs)
tho
11
D
Rise Time Inputs and Outputs
tr
25
ns
12
D
Fall Time Inputs and Outputs
tf
25
ns
Freescale Semiconductor
Typ
tsck
1024 tbus
25
0
ns
ns
ns
113
Device User Guide — 9S12KT256DGV1/D V01.09
A.9.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-23.
SS
(INPUT)
1
12
11 3
11
12
SCK
(CPOL = 0)
(INPUT)
4
2
4
SCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
9
SLAVE MSB OUT
5
MOSI
(INPUT)
10
10
BIT 6 . . . 1
SEE
NOTE
SLAVE LSB OUT
6
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined but normally MSB of character just received.
Figure A-7 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
2
12
11
11
12
SCK
(CPOL = 0)
(INPUT)
4
4
SCK
(CPOL = 1)
(INPUT)
SEE
NOTE SLAVE MSB OUT
7
MOSI
(INPUT)
5
8
10
9
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined but normally LSB of character just received.
Figure A-8 SPI Slave Timing (CPHA =1)
114
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Table A-23 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
P Operating Frequency
fop
DC
1/4
fbus
1
P SCK Period
tsck
4
2048
tbus
2
D Enable Lead Time
tlead
1
tcyc
3
D Enable Lag Time
tlag
1
tcyc
4
D Clock (SCK) High or Low Time
twsck
tcyc − 30
ns
5
D Data Setup Time (Inputs)
tsu
25
ns
6
D Data Hold Time (Inputs)
thi
25
ns
7
D Slave Access Time
ta
1
tcyc
8
D Slave MISO Disable Time
tdis
1
tcyc
9
D Data Valid (after SCK Edge)
tv
25
ns
10
D Data Hold Time (Outputs)
tho
11
D Rise Time Inputs and Outputs
tr
25
ns
12
D Fall Time Inputs and Outputs
tf
25
ns
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0
ns
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Device User Guide — 9S12KT256DGV1/D V01.09
A.10 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing
values shown on table Table A-24. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.10.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
116
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1, 2
3
4
ECLK
PE4
5
9
Addr/Data
(read)
PA, PB
6
16
15
7
data
8
14
13
data
addr
17
11
data
addr
data
12
Addr/Data
(write)
PA, PB
10
19
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
23
ECS
PK7
24
25
26
27
28
29
30
31
32
33
34
R/W
PE2
LSTRB
PE3
NOACC
PE7
35
36
PIPO0
PIPO1, PE6,5
Figure A-9 General External Bus Timing
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Table A-24 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num
C
Rating
Symbol
Min
Typ
Max
Unit
fo
0
25.0
1
tcyc
40
2
1
P Frequency of operation (E-clock)
2
P Cycle time
3
D Pulse width, E low
PWEL
17
3
4
D Pulse width, E high1
PWEH
17
4
5
D Address delay time
tAD
6
D Address valid time to E rise (PWEL–tAD)
tAV
11
6
7
D Muxed address hold time
tMAH
2
7
8
D Address hold to data valid
tAHDS
7
8
9
D Data hold to address
tDHA
2
9
10
D Read data setup time
tDSR
13
10
11
D Read data hold time
tDHR
0
11
12
D Write data delay time
tDDW
13
D Write data hold time
tDHW
2
13
14
D Write data setup time(1) (PWEH–tDDW)
tDSW
10
14
15
D Address access time(1) (tcyc–tAD–tDSR)
tACCA
19
15
16
D E high access time(1) (PWEH–tDSR)
tACCE
4
16
17
D Non-multiplexed address delay time
tNAD
18
D Non-muxed address valid to E rise (PWEL–tNAD)
tNAV
10
18
19
D Non-multiplexed address hold time
tNAH
2
19
20
D Chip select delay time
tCSD
21
D Chip select access time(1) (tcyc–tCSD–tDSR)
tACCS
11
21
22
D Chip select hold time
tCSH
2
22
23
D Chip select negated time
tCSN
8
23
24
D Read/write delay time
tRWD
25
D Read/write valid time to E rise (PWEL–tRWD)
tRWV
10
25
26
D Read/write hold time
tRWH
2
26
27
D Low strobe delay time
tLSD
28
D Low strobe valid time to E rise (PWEL–tLSD)
tLSV
10
28
29
D Low strobe hold time
tLSH
2
29
30
D NOACC strobe delay time
tNOD
31
D NOACC valid time to E rise (PWEL–tLSD)
tNOV
118
8
7
7
16
7
7
7
10
5
12
17
20
24
27
30
31
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Table A-24 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
32
D NOACC hold time
tNOH
2
33
D PIPO0 delay time
tP0D
2
34
D PIPO0 valid time to E rise (PWEL–tP0D)
tP0V
10
35
D PIPO1 delay time(1) (PWEH-tP1V)
tP1D
2
36
D PIPO1 valid time to E fall
tP1V
10
32
7
33
34
7
35
36
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
Freescale Semiconductor
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120
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Appendix B Package Information
This section provides the physical dimensions of the MC9S12K-Family packages.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
B.1 80-pin QFP package
L
60
41
61
B
D
D
S
V
B
P
B
0.20 M C A-B
L
0.20 M H A-B
-B-
0.05 D
-A-
S
S
S
40
-A-,-B-,-DDETAIL A
DETAIL A
21
80
1
A
0.20 M H A-B
S
F
20
-DD
S
0.05 A-B
J
S
0.20 M C A-B
S
D
S
D
M
E
DETAIL C
C
-H-
-CSEATING
PLANE
N
0.20 M C A-B
S
D
S
SECTION B-B
DATUM
PLANE
VIEW ROTATED 90 °
0.10
H
M
G
U
T
DATUM -HPLANE
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
13.90 14.10
13.90 14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
--0.25
0.13
0.23
0.65
0.95
12.35 REF
5°
10 °
0.13
0.17
0.325 BSC
0°
7°
0.13
0.30
16.95 17.45
0.13
--0°
--16.95 17.45
0.35
0.45
1.6 REF
Figure B-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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B.2 100-pin LQFP package
0.2 T L–M N
4X
G
0.2 T L–M N
4X 25 TIPS
76
100
CL
1
X
X = L, M OR N
AB
75
AB
L
VIEW Y
M
B V
BASE METAL
ÉÉ
ÇÇÇ
ÉÉ
ÇÇÇ
F
3X
VIEW Y
V1
B1
25
J
PLATING
0.08
26
T L–M N
M
50
N
A1
U
D
51
SECTION AB–AB
ROTATED 90_ CLOCKWISE
S1
A
S
4X
C
q2
0.08 T
SEATING
PLANE
T
4X
q3
VIEW AA
0.05
(W)
q1
R1
2X R
0.25
C2
GAGE PLANE
C1
(Z)
(K)
E q
VIEW AA
100X
NOTES:
1. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PER SIDE. DIMENSIONS A AND B INCLUDE MOLD
MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07.
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
q
q1
q2
q3
MILLIMETERS
MIN
MAX
14.00 BSC
7.00 BSC
14.00 BSC
7.00 BSC
–––
1.70
0.05
0.20
1.30
1.50
0.10
0.30
0.45
0.75
0.15
0.23
0.50 BSC
0.07
0.20
0.50 REF
0.08
0.20
16.00 BSC
8.00 BSC
0.09
0.16
16.00 BSC
8.00 BSC
0.20 REF
1.00 REF
0_
7_
0_
–––
12_ REF
12_ REF
CASE 983–02
ISSUE E
DATE 01/30/96
Figure B-2 100-pin LQFP Mechanical Dimensions (case no. 983)
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Device User Guide — 9S12KT256DGV1/D V01.09
B.3 112-pin LQFP package
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
108X
G
X
X=L, M OR N
VIEW Y
V
B
L
M
B1
28
57
29
F
D
56
0.13
N
S1
A
S
C2
VIEW AB
θ2
0.050
0.10 T
112X
SEATING
PLANE
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
E
(Y)
(Z)
VIEW AB
M
BASE
METAL
T L-M N
SECTION J1-J1
ROTATED 90 ° COUNTERCLOCKWISE
A1
C
AA
J
V1
θ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE
DAMBAR
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--- 1.600
0.050 0.150
1.350 1.450
0.270 0.370
0.450 0.750
0.270 0.330
0.650 BSC
0.090 0.170
0.500 REF
0.325 BSC
0.100 0.200
0.100 0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090 0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure B-3 112-pin LQFP Mechanical Dimensions (case no. 987)
124
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V01.09, 9 SEP 2004