ON NCP81381 Integrated driver and mosfet Datasheet

NCP81381
Integrated Driver
and MOSFET
The NCP81381 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a single package.
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP81381
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
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MARKING
DIAGRAM
Features
Capable of Average Currents up to 25 A
Capable of Switching at Frequencies up to 2 MHz
Capable of Peak Currents up to 60 A
Compatible with 3.3 V or 5 V PWM Input
Responds Properly to 3−level PWM Inputs
Option for Zero Cross Detection with 3−level PWM
ZCD_EN Input for Diode Emulation with 2−level PWM
Internal Bootstrap Diode
Undervoltage Lockout
Supports Intel® Power State 4
Thermal Warning output
Thermal Shutdown
This is a Pb−Free Device
1
36
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
VCC
CGND
PWM
SMOD#
DISB#
THWN
5
4
3
2
1
PINOUT DIAGRAM
VCCD 7
GL 8
Applications
• Desktop & Notebook Microprocessors
GL 9
GL 10
GL 11
VSW 12
VIN
36 ZCD_EN
35 BOOT
34 PHASED
31 PGND
30 VIN
VSW 13
VSW 14
SMOD from controller
SMOD#
CGND
PHASED
PHASEF
VSW
PGND
27 VIN
26 VIN
VSW 17
VSW 18
DISB#
PWM
PGND
25 VIN
VOUT
PGND 24
PWM from controller
ZCD_EN
29 VIN
28 VIN
37
VSW 15
VSW 16
PGND 23
Zero Current
Detect Enable
DRVON from controller
VIN
THWN
BOOT
PGND 19
PGND 20
VCCD VCC
33 GH
32 PHASEF
38
TEST
PGND 21
PGND 22
5V
81381
ALYWG
G
QFN36 6x4
CASE 485DZ
6
•
•
•
•
•
•
•
•
•
•
•
•
•
(Top View)
Figure 1. Application Schematic
ORDERING INFORMATION
Device
Package
Shipping†
NCP81381MNTXG
QFN36
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 1
1
Publication Order Number:
NCP81381/D
NCP81381
VCCD 7
35 BOOT
33 GH
25 − 30 VIN
VCC 6
LEVEL
SHIFT
UVLO
VCC
12 − 18 VSW
32 PHASEF
34 PHASED
SMOD# 3
DEAD
TIME
CONTROL
PWM 4
SHUTDOWN
TEMP
WARNING SENSE
LOGIC
19 PGND
20 PGND
21 PGND
DISB# 2
22 PGND
LEVEL
SHIFT
23 PGND
24 PGND
31 PGND
THWN 1
37 PGND
VCC
11
GL
10 GL
ZCD
CONTROL
ZCD_EN 36
CGND 5
9
GL
8
GL
38 TEST
Figure 2. Block Diagram
PIN LIST AND DESCRIPTIONS
Pin No.
Symbol
1
THWN
Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
reaches TTHWN, this pin is pulled low.
2
DISB#
Output disable pin. When this pin is pulled to a logic high level, the driver is enabled. There is an
internal pull−down resistor on this pin.
3
SMOD#
Skip Mode pin. 3−state input (see Table 1 LOGIC TABLE):
SMOD# = High ³ States of ZCD_EN and PWM determine whether the NCP81381 performs
ZCD or not.
SMOD# = Mid ³ Connects PWM to internal resistor divider placing a bias voltage
on PWM pin. Otherwise, logic is equivalent to SMOD# in the high state.
SMOD# = Low ³ Placing PWM into mid−state pulls GH and GL low without delay.
There is an internal pull−up resistor to VCC on this pin.
Description
4
PWM
PWM Control Input and Zero Current Detection Enable
5
CGND
Signal Ground
6
VCC
7
VCCD
Control Power Supply Input
8
GL
Low Side FET Gate Access
9
GL
Low Side FET Gate Access
10
GL
Low Side FET Gate Access
11
GL
Low Side FET Gate Access
12
VSW
Switch Node Output
13
VSW
Switch Node Output
14
VSW
Switch Node Output
15
VSW
Switch Node Output
16
VSW
Switch Node Output
17
VSW
Switch Node Output
18
VSW
Switch Node Output
Driver Power Supply Input
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2
NCP81381
PIN LIST AND DESCRIPTIONS (continued)
Pin No.
Symbol
19
PGND
Power Ground
20
PGND
Power Ground
21
PGND
Power Ground
22
PGND
Power Ground
23
PGND
Power Ground
24
PGND
Power Ground
25
VIN
Conversion Supply Power Input
26
VIN
Conversion Supply Power Input
27
VIN
Conversion Supply Power Input
28
VIN
Conversion Supply Power Input
29
VIN
Conversion Supply Power Input
30
VIN
Conversion Supply Power Input
31
PGND
32
PHASEF
33
GH
34
PHASED
Description
Power Ground
Bootstrap Capacitor Return (must be connected to PHASED)
High Side FET Gate Access
Driver Phase Connection (must be connected to PHASEF)
35
BOOT
36
ZCD_EN
Bootstrap Voltage
37
PGND
Power Ground
38
TEST
No connection should be made to this pin. No pad is needed on the PCB footprint
PWM drive logic and zero current detection enable. 3−state input:
PWM = High ³ GH is high, GL is low.
PWM = Mid ³ Diode emulation mode.
PWM = Low ³ GH is low. State of GL is dependent on states of SMOD# and ZCD_EN
(see Table 1 LOGIC TABLE).
ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise) (Note 1)
Pin Name
Min
Max
Unit
VCC, VCCD
−0.3
6.5
V
GH to PHASED (DC)
−0.3
VBOOT − VSW + 0.3
V
GH to PHASED (< 50 ns)
−5
7.7
V
VIN
−0.3
30
V
BOOT (DC)
−0.3
35
V
BOOT (< 20 ns)
−0.3
40
V
BOOT to PHASED (DC)
−0.3
6.5
V
VSW, PHASED, PHASEF (DC)
−0.3
30
V
−5
37
V
−0.3
VSW, PHASED, PHASEF (< 5 ns)
All Other Pins
VVCC + 0.3
V
Single−Pulse Drain−to−Source Avalanche Energy, High−Side FET
(TJ = 25°C, VGS = 5 V, L = 0.1 mH, RG = 25 W, IL = 54 APK)
144
mJ
Single−Pulse Drain−to−Source Avalanche Energy, Low−Side FET
(TJ = 25°C, VGS = 5 V, L = 0.3 mH, RG = 25 W, IL = 31.5 APK)
180
mJ
Single−Pulse Drain−to−Source Avalanche Energy, High−Side FET
(TJ = 25°C, L = 0.15 mH, IL = 90 APK, VDS dV/dt= 30 V / 2 ns)
200
mJ
Single−Pulse Drain−to−Source Avalanche Energy, Low−Side FET
(TJ = 25°C, L = 150 nH, IL = 90 APK, VDS dV/dt= 30 V / 4 ns)
200
mJ
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Absolute Maximum Ratings are not tested in production.
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NCP81381
THERMAL INFORMATION
Rating
Thermal Resistance
Operating Junction Temperature Range (Note 2)
Symbol
Value
Unit
qJA
22
_C/W
RYJ−BT
2.0
_C/W
RYJ−CT
4.0
_C/W
TJ
−40 to +150
_C
−10 to +100
_C
−40 to +150
_C
5.0
W
Operating Ambient Temperature Range
Maximum Storage Temperature Range
TSTG
Maximum Power Dissipation
Moisture Sensitivity Level
MSL
3
2. The maximum package power dissipation must be observed.
3. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
4. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage Range
Pin Name
Min
Typ
Max
Unit
VCC, VCCD
4.5
5.0
5.5
V
VIN
4.5
12
20
V
FSW = 1 MHz, VIN = 12 V, VOUT = 1.1 V
20
A
FSW = 500 kHz, VIN = 12 V, VOUT = 1.1 V
25
A
FSW = 500 kHz, VIN = 12 V, VOUT = 1.1 V,
Duration = 10 ms, Period = 1 s
60
A
100
_C
Conversion Voltage
Continuous Output Current
Peak Output Current
Conditions
Operating Temperature
−10
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVCC = VVCCD = 5.0 V, VVIN = 12 V, VDISB# = 2.0 V, CVCCD = CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the
temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VCC SUPPLY CURRENT
Operating
DISB# = 5 V, ZCD_EN = 5 V,
PWM = 400 kHz
−
1
2
mA
No switching, ZCD enabled
DISB# = 5 V, ZCD_EN = 5 V,
PWM = 0 V
−
−
2
mA
No switching, ZCD disabled
DISB# = 5 V, ZCD_EN = 0 V,
PWM = 0 V
−
−
1.8
mA
Disabled
DISB# = 0 V
ZCD_EN = VCC, SMOD# = VCC
−
0.1
1
mA
10
13
mA
−
27
40
mA
2.9
−
3.3
V
150
−
−
mV
DISB# = 0 V
ZCD_EN = VCC, SMOD# = GND
DISB# = 0 V
ZCD_EN = SMOD# = GND
UVLO Start Threshold
VUVLO
VCC rising
UVLO Hysteresis
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCP81381
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = VVCCD = 5.0 V, VVIN = 12 V, VDISB# = 2.0 V, CVCCD = CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the
temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VCCD SUPPLY CURRENT
Operating
DISB# = 5 V, ZCD_EN = 5 V, PWM =
400 kHz
−
−
15
mA
Enabled, No switching
DISB# = 5 V, PWM = 0 V,
VPHASED = 0 V
−
175
300
mA
Disabled
DISB# = 0 V
−
0.1
1
mA
To Ground, @ 25°C
DISB# INPUT
Input Resistance
−
461
−
kW
Upper Threshold
VUPPER
−
−
2.0
V
Lower Threshold
VLOWER
0.8
−
−
V
200
−
−
mV
Hysteresis
VUPPER – VLOWER
Enable Delay Time
tENABLE
Time from DISB# transitioning HI to
when VSW responds to PWM.
−
−
40
ms
Disable Delay Time
tDISABLE
Time from DISB# transitioning LOW to
when both output FETs are off.
−
25
50
ns
VPWM_HI
2.65
−
−
V
Input Mid−state Voltage
VPWM_MID
1.4
−
2.0
V
Input Low Voltage
VPWM_LO
−
−
0.7
V
Input Resistance
RPWM_HIZ
SMOD# = VSMOD#_HI or VSMOD#_LO
10
−
−
MW
Input Resistance
RPWM_BIAS
SMOD# = VSMOD#_MID
−
63
−
kW
PWM Input Bias Voltage
VPWM_BIAS
SMOD# = VSMOD#_MID
−
1.7
−
V
PWM INPUT
Input High Voltage
PWM Propagation Delay, Rising
tpdlGL
PWM = 2.25 V to GL = 90%;
SMOD# = LOW
−
25
35
ns
PWM Propagation Delay, Falling
tpdlGH
PWM = 0.75 V to GH = 90%
−
15
25
ns
Exiting PWM Mid−state Propagation
Delay, Mid−to−Low
TPWM_EXIT_L
PWM = Mid−to−Low to GL = 10%,
ZCD_EN = High
−
13
25
ns
Exiting PWM Mid−state Propagation
Delay, Mid−to−High
TPWM_EXIT_H
PWM = Mid−to−High to GH = 10%
−
13
25
ns
SMOD# INPUT
VSMOD_HI
2.65
−
−
V
VSMOD#_MID
1.4
−
2.0
V
SMOD# Input Voltage Low
VSMOD_LO
−
−
0.7
V
SMOD# Input Resistance
RSMOD#_UP
Pull−up resistance to VCC
−
440
−
kW
SMOD# Input Voltage High
SMOD# Input Voltage Mid−state
SMOD# Propagation Delay, Falling
TSMOD#_PD_F
SMOD# = Low to GL = 90%,
PWM = Low
−
26
30
ns
SMOD# Propagation Delay, Rising
TSMOD#_PD_R
SMOD# = High to GL = 10%,
ZCD_EN = High, PWM = Low
−
15
30
ns
ZCD_EN INPUT
ZCD_EN Input Voltage High
VZCD_EN_HI
2.0
−
−
V
ZCD_EN Input Voltage Low
VZCD_EN_LO
−
−
0.8
V
ZCD_EN Hysteresis
VZCD_EN_HYS
−
250
−
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NCP81381
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = VVCCD = 5.0 V, VVIN = 12 V, VDISB# = 2.0 V, CVCCD = CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the
temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
to VCC
−
270
−
kW
ZCD_EN INPUT
ZCD_EN Input Resistance
RZCD_EN_PU
ZCD_EN Propagation Delay, Rising
TZCD_EN,PD_R
SMOD# = High,
ZCD_EN = High to GL = 10%
−
40
45
ns
ZCD_EN Propagation Delay, Falling
TZCD_EN,PD_F
SMOD# = High,
ZCD_EN = Low to GL = 90%
−
25
40
ns
ZCD FUNCTION
Zero Cross Detect Threshold
VZCD
−
−6.5
−
mV
ZCD Blanking + Debounce Time
tBLNK
−
330
−
ns
NON−OVERLAP DELAYS
Non−overlap Delay, Leading Edge
tpdhGH
GL Falling = 1 V to GH−VSW
Rising = 1 V
−
13
−
ns
Non−overlap Delay, Trailing Edge
tpdhGL
GH−VSW Falling = 1 V to GL
Rising = 1 V
−
12
−
ns
TTHWN
Temperature at Driver Die
−
150
−
°C
−
15
−
°C
−
180
−
°C
TTHDN_HYS
−
25
−
°C
ITHWN
−
−
5
mA
−
300
−
mV
THERMAL WARNING & SHUTDOWN
Thermal Warning Temperature
Thermal Warning Hysteresis
TTHWN_HYS
Thermal Shutdown Temperature
TTHDN
Thermal Shutdown Hysteresis
THWN Open Drain Current
Temperature at Driver Die
BOOSTSTRAP DIODE
Forward Bias Current = 2.0 mA
Forward Voltage
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
DISB#
t ENABLE
t DISABLE
PWM
tpdl GH
tpdl GL
90%
GH−VSW
1V
1V
tpdh GH
tpdh GL
90%
GL
10%
1V
1V
VSW
Figure 3. Timing Diagram
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NCP81381
Table 1. LOGIC TABLE
INPUT TRUTH TABLE
DISB#
PWM
SMOD# (Note 5)
ZCD_EN
GH
GL
L
X
X
X
L
L
H
H
X
X
H
L
H
L
X
L
L
L
H
L
X
H
L
H
H
MID
H or MID
H
L
ZCD (Note 6)
H
MID
X
L
L
L (Note 7)
H
MID
L
X
L
L (Note 7)
5. PWM input is driven to mid−state with internal divider resistors when SMOD# is driven to mid−state and PWM input is undriven externally.
6. GL goes low following 80 ns de−bounce time, 250 ns blanking time and then SW exceeding ZCD threshold.
7. There is no delay before GL goes low.
Figure 4. Efficiency − 12 V Input, 1.2 V Output,
500 kHz
Figure 5. Efficiency − 19 V Input, 1.2 V Output,
500 kHz
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NCP81381
APPLICATIONS INFORMATION
Theory of Operation
Safety Timer and Overlap Protection Circuit
The NCP81381 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. The NCP81381 supports numerous application
control definitions including ZCD (Zero Current Detect)
with Pin enable and alternately PWM Tristate control.
A PWM input signal is required to control the drive signals
to the high−side and low−side integrated MOSFETs.
It is important to avoid cross−conduction of the two
MOSFETS which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP81381 prevents cross conduction by monitoring
the status of the MOSFET gates and applying the appropriate
amount of non−overlap time (the time between the turn−off
of one MOSFET and the turn−on of the other MOSFET).
When the PWM input pin is driven high, the low−side
MOSFET gate (GL) starts to go low after a propagation
delay (tpdlGL). The time it takes for the low−side MOSFET
to turn off is dependent on the low−side MOSFET gate
charge. The high−side MOSFET gate begins to rise a fixed
time (tpdhGH) after the GL voltage falls below the low−side
MOSFET gate threshold.
When the PWM input pin is driven low, the high−side
MOSFET gate (GH) starts to go low after a propagation
delay (tpdlGH). The time it takes for the high−side MOSFET
to turn off is dependent on the high−side MOSFET gate
charge. The low−side MOSFET gate begins to rise a fixed
time (tpdhGH) after the GH voltage falls below the high−side
MOSFET gate threshold.
Low−Side Driver
The
low−side
driver
drives
an
internal,
ground−referenced low−RDS(on) N−Channel MOSFET.
The voltage supply for the low−side driver is internally
connected to the VCCD and PGND pins.
High−Side Driver
The high−side driver drives an internal, floating
low−RDS(on) N−channel MOSFET. The gate voltage for the
high side driver is developed by a bootstrap circuit
referenced to Switch Node (VSW, PHASEF and PHASED)
pins.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor and resistor. When the
NCP81381 is starting up, the VSW pin is at ground, allowing
the bootstrap capacitor to charge up to VCCD through the
bootstrap diode (See Figure 1). When the PWM input is
driven high, the high−side driver will turn on the high−side
MOSFET using the stored charge of the bootstrap capacitor.
As the high−side MOSFET turns on, the voltage at the VSW,
PHASEF and PHASED pins rise. When the high−side
MOSFET is turned fully on, the switch node will settle to
VIN and the BST pin will settle to VIN + VCCD (excluding
parasitic ringing).
Zero Current Detect Enable Input (ZCD_EN)
The ZCD_EN pin is a logic input pin with an internal
pull−up resistance to VCC.
When ZCD_EN is set low, the NCP81381 will operate in
synchronous rectifier (PWM) mode. This means that
negative current can flow in the LS MOSFET if the load
current is less than ½ delta current in the inductor. When
ZCD_EN is set high, Zero Current Detect PWM
(ZCD_PWM) mode will be enabled
With ZCD_EN set high, when PWM rises above
VPWM_HI, GL will go low and GH will go high after the
non−overlap delay. Subsequently, if PWM falls to less than
VPWM_HI, but stays above VPWM_LO, GL will go high after
the non−overlap delay, and stay high for the duration of the
ZCD Blanking + Debounce time (TBLNK). Once this timer
has elapsed, VSW will be monitored for zero current, and
GL will be pulled low when zero current is detected. The
VSW zero current threshold undergoes an auto−calibration
cycle every time DISB# is brought from low to high.
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (CBST) and an integrated diode to provide current
to the HS Driver. A multi−layer ceramic capacitor (MLCC)
with a value greater than 100 nF should be used as the
bootstrap capacitor. An 4 W resistor in series with CBST is
recommended to decrease VSW overshoot.
Power Supply Decoupling
The NCP81381 will source relatively large currents into
the MOSFET gates. In order to maintain a constant and
stable supply voltage (VCCD) a low−ESR capacitor should
be placed near the power and ground pins. A multi layer
ceramic capacitor (MLCC) between 1 mF and 4.7 mF is
typically used.
A separate supply pin (VCC) is used to power the analog
and digital circuits within the driver. A 1 mF ceramic
capacitor should be placed on this pin in close proximity to
the NCP81381. It is good practice to separate the VCC and
VCCD decoupling capacitors with a resistor (10 W typical)
to avoid coupling driver noise to the analog and digital
circuits that control driver function (See Figure 1).
PWM Input
The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. In conjunction with ZCD_EN
it also determines the state of the LS MOSFET. See Table1
for logic operation. The PWM in some cases must operate
with frequency programming resistances to ground. These
resistances can range from 10 kW to 300 kW depending on
the application. When SMOD# is set to > VSMOD#_HI or
to < VSMOD#_LO, the input impedance to the PWM input
is very high in order to avoid interferences with controllers
that must use programming resistances on the PWM pin.
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NCP81381
Thermal Warning/Thermal Shutdown Output
If VSMOD#_LO < SMOD# < VSMOD#_HI (Mid−State),
internal resistances will set undriven PWM pin voltage to
Mid−State.
The DISB# pin is used to disable the GH to the High−Side
FET to prevent power transfer. The pin has a pull−down
resistance to force a disabled state when it is left
unconnected. DISB# can be driven from the output of a logic
device or set high with a pull−up resistance to VCC.
The THWN pin is an open drain output. When the
temperature of the driver exceeds TTHWN, the THWN pin
will be pulled low indicating a thermal warning. At this
point, the part continues to function normally. When the
temperature drops TTHWN_HYS below TTHWN, the THWN
pin will go high. If the driver temperature exceeds TTHDN,
the part will enter thermal shutdown and turn off both
MOSFETs. Once the temperature falls TTHDN_HYS below
TTHDN, the part will resume normal operation.
VCC Undervoltage Lockout
Skip Mode Input (SMOD#)
The VCC pin is monitored by an Undervoltage Lockout
Circuit (UVLO). VCC voltage above the rising threshold
enables the NCP81381.
The SMOD# tri−state input pin has an internal pull−up
resistance to VCC. When driven high, the SMOD# pin
enables the low side synchronous MOSFET to operate
independently of the internal ZCD function. When the
SMOD# pin is set low during the PWM cycle it disables the
low side MOSFET to allow discontinuous mode operation.
The NCP81381 has the capability of internally connecting
a resistor divider to the PWM pin. To engage this mode,
SMOD# needs to be placed into mid−state. While in
SMOD# mid−state, the IC logic is equivalent to SMOD#
being in the high state.
Disable Input (DISB#)
Table 2. UVLO/DISB# LOGIC TABLE
UVLO
DISB#
Driver State
L
X
Disabled (GH = GL = 0)
H
L
Disabled (GH = GL = 0)
H
H
Enabled (See Table x)
H
Open
Disabled (GH = GL = 0)
Inductor
Current
Inductor
Current
ZCD_EN
PWM
PWM
GH
GH
GL
GL
80 ns
De-bounce
timer
ZCD waits
until timers
expire
ZCD_EN
ZCD
detected
80 ns
250 ns
ZCD
blanking
timer
De-bounce
timer
250 ns
ZCD
blanking
timer
Figure 6. PWM Timing Diagram
NOTES: If the Zero Current Detect circuit detects zero current after the ZCD Wait timer period, the GL is driven low by the
Zero Current Detect signal.
If the Zero Current Detect circuit detects zero current before the ZCD Wait timer period has expired, the Zero Current
detect signal is ignored and the GL is driven low at the end of the ZCD Wait timer period.
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9
NCP81381
Inductor
Current
PWM
GH
SMOD#
triggered
GL
SMOD#
Figure 7. SMOD# Timing Diagram
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge will
trigger the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
Inductor Current 0 A
ZCD
triggered
SMOD# = High
SMOD#
ZCD_EN
PWM
GH
GL
LS FET
is off
LS FET
on until ZCD
TZCD_BLANK +
TDEBOUNCE
Figure 8. ZCD_EN Timing Diagram
NOTE: When ZCD is enabled by pulling ZCD_EN# high, the NCP81381 keeps the LS FET on until it detects zero
current, reducing power loss.
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10
NCP81381
For Use with Controllers with 3−State PWM and No Zero Current Detection Capability:
Table 3. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH NO ZCD
PWM
SMOD#
ZCD_EN
GH
GL
H
H
H
ON
OFF
M
H
H
OFF
ZCD
L
H
H
OFF
ON
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
and low states. To enter into DCM, PWM needs to be
switched to the mid−state.
Whenever PWM transitions to mid−state, GH turns off
and GL turns on. GL stays on for the duration of the
de−bounce timer and ZCD blanking timers. Once these
timers expire, the NCP81381 monitors the SW voltage and
turns GL off when SW exceeds the ZCD threshold voltage.
By turning off the LS FET, the body diode of the LS FET
allows any positive current to go to zero but prevents
negative current from conducting.
This section describes operation with controllers that are
capable of 3 states in their PWM output and relies on the
NCP81381 to conduct zero current detection during
discontinuous conduction mode (DCM).
The SMOD# pin needs to either be set to 5 V or left
disconnected. The NCP81381 has an internal pull−up
resistor that connects to VCC that sets SMOD# to the logic
high state if this pin is disconnected.
The ZCD_EN pin needs to either be set to 5 V or left
disconnected. The NCP81381 has an internal pull−up
resistor connected to VCC that will set ZCD_EN to the logic
high state if this pin is left disconnected.
Figure 9. Timing Diagram − 3−state PWM Controller, No ZCD
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11
NCP81381
For Use with Controllers with 3−state PWM and Zero Current Detection Capability:
Table 4. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH ZCD
PWM
SMOD#
ZCD_EN
GH
GL
H
L
H
ON
OFF
M
L
H
OFF
OFF
L
L
H
OFF
ON
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
and low states. During DCM, the controller is responsible
for detecting when zero current has occurred, and then
notifying the NCP81381 to turn off the LS FET. When the
controller detects zero current, it needs to set PWM to
mid−state, which causes the NCP81381 to pull both GH and
GL to their off states without delay.
This section describes operation with controllers that are
capable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
The SMOD# pin needs to be pulled low (below
VSMOD#_LO).
The ZCD_EN pin needs to either be set to 5 V or left
disconnected. There is an internal pull−up resistor that
connects to VCC and sets ZCD_EN to the logic high state if
this pin is left disconnected.
SMOD# 0 V
ZCD_EN 5 V
IL 0 A
SMOD# = Low
ZCD_EN = High
Controller detects zero current → Sets
PWM to mid−state.
PWM
PWM in mid−state pulls GL low.
GH
GL
Figure 10. Timing Diagram − 3−state PWM Controller, with ZCD
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12
NCP81381
For Use with Controllers with 2−Level PWM and Zero Current Detection Capability:
Table 5. LOGIC TABLE − 2−STATE PWM CONTROLLERS WITH ZCD
PWM
SMOD#
ZCD_EN
GH
GL
H
L
X
ON
OFF
L
L
H
OFF
ON
L
L
L
OFF
OFF
When PWM is in the low state, the state of ZCD_EN
determines whether the converter is placed into diode
emulation mode. When the controller detects positive
inductor current, ZCD_EN should be in the high state,
allowing the LS FET to be on and conducting. Once the
controller detects zero or negative current, ZCD_EN should
be placed into the low state, turning off the LS FET. With the
LS FET turned off, the body diode of the LS FET allows any
positive current that may still be flowing to reach zero, but
prevents the current from flowing in the negative direction.
This section describes operation with controllers that do
not have 3−level PWM output capability but are capable of
zero current detection during discontinuous conduction
mode (DCM).
The SMOD# pin needs to be pulled low (below
VSMOD#_LO).
When PWM is high, GH will always be in the high state
and GL will always be in the low state, regardless of the state
ZCD_EN is in.
SMOD# 0 V
SMOD# = Low
IL 0 A
Controller detects zero
current → Sets ZCD_EN low.
ZCD_EN
Low ZCD_EN
pulls GL low.
PWM
GH
GL
Figure 11. Timing Diagram − 2−state PWM Controller, with ZCD
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13
NCP81381
Recommended PCB Layout
(viewed from top)
INPUT
BYPASS CAPS
VIN
VIN
BOOTSTRAP RC
INPUT BYPASS CAPS
NCP81381
VCC
BYPASS CAP
GND
INPUT
BYPASS CAPS
SNUBBER
VCCD
BYPASS CAP
TESTPOINT
VSW
GND
GND
INDUCTOR
VOUT
OUTPUT BYPASS CAP
OUTPUT BYPASS CAP
VOUT
OUTPUT BYPASS CAPS
Figure 12. Top Copper Layer
OUTPUT BYPASS CAPS
Figure 13. Bottom Copper Layer
Figure 14. Layer 2 Copper Layer (Ground Plane)
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14
NCP81381
PACKAGE DIMENSIONS
QFN36 6x4, 0.4P
CASE 485DZ
ISSUE A
ÉÉ
ÉÉ
PIN ONE
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
D
E
0.15 C
2X
0.15 C
2X
DIM
A
A1
A3
b
D
D2
D3
D4
D5
E
E2
E3
E4
e
G
G1
H
H1
H2
L
L2
TOP VIEW
(A3)
A
0.10 C
0.08 C
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
D2
D4
D5
D3
7
G
G1
18
H
E2
E4
E3
H2
24
1
36
H1
36X
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
30X
6X
e
e/2
SUPPLEMENTAL
BOTTOM VIEW
L
NOTE 3
MILLIMETERS
MIN
MAX
0.90
1.20
0.00
0.05
0.20 REF
0.15
0.25
6.00 BSC
4.95
5.05
0.91
1.01
3.04
3.14
2.70
2.80
4.00 BSC
2.44
2.54
1.14
1.24
2.29
2.39
0.40 BSC
0.52
0.62
0.43
0.53
1.35
1.45
0.60
0.70
0.57
0.68
0.30
0.50
0.15
0.35
L2
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
2.37
2.85
0.78
36X
0.25
2X
1.29
30X
1
0.60
R0.15
1.37
4.30
1.25
1.45
0.78
1.23
DETAIL A
0.63
DETAIL A
1.13
3.26
0.40
PITCH
ALL SIDES
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
15
NO EXPOSED
METAL ALLOWED
0.66
NCP81381
PACKAGE DIMENSIONS
QFN36 6x4, 0.4P
CASE 485DZ
RECOMMENDED SOLDER STENCIL
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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NCP81381/D