AD AD9446BSVZ-1001 16-bit, 80/100 msps adc Datasheet

16-Bit, 80/100 MSPS ADC
AD9446
FEATURES
APPLICATIONS
MRI receivers
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9446 is a 16-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
product operates up to a 100 MSPS, providing superior SNR for
instrumentation, medical imaging, and radar receivers
employing baseband (<100 MHz) IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2
DRGND DRVDD
DFS
AD9446
DCS MODE
BUFFER
VIN+
VIN–
CLK+
CLK–
PIPELINE
ADC
T/H
OUTPUT MODE
16
CMOS
OR
LVDS
OUTPUT
STAGING
2
OR
32
D15 TO D0
2
CLOCK
AND TIMING
MANAGEMENT
DCO
REF
VREF SENSE REFT REFB
05490-001
100 MSPS guaranteed sampling rate (AD9446-100)
83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS)
82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS)
89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS)
95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±3.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
3.3 V and 5 V supply operation
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9446 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
True 16-bit linearity.
2.
High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
3.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
4.
Packaged in a Pb-free, 100-lead TQFP/EP package.
5.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6.
OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9446
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .......................................................................................9
Applications....................................................................................... 1
Pin Configurations and Function Descriptions ......................... 10
General Description ......................................................................... 1
Equivalent Circuits......................................................................... 15
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ........................................... 16
Product Highlights ........................................................................... 1
Theory of Operation ...................................................................... 24
Revision History ............................................................................... 2
Analog Input and Reference Overview ................................... 24
Specifications..................................................................................... 3
Clock Input Considerations...................................................... 26
DC Specifications ......................................................................... 3
Power Considerations................................................................ 27
AC Specifications.......................................................................... 4
Digital Outputs ........................................................................... 27
Digital Specifications ................................................................... 6
Timing ......................................................................................... 27
Switching Specifications .............................................................. 6
Operational Mode Selection ..................................................... 28
Timing Diagrams.......................................................................... 7
Evaluation Board ............................................................................ 29
Absolute Maximum Ratings............................................................ 8
Outline Dimensions ....................................................................... 36
Thermal Resistance ...................................................................... 8
Ordering Guide .......................................................................... 36
ESD Caution.................................................................................. 8
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD9446
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
VOLTAGE REFERENCE
Output Voltage1
VREF = 1.6 V (3.2 V p-p Analog Input Range)
Load Regulation @ 1.0 mA
Reference Input Current (External 1.6 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
VREF = 1.6 V
VREF = 1.0 V (External)
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance 2
Input Capacitance2
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
IAVDD1
IAVDD21
IDRVDD1—LVDS Outputs
IDRVDD1—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
LVDS Outputs
CMOS Outputs (DC Input)
1
2
Temp
Full
AD9446BSVZ-80
Min
Typ
Max
16
Full
Full
Full
25°C
Full
25°C
−5
−3
−2
−0.75
−5
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Guaranteed
±0.1
+5
±0.6
+3
±0.3
+2
±0.4
+0.75
±3.0
+5
AD9446BSVZ-100
Min
Typ
Max
16
−5
−3
−2
−0.85
−6
1.6
±2
1.6
±2
1.5
1.9
3.2
2.0
3.5
3.2
2.0
3.5
3.2
3.8
3.2
1
6
3.14
4.75
3.0
3.0
Guaranteed
±0.1
+5
±0.5
+3
±0.3
+2
±0.4
+0.85
±3.0
+6
3.46
5.25
3.6
3.6
Full
Full
Full
Full
335
204
68
14
365
234
75
Full
Full
1
0.2
Full
Full
2.4
2.2
3.14
4.75
3.0
3.0
3.8
V p-p
V p-p
V
V
kΩ
pF
3.3
5.0
3.3
3.3
3.46
5.25
3.6
3.6
V
V
V
V
368
223
69
14
401
255
75
mA
mA
mA
mA
1
0.2
2.6
mV
% FSR
% FSR
LSB
LSB
V
mV
μA
LSB rms
1
6
3.3
5.0
3.3
3.3
Unit
Bits
2.6
2.3
mV/V
%/V
2.8
W
W
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
Rev. 0 | Page 3 of 36
AD9446
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), AIN = −1 dBFS, DCS on, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 92 MHz
fIN = 125 MHz
fIN = 170 MHz
fIN = 10 MHz (2 V p-p Input)
fIN = 30 MHz (2 V p-p Input)
fIN = 70 MHz (2 V p-p Input)
fIN = 92 MHz (2 V p-p Input)
fIN = 125 MHz (2 V p-p Input)
fIN = 170 MHz (2 V p-p Input)
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 92 MHz
fIN = 125 MHz
fIN = 170 MHz
fIN = 10 MHz (2 V p-p Input)
fIN = 30 MHz (2 V p-p Input)
fIN = 70 MHz (2 V p-p Input)
fIN = 92 MHz (2 V p-p Input)
fIN = 125 MHz (2 V p-p Input)
fIN = 170 MHz (2 V p-p Input)
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 92 MHz
fIN = 125 MHz
fIN = 170 MHz
Temp
Min
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
79.6
80.5
79.2
79.0
78.2
AD9446BSVZ-80
Typ
Max
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
77.1
75.9
74.9
75.5
74.4
81.8
81.6
AD9446BSVZ-100
Min
Typ
Max
80.1
78.8
77.1
78.9
78.2
77.0
dB
dB
dB
dB
dB
dB
dB
dB
78.3
78.3
77.6
77.5
76.7
75.5
76.6
76.6
76.2
76
75.6
75.1
dB
dB
dB
dB
dB
dB
78.9
78.6
80.6
79.0
79.2
74.9
66.0
77.1
76.9
70.5
25°C
25°C
25°C
25°C
25°C
25°C
77.9
77.8
77.1
77.1
75.7
72.5
76.2
76.1
75.9
75.7
75.3
73.6
dB
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
25°C
13.2
13.2
12.9
13.0
12.3
10.8
13.0
12.9
12.8
12.7
12.6
11.6
Bits
Bits
Bits
Bits
Bits
Bits
78.6
76.9
75.5
71.7
73.8
69.1
79.7
79.5
dB
dB
dB
dB
dB
dB
dB
dB
Rev. 0 | Page 4 of 36
80.5
80.4
78.4
78.3
77.9
77.7
77.6
Unit
77.7
AD9446
Parameter
SPURIOUS-FREE DYNAMIC RANGE
(SFDR, Second or Third Harmonic)
fIN = 10 MHz
fIN = 30 MHz
Temp
Min
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
82
82
80
80
79
AD9446BSVZ-80
Typ
Max
84
80
66
84
83
74
25°C
25°C
25°C
25°C
25°C
25°C
92
93
92
90
85
77
94
92
92
89
87
82
dBc
dBc
dBc
dBc
dBc
dBc
−98
−97
fIN = 92 MHz
fIN = 125 MHz
fIN = 170 MHz
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
−98
−96
−95
−95
−96
−92
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 10 MHz (2 V p-p Input)
fIN = 30 MHz (2 V p-p Input)
fIN = 70 MHz (2 V p-p Input)
fIN = 92 MHz (2 V p-p Input)
fIN = 125 MHz (2 V p-p Input)
fIN = 170 MHz (2 V p-p Input)
25°C
25°C
25°C
25°C
25°C
25°C
−97
−97
−94
−97
−97
−93
−93
−96
−94
−99
−95
−95
dBc
dBc
dBc
dBc
dBc
dBc
25°C
96
95
dBFS
25°C
92
92
dBFS
Full
325
540
MHz
fIN = 92 MHz
fIN = 125 MHz
fIN = 170 MHz
fIN = 10 MHz (2 V p-p Input)
fIN = 30 MHz (2 V p-p Input)
fIN = 70 MHz (2 V p-p Input)
fIN = 92 MHz (2 V p-p Input)
fIN = 125 MHz (2 V p-p Input)
fIN = 170 MHz (2 V p-p Input)
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS
fIN = 10 MHz
fIN = 30 MHz
fIN = 70 MHz
TWO-TONE SFDR
fIN = 10.8 MHz @ −7 dBFS,
9.8 MHz @ −7 dBFS
fIN = 70.3 MHz @ −7 dBFS,
69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
Rev. 0 | Page 5 of 36
82
82
79
81
77
87
−98
−89
−89
−89
−90
−89
92
89
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 70 MHz
90
89
AD9446BSVZ-100
Min
Typ
Max
89
−96
−97
−96
−91
−89
−87
−90
−88
AD9446
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR) 1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage 2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Input Resistance
Input Capacitance
1
2
Temp
Full
Full
Full
Full
Full
AD9446BSVZ-80
Min
Typ
Max
AD9446BSVZ-100
Min
Typ
Max
2.0
2.0
0.8
200
+10
−10
−10
2
Full
Full
3.25
Full
Full
247
1.125
Full
Full
Full
Full
0.2
1.3
1.1
0.8
200
+10
2
3.25
0.2
1.5
1.4
2
545
1.375
247
1.125
1.6
1.7
0.2
1.3
1.1
1.5
1.4
2
Unit
V
V
μA
μA
pF
0.2
V
V
545
1.375
mV
V
1.6
1.7
V
V
kΩ
pF
Output voltage levels measured with 5 pF load on each output.
LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High 1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD) 2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD) 3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
1
2
3
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9446BSVZ-80
Min
Typ
Max
AD9446BSVZ-100
Min
Typ
Max
80
100
1
12.5
5.0
5.0
2.1
10
4.0
4.0
3.35
3.6
13
4.8
60
With duty cycle stabilizer (DCS) enabled.
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
Rev. 0 | Page 6 of 36
1
2.3
3.35
3.6
13
60
4.8
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
fsec
rms
AD9446
TIMING DIAGRAMS
N–1
N
N+1
AIN
tCLKL
tCLKH
1/fS
CLK+
CLK–
tPD
N
N – 12
N – 13
DATA OUT
N+1
13 CLOCK CYCLES
05490-002
DCO+
DCO–
tCPD
Figure 2. LVDS Mode Timing Diagram
N–1
N
N+1
VIN
N+2
tCLKL
tCLKH
CLK–
CLK+
tPD
DX
13 CLOCK CYCLES
N – 13
N – 12
N–1
N
05490-003
DCO+
DCO–
Figure 3. CMOS Timing Diagram
Rev. 0 | Page 7 of 36
AD9446
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD1
AVDD2
DRVDD
AGND
AVDD1
AVDD2
AVDD2
D0± to D15±
CLK+/CLK−
OUTPUT MODE,
DCS MODE, DFS
VIN+, VIN−
VREF
SENSE
REFT, REFB
ENVIRONMENTAL
Storage Temperature
Range
Operating Temperature
Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
With
Respect
to
Rating
AGND
AGND
DGND
DGND
DRVDD
DRVDD
AVDD1
DGND
AGND
AGND
−0.3 V to +4 V
−0.3 V to +6 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−4 V to +4 V
−4 V to +6 V
−4 V to +6 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
AGND
AGND
AGND
AGND
–0.3 V to AVDD2 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The heat sink of the AD9446 package must be soldered to
ground.
Table 6.
Package Type
100-lead TQFP/EP
θJA
19.8
θJB
8.3
θJC
2
Unit
°C/W
Typical θJA = 19.8°C/W (heat sink soldered) for multilayer
board in still air.
Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board
in still air.
–65°C to +125°C
–40°C to +85°C
300°C
150°C
Typical θJC = 2°C/W (junction to exposed heat sink) represents
the thermal resistance through heat sink path.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θJA. It is required that the exposed heat sink be soldered to
the ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 36
AD9446
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Offset Error
The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 16-bit resolution indicates that all 65,536
codes must be present over all operating ranges.
(SINAD − 1.76 )
6.02
Gain Error
The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
ENOB =
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Signal-to-Noise Ratio (SNR)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may be a harmonic. SFDR can be reported in dBc (that is, degrades
as signal level is lowered) or dBFS (always related back to converter
full scale).
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Rev. 0 | Page 9 of 36
AD9446
DRVDD
D11–
D11+
D12–
D12+
D13–
D13+
D14–
D14+
D15–
D15+ (MSB)
DRGND
DRVDD
OR–
OR+
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE 1
75
DRGND
74
D10+
3
73
D10–
DFS
4
72
D9+
LVDS_BIAS
5
71
D9–
AVDD1
6
70
D8+
SENSE
7
69
D8–
VREF
8
68
DCO+
AGND
9
67
DCO–
66
D7+
65
D7–
AVDD2 12
64
DRVDD
AVDD2 13
63
DRGND
AVDD2 14
62
D6+
AVDD2 15
61
D6–
AVDD2 16
60
D5+
AVDD2 17
59
D5–
AVDD1 18
58
D4+
AVDD1 19
57
D4–
AVDD1 20
56
D3+
AGND 21
55
D3–
VIN+ 22
54
D2+
VIN– 23
53
D2–
AGND 24
52
D1+
AVDD2 25
51
D1–
DNC
2
OUTPUT MODE
PIN 1
AD9446
LVDS MODE
REFT 10
TOP VIEW
(Not to Scale)
REFB 11
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. 0 | Page 10 of 36
05490-004
D0+
D0– (LSB)
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
CLK–
CLK+
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
AD9446
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
1
Mnemonic
DCS MODE
2
3
DNC
OUTPUT
MODE
DFS
4
5
6, 18 to 20, 32 to 34, 36, 38,
43 to 45, 92 to 97
7
LVDS_BIAS
AVDD1
8
VREF
9, 21, 24, 39, 42, 46, 91, 98,
99, 100, Exposed Heat Sink
10
AGND
11
REFB
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87,
48, 64, 76, 88
49
50
51
52
53
54
55
56
57
58
59
60
61
62
65
66
67
68
69
70
71
72
73
74
77
78
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
D0− (LSB)
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
D7−
D7+
DCO−
DCO+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
SENSE
REFT
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable
DCS (recommended); DCS = high (AVDD1) to disable DCS.
Do Not Connect. These pins should float.
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS =
high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1.6 V reference (3.2 V p-p analog
input range); connect to AVDD1 for external reference.
1.6 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin 11)
with 0.1 μF and 10 μF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 10) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
D0 Complement Output Bit (LVDS Levels).
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
Rev. 0 | Page 11 of 36
AD9446
Pin No.
79
80
81
82
83
84
85
86
89
90
Mnemonic
D12−
D12+
D13−
D13+
D14−
D14+
D15−
D15+ (MSB)
OR−
OR+
Description
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output Bit
D13 True Output Bit.
D14 Complement Output Bit
D14 True Output Bit.
D15 Complement Output Bit.
D15 True Output Bit.
Out-of-Range Complement Output Bit.
Out-of-Range True Output Bit.
Rev. 0 | Page 12 of 36
DRVDD
D5+
D6+
D7+
D8+
D9+
D10+
D11+
D12+
D13+
D14+
DRGND
DRVDD
D15+ (MSB)
OR+
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
AD9446
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE 1
75
DRGND
74
D4+
3
73
D3+
DFS
4
72
D2+
LVDS_BIAS
5
71
D1+
AVDD1
6
70
D0+ (LSB)
SENSE
7
69
DNC
VREF
8
68
DCO+
AGND
9
67
DCO–
66
DNC
65
DNC
AVDD2 12
64
DRVDD
AVDD2 13
63
DRGND
AVDD2 14
62
DNC
AVDD2 15
61
DNC
AVDD2 16
60
DNC
AVDD2 17
59
DNC
AVDD1 18
58
DNC
AVDD1 19
57
DNC
AVDD1 20
56
DNC
AGND 21
55
DNC
VIN+ 22
54
DNC
VIN– 23
53
DNC
AGND 24
52
DNC
AVDD2 25
51
DNC
DNC
2
OUTPUT MODE
PIN 1
AD9446
CMOS MODE
REFT 10
TOP VIEW
(Not to Scale)
REFB 11
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. 0 | Page 13 of 36
05490-005
DNC
DNC
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
CLK–
CLK+
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
AD9446
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
1
Mnemonic
DCS MODE
2, 49 to 62, 65 to 66, 69,
3
DNC
OUTPUT MODE
4
DFS
5
6, 18 to 20, 32 to 34, 36,
38, 43 to 45, 92 to 97
7
LVDS_BIAS
AVDD1
8
VREF
9, 21, 24, 39, 42, 46, 91, 98,
99, 100, Exposed Heat
Sink
10
AGND
11
REFB
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87,
48, 64, 76, 88
67
68
70
71
72
73
74
77
78
79
80
81
82
83
84
85
86
89
90
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
DCO−
DCO+
D0+ (LSB)
D1+
D2+
D3+
D4+
D5+
D6+
D7+
D8+
D9+
D10+
D11+
D12+
D13+
D14+
D15+ (MSB)
OR+
SENSE
REFT
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to
enable DCS (recommended); DCS = high (AVDD1) to disable DCS.
Do Not Connect. These pins should float.
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1
for external reference.
1.6 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin 11)
with 0.1 μF and 10 μF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin 10)
with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Data Clock Output—Complement.
Data Clock Output—True.
D0 True Output Bit (CMOS levels).
D1 True Output Bit.
D2 True Output Bit.
D3 True Output Bit.
D4 True Output Bit.
D5 True Output Bit.
D6 True Output Bit.
D7 True Output Bit.
D8 True Output Bit.
D9 True Output Bit.
D10 True Output Bit.
D11 True Output Bit.
D12 True Output Bit.
D13 True Output Bit.
D14 True Output Bit.
D15 True Output Bit.
Out-of-Range True Output Bit.
Rev. 0 | Page 14 of 36
AD9446
EQUIVALENT CIRCUITS
AVDD2
VIN+
1kΩ
6pF
DRVDD
T/H
X1
3.5V
AVDD2
1kΩ
DX
6pF
05490-009
05490-006
VIN–
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent CMOS Digital Output Circuit
VDD
DRVDD
DRVDD
DCS MODE,
OUTPUT MODE,
DFS
K
1.2V
ILVDSOUT
05490-007
3.74kΩ
05490-010
30kΩ
LVDSBIAS
Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE
Figure 7. Equivalent LVDS_BIAS Circuit
AVDD2
DRVDD
3kΩ
3kΩ
CLK–
CLK+
V
DX–
DX+
V
V
2.5kΩ
2.5kΩ
05490-011
05490-008
V
Figure 11. Equivalent Sample Clock Input Circuit
Figure 8. Equivalent LVDS Digital Output Circuit
Rev. 0 | Page 15 of 36
AD9446
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 3.2 V p-p differential
input, AIN = −1dBFS, internal trimmed reference (nominal VREF = 1.6 V), unless otherwise noted.
0
0
100MSPS
10.3MHz @ –1.0dBFS
SNR = 79.7dB
ENOB = 13.1BITS
SFDR = 90dBc
–10
–20
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05490-012
–110
–120
–130
0
12.5
25.0
37.5
05490-015
AMPLITUDE (dBFS)
–30
100MSPS
92.16MHz @ –1.0dBFS
SNR = 78.9dB
ENOB = 12.7BITS
SFDR = 84dBc
–10
–120
–130
50.0
12.5
0
FREQUENCY (MHz)
Figure 12. AD9446-100 64k Point Single-Tone FFT/100 MSPS/10.3 MHz
37.5
50.0
Figure 15. AD9446-100 64k Point Single-Tone FFT/100 MSPS/92.16 MHz
0.6
0
100MSPS
30.3MHz @ –1.0dBFS
SNR = 79.5dB
ENOB = 12.9BITS
SFDR = 90dBc
–10
–20
0.4
DNL ERROR (MSB)
–30
AMPLITUDE (dBFS)
25.0
FREQUENCY (MHz)
–40
–50
–60
–70
–80
0.2
0
–0.2
–90
–100
05490-013
–120
–130
0
12.5
25.0
37.5
05490-016
–0.4
–110
–0.6
0
50.0
8192
65536
OUTPUT CODE
FREQUENCY (MHz)
Figure 13. AD9446-100 64k Point Single-Tone FFT/100 MSPS/30.3 MHz
Figure 16. AD9446-100 DNL Error vs. Output Code, 100 MSPS, 10.3 MHz
4
0
100MSPS
70.3MHz @ –1.0dBFS
SNR = 79.0dB
ENOB = 12.9BITS
SFDR = 86dBc
–10
–20
–30
3
2
–40
INL ERROR (MSB)
AMPLITUDE (dBFS)
16384 24576 32768 40960 49152 57344
–50
–60
–70
–80
–90
1
0
–1
–2
–100
–130
0
12.5
25.0
37.5
05490-017
–3
05490-014
–110
–120
–4
0
50.0
8192
16384 24576 32768 40960 49152 57344
65536
OUTPUT CODE
FREQUENCY (MHz)
Figure 14. AD9446-100 64k Point Single-Tone FFT/100 MSPS/70.3 MHz
Figure 17. AD9446-100 INL Error vs. Output Code, 100 MSPS, 10.3 MHz
Rev. 0 | Page 16 of 36
AD9446
0
0
80MSPS
10.3MHz @ –1.0dBFS
SNR = 81.8dB
ENOB = 13.2BITS
SFDR = 90dBc
–10
–20
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05490-018
–110
–120
–130
0
12.5
25.0
05490-021
AMPLITUDE (dBFS)
–30
80MSPS
100.3MHz @ –1.0dBFS
SNR = 79.5dB
ENOB = 12.7BITS
SFDR = 92dBc
–10
–120
–130
37.5
12.5
0
FREQUENCY (MHz)
Figure 18. AD9446-80 64k Point Single-Tone FFT/80 MSPS/10.3 MHz
0.6
80MSPS
30.3MHz @ –1.0dBFS
SNR = 81.6dB
ENOB = 13.2BITS
SFDR = 89dBc
–10
–20
0.4
DNL ERROR (MSB)
–30
–40
–50
–60
–70
–80
0.2
0
–0.2
–90
–100
–0.4
05490-019
–110
–120
–130
0
12.5
25.0
05490-022
AMPLITUDE (dBFS)
37.5
Figure 21. AD9446-80 64k Point Single-Tone FFT/80 MSPS/100.3 MHz
0
–0.6
0
37.5
8192
16384 24576 32768 40960 49152 57344
65536
OUTPUT CODE
FREQUENCY (MHz)
Figure 19. AD9446-80 64k Point Single-Tone FFT/80 MSPS/30.3 MHz
Figure 22. AD9446-80 DNL Error vs. Output Code, 80 MSPS, 10.3 MHz
4
0
80MSPS
70.3MHz @ –1.0dBFS
SNR = 80.6dB
ENOB = 12.9BITS
SFDR = 85dBc
–10
–20
–30
3
2
–40
INL ERROR (MSB)
AMPLITUDE (dBFS)
25.0
FREQUENCY (MHz)
–50
–60
–70
–80
–90
1
0
–1
–2
–100
–130
0
12.5
25.0
05490-023
–3
05490-020
–110
–120
–4
0
37.5
8192
16384 24576 32768 40960 49152 57344
65536
OUTPUT CODE
FREQUENCY (MHz)
Figure 20. AD9446-80 64k Point Single-Tone FFT/80 MSPS/70.3 MHz
Figure 23. AD9446-80 INL Error vs. Output Code, 80 MSPS, 10.3 MHz
Rev. 0 | Page 17 of 36
AD9446
95
95
SFDR (dBc) +85°C
SFDR (dBc) –40°C
SFDR (dBc) +25°C
SFDR (dBc) +25°C
90
90
SFDR (dBc) +85°C
SFDR (dBc) –40°C
(dB)
85
(dB)
85
SNR (dB) +25°C
SNR (dB) –40°C
80
80
SNR (dB) +25°C
SNR (dB) –40°C
SNR (dB) +85°C
75
75
70
0
20
40
60
80
100
120
140
160
05490-027
05490-024
SNR (dB) +85°C
70
180
0
20
40
ANALOG INPUT FREQUENCY (MHz)
60
80
100
120
140
160
180
ANALOG INPUT FREQUENCY (MHz)
Figure 24. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS, 3.2 V p-p
Figure 27. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS, 2.0 V p-p
95
86
SFDR (dBc) +85°C
85
SFDR (dBc) +25°C
90
84
SFDR (dBc) –40°C
80M SNR dBFS
83
(dB)
(dB)
85
SNR (dB) +25°C
SNR (dB) –40°C
82
81
80
100M SNR dBFS
80
SNR (dB) +85°C
05490-025
70
0
20
40
60
80
100
120
140
160
05490-039
79
75
78
77
1.8
180
2.0
2.2
2.4
ANALOG INPUT FREQUENCY (MHz)
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
ANALOG INPUT RANGE (V p-p)
Figure 25. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS,
3.2 V p-p, CMOS Output Mode
Figure 28. AD9446-100 SNR vs. Input Range, 30.3 MHz, −30 dBFS
120
130
SFDR dBFS
SFDR dBFS
110
100
90
80
SNR dBFS
SNR dBFS
(dB)
(dB)
70
60
50
40
SFDR dBc
SFDR dBc
30
0
–100
–90
–80
–70
–60
10
05490-026
SNR dB
–50
–40
–30
–20
–10
0
–100
0
ANALOG INPUT AMPLITUDE (dB)
SNR dB
–90
–80
–70
–60
05490-029
20
–50
–40
–30
–20
–10
0
ANALOG INPUT AMPLITUDE (dB)
Figure 26. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS
Figure 29. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS,
CMOS Output Mode
Rev. 0 | Page 18 of 36
AD9446
95
95
SFDR (dBc) –40°C
SFDR (dBc) +85°C
SFDR (dBc) –40°C
90
90
SFDR (dBc) +25°C
SFDR (dBc) +25°C
85
85
SNR (dB) –40°C
SNR (dB) –40°C
SFDR (dBc) +85°C
(dB)
80
(dB)
80
SNR (dB) +85°C
SNR (dB) +25°C
75
75
SNR (dB) +25°C
65
65
05490-030
70
60
0
20
40
60
80
100
120
140
160
05490-033
SNR (dB) +85°C
70
60
180
0
20
ANALOG INPUT FREQUENCY (MHz)
40
60
80
100
120
140
160
180
ANALOG INPUT FREQUENCY (MHz)
Figure 30. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 3.2 V p-p
Figure 33. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 2.0 V p-p
90
95
SFDR (dBc) +25°C
SFDR dBc
88
SFDR (dBc) –40°C
90
86
SFDR (dBc) +85°C
84
85
82
SNR (dB) –40°C
(dB)
(dB)
80
SNR (dB) +25°C
SNR (dB) +85°C
75
80
SNR dB
78
76
70
72
05490-031
60
20
40
60
80
100
120
140
160
70
2.6
180
2.8
3.0
ANALOG INPUT FREQUENCY (MHz)
Figure 31. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 3.2 V p-p,
CMOS Mode
3.8
4.0
4.2
SFDR dBFS
100
100
80
80
SNR dBFS
(dB)
(dB)
3.6
120
SFDR dBFS
60
SNR dBFS
60
40
SFDR dBc
SFDR dBc
20
05490-032
20
SNR dB
0
–100
3.4
Figure 34. AD9446-80 SNR/SFDR vs. Analog Input Common Mode, 80 MSPS
120
40
3.2
ANALOG INPUT COMMON-MODE VOLTAGE
–90
–80
–70
–60
–50
–40
–30
–20
–10
05490-035
0
05490-034
74
65
SNR dB
0
–100
0
ANALOG INPUT AMPLITUDE (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT AMPLITUDE (dB)
Figure 32. AD9446-80 SNR/SFDR vs. Analog Input Level, 80 MSPS
Figure 35. AD9446-80 SNR/SFDR vs. Analog Input Level, 80 MSPS,
CMOS Output Mode
Rev. 0 | Page 19 of 36
AD9446
0
0
100MSPS
9.8MHz @ –7.0dBFS
10.8MHz @ –7.0dBFS
SFDR = 95dBc
–10
–20
–20
–30
–50
–60
–70
–80
–90
–100
–40
–70
–80
–90
–110
05490-037
–110
–120
–140
12.5
0
25.0
37.5
WORST IMD3 dBc
–60
–100
–130
SFDR dBc
–50
SFDR dBFS
WORST IMD3 dBFS
–120
–130
–100
50.0
–90
–80
–70
FREQUENCY (MHz)
0
–10
–20
–20
–30
–30
–40
AMPLITUDE (dBFS)
–40
–30
–20
0
–10
SFDR dBc
WORST IMD3 dBc
–70
–80
–90
80MSPS
9.8MHz @ –7.0dBFS
10.8MHz @ –7.0dBFS
SFDR = 96dBc
–40
–50
–60
–70
–80
–90
–100
SFDR dBFS
–110
WORST IMD3 dBFS
–130
–100
–90
–80
–70
–60
–50
–40
–30
–20
–130
–140
0
–10
05490-042
–120
–120
05490-038
–110
10
0
20
FUNDAMENTAL LEVEL (dB)
30
40
FREQUENCY (MHz)
Figure 37. AD9446-100 Two-Tone SFDR vs. Analog Input Level 100 MSPS/
9.8 MHz, 10.8 MHz
Figure 40. AD9446-80 64k Point Two-Tone FFT/80 MSPS/9.8 MHz, 10.8 MHz
0
0
100MSPS
69.3MHz @ –7.0dBFS
70.3MHz @ –7.0dBFS
SFDR = 92dBc
–10
–20
–30
–10
–20
–30
SPUR AND IMD3 (dB)
–40
–50
–60
–70
–80
–90
–100
–40
–50
–70
–90
–100
–110
05490-040
–110
–140
0
12.5
25.0
37.5
WORST IMD3 dBc
–80
–120
–130
SFDR dBc
–60
SFDR dBFS
–120
–130
–100
50.0
FREQUENCY (MHz)
05490-043
SPUR AND IMD3 (dB)
0
–100
AMPLITUDE (dBFS)
–50
Figure 39. AD9446-100 Two-Tone SFDR vs. Analog Input Level 100 MSPS/
69.3 MHz, 70.3 MHz
–10
–60
–60
FUNDAMENTAL LEVEL (dB)
Figure 36. AD9446-100 64k Point Two-Tone FFT/100 MSPS/9.8 MHz, 10.8 MHz
–50
05490-041
–40
SPUR AND IMD3 (dB)
AMPLITUDE (dBFS)
–30
–10
WORST IMD3 dBFS
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FUNDAMENTAL LEVEL (dB)
Figure 38. AD9446-100 64k Point Two-Tone FFT/100 MSPS/69.3 MHz, 70.3 MHz
Figure 41. AD9446-80 Two-Tone SFDR vs. Analog Input Level 80 MSPS/
9.8 MHz, 10.8 MHz
Rev. 0 | Page 20 of 36
AD9446
16000
18000
SAMPLE SIZE = 65538
14296
17090
16450
SAMPLE SIZE = 65538
16000
14000
12619
11927
14000
12000
10000
FREQUENCY
FREQUENCY
12000
8376
8000
7277
6000
11027
10145
10000
8000
6000
4073
OUTPUT CODE
N+6
N+5
N+3
N+2
N
N+1
OUTPUT CODE
Figure 42. AD9446-100 Grounded Input Histogram
Figure 45. AD9446-80 Grounded Input Histogram
0
0
80MSPS
69.3MHz @ –7.0dBFS
70.3MHz @ –7.0dBFS
SFDR = 92dBc
–10
–20
–30
–0.1
–0.2
–40
GAIN ERROR (%FSR)
–50
–60
–70
–80
–90
–100
–0.3
–0.4
–0.5
–0.6
–110
–0.7
05490-045
–120
–130
–140
10
0
20
30
–0.8
–40
40
05490-048
AMPLITUDE (dBFS)
N–1
N–4
198 30
N–2
146
N–3
10
05490-047
1181
947
3
0
N+4
2000
N+7
N+4
N+3
N+2
N
N+1
N–1
N–2
N–3
80 22
N+6
426
N–4
N–5
N–6
N–7
0
N–5
1458
1192
11 40 315
05490-044
4000
N+5
2000
4393
3916
3424
N–6
4000
–20
0
FREQUENCY (MHz)
20
40
60
80
TEMPERATURE (°C)
Figure 43. AD9446-80 64k Point Two-Tone FFT/80 MSPS/69.3 MHz, 70.3 MHz
Figure 46. AD9446-100 Gain vs. Temperature
0
400
–10
350
–20
300
AVDD1
–40
–50
ISUPPLY (mA)
SFDR dBc
–60
–70
WORST IMD3 dBc
–80
250
200
AVDD2
150
–90
–100
100
SFDR dBFS
DRVDD
–120
–130
–100
WORST IMD3 dBFS
–90
–80
–70
–60
–50
50
05490-046
–110
–40
–30
–20
–10
05490-049
SPUR AND IMD3 (dB)
–30
0
0
0
FUNDAMENTAL LEVEL (dB)
20
40
60
80
100
120
140
SAMPLE RATE (MSPS)
Figure 44. AD9446-80 Two-Tone SFDR vs. Analog Input Level 80 MSPS/
69.3 MHz, 70.3 MHz
Rev. 0 | Page 21 of 36
Figure 47. AD9446-80 Power Supply Current vs. Sample Rate
10.3 MHz @ −1 dBFS
AD9446
82
95
93
81
10.3MHz SFDR dBc
91
80
89
(dB)
(dB)
70.3MHz SFDR dBc
87
30.3MHz SFDR dBc
10.3MHz SFDR dBc
79
85
78
83
30.3MHz SFDR dBc
79
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
05490-050
70.3MHz SFDR dBc
3.8
4.0
76
1.8
4.2
05490-064
77
81
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
ANALOG INPUT RANGE (V p-p)
ANALOG INPUT RANGE (V p-p)
Figure 48. AD9446-100/SFDR vs. Analog Input Range,
100 MSPS
Figure 51. AD9446-100 SNR vs. Analog Input Range,
100 MSPS
95
1.625
93
10.3MHz SFDR dBc
91
1.620
89
(dB)
VREF
30.3MHz SFDR dBc
1.615
87
85
70.3MHz SFDR dBc
83
1.610
1.605
–40
–20
0
20
40
60
79
1.8
05490-065
05490-051
81
2.0
2.2
80
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
ANALOG INPUT RANGE (V p-p)
TEMPERATURE (°C)
Figure 52. AD9446-80 SFDR vs. Analog Input Range,
100 MSPS
Figure 49. AD9446-100 VREF vs. Temperature
84
450
350
82
30.3MHz SNR dB
AVDD1
300
(dB)
81
250
70.3MHz SNR dB
80
200
AVDD2
79
150
78
DRVDD
50
0
0
20
40
60
80
100
120
77
1.8
140
05490-066
100
05490-063
ISUPPLY (mA)
10.3MHz SNR dB
83
400
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
ANALOG INPUT RANGE (V p-p)
SAMPLE RATE (MSPS)
Figure 53. AD9446-80/SNR vs. Analog Input Range,
80 MSPS
Figure 50. AD9446-100 Power Supply Current vs. Sample Rate
10.3 MHz @ −1 dBFS
Rev. 0 | Page 22 of 36
4.2
AD9446
100
100M SFDR dBc
95
80M SFDR dBc
(dB)
90
85
80M SNR dB
80
05490-036
100M SNR dB
75
0
10
20
30
40
50
60
70
80
90
100
110
SAMPLE RATE (MSPS)
Figure 54. AD9446 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz
Rev. 0 | Page 23 of 36
AD9446
THEORY OF OPERATION
The AD9446 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 16-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.
<2 V p-p. However, reducing the range can improve SFDR
performance in some applications. Likewise, increasing the
range up to 3.8 V p-p can improve SNR. Users are cautioned
that the differential nonlinearity of the ADC varies with the
reference voltage. Configurations that use <2.0 V p-p may
exhibit missing codes and therefore degraded noise and
distortion performance.
VIN+
ANALOG INPUT AND REFERENCE OVERVIEW
VIN–
A stable and accurate 0.5 V band gap voltage reference is built
into the AD9446. The input range can be adjusted by varying
the reference voltage applied to the AD9446, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
REFT
ADC
CORE
0.1μF
0.1μF
+
10μF
REFB
0.1μF
VREF
10μF
+
0.1μF
SELECT
LOGIC
Internal Reference Connection
A comparator within the AD9446 detects the potential at the
SENSE pin and configures the reference into three possible states,
which are summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 55), setting VREF to ~1.6 V. If a resistor
divider is connected as shown in Figure 56, the switch again sets
to the SENSE pin. This puts the reference amplifier in a
noninverting mode with the VREF output defined as
SENSE
05490-052
0.5V
AD9446
Figure 55. Internal Reference Configuration
VIN+
R2 ⎞
VREF = 0.5 V × ⎛⎜1 +
⎟
⎝ R1 ⎠
VIN–
In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
REFT
ADC
CORE
0.1μF
0.1μF
+
10μF
REFB
0.1μF
VREF
+
10μF
0.1μF
R2
Internal Reference Trim
SELECT
LOGIC
SENSE
Rev. 0 | Page 24 of 36
R1
0.5V
AD9446
Figure 56. Programmable Reference Configuration
05490-053
The internal reference voltage is trimmed during the production
test; therefore, there is little advantage to the user supplying an
external voltage reference to the AD9446. The gain trim is performed with the AD9446 input range set to 3.2 V p-p nominal
(SENSE connected to AGND). Because of this trim and the
maximum ac performance provided by the 3.2 V p-p analog
input range, there is little benefit to using analog input ranges
AD9446
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Programmable Reference
SENSE Voltage
AVDD
0.2 V to VREF
Resulting VREF (V)
N/A
Resulting Differential Span (V p-p)
2 × external reference
2 × VREF
Programmable Reference
(Set for 2 V p-p)
0.2 V to VREF
R2 ⎞ , R1 = R2 = 1 kΩ
0.5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
2.0
Programmable Reference
(Set for 2 V p-p)
0.2 V to VREF
R2 ⎞ , R1 = 1 kΩ , R2 = 2.8 kΩ
0.5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
3.8
Internal Fixed Reference
AGND to 0.2 V
1.6
3.2
R2 ⎞ (See Figure 56)
0.5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
External Reference Operation
VIN+
1.6V p-p
3.5V
VIN–
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
05490-054
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 2.0 V. See Figure 46 for gain variation vs.
temperature.
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9446 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9446 cannot be realized with a single-ended analog input, so
such configurations are discouraged. Contact sales for
recommendations of other 16-bit ADCs that support singleended analog input configurations.
With the 1.6 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9446 analog input is nominally 3.2 V p-p or 1.6 V p-p on
each input (VIN+ or VIN−).
Figure 57. Differential Analog Input Range for VREF = 1.6 V
The AD9446 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer. The
internal bias network on the input properly biases the buffer for
maximum linearity and range (see the Equivalent Circuits
section). Therefore, the analog source driving the AD9446
should be ac-coupled to the input pins. The recommended
method for driving the analog input of the AD9446 is to use an
RF transformer to convert single-ended signals to differential
(see Figure 58). Series resistors between the output of the
transformer and the AD9446 analog inputs help isolate the
analog input source from switching transients caused by the
internal sample-and-hold circuit. The series resistors, along
with the 1 kΩ resisters connected to the internal 3.5 V bias,
must be considered in impedance matching the transformer
input. For example, if RT is set to 51 Ω, RS is set to 33 Ω and
there is a 1:1 impedance ratio transformer, the input will match a
50 Ω source with a full-scale drive of 16.0 dBm. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board
schematic (see Figure 61).
Rev. 0 | Page 25 of 36
AD9446
0.1μF
AD9446
VIN–
Figure 58. Transformer-Coupled Analog Input Circuit
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-todigital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9446, and the user is
advised to give careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance characteristics. The AD9446 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal ~50% duty cycle. Noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer,
and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9446 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of performance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
by 3 dB to 4 dB with 70 MHz analog input signals when using a
high jitter clock source. (See the AN-501 Application Note,
“Aperture Uncertainty and ADC System Performance.”) For
optimum performance, the AD9446 must be clocked differentially.
The sample clock inputs are internally biased to ~1.5 V, and the
input signal is usually ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. Figure 59 shows one preferred
method for clocking the AD9446. The clock source (low jitter)
is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary
of the transformer limit clock excursions into the AD9446 to
approximately 0.8 V p-p differential. This helps prevent the large
voltage swings of the clock from feeding through to other portions
of the AD9446 and limits the noise presented to the sample
clock inputs.
If a low jitter clock is available, it may help to band-pass filter
the clock reference before driving the ADC clock inputs. Another
option is to ac couple a differential ECL/PECL signal to the encode
input pins, as shown in Figure 60.
CRYSTAL
SINE
SOURCE
ADT1–1WT
CLK+
0.1μF
AD9446
CLK–
HSMS2812
DIODES
05490-056
RS
VIN+
Figure 59. Crystal Clock Oscillator, Differential Encode
VT
0.1μF
ENCODE
ECL/
PECL
0.1μF
AD9446
ENCODE
VT
05490-057
RS
ADT1–1WT
05490-055
ANALOG
INPUT
SIGNAL RT
Figure 60. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) and rms amplitude due only to aperture jitter
(tJ) can be calculated using the following equation:
SNR = 20 log[2πfINPUT × tJ]
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which includes the clock input, analog
input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9446.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
synchronized by the original clock during the last step.
Rev. 0 | Page 26 of 36
AD9446
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9446. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.
The AD9446 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best performance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.
The DRVDD supply of the AD9446 is a dedicated supply for the
digital outputs in either LVDS or CMOS output mode. When in
LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode,
the DRVDD supply can be connected from 2.5 V to 3.6 V for
compatibility with the receiving logic.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9446 is used in LVDS mode; designers are
encouraged to take advantage of this mode. The AD9446
outputs include complimentary LVDS outputs for each data bit
(Dx+/Dx−), the overrange output (OR+/OR−), and the output
data clock output (DCO+/DCO−). The RSET resistor current is
multiplied on-chip, setting the output current at each output
equal to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential
termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended, with a 100 Ω termination resistor
located as close to the receiver as possible. It is recommended to
keep the trace length less than 2 inches and to keep differential
output trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9446 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock is provided as a differential CMOS
signal, DCO+/DCO−. Lower supply voltages are recommended
to avoid coupling switching transients back to the sensitive
analog sections of the ADC. The capacitive load to the CMOS
outputs should be minimized, and each output should be
connected to a single gate through a series resistor (220 Ω) to
minimize switching transients caused by the capacitive loading.
TIMING
The AD9446 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
Rev. 0 | Page 27 of 36
AD9446
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9446 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9446 outputs are CMOS compatible, and the pin assignment
for the device is as defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9446 outputs are LVDS compatible, and
the pin assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS-
Table 10. Digital Output Coding
Code
65,536
32,768
32,767
0
VIN+ − VIN−
Input Span = 3.2 V p-p (V)
+1.600
0
−0.0000488
−1.60
VIN+ − VIN−
Input Span = 2 V p-p (V)
+1.000
0
−0.000122
−1.00
Digital Output
Offset Binary (D15••••••D0)
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Rev. 0 | Page 28 of 36
Digital Output
Twos Complement (D15••••••D0)
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
AD9446
EVALUATION BOARD
Evaluation boards are offered to configure the AD9446 in either
CMOS or LVDS mode only. This design represents a recommended configuration for using the device over a wide range of
sampling rates and analog input frequencies. These evaluation
boards provide all the support circuitry required to operate
the ADC in its various modes and configurations. Complete
schematics are shown in Figure 61 through Figure 64. Gerber
files are available from engineering applications demonstrating
the proper routing and grounding techniques that should be
applied at the system level.
The LVDS mode evaluation boards include an LVDS-to-CMOS
translator, making them compatible with the high speed ADC
FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a
high speed data capture board that provides a hardware solution
for capturing up to 32 kB samples of high speed ADC output
data in a FIFO memory chip (user upgradeable to 256 kB
samples). Software is provided to enable the user to download
the captured data to a PC via the USB port. This software also
includes a behavioral model of the AD9446 and many other
high speed ADCs.
It is critical that signal sources with very low phase noise
(<60 fsec rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal to remove
harmonics and lower the integrated noise at the input is also
necessary to achieve the specified noise performance.
Behavioral modeling of the AD9446 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supports virtual ADC evaluation using ADI proprietary behavioral
modeling technology. This allows rapid comparison between the
AD9446 and other high speed ADCs with or without hardware
evaluation boards.
The evaluation boards are shipped with a 115 V ac to 6 V dc
power supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9446 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see Figure 61).
The user can choose to remove the translator and terminations
to access the LVDS outputs directly.
Rev. 0 | Page 29 of 36
Rev. 0 | Page 30 of 36
Figure 61. AD9446 Evaluation Board Schematic
C5
0.1μF
PRI
SEC
TOUTB
CT
4
3
2
5
1
GND
T2
GND
GND
C8
0.1μF
R6
36Ω
R4
36Ω
C7
0.1μF
C51
10μF
R28
33Ω
R35
33Ω
R9
DNP
C9
0.1μF
C3
0.1μF
OPTIONAL
TINB
4
3
TOUT
PRI
6
2
GND
ETC1-1-13
1
5
TOUTB
C12
0.1μF
TOUT
GND
C40
0.1μF
GND
C86
0.1μF
C91
0.1μF
NC
E15
SEC
CT
PRI
5
4
2
3
1
T5
ADT1-1WT
TINB
GND
C98
DNP GND
C39
10μF
GND
C13
DNP
U1
AD9445/AD9446
ENC
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
ANALOG
L1
10nH
E25
E27
D0_T
D0_C
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
ENCB
05490-059
J4
SMBMST
T1
ETC1-1-13
E41
E24
GND
EXTREF
GND
E26
+
R5
DNP
GND
R2
GND DNP
R1
DNP
VCC
EPAD
DCS MODE
DNC
OUTPUT MODE
DFS
LVDSBIAS
AVDD1
SENSE
VREF
AGND
REFT
REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
VIN+
VIN–
AGND
AVDD2
DRVDD
D11_C
D11_T
D12_C
D12_T
D13_C
D13_T
D14_C
D14_T
D15_C
D15_T
DRGND
DRVDD
OR_C
OR_T
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
R3
3.74kΩ
GND
VCC
SCLK 1
2
3
4
5
6
VCC
7
8
9
GND
10
11
12
5V
C2
13
5V
0.1μF
14
5V
5V 15
16
5V
17
5V
18
VCC
19
VCC
20
VCC
21
GND
22
23
24
GND
25
5V
R11
1kΩ GND
DRGND
D10_T
D10_C
D9_T
D9_C
D8_T
D8_C
DCO
DCOB
D7_T
D7_C
DRVDD
DRGND
D6_T
D6_C
D5_T
D5_C
D4_T
D4_C
D3_T
D3_C
D2_T
D2_C
D1_T
D1_C
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
GND
5V
E2
E3
D5_T
D5_C
D4_T
D4_C
D3_T
D3_C
D2_T
D2_C
D1_T
D1_C
D7_T
D7_C
DRVDD
DRGND
D6_T
D6_C
D8_T/D1_Y
D8_C/D0_Y
DR
DRB
D10_T/D5_Y
D10_C/D4_Y
D9_T/D3_Y
D9_C/D2_Y
DRGND
XTALPWR
EXTREF
DRGND
DRVDD
GND
VCC
101
E9
D12_C/D8_Y
D12_T/D9_Y
D13_C/D10_Y
D13_T/D11_Y
D14_C/D12_Y
D14_T/D13_Y
D15_C/D14_Y
(MSB) D15_T/D15_Y
DRGND
DRVDD
DOR_C
DOR_T/DOR_Y
GND
VCC
VCC
VCC
VCC
VCC
VCC
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
GND
DRVDD
D11_C/D6_Y
D11_T/D7_Y
E14
E10
VCC
E1
E5
GND
E4
DRGND
E6
H3
MTHOLE6
E18
H4
MTHOLE6
VCC
H2
MTHOLE6
E19
H1
MTHOLE6
E66
GND
VCC
1
P1
2
P2
3
P3
4
P4
1
P1
2
P2
3
P3
4
P4
GND
P22
P21
PTMICRO4 PTMICRO4
AD9446
D0_T
D0_C (LSB)
DRVDD
DRGND
GND
VCC
VCC
VCC
GND
ENCB
ENC
GND
VCC
5V
VCC
5V
VCC
VCC
VCC
5V
SEC
GND
R8
50Ω
Rev. 0 | Page 31 of 36
Figure 62. AD9446 Evaluation Board Schematic (Continued)
05490-060
1
3
1
3
2
C33
10μF
GND
+
GND
VIN
5VX
+
4
GND
C89
10μF
OUT
5V
IN
OUT1
GND
ADP3338
L3
FERRITE
L4
FERRITE
L5
FERRITE
PJ-102A
5V
VCC
DRVDD
U14
2
C26
0.1μF
4
3
DNP
CR2
3
2
1
3
C34
10μF
VIN
5VX
GND
5VX
VCCX
GND
+
2
DRVDDX
C42
PRI SEC 0.1μF GND
6
2
1
NC 5
1
VCCX
4
VXTAL
3.3V
U7
IN
OUT1
GND
ADP3338
OUT
C87
10μF
GND
+
ENC
ENCB
CR2 TO MAKE LAYOUT AND PARASITIC
LOADING SYMMETRICAL
T3
ADT1-1WT
P4
POWER OPTIONS
XTALINPUT
J1
SMBMST
C36
DNP
R39
0Ω
ENCODE
1
GND
2
3
J5
SMBMST
R7
DNP
CR1
GND
3
2
1
C6
10μF
GND
+
VIN
VCCX
GND
GND
GND
VEE
VCC
DRVDDX
L2
DNP
7
14
+
C88
10μF
DRGND
+
4
DRGND
U3
3.3V
IN
OUT1
GND
+
C4
10μF
VIN
DRVDDX
DRGND
DRGND
3
2
1
XTALINPUT
C41
0.1μF
ADP3338
1
8
C1
10μF
OUT
~OUT
OUT
U6
ECLOSC
GND
XTALPWR
5V
C44
10μF
GND
+
E30
VXTAL
E20
E31
VXTAL
OPTIONAL ENCODE CIRCUITS
AD9446
AD9446
BYPASS CAPACITORS
VCC
+
C64
10μF
C43
0.1μF
C35
0.1μF
C32
0.1μF
C14
XX
C17
XX
C30
0.01μF
C28
0.1μF
C27
0.1μF
C90
0.1μF
C50
0.1μF
C60
0.1μF
C10
0.1μF
C61
0.1μF
C75
0.1μF
GND
VCC
C11
XX
C16
XX
C15
XX
C31
XX
C38
XX
C29
XX
C19
XX
C69
XX
C70
XX
C45
XX
C37
0.1μF
C48
0.1μF
C18
0.1μF
GND
DRVDD
DRVDD
+
C65
10μF
C47
0.1μF
C23
0.1μF
C21
0.1μF
C20
0.1μF
DRGND
C49
XX
DRGND
5V
EXTREF
+
C56
10μF
C85
0.1μF
C53
0.1μF
C52
0.1μF
C58
0.01μF
GND
+
C55
10μF
GND
5V
C72
XX
C73
XX
C94
0.1μF
C95
0.1μF
C108
XX
C109
XX
C110
XX
C59
0.1μF
C93
0.1μF
C96
0.1μF
GND
C22
0.1μF
C97
0.1μF
C84
0.1μF
GND
Figure 63. AD9446 Evaluation Board Schematic (Continued)
Rev. 0 | Page 32 of 36
C46
0.1μF
05490-061
5V
Rev. 0 | Page 33 of 36
Figure 64. AD9446 Evaluation Board Schematic (Continued)
05490-062
DRGND
D0_T
D1_T
D2_T
D3_T
D4_T
D5_T
D6_T
D7_T
DR
D8_T/D1_Y
D9_T/D3_Y
D10_T/D5_Y
D11_T/D7_Y
D12_T/D9_Y
D13_T/D11_Y
D14_T/D13_Y
D15_T/D15_Y
DOR_T/DOR_Y
DRGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
D4_C
D3_C
D2_C
D1_C
D0_C
DRGND
P11 11
P9 9
P7 7
P5 5
P3 3
P1 1
D5_C
GND
GND
DRB
P19 19
P13 13
D8_C/DO_Y
P21 21
D6_C
D9_C/D2_Y
P23 23
P15 15
D10_C/D4_Y
P25 25
D7_C
D11_C/D6_Y
P27 27
P17 17
D12_C/D8_Y
D14_C/D12_Y
P33 33
P29 29
D15_C/D14_Y
P35 35
D13_C/D10_Y
DOR_C
P37 37
P31 31
DRGND
P6
C40MS
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P39 39
C76
0.1μF
D15_T/D14_Y
D15_C/D14_Y
D14_T/D13_Y
D14_C/D12_Y
D13_T/D11_Y
D13_C/D10_Y
D12_T/D9_Y
D12_C/D8_Y
D11_T/D7_Y
D11_C/D6_Y
D10_T/D5_Y
D10_C/D4_Y
D9_T/D3_Y
D9_C/D2_Y
D8_T/D1_Y
D8_C/D0_Y
D7_T
D7_C
D6_T
D6_C
D5_T
D5_C
D4_T
D4_C
D3_T
D3_C
D2_T
D2_C
D1_T
D1_C
D0_T
D0_C
DRO_T/DOR_Y
DOR_C
DR
DRB
C82
0.1μF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
EN_1_2
1Y
2Y
VCC
GND
3Y
4Y
EN_3_4
C77
0.1μF
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
C78
0.1μF
GND
VCC1
VCC2
GND1
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND2
VCC3
VCC4
GND3
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND4
VCC5
VCC6
GND5
U8
SN75LVDS386
1A
1B
2A
2B
3A
3B
4A
4B
U15
SN75LVDT390
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
16
15
14
13
12
11
10
9
DRVDD
DRGND
DRVDD
DRVDD
DRGND
DRVDD
DRGND
DRVDD
DRVDD
DRGND
DRVDD
DRGND
DRVDD
DRVDD
DRGND
DRVDD
DRVDD
0Ω
R19
DRVDD 0Ω
DRGND R20
DRVDD
ORO
DRO
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
RZ4
R8
R7
R6
R5
R4
R3
R2
R1
9
10
11
12
13
14
15
16
220
RSO16ISO
R8
R7
R6
R5
R4
R3
R2
R1
RZ5
220
RSO16ISO
D0O
D1O
D2O
D3O
D4O
D5O
D6O
D7O
D8O
D9O
D10O
D11O
D12O
D13O
D14O
D15O
DRGND
ORO
DRGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P1 1
P3 3
P5 5
P7 7
P9 9
P11 11
P13 13
P15 15
P17 17
P19 19
P21 21
P23 23
P25 25
P27 27
P29 29
P31 31
P33 33
P35 35
P37 37
P39 39
P7
C40MS
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
DRGND
D0O
D1O
D2O
D3O
D4O
D5O
D6O
D7O
D8O
D9O
D10O
D11O
D12O
D13O
D14O
D15O
GND??
DRO
DRGND
AD9446
AD9446
Table 11. AD9446 Customer Evaluation Board Bill of Material
2
4
1
1
Reference
Designator
C4, C6, C33, C34, C87,
C88, C89
C2, C3, C5, C7, C8,
C9, C10, C11, C12,
C15, C20, C21, C22,
C23, C26, C27, C28,
C32, C35, C38, C40,
C42, C43, C46, C47,
C48, C50, C52, C53,
C59, C60, C76, C77,
C78, C82, C84, C85,
C86, C90, C91, C94,
C95, C96, C97
C30, C58
C39, C56, C64, C65
C51
CR1
7
1
8
20
9
10
11
Item
1
Qty.
7
Description
Capacitor
Package
TAJD
Value
10 μF
Manufacturer
Digi-Key Corporation
Mfg. Part No.
478-1699-2
2
44
Capacitor
402
0.1 μF
Digi-Key Corporation
PCC2146CT-ND
3
4
5
6
Capacitor
Capacitor
Capacitor
Diode
201
TAJD
805
SOT23M5
0.01 μF
10 μF
10 μF
Digi-Key Corporation
Digi-Key Corporation
Digi-Key Corporation
Digi-Key Corporation
CR2
Diode
SOT23M5
Digi-Key Corporation
Header
EHOLE
Mouser Electronics
2
1
3
E1, E2, E3, E4, E5, E6,
E9, E10, E14, E18, E19,
E20, E24, E25, E26, E27,
E30, E31, E36, E41
J1, J4
L1
L3, L4, L5
445-1796-1-ND
478-1699-2
490-1717-1-ND
MA3X71600LCTND
MA3X71600LCTND
517-6111TG
SMA
0603A
1206MIL
Digi-Key Corporation
Coilcraft, Inc.
Mouser Electronics
ARFX1231-ND
0603CS-10NXGBU
81-BLM31P500S
12
13
1
1
P4
P7
SMA
Inductor
EMIFIL®
BLM31PG500SN1L
PJ-002A
Header
PJ-002A
C40MS
Digi-Key Corporation
Samtec, Inc.
14
15
16
17
18
19
1
1
4
1
2
2
R3
R8
R10, R19, R39, L2
R11
R28, R35
RZ4, RZ5
Resistor
Resistor
Resistor
BRES402
Resistor
Resistor array
402
402
402
402
402
16PIN
20
21
22
2
1
1
T3, T5
U1
U14
Transformer
AD9445BSVZ-125
ADP3338-5
Mini-Circuits
Analog Devices, Inc.
Analog Devices, Inc.
23
2
U3, U7
ADP3338-3.3
Analog Devices, Inc.
ADP3338-33
24
25
26
27
28
1
1
2
2
23
SN75LVDT386
SN75LVDT390
Resistor
Capacitor
CAP402
36 Ω
10 μF
XX
Arrow Electronics, Inc.
Arrow Electronics, Inc.
Digi-Key Corporation
Digi-Key Corporation
SN75LVDT386
SN75LVDT390
P36JCT-ND
478-1699-2
29
1
U8
U15
R4, R6
C1, C44, C55 1
C13, C14, C16, C17,
C18, C19, C29, C31,
C36, C37, C41, C45,
C49, C61, C69, C70,
C72, C73, C75, C93,
C108, C109, C1101
C981
ADT1-1WT
SV-100-3
SOT223HS
SOT223HS
TSSOP64
SOIC16PW
402
TAJD
402
CP-002A-ND
TSW-120-08-L-DRA
P3.74KLCT-ND
P49.9LCT-ND
P0.0JCT-ND
P1.0KLCT-ND
P33JCT-ND
742C163220JCTND
ADT1-1WT
AD9445BSVZ-100
ADP3338-5
Capacitor
805
10 μF
Digi-Key Corporation
490-1717-1-ND
Rev. 0 | Page 34 of 36
10 nH
3.74 kΩ
50 Ω
0Ω
1 kΩ
33 Ω
22 Ω
Digi-Key Corporation
Digi-Key Corporation
Digi-Key Corporation
Digi-Key Corporation
Digi-Key Corporation
Digi-Key Corporation
AD9446
Item
30
31
32
Qty.
33
34
35
36
37
38
2
3
1
4
2
2
1
Reference
Designator
E151
J51
P61
Description
Header
SMA
Header
Package
EHOLE
SMA
C40MS
Value
R1, R21
R5, R7, R91
U21
H1, H2, H3, H41
T1, T21
P21, P221
BRES402
BRES402
ECLOSC
MTHOLE6
Balun transformer
Term strip
402
402
DIP4(14)
MTHOLE6
SM-22
PTMICRO4
XX
XX
Parts not populated.
Rev. 0 | Page 35 of 36
Manufacturer
Mouser Electronics
Digi-Key Corporation
Samtec, Inc.
Mfg. Part No.
517-6111TG
ARFX1231-ND
TSW-120-08-L-DRA
M/A-COM
Newark Electronics
ETC1-1-13
AD9446
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
EXPOSED
PAD
TOP VIEW
(PINS DOWN)
9.50 SQ
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
50
25
26
49
BOTTOM VIEW
(PINS UP)
51
26
0.50 BSC
LEAD PITCH
VIEW A
25
50
0.27
0.22
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 65. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9446BSVZ-80 1
AD9446BSVZ-1001
AD9446-100LVDS/PCB
AD9446-80LVDS/PCB
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
100-Lead TQFP_EP
100-Lead TQFP_EP
AD9446-100 LVDS Mode Evaluation Board
AD9446-80 LVDS Mode Evaluation Board
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05490–0–10/05(0)
Rev. 0 | Page 36 of 36
Package Option
SV-100-3
SV-100-3