19-2396; Rev 0; 4/02 Quad Bus LVDS Transceiver in 44 QFN ♦ 1ns (min) Driver Transition Time (0% to 100%) Minimizes Reflections ♦ Guaranteed 7.3pF (max) Bus Load Capacitance ♦ Glitch-Free Power-Up and Power-Down ♦ Hot-Swappable, High-Impedance I/O with VCC = 0V or Open ♦ Guaranteed 200Mbps Driver Data Rate ♦ Low-Jitter Fail-Safe Circuit ♦ Flow-Through Pinout Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9158EGM -40°C to +85°C 44 QFN (7mm ✕ 7mm) DIN1 35 36 37 38 39 RO3 DIN3 GND RO2 DIN2 RO1 41 40 RO4 DIN4 42 N.C. 32 4 31 AVCC DE34 AGND AVCC 7 30 6 29 MAX9158EGM 28 25 11 24 12 23 N.C. N.C. N.C. GND VCC RE12 GND AVCC DE12 AGND N.C. N.C. DO1-/RIN1DO1+/RIN1+ AVCC 22 26 10 21 27 9 20 8 19 N.C. N.C. 5 18 Multipoint Buses 3 17 DSLAMs 33 16 Network Switches/Routers 34 2 15 Digital Cross-Connects Cellular Phone Base Stations 1 14 Add/Drop Muxes N.C. N.C. VCC GND RE34 VCC 13 Applications 43 TOP VIEW (LEADS UNDER PACKAGE) 44 Pin Configuration DO4-/RIN4- The MAX9158 is offered in a 7mm ✕ 7mm 44-lead QFN package, and is fully specified for the -40°C to +85°C extended temperature range. Refer to the MAX9157 data sheet for a quad BLVDS transceiver with hysteresis in 32lead QFN and TQFP packages. Refer to the MAX9129 data sheet for a quad BLVDS driver, ideal for dual multipoint full-duplex buses. ♦ 44-Lead QFN Package DO4+/RIN4+ DO3-/RIN3DO3+/RIN3+ AGND DO2-/RIN2DO2+/RIN2+ The MAX9158’s high-impedance I/Os (except for receiver outputs) when VCC = 0V or open, combined with glitchfree power-up and power-down, allow hot swapping of cards in multicard bus systems; 7.3pF (max) BLVDS I/O capacitance minimizes bus loading. Features QFN Functional Diagram appears at end of data sheet. Typical Operating Circuit MAX9158 MAX9158 MAX9158 CARD 1 CARD 15 CARD 16 1in CARD SPACING Rt = 54Ω Rt = 54Ω ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9158 General Description The MAX9158 is a quad bus LVDS (BLVDS) transceiver for heavily loaded, half-duplex multipoint buses. A 44lead QFN package and flow-through pinout allow the transceiver to be placed near the connector. The MAX9158 drives LVDS levels into a 27Ω load (double terminated, heavily loaded LVDS bus) at up to 200Mbps. An input fail-safe circuit ensures the receiver output is high when the differential inputs are open, or undriven and shorted, or undriven and terminated. The MAX9158 operates from a single 3.3V supply, consuming 77mA supply current with drivers enabled, and 19.9mA with drivers disabled. MAX9158 Quad Bus LVDS Transceiver in 44 QFN ABSOLUTE MAXIMUM RATINGS VCC, AVCC to GND................................................-0.3V to +4.0V DO_+/RIN_+, DO_-/RIN_- to GND ........................-0.3V to +4.0V DIN_, DE_, RE_ to GND.........................................-0.3V to +4.0V RO_ to GND................................................-0.3V to (VCC + 0.3V) AGND to GND .......................................................-0.3V to +0.3V Short-Circuit Duration (DO_+/RIN_+, DO_-/RIN_-) ....Continuous Continuous Power Dissipation (TA = +70°C) 44-Lead QFN (derate 24.3mW/°C above +70°C) ......2105mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C ESD Protection Human Body Model (DO_+/RIN_+, DO_-/RIN_-).............±4kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, RL = 27Ω ±1%, receiver differential input voltage |VID| = 0.1V to 3.0V, receiver input common-mode voltage VCM = 0.05V to 2.4V, receiver input voltage range = 0V to 3.0V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.0 100 mV BLVDS (DO_+/RIN_+, DO_-/RIN_-) Differential Input High Threshold VTH DE_ = low Differential Input Low Threshold VTL DE_ = low -100 -4.3 0.1V ≤VID≤ 0.6V, DE_ = low -15 ±1.7 +15 0.6V <VID≤ 1.2V, DE_ = low -20 ±2.3 +20 Input Current Input Resistance RIN1 VCC = 3.6V, 0V or open, Figure 1 53 RIN2 VCC = 3.6V, 0V or open, Figure 1 148 µA kΩ Power-Off Input Current IINO+, IINO- 0.1V ≤VID≤ 0.6V, VCC = 0V or open -15 ±0.9 +15 0.6V <VID≤ 1.2V, VCC = 0V or open -20 ±1.9 +20 Differential Output Voltage VOD Figure 2 250 398 460 mV Change in Magnitude of VOD for Complementary Output States ∆VOD Figure 2 1 25 mV 1.274 1.435 V 1.9 25 mV 1.473 1.650 V Offset Voltage VOS Figure 2 Change in Magnitude of VOS for Complementary Output States ∆VOS Figure 2 Output High Voltage VOH Figure 2 Output Low Voltage VOL Figure 2 Output Short-Circuit Current 2 IIN+, IIN- mV IOS 1.185 0.950 DIN_ = high, DO_+/RIN_+ = 0V or VCC, DO_-/RIN_- = 0V or VCC -30 DIN_ = low, DO_-/RIN_- = 0V or VCC, DO_+/RIN_+ = 0V or VCC -30 1.075 µA V +30 mA _______________________________________________________________________________________ +30 Quad Bus LVDS Transceiver in 44 QFN (VCC = 3.0V to 3.6V, RL = 27Ω ±1%, receiver differential input voltage |VID| = 0V.1V to 3.0V, receiver input common-mode voltage VCM = 0.05V to 2.4V, receiver input voltage range = 0V to 3.0V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 1 and 2) PARAMETER Differential Output Short-Circuit Current Magnitude (Note 3) Capacitance at Bus Pins (Note 3) SYMBOL IOSD COUTPUT CONDITIONS MIN DIN_ = high or low, VOD = 0V TYP MAX UNITS 14.8 30 mA 7.3 pF Capacitance from DO_+/RIN_+ or DO_-/RIN_- to GND, VCC = 3.6V or 0V LVCMOS/LVTTL OUTPUTS (RO_) Output High Voltage Output Low Voltage VOH VOL IOH = -4.0mA, DE_ = low Open, undriven short, or undriven 27Ω parallel termination VCC 0.3 VCC 0.138 VID = 100mV VCC 0.3 VCC 0.138 IOL = 4.0mA, VID = -100mV, DE_ = low 0.176 0.25 VID = 100mV, VRO_ = VCC - 1.0V, DE_ = low -15 -25.8 -40 VID = -100mV, VRO_ = 1.0V, DE_ = low 12 20.7 40 -45 -130 mA 0.1 +10 µA 4.6 pF Dynamic Output Current IOD Output Short-Circuit Current (Note 4) IOS VID = 100mV, VRO_ = 0V, DE_ = low Output High-Impedance Current IOZ RE_ = high, VRO = 0V or VCC Capacitance at Receiver Output (Note 3) COUTPUT V -10 Capacitance from RO_ to GND, VCC = 3.6V or 0V V mA LVCMOS/LVTTL INPUTS (DIN, DE, RE) Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL GND 0.8 V Input Current IIN VDE_, VRE_, VDIN_ = high or low -20 +20 µA IINO VDE_, VRE_, VDIN_ = 3.6V or 0V, VCC = 0V or open -20 +20 µA ICC DE_ = high, RE_ = low, RL = 27Ω 77 95 mA Supply Current Drivers Enabled and Receivers Disabled ICCD DE_ = high, RE_ = high, RL = 27Ω 77 95 mA Supply Current Drivers Disabled and Receivers Enabled ICCR DE_ = low, RE_ = low 19.9 30 mA Supply Current Drivers Disabled and Receivers Disabled ICCZ DE_ = low, RE_ = high 19.9 30 mA Power-Off Input Current SUPPLY Supply Current Drivers and Receivers Enabled _______________________________________________________________________________________ 3 MAX9158 DC ELECTRICAL CHARACTERISTICS (continued) MAX9158 Quad Bus LVDS Transceiver in 44 QFN AC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, RL = 27Ω ±1%, receiver differential input voltage |VID| = 0.15V to VCC, receiver input voltage range = 0V to VCC, input frequency to differential inputs = 100MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0V to VCC with 2ns (10% to 90%) transition times. Differential input voltage transition time = 1ns (20% to 80%). Receiver input common-mode voltage VCM = 0.075V to 2.4V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRIVER Differential Propagation Delay High to Low tPHLD RE_ = high, CL = 10pF, Figures 3, 4 1.2 1.96 2.5 ns Differential Propagation Delay Low to High tPLHD RE_ = high, CL = 10pF, Figures 3, 4 1.1 1.87 2.4 ns Differential Skew | tPHLD - tPLHD | (Note 6) tSKD1 RE_ = high, CL = 10pF, Figures 3, 4 91 250 ps Channel-to-Channel Skew (Note 7) tCCSK RE_ = high, CL = 10pF, Figures 3, 4 119 350 ps Chip-to-Chip Skew (Note 8) tSKD2 RE_ = high, CL = 10pF, Figures 3, 4 0.45 0.90 ns Chip-to-Chip Skew (Note 9) TSKD3 RE_ = high, CL = 10pF, Figures 3, 4 1.4 ns Rise Time tTLH RE_ = high, CL = 10pF, Figures 3, 4 0.6 1.07 1.4 ns Fall Time tTHL RE_ = high, CL = 10pF, Figures 3, 4 0.6 1.10 1.4 ns Disable Time High to Z tPHZ RE_ = high, CL = 10pF, Figures 5, 6 2.8 5 ns Disable Time Low to Z tPLZ RE_ = high, CL = 10pF, Figures 5, 6 2.8 5 ns Enable Time Z to High tPZH RE_ = high, CL = 10pF, Figures 5, 6 4.6 6 ns Enable Time Z to Low tPZL RE_ = high, CL = 10pF, Figures 5, 6 4.5 6 ns Maximum Operating Frequency (Note 10) fMAX RE_ = high, CL = 10pF, Figures 5, 6 Differential Propagation Delay High to Low tPHLD DE_ = low, Figures 7, 8; CL = 15pF 1.5 2.21 3.5 ns Differential Propagation Delay Low to High tPLHD DE_ = low, Figures 7, 8; CL = 15pF 1.5 2.13 3.5 ns Differential Skew | tPHLD tPLHD | (Note 6) tSKD1 DE_ = low, Figures 7, 8; CL = 15pF 74 250 ps Channel-to-Channel Skew (Note 7) tCCSK DE_ = low, Figures 7, 8; CL = 15pF 96 350 ps Chip-to-Chip Skew (Note 8) tSKD2 DE_ = low, Figures 7, 8; CL = 15pF 0.63 1.6 ns Chip-to-Chip Skew (Note 9) tSKD3 DE_ = low, Figures 7, 8; CL = 15pF 2.0 ns tTLH DE_ = low, Figures 7, 8; CL = 15pF 1.6 ns 100 MHz RECEIVER Rise Time 4 0.5 1.09 _______________________________________________________________________________________ Quad Bus LVDS Transceiver in 44 QFN (VCC = 3.0V to 3.6V, RL = 27Ω ±1%, receiver differential input voltage |VID| = 0.15V to VCC, receiver input voltage range = 0V to VCC, input frequency to differential inputs = 100MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0V to VCC with 2ns (10% to 90%) transition times. Differential input voltage transition time = 1ns (20% to 80%). Receiver input common-mode voltage VCM = 0.075V to 2.4V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.7 1.24 1.8 ns DE_ = low, RL = 500Ω, CL = 15pF, Figures 9, 10 6.0 8 ns tPLZ DE_ = low, RL = 500Ω, CL = 15pF, Figures 9, 10 6.5 8 ns Enable Time Z to High tPZH DE_ = low, RL = 500Ω, CL = 15pF, Figures 9, 10 4.3 7 ns Enable Time Z to Low tPZL DE_ = low, RL = 500Ω, CL = 15pF, Figures 9, 10 4.3 7 ns Maximum Operating Frequency (Note 10) fMAX DE_ = low, CL = 15pF Fall Time tTHL DE_ = low, Figures 7, 8, CL = 15pF Disable Time High to Z tPHZ Disable Time Low to Z 100 MHz Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and ∆VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: Guaranteed by design and characterization. Note 4: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 5: CL includes scope probe and test fixture capacitance. Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |. Note 7: tCCSK is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 8: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5°C of each other. Note 9: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 10: Meets data sheet specifications while operating at minimum fMAX rating. _______________________________________________________________________________________ 5 MAX9158 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = 3.3V, RL = 27Ω, driver CL = 10pF, receiver CL = 15pF, |VID| = 200mV, VCM = 1.2V, fIN = 20MHz, TA = +25°C, unless otherwise noted.) 86 VCC = 3.3V 81 76 VCC = 3.0V 0.399 0.398 0.397 0.1 1 10 100 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 3.0 1000 3.1 3.2 3.3 3.4 3.5 15 3.6 45 DRIVER TRANSITION TIME vs. LOAD CAPACITANCE tTHL tTLH MAX9158 toc05 1.3 DRIVER TRANSITION TIME (ns) 1.2 1.1 105 DRIVER TRANSITION TIME vs. TEMPERATURE MAX9158 toc04 1.3 75 OUTPUT LOAD (Ω) SUPPLY VOLTAGE (V) FREQUENCY (MHz) DRIVER TRANSITION TIME (ns) 1.8 0.2 0.396 71 0.01 MAX9158 toc03 0.400 2.0 DIFFERENTIAL OUTPUT VOLTAGE (V) VCC = 3.6V MAX9158 toc02 96 DIFFERENTIAL OUTPUT VOLTAGE (V) FOUR CHANNELS DRIVEN 91 0.401 MAX9158 toc01 101 DIFFERENTIAL OUTPUT VOLTAGE vs. OUTPUT LOAD DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. FREQUENCY SUPPLY CURRENT (mA) 1.2 tTHL 1.1 tTLH 1.0 0.9 0.8 1.0 0.7 5 10 15 20 25 -15 10 35 60 TEMPERATURE (°C) DRIVER TRANSITION TIME vs. SUPPLY VOLTAGE RECEIVER TRANSITION TIME vs. LOAD CAPACITANCE 1.10 tTLH 1.05 1.00 85 MAX9158 toc07 tTHL 3.0 RECEIVER TRANSITION TIME (ns) MAX9158 toc06 1.15 0.95 2.5 tTHL 2.0 1.5 tTLH 1.0 0.5 0.90 0 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 6 -40 LOAD CAPACITANCE (pF) 1.20 DRIVER TRANSITION TIME (ns) MAX9158 Quad Bus LVDS Transceiver in 44 QFN 3.5 3.6 5 10 15 20 25 LOAD CAPACITANCE (pF) _______________________________________________________________________________________ 30 135 Quad Bus LVDS Transceiver in 44 QFN PIN NAME 1, 2, 11, 12, 23, 24, 32, 33, 34, 44 N.C. No Connection. Not internally connected. 3, 6, 30 VCC Digital Power Supply 4, 28, 31, 39 GND Digital Ground 5 RE34 Receiver Channels 3 and 4 Enable (Enable Low). Drive RE34 low to enable receiver channels 3 and 4. Internal pullup to VCC. 7, 10, 22, 27 AVCC Analog Power Supply. Connect to board VCC. DE34 Driver Channels 3 and 4 Enable (Enable High). Drive DE34 high to enable driver channels 3 and 4. Internal pullup to VCC. 8 9, 17, 25 AGND 13 DO4-/RIN4- 14 DO4+/RIN4+ FUNCTION Analog Ground. Connect to board ground. Channel 4 Inverting BLVDS Input/Output Channel 4 Noninverting BLVDS Input/Output 15 DO3-/RIN3- 16 DO3+/RIN3+ Channel 3 Inverting BLVDS Input/Output 18 DO2-/RIN2- 19 DO2+/RIN2+ 20 DO1-/RIN1- 21 DO1+/RIN1+ 26 DE12 Driver Channels 1 and 2 Enable (Enable High). Drive DE12 high to enable driver channels 1 and 2. Internal pullup to VCC. 29 RE12 Receiver Channels 1 and 2 Enable (Enable Low). Drive RE12 low to enable receiver channels 1 and 2. Internal pullup to VCC. 35 DIN1 Driver Channel 1 Input 36 RO1 Receiver Channel 1 Output 37 DIN2 Driver Channel 2 Input Channel 3 Noninverting BLVDS Input/Output Channel 2 Inverting BLVDS Input/Output Channel 2 Noninverting BLVDS Input/Output Channel 1 Inverting BLVDS Input/Output Channel 1 Noninverting BLVDS Input/Output 38 RO2 Receiver Channel 2 Output 40 DIN3 Driver Channel 3 Input 41 RO3 Receiver Channel 3 Output 42 DIN4 Driver Channel 4 Input 43 RO4 Receiver Channel 4 Output EP EXPOSED PAD Exposed Pad. Solder exposed pad to GND. _______________________________________________________________________________________ 7 MAX9158 Pin Description MAX9158 Quad Bus LVDS Transceiver in 44 QFN Detailed Description The MAX9158 is a four-channel, 200Mbps, 3.3V BLVDS transceiver in a 44-lead QFN package, ideal for driving heavily loaded multipoint buses, typically 16 to 20 cards plugged into a backplane. The MAX9158 receivers accept a differential input and have a fail-safe input circuit. The devices detect differential signals as low as 100mV and as high as VCC. The MAX9158 driver outputs use a current-steering configuration to generate a 9.25mA to 17mA output current. This current-steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The outputs are short-circuit current limited. The MAX9158 current-steering output requires a resistive load to terminate the signal and complete the transmission loop. Because the devices switch the direction of current flow and not voltage levels, the output voltage swing is determined by the value of the termination resistor multiplied by the output current. With a typical 14.75mA output current, the MAX9158 produces a 398mV output voltage when driving a bus terminated with two 54Ω resistors (14.75mA ✕ 27Ω = 398mV). Logic states are determined by the direction of current flow through the termination resistor. Fail-Safe Receiver Inputs The fail-safe feature of the MAX9158 sets the receiver output high when the receiver differential input is: • Open Effect of Capacitive Loading The characteristic impedance of a differential PC board trace is uniformly reduced when equal capacitive loads are attached at equal intervals (provided the transition time of the signal being driven on the trace is longer than the delay between loads). This kind of loading is typical of multipoint buses where cards are attached at 1in or 0.8in intervals along the length of a backplane. The reduction in characteristic impedance is approximated by the following formula: ZDIFF-loaded = ZDIFF-unloaded ✕ SQRT [Co / (Co + N ✕ CL / L)] where: ZDIFF-unloaded = unloaded differential characteristic impedance Co = unloaded trace capacitance (pF/unit length) CL = value of each capacitive load (pF) N = number of capacitive loads L = trace length For example, if Co = 2.5pF/in, CL = 10pF, N = 18, L = 18in, and ZDIFF-unloaded = 120Ω, the loaded differential impedance is: ZDIFF-loaded = 120Ω ✕ SQRT [2.5pF / (2.5pF + 18 x 10pF / 18in)] ZDIFF-loaded = 54Ω In this example, capacitive loading reduces the characteristic impedance from 120Ω to 54Ω. The load seen by • Undriven and shorted • Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the output and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver is in high impedance. A shorted input can occur because of a cable failure. When the input is driven with a differential signal with a common-mode voltage of 0.05V to 2.4V, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and parallel terminated, an internal resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high (Figure 1). VCC RIN2 VCC - 0.3V DO_+/RIN_+ RIN1 RO_ RIN1 D0_-/RIN_- MAX9158 Figure 1. Internal Fail-Safe Circuit 8 _______________________________________________________________________________________ Quad Bus LVDS Transceiver in 44 QFN The MAX9158 driver outputs are current-source drivers and drive larger differential signal levels into loads lighter than 27Ω and smaller levels into loads heavier than 27Ω (see Typical Operating Characteristics curves). To keep loading from reducing bus impedance below the rated 27Ω load, PC board traces can be designed for higher unloaded characteristic impedance. Effect of Transition Times For transition times (measured from 0% to 100%) shorter than the delay between capacitive loads, the loads are seen as low-impedance discontinuities from which the driven signal is reflected. Reflections add and subtract from the signal being driven, causing jitter and decreased noise margin. The MAX9158 output drivers are designed for a minimum transition time of 1ns (rated 0.6ns from 20% to 80%, or 1ns from 0% to 100%) to reduce reflections while being fast enough for high-speed backplane data transmission. Power-On Reset The power-on reset voltage of the MAX9158 is typically 2.25V. When the supply falls below this voltage, the devices are disabled and the receiver inputs/driver outputs are in high impedance. The power-on reset ensures glitch-free power-up and power-down, allowing hot swapping of cards in a multicard bus system without disrupting communications. Operating Modes The MAX9158 features driver/receiver enable inputs that select the bus I/O function (Table 1). Tables 2 and 3 show the driver and receiver operating modes. Applications Information Supply Bypassing Bypass each supply pin with high-frequency surfacemount ceramic 0.1µF and 1nF capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the device. Termination In the example given in the Effect of Capacitive Loading section, the loaded differential impedance of a bus is reduced to 54Ω. Since the bus can be driven from any card position, the bus must be terminated at each end. A parallel termination of 54Ω at each end of the bus placed across the traces that make up the differential pair provides a proper termination. The total load seen by the driver is 27Ω. The MAX9158 drives higher differential signal levels into lighter loads. (See the Differential Output Voltage vs. Output Load graph in the Typical Operating Characteristics section.) A multidrop bus with the driver at one end and receivers connected at regular intervals along the bus has a lowered impedance due to capacitive loading. Assuming a 54Ω impedance, the multidrop bus can be terminated with a single, parallel-connected 54Ω resistor at the far end from the driver. Only a single resistor is required because the driver sees one 54Ω differential trace. The signal swing is larger with a 54Ω load. In general, parallel terminate each end of the bus with a resistor matching the differential impedance of the bus (taking into account any reduced impedance due to loading). Table 1. I/O Enable Functional Table DE_ RE_ Driver Mode H H Receiver Mode L L High-Impedance Mode L H Loopback Mode H L MODE SELECTED Table 2. Driver Mode INPUTS OUTPUTS DE_ DIN_ DO_+/RIN_+ DO_-/RIN_- Input Internal Pullup/Pulldown Resistors H L L H H H H L The MAX9158 includes pullup or pulldown resistors (300kΩ) to ensure that unconnected inputs are defined (Table 4). L X Z Z _______________________________________________________________________________________ 9 MAX9158 a driver located on a card in the middle of the bus is 27Ω because the driver sees two 54Ω loads in parallel. A typical LVDS driver (rated for a 100Ω load) would not develop a large enough differential signal to be reliably detected by an LVDS receiver. The MAX9158 BLVDS drivers are designed and specified to drive a 27Ω load to differential voltage levels of 250mV to 460mV. A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs, contribute to capacitive loading. Keep stubs less than 1in for a good balance between ease of component placement and good signal integrity. Table 3. Receiver Mode OUTPUTS VID = (VDO_+/RIN_+) - (VDO_-/RIN_-) L VID < -100mV L L VID > 100mV H Fail-safe operation guaranteed when DO_+/RIN_+ and DO_-/RIN_- are open, undriven and shorted, or undriven and parallel terminated L H X RO_ Board Layout H Z A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep the LVTTL/LVCMOS and BLVDS signals separated to prevent coupling. Table 4. Input Internal Pullup/Pulldown Resistors D0_+/RIN_+ PIN INTERNAL RESISTOR DE12 Pullup to VCC VCC DE34 Pullup to VCC GND RE12 Pullup to VCC RE34 Pullup to VCC DIN_ None (floating) Traces, Cables, and Connectors RL/2 DIN_ VOS 10 VOD RL/2 DO_-/RIN_- Figure 2. Driver VOD and VOS Test Circuit The characteristics of input and output connections affect the performance of the MAX9158. Use controlledimpedance traces, cables, and connectors with matched characteristic impedance. Ensure that noise couples as common mode by running the traces of a differential pair close together. Reduce within-pair skew by matching the electrical length of the traces of a differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between traces of a differential pair to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. S INPUTS RE_ Avoid the use of unbalanced cables, such as ribbon cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the receiver. VO MAX9158 Quad Bus LVDS Transceiver in 44 QFN CL DO_+/RIN_+ GENERATOR DIN_ RL DO_-/RIN_- 50Ω CL Figure 3. Driver Propagation Delay and Transition Time Test Circuit ______________________________________________________________________________________ Quad Bus LVDS Transceiver in 44 QFN DIN_ 50% tPLHD tPHLD CL 0V DO_+/RIN_+ DO_-/RIN_- VCC VOH 0V DIFFERENTIAL 0V DIN_ RL/2 GND DO_+/RIN_+ VOL DE_ +1.2V GENERATOR 80% 80% 50Ω 0V VOD DO_-/RIN_- 0V VOD = (VDO_+/RIN_+ - VDO_-/RIN_-) 20% RL/2 tTLH 1/4 MAX9158 CL 20% tTHL Figure 5. Driver High-Impedance Delay Test Circuit Figure 4. Driver Propagation Delay and Transition Time Waveforms VCC DE_ 50% 50% 0V tPZH tPHZ D0_+/RIN_+ WHEN DIN_ = VCC DO_-/RIN_- WHEN DIN_ = 0V VOH 50% 50% 1.2V 1.2V 50% DO_+/RIN_+ WHEN DIN_ = 0V DO_-/RIN_- WHEN DIN_ = VCC 50% VOL tPZL tPLZ Figure 6. Driver High-Impedance Delay Waveform DO_+/RIN_+ PULSE GENERATOR RO_ DO_-/RIN_- 50Ω* 50Ω* CL RECEIVER ENABLED 1/4 MAX9158 *50Ω REQUIRED FOR PULSE GENERATOR TERMINATION. Figure 7. Receiver Transition Time and Propagation Delay Test Circuit ______________________________________________________________________________________ 11 MAX9158 VCC 50% MAX9158 Quad Bus LVDS Transceiver in 44 QFN DO_-/RIN_VID 0V (DIFFERENTIAL) 0V (DIFFERENTIAL) DO_+/RIN_+ tPLHD tPHLD VOH 80% 80% 50% 50% 20% 20% RO_ tTLH VOL tTHL Figure 8. Receiver Transition Time and Propagation Delay Timing Diagram VCC S1 RL DO_+/RIN_+ RO_ DO_-/RIN_GENERATOR CL RE_ 50Ω 1/4 MAX9158 CL INCLUDES LOAD AND TEST FIXTURE CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS. Figure 9. Receiver High-Impedance Delay Test Circuit VCC 50% 50% 0V RE_ tPZL VCC tPLZ RO_ WHEN VID = -100mV RO_ WHEN VID = +100mV 50% 0.5V VOL tPZH tPHZ VOH 0.5V 50% GND Figure 10. Receiver High-Impedance Waveforms 12 ______________________________________________________________________________________ Quad Bus LVDS Transceiver in 44 QFN DO1+/RIN1+ Chip Information TRANSISTOR COUNT: 1796 PROCESS: CMOS DIN1 DO1-/RIN1- DE12 RO1 RE12 DO2+/RIN2+ DIN2 DO2-/RIN2RO2 DO3+/RIN3+ DIN3 DO3-/RIN3- DE34 RO3 RE34 DO4+/RIN4+ DIN4 DO4-/RIN4RO4 MAX9158 ______________________________________________________________________________________ 13 MAX9158 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32, 44, 48L QFN .EPS MAX9158 Quad Bus LVDS Transceiver in 44 QFN D2 D CL D/2 b D2/2 k E/2 E2/2 E CL (NE-1) X e E2 k L DETAIL A e (ND-1) X e CL CL L L e A1 A2 e A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 14 ______________________________________________________________________________________ REV. A 1 2 Quad Bus LVDS Transceiver in 44 QFN COMMON DIMENSIONS EXPOSED PAD VARIATIONS ** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV. A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9158 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)