a FEATURES Recovers Signal from +100 dB Noise 2 MHz Channel Bandwidth 45 V/s Slew Rate –120 dB Crosstalk @ 1 kHz Pin Programmable Closed Loop Gains of ⴞ1 and ⴞ2 0.05% Closed Loop Gain Accuracy and Match 100 V Channel Offset Voltage (AD630BD) 350 kHz Full Power Bandwidth Chips Available Balanced Modulator/Demodulator AD630 FUNCTIONAL BLOCK DIAGRAM CM OFF ADJ CM OFF ADJ DIFF OFF ADJ DIFF OFF ADJ 5 4 3 6 2.5k⍀ RINA 1 AD630 AMP A CHA+ 2 CHA– 20 A 12 COMP 11 +VS 13 VOUT 14 RB 15 RF 16 RA 2.5k⍀ RINB 17 AMP B B 10k⍀ CHB+ 18 10k⍀ –V CHB– 19 5k⍀ PRODUCT DESCRIPTION The AD630 is a high precision balanced modulator which combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin-film resistors. Its signal processing applications include balanced modulation and demodulation, synchronous detection, phase detection, quadrature detection, phase sensitive detection, lock-in amplification and square wave multiplication. A network of on-board applications resistors provides precision closed loop gains of ± 1 and ± 2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of +1, +2, +3 or +4. Alternatively, external feedback may be employed allowing the designer to implement his own high gain or complex switched feedback topologies. The AD630 may be thought of as a precision op amp with two independent differential input stages and a precision comparator which is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. In addition, the AD630 has extremely low crosstalk between channels of –100 dB @ 10 kHz. The AD630 is intended for use in precision signal processing and instrumentation applications requiring wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, it can recover a small signal from 100 dB of interfering noise (see lock-in amplifier application). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz. Other features of the AD630 include pin programmable frequency compensation, optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output which indicates which of the two differential inputs is active. This device is now available to Standard Military Drawing (DESC) numbers 5962-8980701RA and 5962-89807012A. COMP 7 SEL B 9 CHANNEL STATUS B/A SEL A 10 8 –VS PRODUCT HIGHLIGHTS 1. The configuration of the AD630 makes it ideal for signal processing applications such as: balanced modulation and demodulation, lock-in amplification, phase detection, and square wave multiplication. 2. The application flexibility of the AD630 makes it the best choice for many applications requiring precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high-speed precision amplification. 3. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. 4. The op-amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. 5. The AD630 can be used as a two channel multiplexer with gains of +1, +2, +3 or +4. The channel separation of 100 dB @ 10 kHz approaches the limit which is achievable with an empty IC package. 6. The AD630 has pin-strappable frequency compensation (no external capacitor required) for stable operation at unity gain without sacrificing dynamic performance at higher gains. 7. Laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD630–SPECIFICATIONS (@ + 25ⴗC and ⴞV = ⴞ15 V unless otherwise noted) S Model Min GAIN Open Loop Gain ± 1, ± 2 Closed Loop Gain Error Closed Loop Gain Match Closed Loop Gain Drift CHANNEL INPUTS VIN Operational Limit1 Input Offset Voltage Input Offset Voltage TMIN to TMAX Input Bias Current Input Offset Current Channel Separation @ 10 kHz COMPARATOR VIN Operational Limit1 Switching Window Switching Window TMIN to TMAX2 Input Bias Current Response Time (–5 mV to +5 mV Step) Channel Status ISINK @ VOL = –VS + 0.4 V3 Pull-Up Voltage AD630J/A Typ Max 90 110 0.1 0.1 2 100 100 10 100 120 800 300 50 100 10 100 ⴞ2.0 300 100 200 OUTPUT VOLTAGE, @ RL = 2 kΩ TMIN to TMAX2 Output Short Circuit Current ⴞ10 160 300 50 ⴞ2.0 300 100 200 90 90 ⴞ5 ± 16.5 5 110 110 4 ± 16.5 5 ⴞ10 25 0 –25 ⴞ2.5 300 (–VS + 33 V) 90 90 ⴞ5 Volts mV mV nA ns mA Volts 110 110 dB dB Volts mA ± 16.5 5 Volts mA 25 +70 +85 µV nA nA dB MHz V/µs µs ± 10 0 –25 Volts µV 2 45 3 4 25 +70 +85 1000 300 50 1.6 2 45 3 Unit dB % % ppm/°C (–VS + 3 V) to (+VS – 1.3 V) ⴞ1.5 (–VS + 33 V) 105 110 4 110 0.1 0.1 2 100 10 100 1.6 2 45 3 Max (–VS + 4 V) to (+VS – 1 V) 500 (–VS + 3 V) to (+VS – 1.5 V) ⴞ1.5 (–VS + 33 V) 85 90 ⴞ5 AD630S Typ 90 (–VS + 4 V) to (+VS – 1 V) 100 1.6 OPERATING CHARACTERISTICS Common-Mode Rejection Power Supply Rejection Supply Voltage Range Supply Current Min 2 (–VS + 3 V) to (+VS – 1.5 V) ⴞ1.5 100 200 AD630K/B Typ Max 0.05 0.05 (–VS + 4 V) to (+VS – 1 V) 500 DYNAMIC PERFORMANCE Unity Gain Bandwidth Slew Rate4 Settling Time to 0.1% (20 V Step) TEMPERATURE RANGES Rated Performance–N Package Rated Performance–D Package Min N/A –55 +125 °C °C NOTES 1 If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. 2 These parameters are guaranteed but not tested for J and K grades. For A, B and S grades they are tested. 3 ISINK @ VOL = (–VS + 1) volt is typically 4 mA. 4 Pin 12 Open. Slew rate with Pins 12 and 13 shorted is typically 35 V/ µs. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 600 mW Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite Storage Temperature, Ceramic Package . . . . –65°C to +150°C Storage Temperature, Plastic Package . . . . . . –55°C to +125°C Lead Temperature Range (Soldering, 10 sec ) . . . . . . . +300°C Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C THERMAL CHARACTERISTICS 20-Pin Plastic DIP (N) 20-Pin Ceramic DIP (D) 20-Pin Leadless Chip Carrier (E) θJC θJA 24°C/W 35°C/W 35°C/W 61°C/W 120°C/W 120°C/W –2– Model Temperature Ranges Package Descriptions Package Options AD630JN AD630KN AD630AD AD630BD AD630SD AD630SD/883B 5962-8980701RA AD630SE/883B 5962-89807012A AD630JCHIPS AD630SCHIPS 0°C to +70°C 0°C to +70°C –25°C to +85°C –25°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C 0°C to +70°C –55°C to +125°C Plastic DIP Plastic DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP LCC LCC Chip Chip N-20 N-20 D-20 D-20 D-20 D-20 D-20 E-20A E-20A REV. C AD630 CHIP METALIZATION AND PINOUT PIN CONFIGURATIONS Dimensions shown in inches and (mm). Contact factory for latest dimensions 20-Lead DIP (D-20 and N-20) RINA 1 20 CH A– CH A+ 2 19 CH B– DIFF OFF ADJ 3 18 CH B+ DIFF OFF ADJ 4 17 RIN B AD630 CM OFF ADJ 5 16 RA TOP VIEW CM OFF ADJ 6 (Not to Scale) 15 RF 14 RB CHANNEL STATUS B/A 7 –VS 8 13 VOUT SEL B 9 12 COMP SEL A 10 11 +VS CHIP AVAILABILITY CH B– CH A+ 3 2 RIN A CH A– DIFF OFF ADJ 20-Contact LCC (E-20A) 1 20 19 DIFF OFF ADJ 4 The AD630 is available in laser trimmed, passivated chip form. The figure shows the AD630 metalization pattern, bonding pads and dimensions. AD630 chips are available; consult factory for details. 18 CH B+ CM OFF ADJ 5 AD630 CM OFF ADJ 6 TOP VIEW (Not to Scale) CHANNEL STATUS B/A 7 17 RIN B 16 RA 15 RF 14 RB –VS 8 15 15 18 10 Vi 5k⍀ 5k⍀ VO 5 2k⍀ 100pF CL = 100pF f = 1kHz 10 5k⍀ 5k⍀ Vi 5 VO RL CAP IN 1k 10k 1 1M 100k 10 FREQUENCY – Hz 100 1k 10k 100k RESISTIVE LOAD – ⍀ 100pF 120 5k⍀ 5k⍀ Vi VO 2k⍀ 100pF 10 5 f = 1kHz CL = 100pF 0 1M Figure 2. Output Voltage vs. Resistive Load Figure 1. Output Voltage vs. Frequency 5 10 15 SUPPLY VOLTAGE – ⴞV Figure 3. Output Voltage Swing vs. Supply Voltage 120 60 0 80 20 0 COMPENSATED dt 60 40 –20 20 –40 0 1 10 100 1k 10k FREQUENCY – Hz 100k Figure 4. Common-Mode Rejection vs. Frequency REV. C 100 OPEN LOOP GAIN – dB 40 – V/s 100 –60 –5 –4 –3 Figure 5. UNCOMPENSATED 45 80 90 60 40 COMPENSATED 135 20 0 2 3 –2 –1 0 1 INPUT VOLTAGE – V 4 5 dVO vs. Input Voltage dt –3– 10 100 1k 10k 100k FREQUENCY – Hz 1M Figure 6. Gain and Phase vs. Frequency 180 10M OPEN LOOP PHASE – Degrees UNCOMPENSATED DVO COMMON MODE REJECTION – dB OUTPUT VOLTAGE – ⴞV RL= 2k⍀ CL = 100pF OUTPUT VOLTAGE – ⴞV OUTPUT VOLTAGE – ⴞV 15 COMP VOUT Typical Performance Characteristics SEL A +VS SEL B 9 10 11 12 13 AD630 –Typical Performance Characteristics 50mV 20mV 50mV/DIV (Vi) 100 90 20mV/DIV (Vo) 20mV/DIV (Vi) 1mV 10V 100 ⴞ10V 20kHz (Vi) 90 1mV/DIV (A) 10V/DIV (Vo) 10 10 0% 100mV/DIV (Vo) 500ns 10k⍀ 2 19 CH B 18 13 VO Vi TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (B) BOTTOM TRACE: Vo 10k⍀ 14 10k⍀ 15 20 12 Vi TOP TRACE 10k⍀ 14 10V 10k⍀ CH A 20 10 0% TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (A) BOTTOM TRACE: Vo 15 5k⍀ 90 500ns 100mV TOP TRACE: Vo BOTTOM TRACE: Vi 16 9 2 CH A 12 VO BOTTOM TRACE 13 Vi TOP TRACE 14 10k⍀ 10k⍀ 1k⍀ MIDDLE TRACE (A) 30pF 15 20 2 CH A 12 VO BOTTOM TRACE 13 10k⍀ 10k⍀ (B) MIDDLE TRACE 10k⍀ HP5082-2811 TEKTRONIX 7A13 10 Figure 7. Channel-to-Channel SwitchSettling Characteristic 5s 1mV/DIV (B) 0% 20mV 1mV 100 Figure 9. Large Signal Inverting Step Response Figure 8. Small Signal Noninverting Step Response TWO WAYS TO LOOK AT THE AD630 The functional block diagram of the AD630 (see page 1) also shows the pin connections of the internal functions. An alternative architectural diagram is shown in Figure 10. In this diagram, the individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This amplifier has two differential input channels, only one of which is active at a time. Vi 2 RA 5k⍀ VO 10 RB 10k⍀ 2.5k⍀ Figure 11. AD630 Symmetric Gain (± 2) RF 10k⍀ A When channel B is selected, the resistors RA and RF are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 12. The amplifier has sufficient loop gain to minimize the loading effect of RB at the virtual ground produced by the feedback connection. When the sign of the comparator input is reversed, input B will be deselected and A will be selected. The new equivalent circuit will be the noninverting gain configuration shown below. In this case RA will appear across the op-amp input terminals, but since the amplifier drives this difference voltage to zero the closed loop gain is unaffected. 13 19 B 12 2.5k⍀ 17 7 SEL B 13 B 9 1 18 18 RF 10k⍀ 14 14 20 A 19 RB 10k⍀ 11 16 2 RA 5k⍀ 15 20 +VS 15 16 B/A 9 SEL A 10 8 –VS Figure 10. Architectural Block Diagram HOW THE AD630 WORKS The two closed loop gain magnitudes will be equal when RF/RA = 1 + RF/RB, which will result from making RA equal to RFRB/ (RF + RB) the parallel equivalent resistance of RF and RB. The basic mode of operation of the AD630 may be more easy to recognize as two fixed gain stages which may be inserted into the signal path under the control of a sensitive voltage comparator. When the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. The AD630 is unique in that it includes Laser-Wafer-Trimmed thinfilm feedback resistors on the monolithic chip. The configuration shown in Figure 11 yields a gain of ±2 and can be easily changed to ±1 by shifting RB from its ground connection to the output. The 5k and the two 10k resistors on the AD630 chip can be used to make a gain of two as shown here. By paralleling the 10k resistors to make RF equal 5k and omitting RB the circuit can be programmed for a gain of ± 1 (as shown in Figure 18a). These and other configurations using the on chip resistors present the inverting inputs with a 2.5k source impedance. The more complete AD630 diagrams show 2.5k resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents. The comparator selects one of the two input stages to complete an operational feedback connection around the AD630. The deselected input is off and has negligible effect on the operation. –4– REV. C AD630 faster the output signal will move. This feature helps insure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations. RF 10k⍀ RA 5k⍀ Vi RB 10k⍀ RF V RA i VO = – The output section of the AD630 includes a current mirror-load (Q24 and Q25), an integrator-voltage gain stage (Q32), and complementary output buffer (Q44 and Q74). The outputs of both transconductance stages are connected in parallel to the current mirror. Since the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. The current mirror translates the differential output current from the active input transconductance amplifier into single ended form for the output integrator. The complementary output driver then buffers the integrator output produce a low impedance output. Figure 12. Inverting Gain Configuration Vi RA 5k⍀ VO = (1+ RF RB ) Vi RF 10k⍀ RB 10k⍀ OTHER GAIN CONFIGURATIONS Many applications require switched gains other than the ± 1 and ± 2 which the self-contained applications resistors provide. The AD630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and RB and RF to give the noninverting gain 1 + RF/RB and subsequent RA to give the desired inverting gain. Note that when the inverting magnitude equals the noninverting magnitude, the value of RA is found to be RB RF/(RB + RF). That is, RA should equal the parallel combination of RB and RF to match positive and negative gain. Figure 13. Noninverting Gain Configuration CIRCUIT DESCRIPTION The simplified schematic of the AD630 is shown in Figure 14. It has been subdivided into three major sections, the comparator, the two input stages and the output integrator. The comparator consists of a front end made up of Q52 and Q53, a flip-flop load formed by Q3 and Q4, and two current steering switching cells Q28, Q29 and Q30, Q31. This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude applied to the comparator inputs will completely select one the switching cells. The sign of this input voltage determine which of the two switching cells is selected. CH A+ CH A– 2 20 +VS CH B+ The feedback synthesis of the AD630 may also include reactive impedance. The gain magnitudes will match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances. Essentially the same considerations apply to the AD630 as to conventional op-amp feedback circuits. Virtually any function which can be realized with simple noninverting “L network” feedback can be used with the AD630. A common arrangement is shown in Figure 15. The low frequency gain of this circuit is 10. The response will have a pole (–3 dB) at a frequency f ⯝ 1/(2 π 100 kΩC) and a zero (3 dB from the high frequency asymptote) at about 10 times this frequency. The 2k resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stability problems, and has a minor effect on the pole-zero locations. CH B– 19 18 11 Q33 Q35 Q34 Q36 i73 i55 Q44 SEL A 10 Q52 Q53 Q62 Q65 Q67 Q70 13 9 C121 SEL B Q30 12 COMP Q31 Q28 C122 Q29 Q24 Q3 –VS VO Q74 Q4 i22 Q32 As a result of the reactive feedback, the high frequency components of the switched input signal will be transmitted at unity gain Q25 i23 C 2k⍀ C 2k⍀ 8 3 4 5 6 DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ 10k⍀ 100k⍀ Vi 2 Figure 14. AD630 Simplified Schematic 20 The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i22 and i23 to the input stage it controls, causing it to become active. The deselected cell blocks the bias to its input stage which, as a consequence, remains off. 11.11k⍀ 13 18 B VO 12 7 9 10 8 The structure of the transconductance stages is such that they present a high impedance at their input terminals and draw no bias current when deselected. The deselected input does not interfere with the operation of the selected input insuring maximum channel separation. –V S Figure 15. AD630 with External Feedback while the low frequency components will be amplified. This arrangement is useful in demodulators and lock-in amplifiers. It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. The output signal will contain the desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain. Another feature of the input structure is that it enhances the slew rate of the circuit. The current output of the active stage follows a quasi-hyperbolic-sine relationship to the differential input voltage. This means that the greater the input voltage, the harder this stage will drive the output integrator, and hence, the REV. C A 19 –5– AD630 because the open collector channel status output inverts the output sense of the internal comparator. SWITCHED INPUT IMPEDANCE The noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration. This means that the input impedance of the circuit undergoes an abrupt change as the gain is switched under control of the comparator. If gain is switched when the input signal is not zero, as it is in many practical cases, a transient will be delivered to the circuitry driving the AD630. In most applications, this will require the AD630 circuit to be driven by a low impedance source which remains “stiff “ at high frequencies. Generally this will be a wideband buffer amplifier. +5V 100k⍀ 1M⍀ 100k⍀ 9 7 10 8 –15V 100⍀ Figure 16. Comparator Hysteresis FREQUENCY COMPENSATION The AD630 combines the convenience of internal frequency compensation with the flexibility of external compensation by means of an optional self-contained compensation capacitor. The channel status output may be interfaced with TTL inputs as shown in Figure 17. This circuit provides appropriate level shifting from the open-collector AD630 channel status output to TTL inputs. In gain of ± 2 applications the noise gain which must be addressed for stability purposes is actually 4. In this circumstance, the phase margin of the loop will be on the order of 60° without the optional compensation. This condition provides the maximum bandwidth and slew-rate for closed-loop gains of |2| and above. +5V +15V 22k⍀ 6.8k⍀ When the AD630 is used as a multiplexer, or in other configurations where one or both inputs are connected for unity gain feedback, the phase margin will be reduced to less than 20°. This may be acceptable in applications where fast slewing is a first priority, but the transient response will not be optimum. For these applications, the self-contained compensation capacitor may be added by connecting Pin 12 to Pin 13. This connection reduces the closed loop bandwidth somewhat, and improves the phase margin. 100k⍀ AD630 IN 914's 7 TTL INPUT 2N2222 8 –15V Figure 17. Channel Status—TTL Interface APPLICATIONS: BALANCED MODULATOR Perhaps the most commonly used configuration of the AD630 is the balanced modulator. The application resistors provide precise symmetric gains of ± 1 and ± 2. The ± 1 arrangement is shown in Figure 18a and the ± 2 arrangement is shown in Figure 18b. These cases differ only in the connection of the 10k feedback resistor (Pin 14) and the compensation capacitor (Pin 12). Note the use of the 2.5 kΩ bias current compensation resistors in these examples. These resistors perform the identical function in the ± 1 gain case. Figure 19 demonstrates the performance of the AD630 when used to modulate a 100 kHz square wave carrier with a 10 kHz sinusoid. The result is the double sideband suppressed carrier waveform. For intermediate conditions, such as gain of ± 1 where loop attenuation is 2, use of the compensation should be determined by whether bandwidth or settling response must be optimized. The optional compensation should also be used when the AD630 is driving capacitive loads or whenever conservative frequency compensation is desired. OFFSET VOLTAGE NULLING The offset voltages of both input stages and the comparator have been pretrimmed so that external trimming will only be required in the most demanding applications. The offset adjustment of the two input channels is accomplished by means of a differential and common-mode scheme. This facilitates fine adjustment of system errors in switched gain applications. With system input tied to 0 V, and a switching or carrier waveform applied to the comparator, a low level square wave will appear at the output. The differential offset adjustment pot can be used to null the amplitude of this square wave (Pins 3 and 4). The common-mode offset adjustment can be used to zero the residual dc output voltage (Pins 5 and 6). These functions should be implemented using 10k trim pots with wipers connected directly to Pin 8 as shown in Figures 18a and 18b. These balanced modulator topologies accept two inputs, a signal (or modulation) input applied to the amplifying channels, and a reference (or carrier) input applied to the comparator. 10k⍀ 6 MODULATION INPUT 10k⍀ CM ADJ DIFF ADJ 4 5 3 2.5k⍀ 1 AMP A 12 A 2 11 20 CHANNEL STATUS OUTPUT 2.5k⍀ 17 The channel status output, Pin 7, is an open collector output referenced to –VS which can be used to indicate which of the two input channels is active. The output will be active (pulled low) when Channel A is selected. This output can also be used to supply positive feedback around the comparator. This produces hysteresis which serves to increase noise immunity. Figure 16 shows an example of how hysteresis may be implemented. Note that the feedback signal is applied to the inverting (–) terminal of the comparator to achieve positive feedback. This is B AMP B 19 CARRIER INPUT 10k⍀ 14 –V 18 +VS 13 10k⍀ AD630 COMP MODULATED OUTPUT SIGNAL 15 16 5k⍀ 7 9 10 8 –VS Figure 18a. AD630 Configured as a Gain-of-One Balanced Modulator –6– REV. C AD630 10k⍀ 6 MODULATION INPUT LVDT SIGNAL CONDITIONER 10k⍀ CM ADJ DIFF ADJ 4 5 Many transducers function by modulating an ac carrier. A Linear Variable Differential Transformer (LVDT) is a transducer of this type. The amplitude of the output signal corresponds to core displacement. Figure 20 shows an accurate synchronous demodulation system which can be used to produce a dc voltage which corresponds to the LVDT core position. The inherent precision and temperature stability of the AD630 reduce demodulator drift to a second order effect. 3 2.5k⍀ 1 AMP A 12 A 2 +VS 11 20 2.5k⍀ 17 B AMP B 19 MODULATED OUTPUT SIGNAL 10k⍀ 14 –V 18 CARRIER INPUT 13 10k⍀ AD630 COMP 15 16 E1000 AD544 SCHAEVITZ AD630 FOLLOWER A LVDT ⴞ2 DEMODULATOR 16 B 5k⍀ 15 10k⍀ 1 2.5k⍀ 5k⍀ 7 9 10 8 2.5kHZ 2V p-p SINUSOIDAL EXCITATION –VS Figure 18b. AD630 Configured as a Gain-of-Two Balanced Modulator 5V 5V 20 10k⍀ 19 14 A C B 17 13 100k⍀ 12 D 1F 2.5k⍀ 9 PHASE SHIFTER 20s MODULATION INPUT 10 Figure 20. LVDT Signal Conditioner AC BRIDGE CARRIER INPUT Bridge circuits which use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pick-up. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low-pass filter. Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter. Figure 21 is an example of an ac bridge system with the AD630 used as a synchronous demodulator. The oscilloscope photograph shows the results of a 0.05% bridge imbalance caused by the 1 Meg resistor in parallel with one leg of the bridge. The top trace represents the bridge excitation, the upper-middle trace is the amplified bridge output, the lower-middle trace is the output of the synchronous demodulator and the bottom trace is the filtered dc system output. This system can easily resolve a 0.5 ppm change in bridge impedance. Such a change will produce a 3.2 mV change in the low-pass filtered dc output, well above the RTO drifts and noise. OUTPUT SIGNAL 10V Figure 19. Gain-of-Two Balanced Modulator Sample Waveforms BALANCED DEMODULATOR The balanced modulator topology described above will also act as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input. The output under these circumstances will be the baseband modulation signal. Higher order carrier components will also be present which can be removed with a low-pass filter. Other names for this function are synchronous demodulation and phase-sensitive detection. PRECISION PHASE COMPARATOR The balanced modulator topologies of Figures 18a and 18b can also be used as precision phase comparators. In this case, an ac waveform of a particular frequency is applied to the signal input and a waveform of the same frequency is applied to the reference input. The dc level of the output (obtained by low-pass filtering) will be proportional to the signal amplitude and phase difference between the input signals. If the signal amplitude is held constant, then the output can be used as a direct indication of the phase. When these input signals are 90° out of phase, they are said to be in quadrature and the AD630 dc output will be zero. 1kHz BRIDGE EXCITATION A AD630 ⴞ2 DEMODULATOR AD524 1k⍀ GAIN 1000 1k⍀ 1k⍀ 16 B 1k⍀ 15 2.5 k⍀ 20 1 10k⍀ A 17 If the input signal is used as its own reference in the balanced modulator topologies, the AD630 will act as a precision rectifier. The high frequency performance will be superior to that which can be achieved with diode feedback and op amps. There are no diode drops which the op amp must “leap over” with the commutating amplifier. PHASE SHIFTER 2.5 k⍀ 13 2 B 1M⍀ PRECISION RECTIFIER-ABSOLUTE VALUE REV. C 5k⍀ 12 FILTER 5k⍀ 5k⍀ 5k⍀ C 10k⍀ 14 9 10 Figure 21. AC Bridge System –7– 2F 2F D 2F 20V 0V BRIDGE EXCITATION (20V/DIV) (A) 100 90 AMPLIFIED BRIDGE OUTPUT (5V/DIV) (B) 0V 0V to Figure 18b and is shown in the upper trace of Figure 24. It is attenuated 100,000 times normalized to the output, B, of the summing amplifier. A noise signal which might represent, for example, background and detector noise in the chopped radiation case, is added to the modulated signal by the summing amplifier. This signal is simply band limited clipped white noise. Figure 24 shows the sum of attenuated signal plus noise in the center trace. This combined signal is demodulated synchronously using phase information derived from the modulator, and the result is low-pass filtered using a 2-pole simple filter which also provides a gain of 100 to the output. This recovered signal is the lower trace of Figure 24. 200s 5V DEMODULATED BRIDGE OUTPUT (5V/DIV) (C) 10 FILTER OUTPUT (2V/DIV) (D) 0% 5V 2V 0V Figure 22. AC Bridge Waveforms The combined modulated signal and interfering noise used for this illustration is similar to the signals often requiring a lock-in amplifier for detection. The precision input performance of the AD630 provides more than 100 dB of signal range and its dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example. A more sophisticated low-pass output filter will aid in rejecting wider bandwidth interference. LOCK-IN AMPLIFIER APPLICATIONS Lock-in amplification is a technique which is used to separate a small, narrow band signal from interfering noise. The lock-in amplifiers acts as a detector and narrow band filter combined. Very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known. The lock-in amplifier is basically a synchronous demodulator followed by a low-pass filter. An important measure of performance in a lock-in amplifier is the dynamic range of its demodulator. The schematic diagram of a demonstration circuit which exhibits the dynamic range of an AD630 as it might be used in a lock-in amplifier is shown in Figure 23. Figure 24 is an oscilloscope photo showing the recovery of a signal modulated at 400 Hz from a noise signal approximately 100,000 times larger; a dynamic range of 100 dB. CLIPPED BAND-LIMITED WHITE NOISE C00784–0–6/00 (rev. C) AD630 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Ceramic DIP (D-20) C B 16 AD542 5k⍀ AD630 15 17 2.5k⍀ 20 19 100R 10k⍀ 1 2.5k⍀ A AD542 13 R B 100R 100dB ATTENUATION 20-Lead Plastic DIP (N-20) 14 10k⍀ C OUTPUT A 10 LOW PASS FILTER 0.1Hz 9 MODULATED CARRIER 400Hz PHASE CARRIER REFERENCE Figure 23. Lock-In Amplifier 5V 5s PRINTED IN U.S.A. 5V MODULATED SIGNAL (A) (UNATTENUATED) 100 90 LCC (E-20A) ATTENUATED SIGNAL PLUS NOISE (B) 10 OUTPUT 0% 5mV 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ Figure 24. Lock-In Amplifier Waveforms The test signal is produced by modulating a 400 Hz carrier with a 0.1 Hz sine wave. The signals produced, for example, by chopped radiation (IR, optical, etc.) detectors may have similar low frequency components. A sinusoidal modulation is used for clarity of illustration. This signal is produced by a circuit similar 0.095 (2.41) 0.075 (1.90) 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 20 1 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) –8– 0.200 (5.08) BSC 0.100 (2.54) BSC A AA A AA A AA 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.055 (1.40) 0.045 (1.14) BOTTOM VIEW 13 9 0.150 (3.81) BSC 0.050 (1.27) BSC 45° TYP REV. C