PD - 91541B
IRLR/U120N
HEXFET® Power MOSFET
l
l
l
l
l
Surface Mount (IRLR120N)
Straight Lead (IRLU120N)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
D
VDSS = 100V
RDS(on) = 0.185Ω
G
Description
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
ID = 10A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
D -P A K
T O -2 52 A A
I-P A K
T O -25 1 A A
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
10
7.0
35
48
0.32
± 16
85
6.0
4.8
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
3.1
50
110
°C/W
1
5/11/98
IRLR/U120N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
100
–––
–––
–––
–––
1.0
3.1
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
IGSS
Typ.
–––
0.12
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
4.0
35
23
22
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.185
VGS = 10V, ID = 6.0A
0.225 W
VGS = 5.0V, ID = 6.0A
0.265
VGS = 4.0V, ID = 5.0A
2.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 6.0A
25
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
20
ID = 6.0A
4.6
nC VDS = 80V
10
VGS = 5.0V, See Fig. 6 and 13
–––
VDD = 50V
–––
ID = 6.0A
ns
–––
RG = 11Ω, VGS = 5.0V
–––
RD = 8.2Ω, See Fig. 10
Between lead,
4.5
–––
nH
6mm (0.25in.)
G
from package
7.5 –––
and center of die contact
440 –––
VGS = 0V
97 –––
pF
VDS = 25V
50 –––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
10
––– –––
showing the
A
G
integral reverse
––– –––
35
p-n junction diode.
S
––– ––– 1.3
V
TJ = 25°C, IS = 6.0A, VGS = 0V
––– 110 160
ns
TJ = 25°C, IF =6.0A
––– 410 620
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 4.7mH
RG = 25Ω, IAS = 6.0A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between lead and
center of die contact
ISD ≤ 6.0A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS, Uses IRL520N data and test conditions.
TJ ≤ 175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRLR/U120N
100
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , D rain-to-S ource C urrent (A )
ID , D rain-to-S ource C urrent (A )
TOP
10
1
2.5V
20µ s P U LS E W ID TH
T J = 25°C
0.1
0.1
1
10
A
10
2.5V
1
20µ s P U LS E W ID TH
T J = 175°C
0.1
100
0.1
V D S , D rain-to-S ource V oltage (V )
3.0
and
R D S (on ) , D rain-to-S ource O n R esistance
(N orm alized)
I D , D ra in -to-S o urc e C urren t (A )
T J = 2 5 °C
T J = 1 7 5 °C
1
VDS = 5 0V
2 0 µ s P U L S E W ID T H
2
4
6
8
V G S , G a te -to -S o u rc e V o lta g e (V )
Fig 3. Typical Transfer Characteristics
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A
100
Fig 2. Typical Output Characteristics
100
0.1
10
V D S , D rain-to-S ource V oltage (V )
Fig 1. Typical Output Characteristics
10
1
10
A
I D = 10A
2.5
2.0
1.5
1.0
0.5
V G S = 10V
0.0
-60 -40 -20
0
20
40
60
80
A
100 120 140 160 180
T J , Junction T em perature (°C )
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRLR/U120N
V GS
C iss
C rss
C oss
=
=
=
=
15
0V ,
f = 1M H z
C gs + C gd , C ds S H O R TE D
C gd
C ds + C gd
V G S , G ate-to-S ource V oltage (V )
C , C apacitanc e (pF )
800
C is s
600
400
C os s
200
C rs s
0
10
V D S = 80V
V D S = 50V
V D S = 20V
12
9
6
3
FO R TE S T C IR C U IT
S E E FIG U R E 13
0
A
1
I D = 6.0A
100
0
V D S , D rain-to-S ource V oltage (V )
15
20
A
25
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
100
O P E R A TIO N IN TH IS A R E A LIM ITE D
B Y R D S (on)
10µ s
I D , D rain C urrent (A )
I S D , R everse D rain C urrent (A )
10
Q G , Total G ate C harge (nC )
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
TJ = 175°C
10
T J = 25°C
1
V G S = 0V
0.1
0.4
0.6
0.8
1.0
1.2
V S D , S ource-to-D rain V oltage (V )
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
5
A
1.4
10
100µ s
1m s
1
10 m s
T C = 25°C
T J = 175°C
S ingle P ulse
0.1
1
A
10
100
1000
V D S , D rain-to-S ource V oltage (V )
Fig 8. Maximum Safe Operating Area
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IRLR/U120N
10
VDS
VGS
I D , D rain C urrent (A m ps)
8
RD
D.U.T.
RG
+
-VDD
6
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
Fig 10a. Switching Time Test Circuit
2
VDS
90%
A
0
25
50
75
100
125
150
175
TC , C ase T em perature (°C )
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U120N
15V
L
VDS
D .U .T
RG
IA S
10V
tp
D R IV E R
+
V
- DD
A
0 .0 1 Ω
Fig 12a. Unclamped Inductive Test Circuit
E A S , S ingle P ulse A valanc he E nergy (m J)
200
TO P
B O TTO M
160
ID
2.4A
4.2A
6.0 A
120
80
40
0
A
25
50
75
100
125
150
175
S tarting T J , Junc tion T em perature (°C )
V (B R )D S S
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRLR/U120N
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
Driver Gate Drive
D=
Period
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLR/U120N
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.02 (.040)
1.64 (.025)
1
2
10.42 (.410)
9.40 (.370)
LE A D A S S IG N M E N T S
1 - GATE
3
0.51 (.020)
M IN.
-B1.52 (.060)
1.15 (.045)
3X
2X
1.14 (.045)
0.76 (.030)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - D R A IN
3 - SOURCE
4 - D R A IN
0.58 (.023)
0.46 (.018)
M A M B
N O TE S :
1 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982.
2.28 (.090)
4.57 (.180)
2 C O N TR O LLIN G D IM E N S IO N : IN C H .
3 C O N F O R M S T O JE D E C O U TLIN E TO -252A A .
4 D IM E N S IO N S S H O W N A RE B E F O R E S O LD E R D IP ,
S O LD E R D IP M A X. +0.16 (.006).
Part Marking Information
TO-252AA (D-PARK)
E XA M P L E : TH IS IS A N IR F R 1 20
W IT H A S S E M B LY
LOT CODE 9U1P
IN TE R N A TIO N A L
R E C T IF IE R
LO G O
A
IR F R
1 20
9U
A S S E M B LY
LOT CODE
8
F IR S T P O R TIO N
OF PART NUMBER
1P
S E C O N D P O R TIO N
OF PART NUMBER
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IRLR/U120N
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A-
0.58 (.023)
0.46 (.018)
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
LE A D A S S IG N M E N T S
4
1 - GATE
2 - D R A IN
6.45 (.245)
5.68 (.224)
3 - SOURCE
4 - D R A IN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
-B-
N O TE S :
1 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982.
2.28 (.090)
1.91 (.075)
2 C O N T R O LLIN G D IM E N S IO N : IN C H .
3 C O N F O R M S TO J E D E C O U T LIN E T O -252A A .
9.65 (.380)
8.89 (.350)
4 D IM E N S IO N S S H O W N A R E B E F O R E S O LD E R D IP ,
S O LD E R D IP M A X. +0.16 (.006).
3X
1.14 (.045)
0.76 (.030)
2.28 (.090)
3X
1.14 (.045)
0.89 (.035)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2X
M A M B
0.58 (.023)
0.46 (.018)
Part Marking Information
TO-251AA (I-PARK)
E X A M P L E : T H IS IS A N IR F U 1 2 0
W IT H A S S E M B L Y
LO T C OD E 9U 1P
IN T E R N A T IO N A L
R E C TIF IE R
LO GO
IR F U
120
9U
ASSEMBLY
LOT CODE
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F IR S T P O R T IO N
OF PART NUMBER
1P
S E C O N D P O R T IO N
OF PART NUMBER
9
IRLR/U120N
Tape & Reel Information
TO-252AA
TR
TRR
1 6.3 ( .6 41 )
1 5.7 ( .6 19 )
12 .1 ( .4 7 6 )
11 .9 ( .4 6 9 )
F E E D D IR E C T IO N
TRL
16 .3 ( .64 1 )
15 .7 ( .61 9 )
8 .1 ( .3 18 )
7 .9 ( .3 12 )
F E E D D IR E C T IO N
NOTES :
1 . C O N T R O LL IN G D IM E N S IO N : M ILL IM E T E R .
2 . A LL D IM E N S IO N S A R E S H O W N IN M ILL IM E T E R S ( IN C H E S ).
3 . O U T L IN E C O N F O R M S T O E IA -4 81 & E IA -54 1.
1 3 IN C H
16 m m
NO TES :
1. O U T L IN E C O N F O R M S T O E IA -4 81 .
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371
Data and specifications subject to change without notice.
5/98
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/