TI1 LMC8101 Rail-to-rail input and output, 2.7v op amp in dsbga package with shutdown Datasheet

LMC8101
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SNOS496F – AUGUST 2000 – REVISED MARCH 2013
LMC8101 Rail-to-Rail Input and Output, 2.7V Op Amp in
DSBGA Package With Shutdown
Check for Samples: LMC8101
FEATURES
DESCRIPTION
1
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+
VS = 2.7V, TA = 25°C, RL to V /2, Typical Values
Unless Specified.
Rail-to-Rail Inputs
Rail-to-Rail Output Swing Within 35mV of
Supplies (RL =2kΩ)
Packages Offered:
– DSBGA package 1.39mm x 1.41mm
– VSSOP package 3.0mm x 4.9mm
Low Supply Current <1mA (max)
Shutdown Current 1µA (Max)
Versatile Shutdown Feature 10µs Turn-On
Output Short Circuit Current 10mA
Offset Voltage ±5 mV (max)
Gain-Bandwidth 1MHz
Supply Voltage Range 2.7V-10V
THD 0.18%
Voltage Noise 36nv/√Hz
The LMC8101 is a Rail-to-Rail Input and Output high
performance CMOS operational amplifier. The
LMC8101 is ideal for low voltage (2.7V to 10V)
applications requiring Rail-to-Rail inputs and output.
The LMC8101 is supplied in the die sized DSBGA as
well as the 8 pin VSSOP packages. The DSBGA
package requires 75% less board space as compared
to the SOT-23 package. The LMC8101 is an upgrade
to the industry standard LMC7101.
The LMC8101 incorporates a simple user controlled
methodology for shutdown. This allows ease of use
while reducing the total supply current to 1nA typical.
This extends battery life where power saving is
mandated. The shutdown input threshold can be set
relative to either V+ or V− using the SL pin (see
Application Notes section for details).
Other enhancements include improved offset voltage
limit, three times the output current drive and lower
1/f noise when compared to the industry standard
LMC7101 Op Amp. This makes the LMC8101 ideal
for use in many battery powered, wireless
communication and Industrial applications.
APPLICATIONS
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Portable Communication (Voice, Data)
Cellular Phone Power Amp Control Loop
Buffer AMP
Active Filters
Battery Sense
VCO Loop
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LMC8101
SNOS496F – AUGUST 2000 – REVISED MARCH 2013
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Connection Diagrams
A2
+
V
A3
SL
A1
+
V
B1
OUTPUT
B3
INVERTING INPUT
C1
SD
-
C3
NONINVERTING
INPUT
V
C2
Figure 1. 8-Pin VSSOP Top View
Figure 2. DSBGA Top View
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
2KV (3)
200V (4)
ESD Tolerance
VIN differential
±Supply Voltage
See (5) (6)
Output Short Circuit Duration
+
−
Supply Voltage (V − V )
12V
V+ +0.8V, V− −0.8V
Voltage at Input/Output pins
Current at Input Pin
Current at Output Pin
±10mA
(5) (6)
±80mA
Current at Power Supply pins
±80mA
−65°C to +150°C
Storage Temperature Range
Junction Temperature (7)
Soldering Information
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
+150°C
Infrared or Convection (20 sec.)
235°C
Wave Soldering (10 sec.)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human body model, 1.5kΩ in series with 100pF.
Machine Model, 0Ω in series with 200pF.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature at 150°C. Output currents in excess of 40mA over long term may adversely affect
reliability.
Short circuit test is a momentary test. Output short circuit duration is infinite for VS < 6V. Otherwise, extended period output short circuit
may damage the device.
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) − TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
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Operating Ratings
Supply Voltage (V+ - V−)
2.7V to 10V
Junction Temperature Range (2)
Package Thermal Resistance (θJA) (2)
(1)
−40°C to +85°C
DSBGA
220°C/W
VSSOP package 8 pin Surface Mount
230°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For ensured specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) − TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
(2)
2.7V Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Average Drift
IB
Input Bias Current
IOS
Input Offset Current
Rin
Cin
Conditions
Limit (2)
Units
±0.70
±5
±7
mV
max
μV/°C
4
See
(3)
±1
±64
pA
max
0.5
32
pA
max
CM
Input Common Mode Resistance
10
GΩ
CM
Input Common Mode Capacitance
10
pF
CMRR
Common Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
CMVR
0V < = VCM < = 2.7V
78
60
VS = 3V
0V < = VCM < = 3V
78
64
60
VS = 2.7V to 3V
57
50
48
dB
min
VS = 2.7V
CMRR > = 50dB
0.0
0.0
V max
3.0
2.7
V min
VS = 3V
CMRR > = 50dB
−0.2
−0.1
V max
3.2
3.1
V min
3162
1000
562
Sinking
RL = 2kΩ to V+/2
VO = 1.35V to 0.25V
3162
804
562
Sourcing
RL = 10kΩ to V+/2
VO = 1.35V to 2.65V
4000
1778
1000
Sinking
RL = 10kΩ to V+/2
VO = 1.35V to 0.05V
4000
Input Common-Mode Voltage Range
AVOL
Sourcing
RL = 2kΩ to V+/2
VO = 1.35V to 2.45V
Large Signal Voltage Gain
VO
Output Swing High
Output Swing Low
(1)
(2)
(3)
Typ (1)
dB
min
V/V min
1778
1000
V/V
min
RL = 2kΩ to V+/2
VID = 100mV
2.67
2.64
2.62
V
min
RL = 10kΩ to V+/2
VID = 100mV
2.69
2.68
2.67
V
min
RL = 2kΩ to V+/2
VID = −100mV
32
100
150
mV
max
RL = 10kΩ to V+/2
VID = −100mV
10
30
70
mV
max
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis.
Positive current corresponds to current flowing into the device.
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2.7V Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Typ (1)
Limit (2)
Units
V+/2
(4)
Sourcing to
VID = 100mV
20
14
6
mA
min
Sinking to V+/2
VID = −100mV (4)
10
5
4
mA
min
1.0
1.2
mA max
Parameter
ISC
Output Short Circuit Current
IS
Supply Current
Conditions
No load, normal operation
0.70
Shutdown mode
0.001
1
µA max
10
15
µs
±1
±64
pA max
1
0.8
V/µs
min
Shutdown Turn-on time
See (5)
Toff
Shutdown Turn-off time
(5)
Iin
"SL" and "SD" Input Current (6)
SR
Slew Rate (7)
AV = +1, RL = 10kΩ to V+/2
VI= 1VPP
fu
Unity Gain-Bandwidth
VI = 10mV, RL = 2kΩ to V+/2
750
KHz
GBW
Gain Bandwidth Product
f = 100KHz
1
MHz
en
Input-Referred Voltage Noise
f = 10KHz, RS = 50Ω
36
nV/√Hz
in
Input-Referred Current Noise
f = 10KHz
1.5
fA/√Hz
Total Harmonic Distortion
f = 1KHz, AV = +1,
VO = 2.2Vpp,
RL = 600Ω to V+/2
0.18
%
Ton
THD
(4)
See
1
µs
Short circuit test is a momentary test. Output short circuit duration is infinite for VS < 6V. Otherwise, extended period output short circuit
may damage the device.
Shutdown Turn-on and Turn-off times are defined as the time required for the output to reach 90% and 10%, respectively, of its final
peak to peak swing when set for Rail to Rail output swing with a 100KHz sine wave, 2KΩ load, and AV = +10.
Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
Slew rate is the slower of the rising and falling slew rates.
(5)
(6)
(7)
±5V Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ =5V, V− = −5V, VCM = VO = 0V, and RL > 1 MΩ to gnd.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
VOS
Input Offset Voltage
TCVos
Input Offset Voltage Average Drift
IB
Input Bias Current
IOS
Rin
Cin
Conditions
Units
±0.7
±5
±7
mV
max
±1
±64
pA max
32
pA max
μV/°C
4
See (3)
Input Offset Current
0.5
Input Common Mode Resistance
10
GΩ
CM
Input Common Mode Capacitance
10
pF
PSRR
Common-Mode Rejection Ratio
−5V < = VCM < = 5V
Power Supply Rejection Ratio
VS = 5V to 10V
CMVR
Input Common-Mode Voltage Range
4
Limit (2)
CM
CMRR
(1)
(2)
(3)
Typ (1)
CMRR ≥ 50 dB
87
70
67
dB
min
80
76
72
dB
min
−5.3
−5.2
−5.0
V
max
5.3
5.2
5.0
V
min
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis.
Positive current corresponds to current flowing into the device.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ =5V, V− = −5V, VCM = VO = 0V, and RL > 1 MΩ to gnd.
Boldface limits apply at the temperature extremes.
Symbol
Typ (1)
Limit (2)
Sourcing
RL = 600Ω
VO = 0V to 4V
34.5
17.8
10
Sinking
RL = 600Ω
VO = 0V to −4V
34.5
17.8
3.16
Sourcing
RL = 2kΩ
VO = 0V to 4.6V
138
31.6
17.8
Sinking
RL = 2kΩ
VO = 0V to −4.6V
138
Parameter
AVOL
Large Signal Voltage Gain
VO
Output Swing High
Output Swing Low
ISC
Conditions
V/mV
min
V/mV
min
RL = 600Ω
VID = 100mV
4.73
4.60
4.54
V
min
RL = 2kΩ
VID = 100mV
4.90
4.85
4.83
V
min
RL = 600Ω
VID = −100mV
−4.85
−4.75
−4.65
V
max
RL = 2kΩ
VID = −100mV
−4.95
4.90
−4.84
V
max
Sourcing, VID = 100mV (4) (5)
49
30
25
mA
min
Sinking, VID = −100mV (4) (5)
90
60
52
mA
min
No load, normal operation
1.1
1.7
1.9
mA
max
0.001
1
µA
10
15
µs
±64
pA max
Output Short Circuit Current
IS
31.6
10
Units
Supply Current
Shutdown mode
(6)
Ton
Shutdown Turn-on time
See
Toff
Shutdown Turn-off time
See (6)
Iin
"SL" and "SD" Input Current
SR
Slew Rate (7)
AV = +10, RL = 10kΩ,
VO = 10Vpp, CL = 1000pF
1.2
V/µs
fu
Unity Gain-Bandwidth
VI = 10mV
RL = 2kΩ
840
KHz
GBW
Gain Bandwidth Product
f = 10KHz
1.3
MHz
en
Input-Referred Voltage Noise
f = 10KHz, Rs = 50Ω
33
nV/√Hz
in
Input-Referred Current Noise
f = 10KHz
1.5
fA/√Hz
Total Harmonic Distortion
f = 10KHz, AV = +1,
VO =8Vpp, RL = 600Ω
0.2
%
THD
(4)
(5)
(6)
(7)
1
±1
µs
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature at 150°C. Output currents in excess of 40mA over long term may adversely affect
reliability.
Short circuit test is a momentary test. Output short circuit duration is infinite for VS < 6V. Otherwise, extended period output short circuit
may damage the device.
Shutdown Turn-on and Turn-off times are defined as the time required for the output to reach 90% and 10%, respectively, of its final
peak to peak swing when set for Rail to Rail output swing with a 100KHz sine wave, 2KΩ load, and AV = +10.
Slew rate is the slower of the rising and falling slew rates.
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Typical Performance Characteristics
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
6
Gain/Phase vs.
Frequency (RL = 2k, VS = ± 1.35V)
Gain/Phase vs.
Frequency (RL = 2k, VS = ± 5V)
Figure 3.
Figure 4.
Gain/Phase vs.
Frequency (RL = Open)
Gain vs. Phase for
various CL VS = ±1.35V
Figure 5.
Figure 6.
Unity Gain Frequency vs.
Supply Voltage
Phase Margin vs.
Supply Voltage
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
Unity Gain Frequency and Phase Margin vs.
Load
Unity Gain Frequency and Phase Margin
vs. Load
Figure 9.
Figure 10.
PSRR vs. Frequency
PSRR vs. Frequency
Figure 11.
Figure 12.
CMRR vs. Frequency
Input Bias Current vs.
Common Mode Voltage @ 85°C
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
8
Input Current vs.
Temperature VS = 10V
VIN vs. VOUT
Figure 15.
Figure 16.
VIN vs. VOUT
VIN vs. VOUT
Figure 17.
Figure 18.
VIN vs. VOUT
Supply Current vs. Supply Voltage
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
Delta VOS vs.
VCM (Ref VCM = 1.35V)
Delta VOS vs.
VCM (Ref VCM = 5V)
Figure 21.
Figure 22.
Offset Voltage vs. VSUPPLY
Output Positive Swing vs.
Supply Voltage RL = 600Ω to V+/2
Figure 23.
Figure 24.
Output Positive Swing vs.
Supply Voltage RL = 2k to V+/2
Output Negative Swing vs.
Supply Voltage RL = 600Ω to V+/2
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
10
Output Negative Swing vs.
Supply Voltage, RL = 2k to V+/2
Short Circuit Sinking Current vs.
Supply Voltage
Figure 27.
Figure 28.
Short Circuit Sourcing Current
vs. Supply Voltage
Undistorted Output Voltage Swing
vs. Output Load Resistance
Figure 29.
Figure 30.
Step Response 1% settling time and % overshoot
vs. Cap Load
Large Signal Step Response
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
Small Signal Step Response
Large Signal Step Response
Figure 33.
Figure 34.
Small Signal Step Response
Small Signal Step Response
Figure 35.
Figure 36.
Large Signal Step Response
Large Signal Step Response
Figure 37.
Figure 38.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
12
Small Signal Step Response
Slew Rate vs. Supply Voltage
Figure 39.
Figure 40.
Slew Rate vs. Capacitive Load
Slew Rate vs. Capacitive Load
Figure 41.
Figure 42.
Slew Rate vs. Capacitive Load
Slew Rate vs. Capacitive Load
Figure 43.
Figure 44.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
Voltage Noise vs. Frequency
Voltage Noise vs.
VCM @ Various Frequencies
Figure 45.
Figure 46.
THD+N vs. Amplitude
THD+N vs. Frequency
Figure 47.
Figure 48.
Sourcing Current vs.
Output Voltage (VS = 2.7V)
Sinking Current vs.
Output Voltage (VS = 2.7V)
Figure 49.
Figure 50.
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Typical Performance Characteristics (continued)
VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified
14
Sourcing Current vs.
Output Voltage (VS = 10V)
Sinking Current vs.
Output Voltage (VS = 10V)
Figure 51.
Figure 52.
Cap Load vs. IOUT
Cap Load vs.
Isolation Resistance
Figure 53.
Figure 54.
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APPLICATION NOTES
SHUTDOWN FEATURES
The LMC8101 is capable of being turned off in order to conserve power. Once in shutdown, the device supply
current is drastically reduced (1µA maximum) and the output will be "Tri-stated".
The shutdown feature of the LMC8101 is designed for flexibility. The threshold level of the SD input can be
referenced to either V-or V+ by setting the level on the SL input. When the SL input is connected to V-, the SD
threshold level is referenced to V-and vice versa. This threshold will be about 1.5V from the supply tied to the SL
pin. So, for this example, the device will be in shutdown as long as the SD pin voltage is within 1V of V-. In order
to ensure that the device would not "chatter" between active and shutdown states, hysteresis is built into the SD
pin transition (see Figure 55 for an illustration of this feature). The shutdown threshold and hysteresis level are
independent of the supply voltage. Figure 55 illustration applies equally well to the case when SL is tied to V+
and the horizontal axis is referenced to V+ instead. The SD pin should not be set within the voltage range from
1.1V to 1.9V of the selected supply voltage since this is a transition region and the device status will be
undetermined.
Figure 55. Supply Current vs. "SD" Voltage
Table 1 summarizes the status of the device when the SL and SD pins are connected directly to V-or V+:
Table 1. LMC8101 Status Summary
SL
SD
LMC8101 Status
V−
V−
Shutdown
−
+
V
V
Active
V+
V+
Shutdown
V+
V−
Active
In case shutdown operation is not needed, as can be seen above, the two pins SL and SD can simply be
connected to opposite supply nodes to achieve "Active" operation. The SL and SD should always be tied to a
node; if left unconnected, these high impedance inputs will float to an undetermined state and the device status
will be undetermined as well.
With the device in shutdown, once "Active" operation is initiated, there will be a finite amount of time required
before the device output is settled to its final value. This time is less than 15µs. In addition, there may be some
output spike during this time while the device is transitioning into a fully operational state. Some applications may
be sensitive to this output spike and proper precautions should be taken in order to ensure proper operation at all
times.
TINY PACKAGE
The LMC8101 is available in the DSBGA package as well the 8 pin VSSOP package. The DSBGA package
requires approximately 1/4 the board area of a SOT-23. This package is less than 1mm in height allowing it to be
placed in absolute minimum height clearance areas such as cellular handsets, LCD panels, PCMCIA cards, etc.
More information about the DSBGA package can be found at: http://www.ti.com/packaing.
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CONVERSION BOARDS
In order to ease the evaluation of tiny packages such as the DSBGA, there is a conversion board
(LMC8101CONV) available to board designers. This board converts a DSBGA device into an 8 pin DIP package
(see Figure 56) for easier handling and evaluation. This board can be ordered from Texas Instruments by
contacting http://www.ti.com.
Figure 56. DSBGA Conversion Board pin-out
INCREASED OUTPUT CURRENT
Compared to the LMC7101, the LMC8101 has an improved output stage capable of up to three times larger
output sourcing and sinking current. This improvement would allow a larger output voltage swing range
compared to the LMC7101 when connected to relatively heavy loads. For lower supply voltages this is an added
benefit since it increases the output swing range. For example, the LMC8101 can typically swing 2.5Vpp with
2mA sourcing and sinking output current (Vs = 2.7V) whereas the LMC7101 output swing would be limited to
1.9Vpp under the same conditions. Also, compared to the LMC7101 in the SOT-23 package, the LMC8101 can
dissipate more power because both the VSSOP and the DSBGA packages have 40% better heat dissipation
capability.
LOWER 1/f NOISE
The dominant input referred noise term for the LMC8101 is the input noise voltage. Input noise current for this
device is of no practical significance unless the equivalent resistance it looks into is 5MΩ or higher.
The LMC8101's low frequency noise is significantly lower than that of the LMC7101. For example, at 10Hz, the
input referred spot noise voltage density is 85 nV√Hz as compared to about 200nV√Hz for the LMC7101. Over a
frequency range of 0.1Hz to 100Hz, the total noise of the LMC8101 will be approximately 60% less than that of
the LMC7101.
LOWER THD
When connected to heavier loads, the LMC8101 has lower THD compared to the LMC7101. For example, with
5V supply at 10KHz and 2Vpp swing (Av = −2), the LMC8101 THD (0.2%) is 60% less than the LMC7101's. The
LMC8101 THD can be kept below 0.1% with 3Vpp at the output for up to 10KHz (refer to the Typical
Performance Characteristics plots).
IMPROVING THE CAP LOAD DRIVE CAPABILITY
This can be accomplished in several ways:
•
Output resistive loading increase:
The Phase Margin increases with increasing load (refer to the Typical Performance Characteristics plots). When
driving capacitive loads, stability can generally be improved by allowing some output current to flow through a
load. For example, the cap load drive capability can be increased from 8200pF to 16000pF if the output load is
increased from 5kΩ to 600Ω (AV = +10, 25% overshoot limit, 10V supply).
•
Isolation resistor between output and cap load:
16
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Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LMC8101
LMC8101
www.ti.com
SNOS496F – AUGUST 2000 – REVISED MARCH 2013
This resistor will isolate the feedback path (where excessive phase shift due to output capacitance can cause
instability) from the capacitive load. With a 10V supply, a 100Ω isolation resistor allows unlimited capacitive load
without oscillation compared to only 300pF without this resistor (AV = +1).
•
Higher supply voltage:
Operating the LMC8101 at higher supply voltages allows higher cap load tolerance. At 10V, the LMC8101's low
supply voltage cap load limit of 300pF improves to about 600pF (AV = +1).
•
Closed loop gain increase:
As with all Op Amps, the capacitive load tolerance of the LMC8101 increases with increasing closed loop gain. In
applications where the load is mostly capacitive and the resistive loading is light, stability increases when the
LMC8101 is operated at a closed loop gain larger than +1.
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Product Folder Links: LMC8101
17
LMC8101
SNOS496F – AUGUST 2000 – REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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Product Folder Links: LMC8101
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMC8101MM
NRND
VSSOP
DGK
8
1000
TBD
Call TI
Call TI
-40 to 85
A11
LMC8101MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A11
LMC8101MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A11
LMC8101TP/NOPB
ACTIVE
DSBGA
YPB
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
A
08
LMC8101TPX/NOPB
ACTIVE
DSBGA
YPB
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
A
08
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMC8101MM
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC8101MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC8101MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC8101TP/NOPB
DSBGA
YPB
8
250
178.0
8.4
1.57
1.57
0.76
4.0
8.0
Q1
LMC8101TPX/NOPB
DSBGA
YPB
8
3000
178.0
8.4
1.57
1.57
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMC8101MM
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMC8101MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMC8101MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMC8101TP/NOPB
DSBGA
YPB
8
250
210.0
185.0
35.0
LMC8101TPX/NOPB
DSBGA
YPB
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YPB0008
D
0.5±0.045
E
TPA08XXX (Rev A)
D: Max = 1.464 mm, Min =1.403 mm
E: Max = 1.464 mm, Min =1.403 mm
4215100/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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