bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 I2C Controlled 4.5A Single Cell USB/Adapter Charger With Narrow VDC Power Path Management and USB OTG Check for Samples: bq24190, bq24192, bq24192I, bq24193 FEATURES 1 • 2 • • • • • • • High Efficiency 4.5A Switch Mode Charger – 92% Charge Efficiency at 2A, 90% at 4A – Accelerate Charge Time by Battery Path Impedance Compensatioin Highest Battery Discharge Efficiency with 12mΩ Battery Discharge MOSFET up to 9A Discharge Current Single Input USB-compliant/Adapter Charger – USB Host or Charging Port D+/D- Detection Compatible to USB Battery Charger Spec 1.2 – Input Voltage and Current Limit Supports USB2.0 and USB 3.0 – Input Current Limit: 100mA, 150mA, 500mA, 900mA, 1.2A, 1.5A, 2A and 3A 3.9V–17V Input Operating Voltage Range – Support All Kinds of Adapter with Input Voltage DPM Regulation USB OTG 5V at 1.3A Synchronous Boost Converter Operation – 93% 5V Boost Efficiency at 1A Narrow VDC (NVDC) Power Path Management – Instant-on Works with No Battery or Deeply Discharged Battery – Ideal Diode Operation in Battery Supplement Mode 1.5MHz Switching Frequency for Low Profile Inductor Autonomous Battery Charging with or without Host Management – Battery Charge Enable – Battery Charge Preconditioning – Charge Termination and Recharge • • • • • • High Accuracy (0°C to 125°C) – ±0.5% Charge Voltage Regulation – ±7% Charge Current Regulation – ±7.5% Input Current Regulation – ±2% Output Regulation in Boost Mode High Integration – Power Path Management – Synchronous Switching MOSFETs – Integrated Current Sensing – Bootstrap Diode – Internal Loop Compensation Safety – Battery Temperature Sensing and Charging Safety Timer – JEITA Guideline Compliant (bq24193) – Thermal Regulation and Thermal Shutdown – Input System Over-Voltage Protection – MOSFET Over-Current Protection Charge Status Outputs for LED or Host Processor Low Battery Leakage Current and Support Shipping Mode 4mm x 4mm QFN-24 Package APPLICATIONS • • • • • Tablet PC Smart Phone Portable Audio Speaker Portable Media Players Internet Devices 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The bq24190, bq24192, bq24192I, and bq24193 are highly-integrated switch-mode battery charge management and system power path management devices for single cell Li-Ion and Li-polymer battery in a wide range of tablet and other portable devices. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution. The device supports a wide range of input sources, including standard USB host port, USB charging port and high power DC adapter. To set the default input current limit, the bq24190 detects the input source following the USB battery charging spec 1.2, and the bq24192, bq24192I, and bq24193 takes the results from detection circuit in the system, such as USB PHY device. The bq24190,192,192I, and 193 are compliant with USB 2.0 and USB 3.0 power specifications with input current and voltage regulation. Meanwhile, the bq24190, bq24192, bq24192I, and bq24193 meets USB On-the-Go operation power rating specification by supplying 5V on the VBUS with a current limit up to 1.3A. The power path management regulates the system slightly above battery voltage but does not drop below 3.5V minimum system voltage (programmable). With this feature, the system maintains operation even when the battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power path management automatically reduces the charge current to zero. As the system load continues to increase, the power path discharges the battery until the system power requirement is met. This supplement mode operation prevents overloading the input source. The devices initiate and complete a charging cycle without software control. It automatically detects the battery voltage and charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the charging cycle, the charger automatically terminates when the charge current is below a preset limit in the constant voltage phase. When the full battery falls below the recharge threshold, the charger will automatically start another charging cycle. The bq24190, bq24192, bq24192I, and bq24193 provide various safety features for battery charging and system operation, including dual pack negative thermistor monitoring, charging safety timer and over-voltage/overcurrent protections. The bq24193 supports JEITA guideline compliant temperature profile. The thermal regulation reduces charge current when the junction temperature exceeds 120°C (programmable). The STAT output reports the charging status and any fault conditions. The PG output in the bq24192, bq24192I, and bq24193 indicates if a good power source is present. The INT immediately notifies the host when a fault occurs. The bq24190, bq24192, bq24192I, and bq24193 are available in a 24-pin, 4x4 mm2 thin QFN package. bq2419x Family Table bq24190 2 2 bq24192 bq24192I bq24193 I C Address 6BH 6BH 6BH 6BH USB Detection D+/D– PSEL PSEL PSEL Default VINDPM 4.36V 4.36V 4.44V 4.36V Default Battery Voltage 4.208V 4.208V 4.112V 4.208V Default Charge Current 2.048A 2.048A 1.024A 2.048A Default Adapter Current Limit 1.5A 3A 1.5A 3A Maximum Pre-charge Current 2.048A 2.048A 640mA 2.048A Charging Temperature Profile Cold/Hot 2 TS pins Cold/Hot 2 TS pins Cold/Hot 2 TS pins JEITA 1 TS pin Status Output STAT STAT, PG STAT, PG STAT, PG STAT During Fault Blinking @ 1Hz Blinking @ 1Hz 10k to ground Blinking @ 1Hz Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 ORDERING INFORMATION PART NUMBER PART MARKING PACKAGE bq24190 bq24190 24-pin 4mmx4mm VQFN bq24192 bq24192I bq24193 bq24192 bq24192I bq24193 Copyright © 2012, Texas Instruments Incorporated 24-pin 4mmx4mm VQFN 24-pin 4mmx4mm VQFN 24-pin 4mmx4mm VQFN ORDERING NUMBER QUANTITY bq24190RGER 3000 bq24190RGET 250 bq24192RGER 3000 bq24192RGET 250 bq24192IRGER 3000 bq24192IRGET 250 bq24193RGER 3000 bq24193RGET 250 Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 3 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com APPLICATION DIAGRAM bq24190 5V USB SDP/DCP VBUS PMID 1μF 1μH 10μF 47nF 6.8μF USB SYS: 3.5V-4.35V SW 10μF 10μF 10μF BTST REGN D+ 4.7μF D– SYS PGND 2.2kW SYS STAT VREF BAT 10kW 353W 10μF (1.5A max) 10kW 10kW SDA SCL INT OTG CE Host ILIM REGN 5.52kW TS1 TS2 31.23kW Power Pad 10kW (103-AT) Figure 1. bq24190 with D+/D- Detection and USB On-The-Go (OTG) bq24192 5V USB or 5V Adapter SYS: 3.5V-4.35V SW VBUS PMID 1μF 2.2μH 47nF 6.8μF 10μF 10μF BOOT REGN 4.7μF SYS PGND 2.2kW PG STAT VREF 10kW 10kW PHY BAT 10μF 177W (3A max) 10kW SDA SCL INT OTG CE Host SYS PSEL ILIM REGN 5.52kW TS1 TS2 31.23kW Power Pad 10kW (103-AT) Figure 2. bq24192 with PSEL and USB On-The-Go (OTG) 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 bq24192I 5V USB 15V Adapter SYS: 3.5V-4.35V SW VBUS PMID 1μF 2.2μH 47nF 6.8μF 10μF 10μF BOOT REGN 4.7μF SYS PGND 2.2kW 10kW SYS PG STAT VREF 10kW BAT 10kW SDA SCL INT OTG CE Host PHY ILIM 10μF 353W (1.5A max) REGN 10kW TS1 TS2 10kW PSEL Power Pad Figure 3. bq24192I with PSEL, USB On-The-Go (OTG), No Thermistor Connections bq24193 12V Adapter SYS: 3.5V-4.35V SW VBUS PMID 1μF 2.2μH 47nF 10μF 10μF 10μF BOOT REGN 1μF SYS PGND 2.2kW PG STAT VREF 10kW 10kW BAT 10μF 265W (2A max) 10kW SDA SCL INT OTG CE Host SYS PSEL ILIM REGN 2.27kW TS1 TS2 10kW (103-AT) 6.86kW Power Pad Figure 4. bq24193 with PSEL, USB On-The-Go (OTG) and Support JEITA Profile Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 5 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM VBUS PMID Q1 3.8V UVLO Q1 Gate Control VBATz +80mV SLEEP REGN REGN LDO EN_HIZ ACOV 18V BTST FBO VBUS VBUS_OVP_BOOST 5.4V I(Q2) VINDPM 100mA IINDPM 3.2A I(Q3) Q2_UCP_BOOST SW Q3_OCP_BOOST BAT 104%xVBAT_REG BAT IC TJ TREG VBAT_REG REGN BATOVP 100mA UCP I(Q2) Q2_OCP I(Q3) SYS Q2 CONVERTER CONTROL PGND 7A VSYSMIN ICHG_REG Q3 EN_HIZ EN_CHARGE EN_BOOST V(BTST-SW) REFRESH 4.2V SYS ICHG VBAT_REG ICHG_REG REF DAC BAD_SRC CONVERTER CONTROL TSHUT STATE MACHINE ILIM D+ (190) D– (190) PSEL(192/192I/193) USB Host Adapter Detection USB Adapter 1.5A BAT_GD RECHRG INT BAT BAT bq2419x 4.1V BAT ICHG TERMINATION CHARGE ITERM CONTROL SUSPEND STATE 2.8V MACHINE BATLOWV BAT bq24190/192/193 STAT bq24192I I2C Interface SCL 6 Q4 IC TJ TSHUT 3.6V OTG PG(192/192I/193) 30mA IDC Q4 Gate Control Submit Documentation Feedback SDA BATSHORT BATTERY THERMISTER SENSING (bq24190/192/ 192I Hot/Cold) (bq24193 JEITA) TS1 TS2 2V BAT CE Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 VBUS PMID REGN BTST SW SW VBUS PMID REGN BTST SW SW PINOUTS 24 23 22 21 20 19 24 23 22 21 20 19 VBUS 1 18 PGND VBUS 1 D+ 2 17 PGND PSEL 2 18 PGND 17 PGND 16 SYS 15 SYS bq24192 D– 3 16 SYS PG 3 bq24192I bq24190 STAT 4 15 SYS STAT 4 bq24193 BAT SDA 13 BAT SDA 6 13 BAT 8 9 10 11 OTG CE ILIM TS1 12 TS2 7 INT 6 7 8 9 10 11 12 TS2 14 TS1 5 ILIM SCL CE BAT OTG 14 INT SCL 5 PIN FUNCTIONS PIN TYPE DESCRIPTION 1,24 P Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC. (Refer to Application Information Section for details) D+ (bq24190) 2 I Analog Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2. PSEL (bq24192 bq24192I bq24193) – I Digital Power source selection input. High indicates a USB host source and Low indicates an adapter source. D– (bq24190) 3 I Analog Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2. PG (bq24192 bq24192I bq24193) – O Digital Open drain active low power good indicator. Connect to the pull up rail via 10kohm resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30mA. STAT 4 O Digital Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10kohm. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in bq24190, bq24192, bq24193 blinks at 1Hz, and STAT pin in bq24192I has a 10kΩ resistor to ground. SCL 5 I Digital I2C Interface clock. Connect SCL to the logic rail through a 10kΩ resistor. SDA 6 I/O Digital I2C Interface data. Connect SDA to the logic rail through a 10kΩ resistor. INT 7 O Digital Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active low, 256us pulse to host to report charger device status and fault. OTG 8 I Digital USB current limit selection pin during buck mode, and active high enable pin during boost mode. NAME NO. VBUS In buck mode with USB host (PSEL=High), when OTG = High, IIN limit = 500mA and when OTG = Low, IIN limit = 100mA. The boost mode is activated when the REG01[5:4]=10 and OTG pin is High. CE 9 I Digital Active low Charge Enable pin. Battery charging is enabled when REG01[5:4]=01 and CE pin = Low. CE pin must be pulled high or low. ILIM 10 I Analog ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × 530. The actual input current limit is the lower one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500mA. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 7 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com PIN FUNCTIONS (continued) PIN TYPE DESCRIPTION NAME NO. TS1 11 I Analog Temperature qualification voltage input #1. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS1 to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor. TS1 and TS2 pins have to be shorted together in bq24193. TS2 12 I Analog Temperature qualification voltage input #2. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS2 to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor. TS1 and TS2 pins have to be connected together in bq24193. BAT 13,14 P Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin. SYS 15,16 P System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. (Refer to Application Information Section for inductor and capacitor selection) PGND 17,18 P Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the nchannel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin. SW 19,20 O Analog Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047µF bootstrap capacitor from SW to BTST. BTST 21 P PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047µF bootstrap capacitor from SW to BTST. REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode. For VBUS above 6V, connect 1-µF ceramic capacitor from REGN to analog GND. For VBUS below 6V, connect a 4.7-μF (10V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS1 and TS2 pins. PMID 23 O Analog PowerPAD – P Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance, connect a 1-µF capacitor on VBUS to PGND, and the rest all on PMID to PGND. (Refer to Application Information Section for details) Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD™ to the board, and have vias on the Power Pad plane star-connecting to PGND and ground plane for high-current power converter. ABSOLUTE MAXIMUM RATINGS VALUE Voltage range (with respect to GND) Output sink current VBUS –2 V – 20 V PMID, STAT, PG –0.3 V –20 V BTST –0.3 V – 26 V SW –2 V – 20 V BAT, SYS (converter not switching) –0.3 V – 6 V SDA, SCL, INT, OTG, ILIM, REGN, TS1, TS2, CE, PSEL, D+, D– –0.3 V – 7 V BTST TO SW –0.3 V – 7 V PGND to GND –0.3 V – 0.3 V INT, STAT, PG 6mA Junction temperature –40°C to 150°C Storage temperature –65°C to 150°C RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 3.9 17 (1) V 3 A Output current (SYS) 4.5 A Battery voltage 4.4 V VIN Input voltage IIN Input current ISYS VBAT (1) 8 The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 RECOMMENDED OPERATING CONDITIONS (continued) MIN MAX UNIT 4.5 A 6 (continuous) 9 (peak) (up to 1 sec duration) A 85 °C Fast charging current IBAT Discharging current with internal MOSFET TA Operating free-air temperature range –40 THERMAL INFORMATION RGE PACKAGE THERMAL METRIC (1) 24-PIN θJA Junction-to-ambient thermal resistance 32.2 θJCtop Junction-to-case (top) thermal resistance 29.8 θJB Junction-to-board thermal resistance 9.1 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 9.1 θJCbot Junction-to-case (bottom) thermal resistance 2.2 UNITS °C/W space (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS QUIESCENT CURRENTS VVBUS < VUVLO, VBAT = 4.2 V, leakage between BAT and VBUS IBAT IVBUS IOTGBOOST Battery discharge current (BAT, SW, SYS) Input supply current (VBUS) Battery Discharge Current in boost mode 5 µA High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1) 12 20 µA High-Z Mode, or no VBUS, REG07[5] = 0, –40°C – 85°C 32 55 µA VVBUS = 5 V, High-Z mode 15 30 µA VVBUS = 17 V, High-Z mode 30 50 µA VVBUS > VUVLO, VVBUS > VBAT, converter not switching 1.5 3 mA VVBUS > VUVLO, VVBUS > VBAT, converter switching, VBAT=3.2V, ISYS=0A 4 mA VVBUS > VUVLO, VVBUS > VBAT, converter switching, VBAT=3.8V, ISYS=0A 15 mA 4 mA VBAT=4.2V, Boost mode, IVBUS = 0A, converter switching VBUS/BAT POWER UP VVBUS_OP VBUS operating range VVBUS_UVLOZ VBUS for active I2C, no battery VVBUS rising 3.9 3.6 VSLEEP Sleep mode falling threshold VVBUS falling, VVBUS-VBAT 35 VSLEEPZ Sleep mode rising threshold VVBUS rising, VVBUS-VBAT VACOV VBUS over-voltage rising threshold VVBUS rising VACOV_HYST VBUS Over-Voltage Falling Hysteresis VVBUS falling VBAT_UVLOZ Battery for active I2C, no VBUS VBAT rising VBAT_DPL Battery depletion threshold VBAT falling 2.4 2.6 V VBAT_DPL_HY Battery depletion rising hysteresis VBAT rising 170 230 mV VVBUSMIN Bad adapter detection threshold VVBUS falling 3.8 V IBADSRC Bad adapter detection current source 30 mA tBADSRC Bad source detection duration 30 ms Copyright © 2012, Texas Instruments Incorporated 17 V 80 120 mV 170 250 300 mV 17.4 18 V 700 mV V 2.3 V Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 9 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.35 V POWER PATH MANAGEMENT VSYS_RANGE System regulation voltage Isys = 0A, Q4 off, VBAT up to 4.2 V, REG01[3:1]=101, VSYSMIN = 3.5 V 3.5 VSYS_MIN System voltage output REG01[3:1]=101, VSYSMIN = 3.5 V 3.55 RON(RBFET) Internal top reverse blocking MOSFET onresistance Measured between VBUS and PMID 23 38 RON(HSFET) Internal top switching MOSFET onresistance between PMID and SW TJ = –40°C – 85°C 27 35 TJ = -40°C – 125°C 27 45 RON(LSFET) Internal bottom switching MOSFET onresistance between SW and PGND TJ = –40°C – 85°C 32 45 TJ = -40°C – 125°C 32 48 VFWD BATFET forward voltage in supplement mode BAT discharge current 10mA 30 VSYS_BAT SYS/BAT Comparator VSYS falling VBATGD Battery good comparator rising threshold VBAT rising VBATGD_HYST Battery good comparator falling threshold VBAT falling 3.65 V 3.55 mΩ mΩ mV 90 3.4 mΩ mV 3.7 100 V mV BATTERY CHARGER VBAT_REG_ACC Charge voltage regulation accuracy VBAT = 4.112V and 4.208V –0.5% 0.5% VBAT = 3.8V, ICHG = 1792mA, TJ = 25°C –4% 4% VBAT = 3.8V, ICHG = 1792mA, TJ = –20°C – 125°C –7% IICHG_REG_ACC Fast charge current regulation accuracy ICHG_20pct Charge current with 20% option on VBAT = 3.1V, ICHG = 104mA, REG02=03 75 100 125 mA VBATLOWV Battery LOWV falling threshold Fast charge to precharge, REG04[1] = 1 2.6 2.8 2.9 V VBATLOWV_HYST Battery LOWV rising threshold Precharge to fast charge, REG04[1] = 1 2.8 3.0 3.1 V IPRECHG_ACC Precharge current regulation accuracy VBAT = 2.6V, ICHG = 256mA –20% ITERM_ACC Termination current accuracy ITERM = 256mA, ICHG = 960mA –20% VSHORT Battery Short Voltage VBAT falling 1.8 V VSHORT_HYST Battery Short Voltage hysteresis VBAT rising 200 mV ISHORT Battery short current VBAT<2.2V 100 mA VRECHG Recharge threshold below VBAT_REG VBAT falling, REG04[0] = 0 100 mV tRECHG Recharge deglitch time VBAT falling, REG04[0]=0 20 TJ = 25°C 12 15 TJ = –40°C – 125°C 12 20 RON_BATFET SYS-BAT MOSFET on-resistance 7% 20% 20% ms mΩ INPUT VOLTAGE/CURRENT REGULATION VINDPM_REG_ACC Input voltage regulation accuracy USB Input current regulation limit, VBUS = 5V, current pulled from SW IUSB_DPM –2% 2% USB100 85 100 mA USB150 125 150 mA USB500 440 500 mA USB900 750 900 mA 1.4 1.6 A AxΩ IADPT_DPM Input current regulation accuracy Input current limit 1.5A IIN_START Input current limit during system start up VSYS<2.2V KILIM IIN = KILIM/RILIM IINDPM = 1.5A 1.5 100 mA 440 485 530 0.5 0.6 0.7 V 14 µA D+/D- DETECTION VD+_SRC D+ voltage source ID+_SRC D+ connection check current source ID–_SINK D– current sink 7 150 µA D–, switch open 50 –1 100 1 µA D+, switch open –1 1 µA ID_LKG Leakage current into D+/D– VD+_LOW D+ Low comparator threshold 0.7 0.8 V VD–_LOWdatref D– Low comparator threshold 250 400 mV RD–_DWN D– Pulldown for connection check 14.25 24.8 kΩ tSDP_DEFAULT Charging timer with 100mA USB host in default mode 10 Submit Documentation Feedback 45 mins Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BAT OVER-VOLTAGE PROTECTION VBATOVP Battery over-voltage threshold VBAT rising, as percentage of VBAT_REG 104% VBATOVP_HYST Battery over-voltage hysteresis VBAT falling, as percentage of VBAT_REG 2% tBATOVP Battery over-voltage deglitch time to disable charge 1 µs THERMAL REGULATION AND THERMAL SHUTDOWN TJunction_REG Junction temperature regulation accuracy REG06[1:0] = 11 TSHUT Thermal shutdown rising temperature Temperature increasing TSHUT_HYS Thermal shutdown hysteresis 115 120 125 160 °C °C 30 °C Thermal shutdown rising deglitch Temperature increasing delay 1 ms Thermal shutdown falling deglitch Temperature decreasing delay 1 ms COLD/HOT THERMISTER COMPARATOR (bq24190,bq24192,bq24192I) VLTF Cold temperature threshold, TS pin voltage rising threshold Charger suspends charge. As Percentage to VREGN 73% 73.5% 74% VLTF_HYS Cold temperature hysteresis, TS pin voltage falling As Percentage to VREGN 0.2% 0.4% 0.6% VHTF Hot temperature TS pin voltage falling threshold As Percentage to VREGN 46.6% 47.2% 48.8% VTCO Cut-off temperature TS pin voltage falling threshold As Percentage to VREGN 44.2% 44.7% 45.2% Deglitch time for temperature out of range detection VTS > VLTF, or VTS < VTCO, or VTS < VHTF 10 ms JEITA THERMISTER COMPARATOR (bq24193) VT1 T1 (0°C) threshold, Charge suspended T1 below this temperature. VTS rising, As Percentage to VREGN VT1_HYS Charge back to ICHG/2 and 4.2V above this temperature Hysteresis, VTS falling VT2 T2 (10°C) threshold, Charge back to ICHG/2 and 4.2V below this temperature VTS rising, as percentage of VREGN VT2_HYS Charge back to ICHG and 4.2V above this temperature Hysteresis, VTS falling VT3 T3 (45°C) threshold, Charge back to ICHG and 4.05V above this temperature VTS falling, as percentage of VREGN VT3_HYS Charge back to ICHG and 4.2V below this temperature Hysteresis, VTS rising VT5 T5 (60°C) threshold, charge suspended above this temperature VTS falling, as percentage of VREGN VT5_HYS Charge back to ICHG and 4.05V below this temperature Hysteresis, VTS rising 70.2% 70.8% 71.4% 0.6% 68.0% 68.6% 69.2% 0.8% 55.5% 56.1% 56.7% 0.8% 47.6% 48.1% 48.6% 1.2% CHARGE OVER-CURRENT COMPARATOR IHSFET_OCP HSFET over-Current threshold IBATFET_OCP System over load threshold 5.3 7 A 9 A CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE) VLSFET_UCP LSFET charge under-current falling threshold From sync mode to non-sync mode 100 mA PWM OPERATION FSW PWM Switching frequency, and digital clock DMAX Maximum PWM duty cycle VBTST_REFRESH Bootstrap refresh comparator threshold Copyright © 2012, Texas Instruments Incorporated 1300 1500 1700 kHz 97% VBTST-VSW when LSFET refresh pulse is requested, VBUS=5V 3.6 VBTST-VSW when LSFET refresh pulse is requested, VBUS>6V 4.2 V Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 11 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BOOST MODE OPERATION VOTG_REG OTG output voltage I(VBUS) = 0 VOTG_REG_ACC OTG output voltage accuracy I(VBUS) = 0 IOTG OTG mode output current VOTG_OVP OTG over-voltage threshold VOTG_ILIM LSFET cycle-by-cycle current limit VOTG_HSZCP HSFET under current falling threshold IRBFET_OCP RBFET over-current threshold 5.00 –2% REG01[0] = 0 0.5 REG01[0] = 1 1.3 A A 5.3 3.2 V 2% 5.5 V 4.6 A 100 mA REG01[0] = 1 1.4 1.8 2.7 REG01[0] = 0 0.6 1.1 1.8 A REGN LDO VREGN REGN LDO output voltage IREGN REGN LDO current limit VVBUS = 10V, IREGN = 40mA 5.6 6 6.4 VVBUS = 5V, IREGN = 20mA 4.75 4.8 4.85 VVBUS = 10V, VREGN = 3.8V 50 V V mA LOGIC I/O PIN CHARACTERISTICS (OTG, CE, PSEL, STAT, PG) VILO Input low threshold VIH Input high threshold 0.4 VOUT_LO Output low saturation voltage Sink current = 5 mA IBIAS High level leakage current Pull up rail 1.8V 1.3 V V 0.4 V 1 µA I2C INTERFACE (SDA, SCL, INT) VIH Input high threshold level VPULL-UP = 1.8V, SDA and SCL VIL Input low threshold level VPULL-UP = 1.8V, SDA and SCL 1.3 0.4 V VOL Output low threshold level Sink current = 5mA 0.4 V IBIAS High-level leakage current VPULL-UP = 1.8V, SDA and SCL 1 µA fSCL SCL clock frequency 400 kHz V DIGITAL CLOCK AND WATCHDOG TIMER fHIZ Digital crude clock REGN LDO disabled 15 35 50 kHz fDIG Digital clock REGN LDO enabled 1300 1500 1700 kHz tWDT REG05[5:4]=11 REGN LDO enabled 136 160 sec TYPICAL CHARACTERISTICS Table 1. Tables of Figures FIGURE NO. CHARGING EFFICIENCY vs. CHARGING CURRENT Figure 5 SYSTEM LIGHT LOAD EFFICIENCY vs SYSTEM LOAD CURRENT Figure 6 BOOST MODE EFFICIENCY vs VBUS LOAD CURRENT Figure 7 SYS VOLTAGE REGULATION vs SYSTEM LOAD Figure 8 BOOST MODE VBUS VOLTAGE REGULATION vs VBUS LOAD CURRENT Figure 9 SYS VOLTAGE vs TEMPERATURE Figure 10 BAT VOLTAGE vs TEMPERATURE Figure 11 INPUT CURRENT LIMIT vs TEMPERATURE Figure 12 CHARGE CURRENT vs TEMPERATURE Figure 13 Power Up from USB100mA (VBAT 3.2V) Figure 14 Power Up with Charge Disabled (VBAT 3.2V) Figure 15 Power Up with Charge Enabled Figure 16 Charge Enable (VBUS 5V) Figure 17 Charge Disable (VBUS 12V) Figure 18 Input Current DPM Response without Battery (VBUS 5V, IIN 3A, Charge Disable) Figure 19 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS (continued) Table 1. Tables of Figures (continued) FIGURE NO. Load Transient during Supplement Mode (VBUS 9V, IIN 1.5A, VBAT 3.8V) Figure 20 PWM Switching Waveform (VBUS 12V, VBAT 3.8V, ICHG 3A) Figure 21 PFM Switching Waveform (VBUS 9V, No Battery, ISYS 10 mA, Charge Disable) Figure 22 Boost Mode Switching Waveform (VBAT 3.8V, ILOAD 1A) Figure 23 Boost Mode Load Transient (VBAT 3.8V) Figure 24 CHARGING EFFICIENCY vs CHARGING CURRENT 95 95 VBUS = 5 V VBUS = 7 V VBUS = 9 V VBUS = 12 V 90 Efficiency (%) 93 Efficiency (%) SYSTEM LIGHT LOAD EFFICIENCY vs SYSTEM LOAD CURRENT 91 89 85 80 87 75 85 70 VBUS = 5 V VBUS = 9 V 0 1 2 3 Load Current (A) 100 4 0 5 100 200 300 400 500 Load Current (mA) C011 600 C012 Figure 5. Figure 6. BOOST MODE EFFICIENCY vs VBUS LOAD CURRENT SYS VOLTAGE REGULATION vs SYSTEM LOAD 3.70 VBAT = 3.2 V VBAT = 3.8 V 3.68 SYS Voltage (V) Efficiency (%) 95 90 85 3.66 3.64 3.62 VBUS = 5 V VBUS = 17 V 3.60 80 0 500 1000 VBUS Load Current (A) 1500 C013 0 1 2 Figure 7. Copyright © 2012, Texas Instruments Incorporated 3 4 System Load Current (A) 5 C014 Figure 8. Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 13 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com BOOST MODE VBUS VOLTAGE REGULATION vs VBUS LOAD CURRENT SYS VOLTAGE vs TEMPERATURE 5.04 3.80 5.02 3.75 5.00 SYS Voltage (V) VBUS Voltage (V) SYSMIN 3.5 V 4.98 4.96 4.94 3.70 3.65 3.60 VBAT = 3.2 V 4.92 3.55 VBAT = 3.8 V VBAT = 4.2 V 4.90 0 200 400 3.50 600 800 1000 1200 ±50 1400 VBUS Load Current (A) 0 50 100 150 Temperature (ƒC) C005 Figure 9. Figure 10. BAT VOLTAGE vs TEMPERATURE INPUT CURRENT LIMIT vs TEMPERATURE 4.25 C001 2000 1800 Input Current Limit (A) BAT Voltage (V) 4.21 4.17 4.13 4.09 1600 1400 1200 1000 IIN = 500 mA 800 IIN = 1.5 A 600 IIN = 2 A VREG = 4.112 V VREG = 4.208 V 4.05 400 ±50 0 50 100 ±50 150 Temperture (ƒC) 0 50 100 150 Temperature (ƒC) C002 Figure 11. Figure 12. CHARGE CURRENT vs TEMPERATURE bq24190 Power Up from USB100mA (VBAT 3.2V) C003 5 4.5 VBUS 5V/div Charge Current (A) 4 3.5 REGN 5V/div 3 2.5 2 SYS 2V/div 1.5 1 IIN 200mA/div TREG 80 C TREG 120 C 0.5 0 40 50 60 70 80 90 100 Temperture (ƒC) 110 120 100ms/div 130 C009 Figure 13. 14 Submit Documentation Feedback Figure 14. Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 bq24192 Power Up with Charge Disabled (VBAT 3.2V) bq24193 Power Up with Charge Enabled VBUS 5V/div VBUS 5V/div REGN 5V/div REGN 5V/div SYS 2V/div SYS 2V/div /PG 2V/div IBAT 2A/div 40ms/div 100ms/div Figure 15. Figure 16. Charge Enable (VBUS 5V) Charge Disable (VBUS 12V) STAT 2V/div STAT 2V/div /CE 5V/div /CE 5V/div SW 5V/div SW 10V/div IBAT 1A/div IBAT 2A/div 400us/div 4us/div Figure 17. Figure 18. Input Current DPM Response without Battery (VBUS 5V, IIN 3A, Charge Disable) Load Transient during Supplement Mode (VBUS 9V, IIN 1.5A, VBAT 3.8V) SYS 3.4V Offset 200mV/div SYS 3.4V offset 200mV/div ISYS 5A/div IIN 2A/div IIN 1A/div IBAT 2A/div ISYS 2A/div 2ms/div 2ms/div Figure 19. Figure 20. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 15 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 PWM Switching Waveform (VBUS 12V, VBAT 3.8V, ICHG 3A) www.ti.com PFM Switching Waveform (VBUS 9V, No Battery, ISYS 10 mA, Charge Disable) SYS 3.4V offset 100mV/div SW 5V/div SW 5V/div IL 1A/div IL 1A/div 0 4us/div 400ns/div Figure 21. Figure 22. Boost Mode Switching Waveform (VBAT 3.8V, ILOAD 1A) Boost Mode Load Transient(VBAT 3.8V) VBUS 5V offset 200mV/div SW 5V/div IBAT 500mA/div IL 1A/div IVBUS 500mA/div 4ms/div 400ns/div Figure 23. 16 Submit Documentation Feedback Figure 24. Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 I2C Registers Address: 6BH. REG00-07 support Read and Write. REG08-0A are read only. Input Source Control Register REG00 (bq24190, bq24192, bq24193 default 00110000, or 30; bq24192I default 00111000, or 38) BIT DESCRIPTION Bit 7 EN_HIZ 0 – Disable, 1 – Enable Input Voltage Limit Bit 6 VINDPM[3] 640mV Bit 5 VINDPM[2] 320mV Bit 4 VINDPM[1] 160mV Bit 3 VINDPM[0] 80mV Input Current Limit (Actual input current limit is the lower of I2C and ILIM) Bit 2 IINLIM[2] 000 – 100mA, 001 – 150mA, 010 – 500mA, 011 – 900mA, 100 – 1.2A, 101 – 1.5A, Bit 1 IINLIM[1] 110 – 2A, 111 – 3A Bit 0 IINLIM[0] Default: Disable (0) Offset 3.88V, Range: 3.88V-5.08V Default: bq24190/bq24192/bq24193: 4.36V (0110) bq24192i: 4.44V (0111) Default SDP: 100mA (000)(OTG pin=0) or 500mA (010) (OTG pin=1) Default DCP/CDP: bq24190/bq24192I: 1.5A (101), bq24192/bq24193: 3A (111) Power-On Configuration Register REG01 (default 00011011, or 1B) BIT Bit 7 Register Reset DESCRIPTION 0 – Keep current register setting, 1 – Reset to default 0 – Normal ; 1 – Reset I2C Watchdog Timer Reset Charger Configuration Bit 5 CHG_CONFIG[1] 00 – Charge Disable, 01 – Charge Battery, 10/11 – OTG Bit 4 CHG_CONFIG[0] Minimum System Voltage Limit Bit 3 SYS_MIN[2] 0.4V Bit 2 SYS_MIN[1] 0.2V Bit 1 SYS_MIN[0] 0.1V Boost Mode Current Limit Bit 0 BOOST_LIM 0 – 500mA, 1 – 1.3A Bit 6 NOTE Default: Keep current register setting (0) Back to 0 after register reset Default: Normal (0) Back to 0 after timer reset Default: Charge Battery (01) Offset: 3.0V, Range 3.0V-3.7V Default: 3.5V (101) Default: 1.3A (1) Charge Current Control Register REG02 (bq24190, bq24192, bq24193 default 01100000, or 60; bq24192I default 00100000, or 20) BIT Fast Charge Current Limit Bit 7 ICHG[5] Bit 6 ICHG[4] Bit 5 ICHG[3] Bit 4 ICHG[2] Bit 3 ICHG[1] Bit 2 ICHG[0] Bit 1 Reserved Bit 0 FORCE_20PCT DESCRIPTION NOTE 2048mA 1024mA 512mA 256mA 128mA 64mA 0 - Reserved 0 – ICHG as REG02[7:2] programmed 1 – ICHG as 20% of REG02[7:2] programmed Offset: 512mA Range: 512-4544mA Default: bq24190, bq24192, bq24193: 2048mA (011000), bq24192I: 1024mA (001000) Copyright © 2012, Texas Instruments Incorporated Default: ICHG as REG02[7:2] programmed (0) Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 17 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Pre-Charge/Termination Current Control Register REG 03 (default 00010001, or 11) BIT DESCRIPTION Pre-Charge Current Limit Bit 7 IPRECHG[3] 1024mA Bit 6 IPRECHG[2] 512mA Bit 5 IPRECHG[1] 256mA Bit 4 IPRECHG[0] 128mA Termination Current Limit Bit 3 ITERM[3] 1024mA Bit 2 ITERM[2] 512mA Bit 1 ITERM[1] 256mA Bit 0 ITERM[0] 128mA NOTE Offset: 128mA, Range: bq24190, bq24192, bq24193: 128mA – 2048mA bq24192I: 128mA – 640mA(0100) Default: 256mA (0001) Offset: 128mA Range: 128mA – 2048mA Default: 256mA (0001) Charge Voltage Control Register REG04 (bq24190, bq241192, bq241193 default: 10110010, or B2; bq24192I default 10011010, or 9A) BIT DESCRIPTION Charge Voltage Limit Bit 7 VREG[5] 512mV Bit 6 VREG[4] 256mV Bit 5 VREG[3] 128mV Bit 4 VREG[2] 64mV Bit 3 VREG[1] 32mV Bit 2 VREG[0] 16mV Battery Precharge to Fast Charge Threshold Bit 1 BATLOWV 0 – 2.8V, 1 – 3.0V Battery Recharge Threshold (below battery regulation voltage) Bit 0 VRECHG 0 – 100mV, 1 – 300mV NOTE Offset: 3.504V Range: 3.504V – 4.400V (111000) Default: bq24190, bq24192, bq24193: 4.208V (101100) bq24192I: 4.112V (100110) Default: 3.0V (1) Default: 100mV (0) Charge Termination/Timer Control Register REG05 (default 10011010, or 9A) BIT DESCRIPTION Charging Termination Enable Bit 7 EN_TERM 0 – Disable, 1 – Enable Termination Indicator Threshold Bit 6 TERM_STAT 0 – Match ITERM, 1 – STAT pin high before actual termination when charge current below 800 mA I2C Watchdog Timer Setting Bit 5 WATCHDOG[1] 00 – Disable timer, 01 – 40s, 10 – 80s, 11 – Bit 4 WATCHDOG[0] 160s Charging Safety Timer Enable Bit 3 EN_TIMER 0 – Disable, 1 – Enable Fast Charge Timer Setting Bit 2 CHG_TIMER[1] 00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, 11 – 20 Bit 1 CHG_TIMER[0] hrs JEITA Low Temperature Current Setting Bit 0 JEITA_ISET 0 – 50%, 1 – 20% (0°C-10°C) 18 Submit Documentation Feedback NOTE Default: Enable termination (1) Default Match ITERM (0) Default: 40s (01) Default: Enable (1) Default: 8hours (01) (See Charging Safety Timer for details) Percentage w.r.t ICHG REG02[7:2] Default: 50% (0) Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 IR Compensation / Thermal Regulation Control Register REG06 (default 00000011, or 03) BIT DESCRIPTION IR Compensation Resistor Setting Bit 7 BAT_COMP[2] 40mΩ Bit 6 BAT_COMP[1] 20mΩ Bit 5 BAT_COMP[0] 10mΩ IR Compensation Voltage Clamp (above regulation voltage) Bit 4 VCLAMP[2] 64mV Bit 3 VCLAMP[1] 32mV Bit 2 VCLAMP[0] 16mV Thermal Regulation Threshold Bit 1 TREG[1] 00 – 60°C, 01 – 80°C, 10 – 100°C, 11 – 120°C Bit 0 TREG[0] NOTE Range: 0 – 70mΩ Default: 0Ω (000) Range: 0 – 112 mV Default: 0mV (000) Default: 120°C (11) Misc Operation Control Register REG07 (default 01001011, or 4B) BIT DESCRIPTION NOTE Force DPDM detection (bq24190) or set default input current limit from PSEL/OTG pins (bq24192, bq24192I, bq24193) Bit 7 DPDM_EN 0 – Not in D+/D– detection; Default: Not in D+/D– detection (0), Back to 0 after detection complete 1 – Force D+/D– detection Safety Timer Setting during Input DPM and Thermal Regulation Bit 6 TMR2X_EN 0 – Safety timer not slowed by 2X during input DPM Default: Safety timer slowed by 2X (1) or thermal regulation, 1 – Safety timer slowed by 2X during input DPM or thermal regulation Force BATFET Off Bit 5 BATFET_Disable 0 – Allow Q4 turn on, 1 – Turn off Q4 Default: Allow Q4 turn on(0) Bit 4 JEITA_VSET (45°C0 – 4.05V, 1 – 4.2V Default: 4.05V (0) 60°C) Bit 3 Reserved 1 - Reserved Bit 2 Reserved 0 - Reserved Bit 1 INT_MASK[1] 0 – No INT during CHRG_FAULT, 1 – INT on Default: INT on CHRG_FAULT (1) CHRG_FAULT Bit 0 INT_MASK[0] 0 – No INT during BAT_FAULT, 1 – INT on Default: INT on BAT_FAULT (1) BAT_FAULT System Status Register REG08 BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] CHRG_STAT[0] DPM_STAT PG_STAT THERM_STAT VSYS_STAT DESCRIPTION 00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 – OTG 00 – Not Charging, 01 – Pre-charge (<VBATLOWV), 10 – Fast Charging, 11 – Charge Termination Done 0 – Not DPM, 1 – VINDPM or IINDPM 0 – Not Power Good, 1 – Power Good 0 – Normal, 1 – In Thermal Regulation 0 – Not in VSYSMIN regulation (BAT>VSYSMIN), 1 – In VSYSMIN regulation (BAT<VSYSMIN) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 19 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Fault Register REG09 BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WATCHDOG_FAULT BOOST_FAULT CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT NTC_FAULT[2] NTC_FAULT[1] NTC_FAULT[0] DESCRIPTION 0 – Normal, 1- Watchdog timer expiration 0 – Normal, 1 – VBUS overloaded (OCP), or VBUS OVP in boost mode 00 – Normal, 01 – Input fault (VBUS OVP or VBAT<VBUS<3.8V), 10 - Thermal shutdown, 11 – Charge Safety Timer Expiration 0 – Normal, 1 – BATOVP bq24190, bq24192, bq24192I: 000 – Normal, 001 – TS1 Cold, 010 – TS1 Hot, 011 – TS2 Cold, 100 – TS2 Hot, 101 – Both Cold, 110 – Both Hot bq24193: 000 – Normal, 010 – Warm, 011 – Cool, 101 – Cold, 110 – Hot Vender / Part / Revision Status Register REG0A BIT Bit 7 Reserved Bit 6 Reserved Device Configuration Bit 5 PN[2] Bit 4 PN[1] Bit 3 PN[0] Bit 2 TS_PROFILE Bit 1 DEV_REG[0] Bit 0 DEV_REG[1] DESCRIPTION 0 - Reserved 0 - Reserved bq24190 – 100, bq24192, bq24193 – 101, bq24192I – 011 0 – Cold/Hot window (bq24190, bq24192, bq24192I), 1 – JEITA profile (bq24193) 11 DETAILED DESCRIPTION The bq24190, bq24192, bq24192I, bq24193 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between system and battery. The device also integrates the bootstrap diode for the high-side gate drive. Device Power Up Power-On-Reset (POR) The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR. Power Up from Battery without DC Source If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again. BATFET Turn Off The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and supplement mode. 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 Shipping Mode When end equipment is assembled, the system is connected to battery through BATFET. There will be a small leakage current to discharge the battery even when the system is powered off. In order to extend the battery life during shipping and storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage. In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4]=00) and disable BATFET (REG07[5]=1) at the same time. Once the BATFET is disabled, the BATFET can be turned on by plugging in adapter. Power Up from DC Source When the DC source plugs in, the bq24190, bq24192, bq24192I, bq24193 checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter. REGN LDO The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS1/TS2 external resistors. The pull-up rail of STAT and PG can be connected to REGN as well. The REGN is enabled when all the conditions are valid. 1. VBUS above UVLOZ 2. VBUS above battery + VSLEEPZ in buck mode or VBUS below battery + VSLEEPZ in boost mode 3. After typical 220ms delay (100ms minimum) is complete If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than 50µA from VBUS during HIZ state. The battery powers up the system when the device is in HIZ. Input Source Qualification After REGN LDO powers up, the bq24190, bq24192, bq24192I, bq24193 checks the current capability of the input source. The input source has to meet the following requirements to start the buck converter. 1. VBUS voltage below 18V (not in ACOV) 2. VBUS voltage above 3.8V when pulling 30mA (poor source detection) Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin (bq24192, bq24192I, bq24193) goes low. An INT is asserted to the host. If the device fails the poor source detection, it will repeat the detection every 2 seconds. Input Current Limit Detection The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable device is attached to a USB host, the USB specification requires the portable device to draw limited current (100mA/500mA in USB 2.0, and 150mA/900mA in USB 3.0). If the portable device is attached to a charging port, it is allowed to draw up to 1.5A. After the PG is LOW or REG08[2] goes HIGH, the charger device always runs input current limit detection when a DC source plugs in unless the charger is in HIZ during host mode. The bq24190 follows battery charging specification 1.2 (bc1.2) to detect input source through USB D+/D– lines. The bq24192, bq24192I, bq24193 sets input current limit through PSEL and OTG pins. After the input current limit detection is done, the host can write to REG00[2:0] to change the input current limit. D+/D– Detection Sets Input Current Limit in bq24190 The bq24190 contains a D+/D– based input source detection to program the input current limit. The D+/Ddetection has two steps: data contact detect (DCD) followed by primary detection. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 21 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com D+ VDP_SRC VLGC_HI IDP_SRC CHG_DET VDAC_REF IDM_SINK D- RDM_DWN Figure 25. USB D+/D- Detection DCD (Data Contact Detection) uses a current source to detect when the D+/D– pins have made contact during an attach event. The protocol for data contact detect is as follows: • Detect VBUS present and REG08[2]=1 (power good) • Turn on D+ IDP_SRC and the D– pull-down resistor RDM_DWN for 40ms • If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec. • Turn off IDP_SRC and disconnect RDM_DWN The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP). The protocol for primary detection is as follows: • Turn on VDP_SRC on D+ and IDM_SINK on D– for 40ms • If PD is attached to a USB host (SDP), the D– is low. If PD is attached to a charging port (CDP or DCP), the D– is high • Turn off VDP_SRC and IDM_SINK Table 2 shows the input current limit setting after D+/D– detection. Table 2. bq24190 USB D+/D– Detection D+/D– DETECTION OTG INPUT CURRENT LIMIT REG08[7:6] 0.5 sec timer expired in DCD (D+/D- floating) — 100 mA 00 USB Host LOW 100 mA 01 USB Host HIGH 500 mA 01 Charging Port — 1.5 A 10 PSEL/OTG Pins Set Input Current Limit in bq24192, bq24192I, bq24193 The bq24192, bq24192I, bq24193 has PSEL instead of D+/D–. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. Table 3. bq24192, bq24192I, bq24193 Input Current Limit Detection 22 PSEL OTG INPUT CURRENT LIMIT REG08[7:6] HIGH LOW 100 mA 01 HIGH HIGH 500 mA 01 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 Table 3. bq24192, bq24192I, bq24193 Input Current Limit Detection (continued) PSEL LOW OTG INPUT CURRENT LIMIT REG08[7:6] — 1.5A (bq24192I) 3A (bq24192, bq24193) 10 HIZ State wth 100mA USB Host In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the portable device successfully. When the input source is 100mA USB host, and the battery is above bat-good threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state, the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets REG00[7] to 1, and the VBUS current during HIZ state will be less than 30µA. The system is supplied by the battery. Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7]=0. When the processor host wakes up, it is recommended to first check if the charger is in HIZ state. In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another source plugs in, the charger IC will run detection again, and update the input current limit. Force Input Current Limit Detection The host can force the charger device to run input current limit detection by setting REG07[7]=1. After the detection is complete, REG07[7] will return to 0 by itself. Converter Power-Up After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery. The bq24190, bq24192, bq24192I, bq24193 provides soft-start when ramp up the system rail. When the system rail is below 2.2V, the input current limit is forced to 100mA. After the system rises above 2.2V, the charger device sets the input current limit set by the lower value between register and ILIM pin. As a battery charger, the bq24190, bq24192, bq24192I, bq24193 deploys a 1.5MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design. A type III compensation network allows using ceramic capacitors at the output of the converter. An internal sawtooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage. In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS. Boost Mode Operation from Battery The bq24190, bq24192, bq24192I, bq24193 supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 500mA output requirement. The maximum output current is 1.3A. The boost operation can be enabled if the following conditions are valid: 1. BAT above BATLOWV threshold (VBATLOWV set by REG04[1]) 2. VBUS less than BAT+VSLEEP (in sleep mode) 3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4]=10) 4. After 220ms delay from boost mode enable In boost mode, the bq24190, bq24192, bq24192I, bq24193 employs a 1.5MHz step-up switching regulator. Similar to buck operation, the device switches from PWM operation to PFM operation at light load to improve efficiency. During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5V and the output current can reach up to 500mA or 1.3A, selected via I2C (REG01[0]). Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 23 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Any fault during boost operation, including VBUS over-voltage or over-current, sets the fault register REG09[6] to 1 and an INT is asserted. Power Path Management The bq24190, bq24192, bq24192I, bq24193 accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both. Narrow VDC Architecture The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5V). When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET. When the battery charging is disabled or terminated, the system is always regulated at 150mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation. 4.5 4.3 Charge Enabled 4.1 SYS (V) Charge Disabled 3.9 3.7 3.5 Minimum System Voltage 3.3 3.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 BAT (V) Figure 26. V(SYS) vs V(BAT) Dynamic Power Management To meet maximum current limit in USB spec and avoid over loading the adapter, the bq24190, bq24192, bq24192I, bq24193 features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit. When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery. During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high. Figure 27 shows the DPM response with 9V/1.2A adapter, 3.2V battery, 2.8A charge current and 3.4V minimum system voltage setting. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 Voltage VBUS 9V SYS 3.6V 3.4V 3.2V 3.18V BAT Current 4A ICHG 3.2A 2.8A ISYS 1.2A 1.0A 0.5A IIN -0.6A DPM DPM Supplement Figure 27. DPM Response Supplement Mode When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Figure 28 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold. 4.5 4.0 CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 V(BAT-SYS) (mV) Figure 28. BATFET V-I Curve Battery Charging Management The bq24190, bq24192, bq24192I, bq24193 charges 1-cell Li-Ion battery with up to 4.5A charge current for high capacity tablet battery. The 12mΩ BATFET improves charging efficiency and minimizes the voltage drop during discharging. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 25 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Autonomous Charging Cycle With battery charging enabled at POR (REG01[5:4]=01), the bq24190, bq24192, bq24192I, bq24193 can complete a charging cycle without host involvement. The device default charging parameters are listed in Table 4. Table 4. Charging Parameter Default Setting (1) A • • • • • DEFAULT MODE bq24190, bq24192 bq24192I bq24193 Charging Voltage 4.208 V 4.112 V 4.208 V Charging Current 2.036 A 1.012 A 2.036 A Pre-charge Current 256 mA 256 mA 256 mA Termination Current 256 mA 256 mA 256 mA Temperature Profile Hot/Cold Hot/Cold JEITA Safety Timer 8 hours (1) 8 hours (1) 8 hours (1) See section Charging Safety Timer for more information. new charge cycle starts when the following conditions are valid: Converter starts Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low No thermistor fault on TS1 and TS2 No safety timer fault BATFET is not forced to turn off (REG07[5]) The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the bq24190, bq24192, bq24192I, bq24193 automatically starts another charging cycle. The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host. The host can always control the charging operation and optimize the charging parameters by writing to the registers through I2C. Battery Charging Profile The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current. Table 5. Charging Current Setting 26 VBAT CHARGING CURRENT REG DEFAULT SETTING REG08[5:4] <2V 100mA – 01 2V-3V REG03[7:4] 256mA 01 >3V REG02[7:2] 2048mA (bq24190/192/193) 1024mA (bq24192I) 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate. Regulation Voltage (3.5V – 4.4V) Battery Voltage Fast Charge Current (500mA-4020mA) Charge Current VBAT_LOWV (2.8V/3V) VBAT_SHORT (2V) IPRECHARGE (128mA-2048mA) ITERMINATION (128mA-2048mA) IBATSHORT (100mA) Trickle Charge Pre-charge Fast Charge and Voltage Regulation Safety Timer Expiration Figure 29. Battery Charging Profile Battery Path Impedance IR Compensation To speed up the charging cycle, we would like to stay in constant current mode as long as possible. In real system, the parasitic resistance, including routing, connector, MOSFETs and sense resistor in the battery pack, may force the charger device to move from constant current loop to constant voltage loop too early, extending the charge time. The bq24190, bq24192, bq24192I, bq24193 allows the user to compensate for the parasitic resistance by increasing the voltage regulation set point according to the actual charge current and the resistance. For safe operation, the user should set the maximum allowed regulation voltage to REG06[4:2], and the minimum trace parasitic resistance (REG06[7:5]). ( ) VBATREG_ACTUAL = VBATREG_I2C + lower of ICHRG_ACTUAL × RCOMP and VCLAMP (1) Thermistor Qualification The high capacity battery usually has two or more single cells in parallel. The bq24190, bq24192, bq24192I provides two TS pins to monitor the thermistor (NTC) in each cell independently. The bq24193 applies JEITA profile with TS1/TS2 shorted. Cold/Hot Temperature Window (bq24190, bq24192, bq24192I) The bq24190, bq24192, bq24192I continuously monitors battery temperature by measuring the voltage between the TS pins and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits until the battery temperature is within the VLTF to VHTF range. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 27 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com REGN bq2419x RT1 TS RT2 RTH 103AT Figure 30. TS Resistor Network When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended. TEMPERATURE RANGE TO INITIATE CHARGE TEMPERATURE RANGE DURING A CHARGE CYCLE VREF VREF CHARGE SUSPENDED CHARGE SUSPENDED VLTF VLTF VLTFH VLTFH CHARGE at full C CHARGE at full C VHTF VTCO CHARGE SUSPENDED CHARGE SUSPENDED AGND AGND Figure 31. TS Pin Thermistor Sense Thresholds Assuming a 103AT NTC thermistor is used on the battery pack Figure 31, the value RT1 and RT2 can be determined by using the following equation: æ 1 1 ö VVREF ´ RTHCOLD ´ RTHHOT ´ ç ÷ VLTF VTCO ø è RT2 = æV ö æV ö RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷ è VLTF ø è VTCO ø VVREF -1 VLTF RT1 = 1 1 + RT2 RTHCOLD (2) Select 0°C to 45°C range for Li-ion or Li-polymer battery, RTHCOLD = 27.28 kΩ RTHHOT = 4.911 kΩ RT1 = 5.52 kΩ RT2 = 31.23 kΩ 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 JEITA Guideline Compliance (bq24193) To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges. To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the T1–T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5 range. At cool temperature (T1–T2), JEITA recommends the charge current to be reduced to at least half of the charge current or lower. At warm temperature (T3–T5), JEITA recommends charge voltage less than 4.1V. The bq24193 provides flexibility voltage/current settings beyond the JEITA requirement. The voltage setting at warm temperature (T3–T5) can be 4.2V or 4.05V (REG07 bit[4]). The current setting at cool temperature (T1–T2) can be further reduced to 20% of fast charge current (REG05 bit[0]). bq2419x Charging Current 1ICHG 4.2V bq2419x Charging Voltage VSET=1 4.10V 4.05V 0.5ICHG ISET=1 VSET=0 0.2ICHG ISET=0 T1 T2 00C 100C T3 450C T5 60 0C T1 T2 00C 100C T3 450C T5 600C The resistor bias network has been updated as below. 1 ö æ 1 VVREF ´ RTHCOLD ´ RTHHOT ´ ç ÷ VT1 VT5 è ø RT2 = æ VVREF ö æ VVREF ö RTHHOT ´ ç - 1÷ - RTHCOLD ´ ç - 1÷ VT5 VT1 è ø è ø VVREF -1 VT1 RT1 = 1 1 + RT2 RTHCOLD (3) Select 0°C to 60°C range for Li-ion or Li-polymer battery, RTHT1 = 27.28 kΩ RTHT5 = 3.02 kΩ RT1 = 2.27 kΩ RT2 = 6.86 kΩ Charging Termination The bq24190, bq24192, bq24192I, bq24193 terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode. When termination occurs, the status register REG09[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7]. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 29 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Termination when REG02[0] = 1 When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the termination current. The charger device termination function should be disabled. When the battery is charged to fully capacity, the host disables charging through CE pin or REG01[5:4]. Termination when REG05[6] = 1 Usually the STAT bit indicates charging complete when the charging current falls below termination threshold. Write REG05[6]=1 to enable an early “charge done” indication on STAT pin. The STAT pin goes high when the charge current reduces below 800mA. The charging cycle is still on-going until the current falls below the termination threshold. Charging Safety Timer The bq24190, bq24192, bq24192I, bq24193 has safety timer to prevent extended charging cycle due to abnormal battery conditions. In default mode, the device keeps charging the battery with 5-hour fast charging safety timer regardless of REG05[2:1] default value. At the end of the 5 hours, the EN_HIZ (REG00[7]) is set to signal the buck converter stops and the system load is supplied by the battery. The EN_HIZ bit can be cleared to restart the buck converter. In host mode, the device keeps charging the battery until the fast charging safety timer expired. The duration of safety timer can be set by the REG05[2:1] bits (default = 8 hours). At the end of safety timer, the EN_HIZ (REG00[7]) is cleared to signal the buck converter continues to operation to supply system load. The safety timer is 1 hour when the battery is below BATLOWV threshold. The user can program fast charge safety timer through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]). The following actions restart the safety timer: • At the beginning of a new charging cycle • Toggle the CE pin HIGH to LOW to HIGH (charge enable) • Write REG01[5:4] from 00 to 01 (charge enable) • Write REG05[3] from 0 to 1 (safety timer enable) • Write REG01[7] to 1 (software reset) During input voltage/current regulation or thermal regulation, the safety timer counts at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6]. USB Timer when Charging from USB100mA Source The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ. Host Mode and Default Mode The bq24190, bq24192, bq24192I, bq24193 is a host controlled device, but it can operate in default mode without host management. In default mode, bq24190, bq24192, bq24192I, bq24193 can be used as an autonomous charger with no host or with host in sleep. When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW. After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in the default settings. Any write command to bq24190, bq24192, bq24192I, bq24193 transitions the device from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting REG05[5:4]=11. 30 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 POR watchdog timer expired Reset registers I2C interface enabled Host Mode Y I2C Write? Start watchdog timer Host programs registers N Default Mode Reset watchdog timer Reset registers N Reset REG01 bit[6]? Y Y N I2C Write? Y Watchdog Timer Expired? N Figure 32. Watchdog Timer Flow Chart Plug in USB100mA Source with Good Battery When the input source is detected as 100mA USB host, and the battery voltage is above batgood threshold (VBATGD), the charger device enters HIZ state to meet the battery charging spec requirement. If the charger device is in host mode, it will stay in HIZ state even after the USB100mA source is removed, and the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The host can write REG00[7] to 0 to exit HIZ state. If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state automatically. When the input source plugs in again, the charger IC runs detection on the input source and update the input current limit. USB Timer when Charging from USB100mA Source The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ. Status Outputs (PG, STAT, and INT) Power Good Indicator (PG) In bq24192, bq24192I, bq24193, PG goes LOW to indicate a good input source when: 1. VBUS above UVLO 2. VBUS above battery (not in sleep) 3. VBUS below ACOV threshold 4. VBUS above 3.8V when 30mA current is applied (not a poor source) Charging Status Indicator (STAT) The bq24190, bq24192, bq24192I, bq24193 indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 31 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Table 6. STAT Pin State CHARGING STATE STAT Charging in progress (including recharge) LOW Charging complete HIGH Sleep mode, charge disable HIGH Charge suspend (Input over-voltage, TS fault, timer fault, input or system overvoltage) blinking at 1Hz (bq24190, bq24192, bq24193) or 10kΩ pull down (bq24192I) When a fault occurs, instead of blinking, the STAT pin in bq24192I has a 10kΩ pull-down resistor to ground. When the pull-up resistor is 30kΩ, the STAT voltage during fault is 1/4 of the pull-up rail. Interrupt to Host (INT) In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256us INT pulse. • USB/adapter source identified (through PSEL or DPDM detection, with OTG pin) • Good input source detected – not in sleep – not in ACOV – current limit above 30mA • Input removed or ACOV • Charge Complete • Any FAULT event in REG09 When a fault occurs, the charger device sends out INT and latches the fault state in REG09 until the host reads the fault register. Before the host reads REG09, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC fault is not latched and always reports the current thermistor conditions. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads fault register status from the last INT and the 2nd reads the current fault register status. Protections Input Current Limit on ILIM For safe operation, the bq24190, bq24192, bq24192I, bq24193 has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as: 1V IINMAX = ´ 530 RILIM (4) The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3A, and ILIM has a 353Ω resistor to ground for 1.5A, the input current limit is 1.5A. ILIM pin can be used to set the input current limit rather than the register settings. The device regulates ILIM pin at 1V. If ILIM voltage exceeds 1V, the device enters input current regulation (Refer to Dynamic Power Path Management section). The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current following Equation 5: V IIN = ILIM ´ IINMAX (5) 1V For example, if ILIM pin sets 2A, and the ILIM voltage is 0.6V, the actual input current 1.2A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1V. If ILIM pin is short, the input current limit is set by the register. 32 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 Thermal Regulation and Thermal Shutdown The bq24190, bq24192, bq24192I, bq24193 monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the user to optimize the system thermal performance. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high. Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host. Voltage and Current Monitoring in Buck Mode The bq24190, bq24192, bq24192I, bq24193 closely monitors the input and system voltage, as well as HSFET and LSFET current for safe buck mode operation. Input Over-Voltage (ACOV) The maximum input voltage for buck mode operation is 18V. If VBUS voltage exceeds 18V, the device stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT is asserted to the host. System Over-Voltage Protection (SYSOVP) The charger device monitors the voltage at SYS. When system over-voltage is detected, the converter is stopped to protect components connected to SYS from high voltage damage. Voltage and Current Monitoring in Boost Mode The bq24190, bq24192, bq24192I, bq24193 closely monitors the VBUS voltage, as well as HSFET and LSFET current to ensure safe boost mode operation. VBUS Over-Voltage Protection The boost mode regulated output is 5V. When an adapter plugs in during boost mode, the VBUS voltage will rise above regulation target. Once the VBUS voltage exceeds 5.3V, the bq24190, bq24192, bq24192I, bq24193 stops switching and the device exits boost mode. The fault register REG09[6] is set high to indicate fault in boost operation. An INT is asserted to the host. Battery Protection Battery Over-Current Protection (BATOVP) The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[5] goes high and an INT is asserted to the host. Charging During Battery Short Protection If the battery voltage falls below 2V, the charge current is reduced to 100mA for battery safety. System Over-Current Protection If the system is shorted or exceeds the over-current limit, the BATFET is latched off. DC source insertion on VBUS is required to reset the latch-off condition and turn on BATFET. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 33 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com Serial Interface The bq24190, bq24192, bq24192I, bq24193 uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100kbits), and fast mode (up to 400kbits). Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pullup resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain. Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred. SDA SCL Data line stable; Data valid Change of data allowed Figure 33. Bit Transfer on the I2C Bus START and STOP Conditions All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition. SDA SDA SCL SCL STOP (P) START (S) Figure 34. START and STOP conditions 34 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 Byte Format Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL. Acknowledgement signal from receiver Acknowledgement signal from slave MSB SDA SCL S or Sr 2 1 7 8 2 1 9 ACK START or Repeated START 8 9 ACK P or Sr STOP or Repeated START Figure 35. Data Transfer on the I2C Bus Acknowledge (ACK) and Not Acknowledge (NACK) The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer. Slave Address and Data Direction Bit After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). SDA SCL S 1-7 8 9 START ADDRESS R/W ACK 8 1-7 9 8 1-7 ACK DATA DATA 9 P ACK STOP Figure 36. Complete Data Transfer Single Read and Write 1 7 1 1 8 1 8 1 1 S Slave Address 0 ACK Reg Addr ACK Data Addr ACK P Figure 37. Single Write 1 7 1 1 8 1 1 7 1 1 S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK 8 1 1 Data NCK P Figure 38. Single Read Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 35 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com If the register address is not defined, the charger IC send back NACK and go back to the idle state. Multi-Read and Multi-Write The charger device supports multi-read and multi-write on REG00 through REG08. 1 7 1 1 8 1 S Slave Address 0 ACK Reg Addr ACK 8 1 8 1 8 1 1 Slave Address ACK Data to Addr+1 ACK Data to Addr+1 ACK P Figure 39. Multi-Write 1 7 1 1 8 1 1 7 1 1 S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK 8 Data @ Addr 1 8 1 8 1 1 ACK Data @ Addr+1 ACK Data @ Addr+1 ACK P Figure 40. Multi-Read The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write. 36 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 bq24190, bq24192 bq24192I, bq24193 www.ti.com SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 APPLICATION INFORMATION Inductor Selection The bq24190, bq24192, bq24192I, bq24193 has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ³ ICHG + (1/ 2 ) IRIPPLE (6) The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs) and inductance (L): V ´ D ´ (1 - D) IRIPPLE = IN ¦s ´ L (7) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. Typical inductor value is 2.2µH. Input Capacitor Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation: ICIN = ICHG ´ D ´ (1 - D) (8) For best performance, VBUS should be decouple to PGND with 1μF capacitance. The remaining input capacitor should be place on PMID. Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 15V input voltage. Output Capacitor Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given: I ICOUT = RIPPLE » 0.29 ´ IRIPPLE 2´ 3 (9) The output capacitor voltage ripple can be calculated as follows: VOUT æç VOUT ö÷ 1 DVO = VIN ÷ 8LC¦ s2 çè ø (10) At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The charger device has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 15kHz and 25kHz. With 2.2µH inductor, the typical output capacitor value is 20µF. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24190 bq24192 bq24192I bq24193 37 bq24190, bq24192 bq24192I, bq24193 SLUSAW5A – JANUARY 2012 – REVISED OCTOBER 2012 www.ti.com PCB Layout The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 41) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane. 2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane. 4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground. 5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible. 7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 8. The via size and number should be enough for a given current path. See the EVM design for the recommended component placement with trace and via locations. For the QFN information, refer to SCBA017 and SLUA271. Figure 41. High Frequency Current Path 38 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: bq24190 bq24192 bq24192I bq24193 PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) BQ24190RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24190RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24192IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24192IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24192RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24192RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24193RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24193RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing BQ24190RGER VQFN RGE 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24190RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24192IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24192IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24192RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24192RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24193RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24193RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24190RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24190RGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24192IRGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24192IRGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24192RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24192RGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24193RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24193RGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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