Gennum GS9005BCPJ Genlinx-tm gs9005b serial digital receiver Datasheet

GENLINX ™ GS9005B
Serial Digital Receiver
DATA SHEET
FEATURES
DEVICE DESCRIPTION
•
The GS9005B is a monolithic IC designed to receive SMPTE
259M serial digital video signals. This device performs the
functions of automatic cable equalization and data and clock
recovery.
It interfaces directly with the GENLINX™
GS9000B or GS9000S decoder, and GS9010A Automatic
Tuning Subsystem.
•
•
•
•
•
•
automatic cable equalization (typically 300m of high
quality cable at 270Mb/s)
fully compatible with SMPTE 259M and operational
to 400 Mb/s
adjustment free receiver when used with the
GS9000B or GS9000S decoder and GS9010A
Automatic Tuning Sub-system
signal strength indicator
selectable cable or direct digital inputs
28 pin PLCC packaging
Pb-free and Green
The VCO centre frequencies are controlled by external resistors
which can be selected by applying a two bit binary code to the
Standards Select input pins.
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An additional feature is the Signal Strength Indicator output
which provides a 0.5V to 0V analog output relative to VCC
indicating the amount of equalization being applied to the
signal.
APPLICATIONS
• 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces
The GS9005B is packaged in a 28 pin PLCC operating from
a single +5 or -5 volt supply.
ORDERING INFORMATION
Part Number
Package
Temperature
Pb-Free and Green
GS9005BCPJ
28 Pin PLCC
0°C to 70°C
No
GS9005BCTJ
28 Pin PLCC
Tape
0°C to 70°C
No
GS9005BCPJE3
28 Pin PLCC
0°C to 70°C
Yes
SPECIAL NOTE: RVCO1 and RVCO2 are functional over a
reduced temperature range of TA=0° C to 50° C. RVCO0
and RVCO3 are functional over the full temperature range
of TA=0° C to 70° C. This limitation does not affect
operation with the GS9010A ATS.
GS9005B
28
SIGNAL
STRENGTH
INDICATOR
FILTER
CONTROL
16
PEAK
DETECTOR
VOLTAGE
VARIABLE
FILTER
CABLE 8,9
IN
AGC
2 CAPACITOR
OUTPUT 'EYE'
MONITOR
LOGIC
COMPARATOR
DC
RESTORER
Σ
ANALOG
DIGITAL
SELECT
EQUALIZER
1
A/D
DIGITAL 5,6
IN
24
DATA
LATCH
25
SERIAL DATA
SERIAL DATA
22
23
SERIAL CLOCK
SERIAL CLOCK
PHASE
COMPARATOR
CARRIER
DETECT
10
19
CARRIER
DETECT
÷2
ƒ/2 ENABLE
CHARGE
PUMP
20
LOOP
FILTER 12
VCO
STANDARD
SELECT
21
SS0
SS1
PLL
13 14 15 17
Revision Date: July 2004
FUNCTIONAL BLOCK DIAGRAM
Document No. 32466 - 0
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan
Tel: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE / UNITS
Supply Voltage
CAUTION
ELECTROSTATIC
5.5 V
SENSITIVE DEVICES
Input Voltage Range (any input)
VCC+0.5 to VEE-0.5 V
DC Input Current (any one input)
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
5 mA
Power Dissipation
750 mW
0°C £ TA £70°C
Operating Temperature Range
-65°C £ TS£150°C
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
260°C
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GS9005B RECEIVER DC ELECTRICAL CHARACTERISTICS
VS = 5V, T A = 0°C to 70°C, R L = 100Ω to (VCC - 2V) unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
Operating Range
MIN
TYP
MAX
UNITS
4.75
5.0
5.25
V
NOTES
Supply Voltage
VS
Power Consumption
PD
-
500
700
mW
Supply Current (Total)
IS
-
122
160
mA
Serial Data &
- High
VOH
TA = 25°C
-1.025
-
-0.88
V
with respect to VCC
Clock Output
- Low
VOL
TA = 25°C
-1.9
-
-1.6
V
with respect to V CC
see Figure13
Logic Inputs
- High
VIH MIN
+2.0
-
-
V
with respect to V EE
(1, 10, 20, 21)
- Low
VIL MAX
-
-
+0.8
V
with respect to VEE
-
0.2
0.4
V
with respect to VEE Open
4.0
5.0
-
V
Collector - Active High
-0.6
-
0
V
with respect to VCC
200
-
2000
mVp-p
Differential Drive
MAX
UNITS
NOTES
Carrier Detect
VCDL
Output Voltage
VCDH
Signal Strength
Indicator Output
Direct Digital Input
VSS
RL = 10 kΩ to V CC
See Note 2
VDDI
Levels (5, 6)
GS9005B RECEIVER AC ELECTRICAL CHARACTERISTICS
VS = 5V, TA = 0°C to 70°C, RL = 100Ω to (V CC - 2V) unless otherwise shown.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
Serial Data Bit Rate
BRSDO
TA = 25°C
100
-
400
Mb/s
Serial Clock Frequency
ƒSLK
TA = 25°C
100
-
400
MHz
see Figure11
Output Signal Swing
VO
TA = 25°C
700
800
900
mV p-p
see Figure12
Serial Data to Serial Clock
Synchronization
td
See Waveforms
-
-500
-
ps
Lock Times
tLOCK
See Note 1
-
-
10
µs
Equalizer Gain
AVEQ
TA = 25°C
30
36
-
dB
Jitter
tJ
TA = 25°C
-
±100
-
ps p-p
Data lags Clock
at 135 MHz
see Figure15
0 metres, 270 Mb/s
Input Resistance (SDI/SDI)
R IN
TA = 25½C
3k
5k
-
Ω
Input Capacitance (SDI/SDI)
CIN
T A = 25½C
-
1.8
-
pF
Output Eye Monitor
VOEM
RL = 50Ω to V CC
40
-
mVp-p
-
see Figure14
see Figure14
NOTES: 1. Switching between two sources of the same data rate.
2. With weaker signals VSS approaches VCC.
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GS9005B Re - clocking Receiver - Detailed Device Description
The GS9005B Reclocking Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and circuitry
necessary to re-clock and regenerate the NRZI serial data
stream.
Packaged in a 28 pin PLCC, the receiver operates from a
single five volt supply at data rates in excess of 400 Mb/s.
Typical power consumption is 500 mW. Typical output jitter is
±100 ps at 270 Mb/s.
Serial Digital signals are applied to either a built-in analog
cable equalizer via the SDI and SDI inputs (pins 8,9) or via the
direct digital inputs DDI and DDI (pins 5,6).
A logical HIGH applied to the Analog/Digital Select input (1)
routes the equalized signal while a logic LOW routes the
direct digital signal to the reclocker.
Phase Locked Loop
The phase comparator itself compares the position of
transitions in the incoming signal with the phase of the local
oscillator (VCO). The error-correcting output signals are fed
to the charge pump in the form of short pulses. The charge
pump converts these pulses into a “charge packet” which is
accurately proportional to the system phase error.
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The charge packet is then integrated by the second-order
loop filter to produce a control voltage for the VCO.
Cable Equalizer
The Serial Digital signal is connected to the input either
differentially or single ended with the unused input being
decoupled. The equalized signal is generated by passing the
cable signal through a voltage variable filter having a
characteristic which closely matches the inverse cable loss
characteristic. Additionally, the variation of the filter
characteristic with control voltage is designed to imitate the
variation of the inverse cable loss characteristic as the cable
length is varied.
The amplitude of the equalized signal is monitored by a peak
detector circuit which produces an output current with a
polarity corresponding to the difference between the desired
peak signal level and the actual peak signal level. This output
is integrated by an external AGC filter capacitor (AGC
CAP pin 2), providing a steady control voltage for the voltage
variable filter.
A separate signal strength indicator output, (SSI pin 28),
proportional to the amount of AGC is also provided. As the
filter characteristic is varied automatically by the application
of negative feedback, the amplitude of the equalized signal is
kept at a constant level which is representative of the original
amplitude at the transmitter.
The equalized signal is then DC restored, effectively restoring
the logic threshold of the equalized signal to its correct level
irrespective of shifts due to AC coupling.
As the final stage of signal conditioning, a comparator converts
the analog output of the DC restorer to a regenerated digital
output signal.
An OUTPUT 'EYE' MONITOR (pin 16), allows verification of
signal integrity after equalization but before reslicing.
Analog/Digital Select
A 2:1 multiplexer selects either the equalized (analog) signal
or a differential ECL data (digital) signal as input to the
reclocker PLL.
During periods when there are no transitions in the signal, the
loop filter voltage is required to hold precisely at its last value
so that the VCO does not drift significantly between corrections.
Commutating diodes in the charge pump keep the output
leakage current extremely low, minimizing VCO frequency
drift.
The VCO is implemented using a current-controlled
multivibrator, designed to deliver good stability, low phase
noise and wide operating frequency capability. The frequency
range is design-limited to ±10% about the oscillator centre
frequency.
VCO Centre Frequency Selection
The centre frequency of theVCO is set by one of four external
current reference resistors (RVCO0-RVCO3) connected to
pins 13,14,15 or 17. These are selected by two logic inputs
SS0 and SS1 (pins 20, 21) through a 2:4 decoder according
to the following truth table.
SS1
SS0
Resistor Selected
0
0
RVCO0 (13)
0
1
RVCO1 (14)
1
0
RVCO2 (15)
1
1
RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Subsystem and the GS9000B or GS9000S Decoder may be used
in conjunction with the GS9005B to obtain adjustment free
and automatic standard select operation (see Figure 20).
With the VCO operating at twice the clock frequency, a clock
phase which is centred on the eye of the locked signal is used
to latch the incoming data, thus maximising immunity to
jitter-induced errors. The alternate phase is used to latch the
output re-clocked data SDO and SDO (pins 25, 24). The true
and inverse clock signals themselves are available from the
SCO and SCO pins 23 and 22.
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AGC
VCC1 VEE1 CAP
4
SERIAL
DATA OUT
(SD0)
SERIAL
CLOCK OUT
(SCK)
A/D
SSI
VEE2
28
27
VCC4
tD
tD
50%
3
2
26
DDI
5
25
SD0
DDI
6
24
SD0
VCC2
7
23
SC0
SDI
8
22
SC0
SDI
9
21
SS1
50%
GS9005B
TOP VIEW
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Fig.1 Waveforms
ƒ/2 EN
10
VEE3
11
12
13
14
15
16
17
20
SS0
19
CD
18
LOOP RVCO0 RVCO1 RVCO2 OEM RVCO3 VCC3
FILT
Fig. 2 GS9005B Pin Connections
GS9005B PIN DESCRIPTIONS
PIN NO.
1
SYMBOL
A/D
TYPE
Input
DESCRIPTION
Analog/Digital Select. TTL compatible input used to select the input signal source. A logic HIGH routes the
Equalizer inputs (pins 8 and 9) to the PLL and a logic LOW routes the Direct Digital inputs (pins 5 and 6)
to the PLL.
2
3
4
5,6
AGC CAP
Input
AGC Capacitor. Connection for the AGC capacitor.
VEE1
Power Supply. Most negative power supply connection. (Equalizer)
VCC1
Power Supply. Most positive power supply connection. (Equalizer)
DDI/DDI
Input
Direct Data Inputs (true and inverse). Pseudo-ECL, differential serial data inputs. These are selected
when the A/D input (pin 1) is at logic LOW and are self biased to 1.2 volts below VCC. They may be
directly driven from true ECL drivers when VEE = -5V and VCC= 0 V.
7
8,9
VCC2
SDI/SDI
Power Supply. Most positive power supply connection. ( Phase detector, A/D select, carrier detect).
Input
Serial Data Inputs (true and inverse). Differential analog serial data inputs. Inputs must be AC
coupled and may be driven single ended. These inputs are selected when the A/D input (pin 1) is
logic HIGH.
10
11
12
13
ƒ/2 EN
Input
ƒ/2 Enable-TTL compatible input used to enable the divide by 2 function.
VEE3
Power Supply. Most negative power supply connection. (VCO, Mux, Standard Select)
LOOP FILT
Loop Filter. Node for connecting the loop filter components.
RVCO0
Input
VCO Resistor 0. Analog current input used to set the centre frequency of the VCO when the two
Standard Select bits (pins 20 and 21) are set to logic 0,0. A resistor is connected from this pin to VEE.
14
RVCO1
Input
VCO Resistor 1. Analog current input used to set the centre frequency of the VCO when Standard
Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to VEE.
15
RVCO2
Input
VCO Resistor 2. Analog current input used to set the centre frequency of the VCO when Standard
Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to VEE.
16
OEM
Output
Output Eye Monitor Analog voltage representing the serial bit stream after equalization but before reslicing.
17
RVCO3
Input
VCO Resistor 3. Analog current input used to set the centre frequency of the VCO when the two
Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to VEE.
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GS9005B PIN DESCRIPTIONS cont.
PIN NO
SYMBOL
18
VCC3
19
CD
TYPE
DESCRIPTION
Power Supply. Most positive power supply connection. (VCO, MUX, standards select).
Output
Carrier Detect. Open collector output which goes HIGH when a signal is present at either the Serial
Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S
in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should
see a low impedance (e.g. 1nF to AC Gnd)
20,21
SS0, SS1 Inputs
Standard Select Inputs. TTL inputs to the 2:4 multiplexer used to select one of four VCO centre
frequency setting resistors (RVCO0 - RVCO3). When both SS0 and SS1 are LOW, RVCO0 is selected.
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When SS0 is HIGH and SS1 is LOW, RVCO1 is selected. When SS0 is LOW and SS1 is HIGH, RVCO2
is selected and when both SS0 and SS1 are HIGH, RVCO3 is selected. These pins should see a
low impedance (e.g. 1nF to AC Gnd)
22,23
SCO/SCO Outputs
Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the extracted serial clock.
These outputs require 390 Ω pull-down resistors to VEE.
24,25
SDO/SDO Outputs
Serial Data Outputs (inverse and true). Pseudo-ECL differential outputs of the regenerated serial data.
These outputs require 390 Ω pull-down resistors to VEE.
26
27
28
VCC4
Power Supply. Most positive power supply connection. (ECL outputs)
VEE2
Power Supply. Most negative power supply connection. (Phase detector, A/D select, Carrier detect)
SSI
Signal Strength Indicator. Analog output which indicates the amount of AGC action. This output
indirectly indicates the amount of equalization and thus cable length.
INPUT / OUTPUT CIRCUITS
VCC
+
-
VCC
1.2V
VCC
16µA
2k
2k
1k
1k
VCC
A/D
Pin 1
DDI
Pin 5
DDI
Pin 6
50µA
380µA
+
1.6V
-
Fig. 3 Pins 1, 5 and 6
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INPUT / OUTPUT CIRCUITS cont.
IVCO
(1.9 - 2.4V)
LOOP FILTER
(1.8 - 2.7V)
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Pin 13 RVCO 0
Pin 14 RVCO 1
400
400
400
Pin 15
RVCO 2
400
Pin 17 RVCO 3
Fig. 4 Pins 13, 14, 15 and 17
VCC
VCC4
200
200
10k
10k
SDO or SCO
Pin 25, 24
SDO or SCO
Pin 23, 22
VCC
VCC
3k
800
Fig. 5 Pins 25, 24, 23 and 22
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INPUT / OUTPUT CIRCUITS cont.
VCC
VCC
VCC
500
SSI
Pin 28
VCC
1.5k
5k
AGC CAP
Pin 2
VCC
+
-
2k
2V
LOOP FILTER
Pin 12
1k
+
-
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0.4V
5k
5k
620
SDI
Pin 8
SDI
Pin 9
920µA
920µA
Fig. 7 Pin 12
Fig. 6 Pins 28, 2, 8 and 9
VCC
VCC
10k
CD
Pin 19
OEM
Pin 16
200
5mA
5mA
Fig. 9 Pin 19
Fig. 8 Pin 16
VCC
VCC
VCC
40µA
40µA
VCC
VCC
18µA
SS1
Pin 21
ƒ/2 EN
Pin 10
55µA
480µA
+
-
1.6V
SSO
Pin 20
Fig. 10 Pins 20, 21 and 10
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TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25°C)
900
500
450
SERIAL OUTPUTS (mV)
FREQUENCY (MHz)
850
400
350
300
250
ƒ/2 OFF
200
VS = 5.25V
800
VS = 5.00V
750
700
VS = 4.75V
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ƒ/2 ON
150
650
100
50
600
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
FREQUENCY SETTING RESISTANCE (ký)
TEMPERATURE (°C)
Fig. 11 Clock Frequency
Fig. 12 Serial Outputs
60
70
140
135
VS = 5.25V
CURRENT (mA)
130
125
VS = 5.00V
120
VS = 4.75V
115
110
105
100
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
Fig. 13 Supply Current
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+5V
+5V
ANALOG
DIGITAL
10µ
+
SSI
0.1µ
+5V
0.1µ
0.1µ
390
0.1µ
390
VCC4
VEE2
SSI
1 28 27 26
A/D
2
AGC
3
VEE1
ECL
DATA
INPUTS 5 DDI
6
DDI
7
VCC2
8 SDI
VCC1
4
25
SDO
SDO
100
24
100
DATA
DATA
23
100
CLOCK
22
100
CLOCK
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INPUT
75
47p
SCO
GS9005B
SCO
SS1
9 SDI
VCC3
RVCO3
EYEOUT
RVCO2
RVCO1
75
RVCO0
11 VEE3
LOOP
47p
SS0
10 ƒ/2
CD
12 13 14 15 16 17 18
22n
21
+5V
390
20
390
CARRIER
DETECT
OUTPUT
19
10k
+5V
113
0.1µ
5.6p
910
+5V
10n
÷2
÷1
See Figure 18
STAR
ROUTED
LOOP
VOLTAGE
TEST
POINT
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
Fig.14 GS9005B Typical Test Circuit Using +5V Supply
TEST SETUP
Figure 14 shows a typical circuit for the GS9005B using a +5
volt supply. The four 0.1µF decoupling capacitors must be
placed as close as possible to the corresponding VCC pins.
When the Direct Digital Inputs are not used, one of these
inputs should be connected to VCC to avoid picking up noise
and unwanted signals.
The loop voltage can be conveniently measured across the
10nF capacitor in the loop filter. Tuning procedures are
described in the Temperature Compensation Section
(page 11). The fixed value frequency setting resistors should
be placed close to the corresponding pins on the GS9005B.
The Carrier Detect is an open-collector active high output
requiring a pull-up resistor of approximately 10 kΩ.
The layout of the loop filter and RVCO components requires
careful attention. This has been detailed in an application
note entitled "Optimizing Circuit and Layout Design of the
GS9005A/15A", Document No. 521 - 32 - 00.
The SS0, SS1, CD pins should see a low AC impedance. This
is particularly important when driving the SS0, SS1 pins with
external logic. The use of 1 nF decoupling capacitors at these
pins ensures this.
Figure 15 shows the GS9005B connections when using a -5
volt supply.
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ANALOG
DIGITAL
10µ
+
SSI
-5V
0.1µ
-5V
0.1µ
0.1µ
-5V
390
-5V
390
VCC4
SSI
VEE2
1 28 27 26
A/D
2
AGC
3
VEE1
VCC1
4
ECL
DATA
INPUTS 5
25
100
DATA
24
100
DATA
23
100
CLOCK
22
100
CLOCK
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6
0.1µ
7
SCO
8 SDI
SS1
VCC3
11 VEE3
75
SS0
RVCO3
10 ƒ/2
EYEOUT
9 SDI
RVCO2
47p
GS9005B
RVCO1
47p
SCO
VCC2
RVCO0
-5V
75
SDO
DDI
LOOP
INPUT
SDO
DDI
CD
21
390
20
390
19
10k
12 13 14 15 16 17 18
113
22n
CARRIER
DETECT
OUTPUT
0.1µ
5.6p
910
-5V
10n
÷2
÷1
See Figure 18
-5V
STAR
-5V ROUTED
LOOP
VOLTAGE
-5V
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
Fig. 15 GS9005B Typical Test Circuit Using -5V Supply
VCO Frequency Setting Resistors
There are two modes of VCO operation available in the
GS9005B. When the ƒ/2 ENABLE (pin 10) is LOW, any of the
four VCO frequency setting resistors, RVCO0 through RVCO3
(pins 13, 14, 15 and 17) may be used for any data rate from 100
Mb/s to over 400 Mb/s. For example, for 143 Mb/s data
rate, the value of the total RVCO resistance is approximately
6k8 and for 270 Mb/s operation, the value is approximately
3k5. The 5k potentiometers will then tune the desired data
rate near their mid-points.
Jitter performance at the lower data rates (143, 177 Mb/s) is
improved by operating the VCO at twice the normal frequency.
This is accomplished by enabling the ƒ/2 function which
activates an additional divide by two block in the PLL section
of the GS9005B.
The selection is dependent upon the level of the STANDARD
SELECT BIT, SS1 (pin 21). When SS1 is LOW, RVCO0 and
RVCO1 (pins 13 and 14) are used for the higher data rates.
When SS1 is HIGH, the VCO frequency is now twice the bit rate
and its frequency is set by RVCO2 and RVCO3 (pins 15 and
17).
For 143 Mb/s and 270 Mb/s operation, (the VCO is at 286 MHz
and 270 MHz respectively) the total resistance required is
approximately the same for both data rates. This also applies
for 177 Mb/s and 360 Mb/s operation (the VCO is tuned
to 354 MHz and 360 MHz respectively). This means that one
potentiometer may be used for each frequency pair with only
a small variation of the fixed resistor value. This halves the
number of adjustments required.
When the ƒ/2 ENABLE is HIGH two of the RVCO pins are
assigned to data rates below 200 Mb/s and two are assigned
to data rates over 200 Mb/s.
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Temperature Compensation
Figure 16 shows the connections for the frequency setting
resistors for the various data rates. The compensation shown
for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to
a maximum ambient temperature of 50°C. If the Divide by 2
function is not enabled by the ƒ/2 ENABLE input, no compensation is needed for the 143 Mb/s and 177 Mb/s data rates.
The resistor connections are shown in Figure 17. In both
cases, the 0.1 µF capacitor that bypasses the potentiometer
should be star routed to VEE 3.
1k
10k
0.1µF
VEE
Divide by 2 is OFF
143Mb/s and 177 Mb/s using any RVCO0 pins
Fig. 17
Non - Temperature Compensated Resistor Values
D
E
D
S
N
E GN
M SI
M
E
O
D
C
E
R EW
T
N
O
N OR
F
5.6k
4.3k
1.3k
1.3k
for 143 Mb/s and 177 Mb/s
1N914
5k
0.1µF
1N914
5k
0.1µF
Loop Bandwidth
VEE
The loop bandwidth is dependant upon the internal PLL gain
constants along with the loop filter components connected to
pin 12. In addition, the impedance seen by the RVCO pin also
influences the loop characteristics such that as the impedance drops, the loop gain increases.
VEE
Divide by 2 is OFF
Divide by 2 is ON
270 Mb/s using RVCO0 or RVCO1
143 Mb/s using RVCO2 or RVCO3
Applications Circuit
1k
1k
1k
0.1µF
Figure 18 shows an application of the GS9005B in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Subsystem IC and a GS9000B or GS9000S Decoder IC. The
GS9005B may be replaced with a GS9015B Reclocker IC
if cable equalization is not required.
1k
0.1µF
1N914
1N914
VEE
VEE
Divide by 2 is OFF
360 Mb/s using RVCO0 or RVCO1
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the incoming
data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2.
Divide by 2 is ON
177 Mb/s using RVCO2 or RVCO3
Fig. 16 Frequency Setting Resistor Values
& Temperature Compensation
Temperature Compensation Procedure
In order to correctly set the VCO frequency so that the PLL will
always re-acquire lock over the full temperature range, the
following procedure should be used. The circuit should be
powered on for at least one minute prior to starting this
procedure.
Monitor the loop filter voltage at the junction of the loop filter
resistor and 10 nF loop filter capacitor (LOOP FILTER TEST
POINT). Using the appropriate network shown above, the
VCO frequency is set by first tuning the potentiometer so that
the PLL loses lock at the low end (lowest loop filter voltage).
The loop filter voltage is then slowly increased by adjusting the
the potentiometer to determine the error free low limit of the
capture range. Error free operation is determined by using a
suitable CRC or EDH measurement method to obtain a stable
signal with no errors. Record the loop filter voltage at this point
as VCL. Now adjust the potentiometer so that the loop filter
voltage is 250 mV above VCL.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver VCO frequency over a set
range until the system is correctly locked. An automatic
fine tuning (AFT) loop maintains the VCO control voltage at
it's centre point through continuous, long term adjustments
of the VCO centre frequency.
When an interruption to the incoming data stream is
detected by the Receiver, the Carrier Detect goes LOW
and opens the AFT loop in order to maintain the correct
VCO frequency for a period of at least 2 seconds. This
allows the Receiver to rapidly relock when the signal is reestablished.
During normal operation, the GS9000B or GS9000S Decoder
provides continuous HSYNC pulses which disable the
ramp/oscillator of the GS9010A. This maintains the
correct Receiver VCO frequency.
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Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B
Deserializer Evaluation Board.”
The use of a star grounding technique is required for the loop filter components of the GS9005B/15B.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005B
and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna
is formed when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
D
E
D
S
N
E GN
M SI
M
E
O
D
C
E
R EW
T
N
O
N OR
F
SWF
SSI
VCC
0.1µ
10µ
+
DVCC
+5V
VCC
+5V
100
3.3k
100
0.1µ
+
0.1µ
DGND
GS9005B
VCC3
5
24
100
6
23
100
7
100
8
V
SS1 21 CC
SS0 20
390
9
390
10
19
CD
12 13 14 15 16 17 18
SDI
SCI
(4)
PD5
SCI
GS9000B
or GS9000S
PD4
SST
DVCC
VCC
VSS
PD6
100
24
100
23
100
22
100
100
20
100
PD1 19
100
PD2
12 13 14 15 16
25
21
PD3
SS0
11
PARALLEL DATA BIT 8
PD7
SDI
SS1
PARALLEL DATA BIT 9
28 27 26
PD8
1
PD9
VSS
2
HSYNC
VSS
100
22
SCO
RVCO3
EYEOUT
RVCO2
RVCO1
VEE3
RVCO0
11
25
3
SWF
SSI
VCC4
A/D
VEE2
AGC
SCO
9 SDI
10 ƒ/2
5.6p
(1)
VEE1
VCC1
DDI
75
22n
SDO
8 SDI
47p
390
SDO
VCC2
4
28 27 26
VDD
47p
1
DDI
LOOP
75
7
2
PDO
0.1µ
6
3
PCLK
VCC
5
390
4
SYNC WARNING FLAG
HSYNC OUTPUT
DGND
SWC
DGND
ECL
DATA
INPUT
INPUT
INPUT SELECTION
0.1µ
SCE
GND
100
DGND
VCC
VCC
VDD
10µ
VDD
10µ
+
17
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
DVCC
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
18
SYNC CORRECTION ENABLE
0.1µ
113
(2)
910
0.1µ
0.1µF
100
100
DGND
10n
DGND
1.2k
DVCC
VCC
1.2k
(3)
0.1µ
68k
50k
22n
VCC
120
STAR
ROUTED
DGND
GS9010A
6.8µ
+
1
(2)
6.8µ
2
+
3
4
3.3n 5
VCC
P/N
OUT
IN-
COMP
LF
6
ƒ/2
7
VCC
8
SWF
STDT
16
0.1µ
15
VCC
14
CD
13
HSYNC
12
GND
11
OSC
10
DLY
9
FVCAP
VCC
STANDARD TRUTH TABLE
100k
82n
(2)
0.68µ
All resistors in ohms, all capacitor
in microfarads, all inductors in
henries unless otherwise stated.
VCC
0.1µ
180n
SWF
ƒ/2
P/N
STANDARD
0
0
4:2:2 - 270
0
1
4:2:2 - 360
1
0
4ƒsc - NTSC
1
1
4ƒsc - PAL
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8µF capacitors (connected across pins 2 and 3
of the GS9010A) may be replaced with a
1.0 µF non-polarized capacitor provided that:
(a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
0.33 µF capacitor and
(b) the GS9005B/15B Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(4) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
a maximum frequency of 300 Mbps.
Fig. 18 Typical Application Circuit
REVISION NOTES
New document.
DOCUMENT IDENTIFICATION
PRODUCT PROPOSAL
This data has been compiled for market investigation purposes
only, and does not constitute an offer for sale.
ADVANCE INFORMATION NOTE
This product is in development phase and specifications are
subject to change without notice. Gennum reserves the right to
remove the product at any time. Listing the product does not
constitute an offer for sale.
PRELIMINARY
The product is in a preproduction phase and specifications are
subject to change without notice.
DATA SHEET
The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.
For latest product information, visit www.gennum.com
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright July 2004 Gennum Corporation. All rights reserved. Printed in Canada.
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