Integrated Circuit Systems, Inc. ICS94201 Programmable System Frequency Generator for PII/III™ Pin Configuration Output Features: • 2 - CPUs @ 2.5V • 13 - SDRAM @ 3.3V • 3 - 3V66 @ 3.3V • 8 - PCI @3.3V • 1 - 24/48MHz@ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - REF @3.3V, 14.318MHz Features: • Programmable ouput frequency. • Programmable ouput rise/fall time for PCI and SDRAM clocks. • Programmable 3V66 to PCI skew. • Spread spectrum for EMI control with programmable spread percentage. • Watchdog timer technology to reset system if over-clocking causes malfunction. • Support power management through PD#. • Uses external 14.318MHz crystal. • FS pins for frequency select Key Specifications: • CPU Output Jitter: <250ps • IOAPIC Output Jitter: <500ps • 48MHz, 3V66, PCI Output Jitter: <500ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps • For group skew timing, please refer to the Group Timing Relationship Table. VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *(FS0)PCICLK0 1 *(FS1)PCICLK1 1 *(SEL24_48#)PCICLK2 GNDPCI PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GNDSDR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 REF0(FS4)* VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GNDLCPU GNDSDR SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 24_48MHz(FS2)* 1 48MHz(FS3)* VDD48 VDDSDR SDRAM8 SDRAM9 GNDSDR 56-Pin 300 mil SSOP 1. These pins will have 1.5 to 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum FS[4:0] PD# SEL24_48# SDATA SCLK 94201 Rev A - 05/24/01 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ICS94201 Recommended Application: 810/810E and Solano (815) type chipset REF0 CPU DIVDER 2 CPUCLK [1:0] SDRAM DIVDER 12 SDRAM [11:0] SDRAM_F Control Logic Config. Reg. IOAPIC DIVDER IOAPIC PCI DIVDER 8 3V66 DIVDER 3 PCICLK [7:0] 3V66 [2:0] ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS94201 General Description The ICS94201 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. The ICS94201 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. Pin Configuration PI N PI N N A M E N U M B ER 1, 9, 10, 18, 25, VDD 32, 33, 37, 45 TYPE PWR 2 X1 IN 3 X2 O UT GN D PWR 4, 5, 14, 21, 28, 29, 36, 41, 49 D E S C R I PT I O N 3.3V power supply C rystal input, has internal load cap (33pF) and feedback resistor from X2 C rystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 8, 7, 6 3V66 [2:0] O UT 3.3V Fixed 66MHz clock outputs for HUB 11 PC IC LK 01 FS0 O UT IN 3.3V PC I clock output, with Synchronous C PUC LK s Logic input frequency select bit. Input latched at power on. PCICLK11 OUT 3.3V PC I clock output, with Synchronous C PUC LK s 12 FS1 IN Logic input frequency select bit. Input latched at power on. SEL_24_48# IN Logic input to select output. 13 20, 19, 17, 16, 15 PCICLK21 OUT 3.3V PC I clock output, with Synchronous C PUC LK s PC IC LK [7:3] O UT 3.3V PC I clock outputs, with Synchronous C PUC LK s 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VC O and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input 24 SDATA O UT 34 35 38 48, 47, 46, 44, 43, 42, 40, 39, 31, 30, 27, 26 50 FS3 48MHz FS2 IN O UT IN Data input for I2C serial input. Logic input frequency select bit. Input latched at power on. 3.3V Fixed 48MHz clock output for USB Logic input frequency select bit. Input latched at power on. 24_48MHz OUT 3.3V 24_48MHz output, selectable through pin 13, default is 24MHz. SDRAM_F O UT 3.3V SDRAM output can be turned off through I2C SDRAM [11:0] O UT 3.3V output. All SDRAM outputs can be turned off through I2C GN DL PWR Ground for 2.5V power supply for C PU & APIC 5 1, 5 2 C PUC LK [1:0] O UT 2.5V Host bus clock output. O utput frequency derived from FS pins. 53, 55 54 VDDL IO APIC FS4 PWR O UT IN 2.5V power suypply for C PU, IO APIC 2.5V clock outputs running at 16.67MHz. Logic input frequency select bit. Input latched at power on. REF01 O UT 3.3V, 14.318MHz reference clock output. 56 2 ICS94201 General I2C serial interface information for the ICS94201 How to Write: How to Read: • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 28 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 6 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 6). • Controller (host) will need to acknowledge each byte • Controller (host) will send a stop bit How to Read: How to Write: Controller (Host) Start Bit Address D2(H) Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver) ICS (Slave/Receiver) ACK Byte Count ACK Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK If 7H has been written to B6 ACK Dummy Byte Count Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 ACK Byte 7 Byte 26 ACK If 1AH has been written to B6 ACK If 1BH has been written to B6 ACK If 1CH has been written to B6 ACK Stop Bit Byte 27 ACK Byte 28 ACK Stop Bit *See notes on the following page. 3 Byte26 Byte 27 Byte 28 ICS94201 Brief I2C registers description for ICS94201 Programmable System Frequency Generator R egister Name Functionality & Frequency Select Register Output Control Registers Byte 0 1-5 D escription Pwd Default Output frequency, hardware / I2 C frequency select, spread spectrum & output enable control register. See individual byte des cription Active / inactive output control registers. See individual byte des cription W riting to this register will configure byte count and how many byte will be read back. 06 H Do not write 00 H to this byte. The inverse of the latched inputs level could See individual byte Latched Inputs Read Back 7 des cription be read back from this register. Register W atchdog enable, watchdog status and 000,0000 W atchdog Control Registers 8 Bit[6:0] programmable 'safe' frequency' can be configured in this register. This bit selects whether the output 0 VCO Control Selection Bit 8 Bit[7] frequency is controled by hardware/byte 0 configurations or byte 14&15 programming. W riting to this register will configure the FFH W atchdog Timer Count Register 9 number of seconds for the watchdog timer to reset. This is an unused register. W riting to this ICS Reserved Register 10 00 H register will not affect device functionality. Byte 11 bit[3:0] is ICS vendor id - 0001. Device ID, Vendor ID & Revision ID See individual byte 11-12 Other bits in these 2 registers designate des cription Registers device revision ID of this part. Don't write into this register, writing 1's will ICS Reserved Register 13 00 H cause malfunction. These registers control the dividers ratio Depend on VCO Frequency Control Registers 14-15 into the phase detector and thus control the hardware/byte 0 configuration VCO output frequency. Byte Count Read Back Register Spread Spectrum Control Registers 6 16-17 Output Dividers Control Registers 18-20 Group Skews Control Registers 21-23 Output Rise/Fall Time Select Registers 24 These registers control the spread percentage amount. Changing bits in these registers result in frequency divider ratio changes. Incorrect configuration of group output divider ratio can cause system malfunction. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the group rise and fall time. Depend on hardware/byte 0 configuration Depend on hardware/byte 0 configuration See individual byte des cription See individual byte des cription Notes: 1. 2. 3. 4. 5. 6. 7. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to read back is defined by writing to byte 6. When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8-bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 4 ICS94201 Byte 0: Functionality and frequency select register (Default=0) Bit Bit2 Bit7 Bit6 Bit5 Bit4 VCO/REF Divider FS4 FS3 FS2 FS1 FS0 Bit (2,7:4) Bit 3 Bit 1 Bit 0 PWD Description VCO MHz VCO/ CPUCLK SDRAM CPU MHz MHz 0 0 0 0 0 501/18 398.52 6 0 0 0 0 1 352/14 360.00 6 0 0 0 1 0 504/18 400.91 6 0 0 0 1 1 315/11 410.02 6 0 0 1 0 0 440/15 420.00 6 0 0 1 0 1 440/14 450.00 6 0 0 1 1 0 503/15 480.14 6 0 0 1 1 1 313/9 497.95 6 0 1 0 0 0 515/37 199.29 2 0 1 0 0 1 440/35 180.29 2 0 1 0 1 0 518/37 200.45 2 0 1 0 1 1 446/31 206.00 2 0 1 1 0 0 484/33 210.00 2 0 1 1 0 1 507/33 219.98 2 0 1 1 1 0 514/32 229.99 2 0 1 1 1 1 447/16 400.01 2 1 0 0 0 0 501/18 398.52 3 1 0 0 0 1 454/13 500.03 3 1 0 0 1 0 504/18 400.91 3 1 0 0 1 1 488/17 411.02 3 1 0 1 0 0 440/15 420.00 3 1 0 1 0 1 395/13 435.05 3 1 0 1 1 0 440/14 450.00 3 1 0 1 1 1 503/15 480.14 3 1 1 0 0 0 501/18 398.52 3 1 1 0 0 1 454/13 500.03 3 1 1 0 1 0 504/18 400.91 3 1 1 0 1 1 488/17 411.02 3 1 1 1 0 0 440/15 420.00 3 1 1 1 0 1 395/13 435.05 3 1 1 1 1 0 440/14 450.00 3 1 1 1 1 1 503/15 480.14 3 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,7:4 0- Normal 1- Spread spectrum enable ± 0.35% Center Spread 0- Running 1- Tristate all outputs 66.43 60.00 66.80 68.33 70.00 75.00 80.00 83.00 99.65 90.00 100.23 103.00 105.00 110.00 115.00 200.00 132.86 166.67 133.64 137.00 140.00 145.00 150.00 160.00 132.86 166.67 133.64 137.00 140.00 145.00 150.00 160.00 99.65 90.00 100.20 102.50 105.00 112.50 120.00 124.50 99.65 90.00 100.23 103.00 105.00 110.00 115.00 200.00 132.86 166.67 133.64 137.00 140.00 145.00 150.00 160.00 99.65 125.00 100.23 102.75 105.00 108.75 112.50 120.00 3V66 MHz PCICLK MHz IOAPIC MHz 66.43 60.00 66.80 68.33 70.00 75.00 80.00 83.00 66.43 60.00 66.84 68.67 70.00 73.33 76.67 133.33 66.43 83.34 66.82 68.50 70.00 72.50 75.00 80.00 66.93 83.34 66.82 68.50 70.00 72.50 75.00 80.00 33.21 30.00 33.40 34.17 35.00 37.50 40.00 41.50 33.21 30.00 33.41 34.33 35.00 36.67 38.33 66.66 33.21 41.67 33.41 34.25 35.00 36.25 37.50 40.00 33.21 41.67 33.41 34.25 35.00 36.25 37.50 40.00 16.61 15.00 16.70 17.08 17.50 18.75 20.00 20.75 16.61 15.00 16.70 17.17 17.50 18.33 19.17 33.33 16.61 20.83 16.70 17.13 17.50 18.13 18.75 20.00 16.61 20.83 16.7 17.13 17.50 18.13 18.75 20.00 Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 5 Note 1 0 1 0 ICS94201 Byte 2: Output Control Register (1 = enable, 0 = disable) Byte 1: Output Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 35 34 38 PWD X X X 1 1 1 1 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description FS3# FS0# FS2# 24MHz (Reserved) 48MHz (Reserved) SDRAM_F Byte 3: Output Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 26 27 30 31 PWD 1 1 1 1 1 1 1 1 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 4: Output Control Register (1 = enable, 0 = disable) Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5: Output Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 39 40 42 43 44 46 47 48 Pin# 8 6 7 54 51 52 PWD 1 1 1 X 1 X 1 1 Description 3V66_2 3V66_0 3V66_1 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0 Byte 6: Byte Count Read Back Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8 Pin# - PWD 0 0 0 0 0 1 1 0 Description R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) Note: Writing to this register will configure byte count and how many bytes will be read back, default is 6 bytes. Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 6 ICS94201 Byte 7: Latch Inputs Readback Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 0 X X X X X Byte 8: VCO Control Selection Bit & Watchdog Timer Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) (Reserved) (Reserved) FS4# FS3# FS2# FS1# FS0# PWD 0 0 0 0 0 0 0 0 Description 0=Hw/B0 freq / 1=B14&15 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, FS4 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0 Note: FS values in bit [0:4] will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0. Byte 9: Watchdog Timer Count Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 1 1 1 1 1 1 1 Byte 10: ICS Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description The decimal representation of these 8 bits correspond to 580ms or 2ms (selectable by byte 13 bit 4) the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 256X 580ms = 148 seconds PWD 0 0 0 0 0 0 0 0 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Note: This is an unused register. Writing to this register will not affect device performance or functionality. Byte 11: Vender ID & Device ID Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X 0 0 0 1 Byte 12: Revision ID Register Description Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Device ID Device ID Device ID Device ID Vendor ID Vendor ID Vendor ID Vendor ID Note: ICS Vendor ID is 0001 as in Number 1 in frequency generation. PWD X X X X X X X X Description Revision ID Revision ID Revision ID Revision ID Device ID Device ID Device ID Device ID Note: Device ID and Revision ID values will be based on individual device and its revision. Notes: 1. PWD = Power on Default 7 ICS94201 Byte 13: ICS Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 14: VCO Frequency Control Register PWD Description 0 (Reserved) 0 (Reserved) 0 (Reserved) W0 timer base select 0 0=580ms 1=2ms 0 (Reserved) 0 (Reserved) 0 (Reserved) 0 (Reserved) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0 Note: The decimal representation of these 7 bits (Byte 14 [6:0]) + 2 is equal to the REF divider value . Note: DON'T write a '1' into this register, it will cause malfunction. Byte 15: VCO Frequency Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1 Note: The decimal representation of these 9 bits (Byte 15 bit [7:0] & Byte 14 bit [7] ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 15 bit & byte 14 bit 7. To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desired gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 6 for readback of 25 bytes (byte 0-24). 3. Read back byte 16-24 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 8 bit 7 indicating you want to use byte 14 and 15 to control the VCO frequency. 6. Write to byte 14 & 15 with the desired VCO & REF divider values. 7. Write to byte 16 to 24 with the values you copy from step 3. This maintains the output divider mux controls the same gear ratio. 8. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needs to be changed again, user only needs to write to byte 14 and 15 unless the system is to reboot. 8 ICS94201 Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with the wrong spread percentage and/or group to group divider ratio programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. Users can also utilize software utility provided to program the VCO frequency from ICS Application Engineering. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spread amount desired. See Application note for software support. Byte 16: Spread Sectrum Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Byte 17: Spread Spectrum Control Register Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X 0 X X X X X X Description Divider control Bit26 Divider control Bit25 Divider control Bit24 Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bit9 Spread Spectrum Bit8 Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure. Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure. Byte 18: Output Dividers Control Register Byte 19: Output Dividers Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description Output Divider MUX Control Bit7 Output Divider MUX Control Bit6 Output Divider MUX Control Bit5 Output Divider MUX Control Bit4 Output Divider MUX Control Bit3 Output Divider MUX Control Bit2 Output Divider MUX Control Bit1 Output Divider MUX Control Bit0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description Output Divider MUX Control Bit15 Output Divider MUX Control Bit14 Output Divider MUX Control Bit13 Output Divider MUX Control Bit12 Output Divider MUX Control Bit11 Output Divider MUX Control Bit10 Output Divider MUX Control Bit9 Output Divider MUX Control Bit8 Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction. Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction. Notes: 1. PWD = Power on Default 2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass. 9 ICS94201 Byte 20: Output Dividers Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Byte 21: ICS Reserved Register Description Output Divider MUX Control Bit23 Output Divider MUX Control Bit22 Output Divider MUX Control Bit21 Output Divider MUX Control Bit20 Output Divider MUX Control Bit19 Output Divider MUX Control Bit18 Output Divider MUX Control Bit17 Output Divider MUX Control Bit16 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 0 0 0 0 0 0 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction. Note: This is an unused register. Writing to this register will not affect device performance or functionality. Byte 22: Group Skew Control Register Byte 23: Group Skew Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 0 1 0 0 0 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description 3V66 to PCI Skew Bit3 3V66 to PCI Skew Bit2 3V66 to PCI Skew Bit1 3V66 to PCI Skew Bit0 (Reserved) (Reserved) (Reserved) (Reserved) Description (Reserved) (Reserved) (Reserved) (Reserved) 3V66 to IOAPIC Skew Bit 3 3V66 to IOAPIC Skew Bit 2 3V66 to IOAPIC Skew Bit 1 3V66 to IOAPIC Skew Bit 0 Notes: 1. PWD = Power on Default 2. The power on default for byte 16-20 depends on the hardware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value. Byte 24: Output Rise/Fall Time Select Register PWD 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Note: Default 3V66 to IOAPIC skew is 2.5ns bit [3:0]=0111. Each increment or decrement of bit 4 to 7 will introduce 100ps delay or advance on all IOAPIC clocks. Note: Default 3V66 to PCI skew is 2.5ns bit [7:4]=1001. Each increment or decrement of bit 4 to 7 will introduce 100ps delay or advance on all PCI clocks. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD Description (Reserved) REF 0=Normal, 1=Weak 24,48Mhz 0=Normal, 1=Weak (Reserved) PCI 0=Normal, 1=Weak 3V66 0=Normal, 1=Weak SDRAM 0=Normal, 1=Weak (Reserved) 10 ICS94201 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND –0.5 V to VDD +0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table1 Group 1 CPU 66 MHz CPU 100 MHz CPU 133 MHz CPU 133 MHz SDRAM 100 MHz SDRAM 100 MHz SDRAM 100 MHz SDRAM 133 MHz Offset Tolerance Offset Tolerance Offset Tolerance Offset CPU to SDRAM 2.5 ns 500 ps 5.0 ns 500 ps 0.0 ns 500 ps 3.75 ns Tolerance 500 ps CPU to 3V66 7.5 ns 500 ps 5.0 ns 500 ps 0.0 ns 500 ps 0.0 ns 500 ps SDRAM to 3V66 0.0 ns 500 ps 0.0 ns 500 ps 0.0 ns 500 ps 3.75 ns 500 ps 3V66 to PCI 1.5-3.5ns 500 ps 1.5-3.5ns 500 ps 1.5-3.5ns 500 ps 1.5-3.5ns 500 ps PCI to IOAPIC 0.0 ns 1.0 ns 0.0 ns 1.0 ns 0.0 ns 1.0 ns 0.0 ns 1.0 ns USB & DOT Asynch N/A Asynch N/A Asynch N/A Asynch N/A Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 2 VSS-0.3 Input Low Voltage VIL Input High Current IIH VIN = VDD -5 VIN = 0 V; Inputs with no pull-up resistors -5 IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors -200 IIL2 CL = max cap loads; IDD3.3OP Operating Supply CPU=66-133 MHz, SDRAM=100 MHz CPU=133 MHz, SDRAM=133 MHz Current IDD2.5OP CL = max cap loads; CL = 0 pF; Input address to VDD or GND IDD3.3PD Powerdown Current Input Frequency Pin Inductance Input Capacitance1 1 Transition time 1 Settling time Clk Stabilization1 Delay1 1 Fi Lpin CIN COUT CINX VDD = 3.3 V Ttrans TYP MAX VDD+0.3 0.8 5 µA 334 350 465 20 280 500 70 600 14.318 Logic Inputs Output pin capacitance X1 & X2 pins 27 UNITS V V µA 7 5 6 45 mA µA MHz nH pF pF pF To 1st crossing of target frequency 3 ms Ts From 1st crossing to 1% target frequency 3 ms TSTAB tPZH,tPZL tPHZ,tPLZ From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 3 10 10 ms ns ns Guaranteed by design, not 100% tested in production. 11 1 1 ICS94201 Electrical Characteristics - CPU TA = 0 - 70º C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance1 RDSP2B Vo=VDD*(0.5) Output Impedance1 RDSN2B Vo=VDD*(0.5) IOH = -1 mA Output High Voltage VOH2B Output Low Voltage VOL2B IOL = 1 mA VOH@MIN = 1 V IOH2B Output High Current VOH@MAX = 2.375V VOL@MIN = 1.2 V IOL2B Output Low Current VOL@MAX =0.3V Rise Time1 tr2B VOL = 0.4 V, VOH = 2.0 V Fall Time1 tf2B VOH = 2.0 V, VOL = 0.4 V Duty Cycle1 dt2B VT = 1.25 V 1 Skew tsk2B VT = 1.25 V VT = 1.25 V, CPU 66, SDRAM 100 CPU 100, SDRAM 100 tjcyc-cyc2B Jitter, Cycle-to-cycle1 CPU 133, SDRAM 100 CPU 133, SDRAM 133 1 Guaranteed by design, not 100% tested in production. MIN 13.5 13.5 2 -27 27 0.4 0.4 45 TYP 15 16.5 2.48 0.04 -60 -7 63 20 1 1 50 30 300 240 400 300 MAX UNITS 45 Ω 45 Ω V 0.4 V -27 mA TYP MAX UNITS 55 Ω 55 Ω V 0.55 V -33 mA 30 1.6 1.6 55 175 350 250 500 350 mA ns ns % ps ps Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance1 RDSP1 VO = VDD*(0.5) Output Impedance1 RDSN1 VO = VDD*(0.5) 2.4 Output High Voltage Output Low Voltage VOH1 VOL1 Output High Current IOH1 Output Low Current IOL1 Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1 1.6 ns 1 tf1 dt1 VOH = 2.4 V, VOL = 0.4 V 0.4 0.9 1.6 ns VT = 1.5 V 45 49 55 % tsk1 VT = 1.5 V 35 175 ps tjcyc-cyc1 VT = 1.5 V 220 500 ps Fall Time 1 Duty Cycle Skew 1 Jitter, Cycle-to-cycle1 1 IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V MIN 12 12 Guaranteed by design, not 100% tested in production. 12 -33 30 38 mA ICS94201 Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) 1 PARAMETER Output Impedance1 Output Impedance1 SYMBOL RDSP4B RDSN4B CONDITIONS Output High Voltage Output Low Voltage VOH4B VOL4B Output High Current IOH4B Output Low Current IOL4B Rise Time1 tr4B VOL = 0.4 V, VOH = 2.0 V 0.4 1.2 1.6 ns Fall Time1 tf4B VOH = 2.0 V, VOL = 0.4 V 0.4 1.1 1.6 ns Duty Cycle1 Jitter, Cycle-to-cycle1 dt4B tjcyc-cyc4B VT = 1.25 V 45 50 55 % 240 500 ps Vo=VDD*(0.5) Vo=VDD*(0.5) IOH = -5.5 mA IOL = 9 mA VOH@MIN = 1.4 V VOH@MAX = 2.5V VOL@MIN = 1.0 V VOL@MAX =0.2V MIN 9 9 2 TYP -36 36 MAX UNITS 3 Ω 30 Ω V 0.4 V -21 mA 31 VT = 1.25 V mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance1 Output Impedance1 SYMBOL RDSP3 RDSN3 Output High Voltage Output Low Voltage VOH3 VOL3 Output High Current IOH3 Output Low Current IOL3 IOH = -1 mA IOL = 1 mA VOH@MIN = 2 V VOH@MAX = 3.135V VOL@MIN = 1 V VOL@MAX =0.4V MIN 10 10 2.4 TYP -54 54 MAX UNITS 24 Ω 24 Ω V 0.4 V -46 mA 53 mA 1 tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 0.9 1.6 ns 1 tf3 VOH = 2.4 V, VOL = 0.4 V 0.4 0.8 1.6 ns dt3 VT = 1.5 V 45 49 55 % tsk3 VT = 1.5 V 100 250 ps tjcyc-cyc3 VT = 1.5 V 350 500 ps Rise Time Fall Time 1 Duty Cycle 1 CONDITIONS Vo=VDD*(0.5) Vo=VDD*(0.5) Skew Jitter, cycle-to-cycle1 1 Guaranteed by design, not 100% tested in production. 13 ICS94201 Electrical Characteristics - PCI TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated) PARAMETER Output Impedance1 Output Impedance1 SYMBOL RDSP1 RDSN1 Output High Voltage Output Low Voltage VOH1 VOL1 Output High Current IOH1 Output Low Current IOL1 Rise Time1 tr1 Fall Time 1 tf1 Duty Cycle1 dt1 tsk1 VT = 1.5 V VT = 1.5 V tjcyc-cyc1 VT = 1.5 V Skew1 Jitter, cycle-to-cycle1 1 CONDITIONS Vo=VDD*(0.5) Vo=VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@MIN = 1 V VOH@MAX = 3.135V VOL@MIN = 1.95 V VOL@MAX =0.4V MIN 12 12 2.4 TYP -33 30 MAX UNITS 55 Ω Ω 55 V 0.55 V -33 mA 38 VOL = 0.4 V, VOH = 2.4 V, PCI0-3 PCI3-7 VOL = 2.4 V, VOH = 0.4 V, PCI0-3 PCI3-7 0.5 0.5 45 mA 1.8 2.2 2 2.5 1.8 2 2.3 2.5 51 150 55 500 % ps 200 500 ps ns ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF, 24_48MHz, 48MHz TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance1 RDSP5 VO = VDD*(0.5) Output Impedance1 RDSN5 VO = VDD*(0.5) TYP MAX UNITS 60 Ω 60 Ω V 0.4 V -23 mA Output High Voltage Output Low Voltage VOH5 VOL5 Output High Current IOH5 Output Low Current IOL5 Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V 0.4 2 4 ns 1 VOH = 2.4 V, VOL = 0.4 V 0.4 2 4 ns Duty Cycle tf5 dt5 VT = 1.5 V 45 53 55 % Jitter, cycle-to-cycle1 tjcyc-cyc5 VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks 200 2300 500 3000 ps Fall Time 1 1 MIN 20 20 IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Guaranteed by design, not 100% tested in production. 14 2.4 -29 29 27 mA ICS94201 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS94201 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 15 ICS94201 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 16 ICS94201 0ns 10ns 20ns 30ns Cycle Repeats CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 100MHz SDRAM 133MHz 3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz Group Offset Waveforms 17 40ns ICS94201 c N L E1 INDEX AREA E 1 2 h x 45° D A A1 SYMBOL A A1 b c D E E1 e h L N α In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° -Ce SEATING PLANE b .10 (.004) C N 56 VARIATIONS D mm. MIN MAX 18.31 18.55 D (inch) MIN .720 MAX .730 Reference Doc.: JEDEC Publication 95, MO-118 300 mil SSOP Package 10-0034 Ordering Information ICS94201yFT Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 18 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.