ON MC34065P High performance dual channel current mode controller Datasheet

Order this document by MC34065/D
The MC34065 is a high performance, fixed frequency, dual current mode
controllers. It is specifically designed for off–line and dc–to–dc converter
applications offering the designer a cost effective solution with minimal
external components. This integrated circuit feature a unique oscillator for
precise duty cycle limit and frequency control, a temperature compensated
reference, two high gain error amplifiers, two current sensing comparators,
Drive Output 2 Enable pin, and two high current totem pole outputs ideally
suited for driving power MOSFETs.
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
and a latch for single pulse metering of each output.
The MC34065 and MC33065 are available in dual–in–line and surface
mount packages.
• Unique Oscillator for Precise Duty Cycle Limit and Frequency Control
•
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•
•
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HIGH PERFORMANCE
DUAL CHANNEL CURRENT
MODE CONTROLLER
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 648
16
1
Current Mode Operation to 500 kHz
Automatic Feed Forward Compensation
Separate Latching PWMs for Cycle–By–Cycle Current Limiting
DW SUFFIX
PLASTIC PACKAGE
CASE 751G
(SO–16L)
Internally Trimmed Reference with Undervoltage Lockout
Drive Output 2 Enable Pin
Two High Current Totem Pole Outputs
16
1
Input Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
PIN CONNECTIONS
Representative Block Diagram
VCC
Vref
15
5.0 V
Reference
R
Sync Input
RT
CT
Voltage
Feedback 1
CT 2
VCC
Undervoltage
Lockout
3
Oscillator
2
4
Compensation 1
Latching
PWM 1
+
–
Error
Amp 1
15 Vref
14 Drive Output 2
Enable
13 Voltage Feedback 2
RT 3
Voltage Feedback 1 4
Vref
Undervoltage
Lockout
R
1
16 VCC
Sync Input 1
16
Drive
7 Output 1
Compensation 1 5
12 Compensation 2
Current Sense 1 6
11 Current Sense 2
Drive Output 1 7
10 Drive Output 2
Gnd 8
9 Drive Gnd
(Top View)
Current
6 Sense 1
5
Drive
10 Output 2
Drive Output 2
Enable 14
Voltage
Feedback 2 13
Compensation 2
Latching
PWM 2
+
–
Error
Amp 2
ORDERING INFORMATION
Device
Current
11 Sense 2
12
Gnd
8
Drive Gnd 9
This device contains 208 active transistors.
MC34065DW
MC34065P
MC33065DW
MC33065P
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Operating
Temperature Range
TA = 0° to +70°C
TA = –40° to +85°C
Package
SO–16L
Plastic DIP
SO–16L
Plastic DIP
Rev 1
1
MC34065 MC33065
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
(ICC + IZ)
50
mA
Output Current, Source or Sink (Note 1)
IO
1.0
A
Output Energy (Capacitive Load per Cycle)
W
5.0
µJ
Current Sense, Enable, and Voltage Feedback Inputs
Vin
–0.3 to +5.5
V
Sync Input
High State (Voltage)
Low State (Reverse Current)
VIH
IIL
5.5
–5.0
V
mA
Error Amp Output Sink Current
IO
10
mA
PD
RθJA
862
145
mW
°C/W
PD
RθJA
TJ
1.25
100
W
°C/W
+150
°C
Total Power Supply and Zener Current
Power Dissipation and Thermal Characteristics
DW Suffix, Plastic Package Case 751G
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
P Suffix, Plastic Package Case 648
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
Operating Junction Temperature
Operating Ambient Temperature
MC34065
MC33065
0 to +70
–40 to +85
Storage Temperature Range
NOTE:
°C
TA
Tstg
–65 to +150
°C
ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 8.2 kΩ, CT = 3.3 nF, for typical values TA = 25°C, for
min/max values TA is the operating ambient temperature range that applies [Note 3].)
Characteristics
Symbol
Min
Typ
Max
Unit
Vref
Regline
4.9
5.0
5.1
V
–
2.0
20
mV
Regload
Vref
–
3.0
25
mV
4.85
–
5.15
V
ISC
30
100
–
mA
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Line Regulation (VCC = 11 V to 15 V)
Load Regulation (IO = 1.0 mA to 10 mA)
Total Output Variation over Line, Load, and Temperature
Output Short Circuit Current
OSCILLATOR AND PWM SECTIONS
Total Frequency Variation over Line and Temperature
VCC = 11 V to 15 V, TA = Tlow to Thigh
MC34065
MC33065
fosc
Frequency Change with Voltage (VCC = 11 V to 15 V)
Duty Cycle at each Output
Maximum
Minimum
kHz
46.5
45
49
49
51.5
53
∆fosc/∆V
–
0.2
1.0
DCmax
DCmin
46
–
49.5
–
52
0
IIH
IIL
–
–
170
80
250
160
%
%
µA
Sync Input Current
High State (Vin = 2.4 V)
Low State (Vin = 0.8 V)
NOTES: 1. Maximum package power dissipation limits must be observed.
2. Adjust VCC above the startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible:
Tlow = 0°C for the MC34065
Thigh = +70°C for MC34065
Tlow = –40°C for the MC33065
Thigh = +85°C for MC33065
4. This parameter is measured at the latch trip point with VFB = 0 V
DV Compensation
5. Comparator gain is defined as AV
DV Current Sense
+
2
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V [Note 2], RT = 8.2 kΩ, CT = 3.3 nF, for typical values TA = 25°C, for
min/max values TA is the operating ambient temperature range that applies [Note 3].)
Characteristics
Symbol
Min
Typ
Max
Unit
VFB
IIB
2.42
2.5
2.58
V
–
– 0.1
–1.0
µA
65
100
–
dB
Unity Gain Bandwidth (TJ = 25°C)
AVOL
BW
0.7
1.0
–
MHz
Power Supply Rejection Ratio (VCC = 11 V to 15 V)
PSRR
60
90
–
dB
Output Current
Source (VO = 3.0 V, VFB = 2.3 V)
Sink (VO = 1.2 V, VFB = 2.7 V)
Isource
Isink
–0.45
2.0
–1.0
12
–
–
VOH
VOL
5.0
–
6.2
0.8
–
1.1
2.75
3.0
3.25
V/V
Maximum Current Sense Input Threshold (Note 4)
AV
Vth
430
480
530
mV
Input Bias Current
IIB
–
–2.0
–10
µA
tPLN(In/Out)
–
150
300
ns
Enable Pin Voltage
High State (Output 2 Enabled)
Low State (Output 2 Disabled)
VIH
VIL
3.5
0
–
–
Vref
1.5
Low State Input Current (VIL = 0 V)
IIB
100
250
400
VOL
–
–
13
12
0.1
1.6
13.5
13.4
0.4
2.5
–
–
–
0.1
1.1
V
Output Voltage Rise Time (CL = 1.0 nF)
VOL(UVLO)
tr
–
28
150
ns
Output Voltage Fall Time (CL = 1.0 nF)
tf
–
25
150
ns
Vth
VCC(min)
13
14
15
V
9.0
10
11
V
–
–
0.6
20
1.0
25
15.5
17
19
ERROR AMPLIFIERS
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 5.0 V)
Open Loop Voltage Gain (VO = 2.0 to 4.0 V)
mA
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 4 and 5)
Propagation Delay (Current Sense Input to Output)
DRIVE OUTPUT 2 ENABLE PIN
V
µA
DRIVE OUTPUTS
Output Voltage
Low State (Isink = 20 mA)
(Isink = 200 mA)
High State (Isource = 20 mA)
(Isource = 200 mA)
V
VOH
Output Voltage with UVLO Activated (VCC = 6.0 V, Isink = 1.0 mA)
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
Minimum Operating Voltage After Turn–On
TOTAL DEVICE
Power Supply Current
Startup (VCC = 12 V)
Operating (Note 2)
ICC
Power Supply Zener Voltage (ICC = 30 mA)
VZ
mA
V
NOTES: 1. Maximum package power dissipation limits must be observed.
2. Adjust VCC above the startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible:
Tlow = 0°C for the MC34065
Thigh = +70°C for MC34065
Tlow = –40°C for the MC33065
Thigh = +85°C for MC33065
4. This parameter is measured at the latch trip point with VFB = 0 V
5. Comparator gain is defined as AV
Compensation
+ DDVV Current
Sense
MOTOROLA ANALOG IC DEVICE DATA
3
MC34065 MC33065
PIN FUNCTION DESCRIPTION
Pin
Function
Description
1
Sync Input
A narrow rectangular waveform applied to this input will synchronize the oscillator. A dc voltage
within the range of 2.4 V to 5.5 V will inhibit the oscillator.
2
CT
Timing capacitor CT connects from this pin to ground setting the free–running oscillator frequency
range.
3
RT
Resistor RT connects from this pin to ground precisely setting the charge current for CT. RT must
be between 4.0 k and 16 k.
4
Voltage Feedback 1
This pin is the inverting input of Error Amplifier 1. It is normally connected to the switching power
supply output through a resistor divider.
5
Compensation 1
This pin is the output of Error Amplifier 1 and is made available for loop compensation.
6
Current Sense 1
A voltage proportional to the inductor current is connected to this input. PWM 1 uses this
information to terminate conduction of output switch Q1.
7
Drive Output 1
This pin directly drives the gate of a power MOSFET Q1. Peak currents up to 1.0 A are sourced
and sunk by this pin.
8
Gnd
This pin is the control circuitry ground return and is connected back to the source ground.
9
Drive Gnd
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
10
Drive Output 2
This pin directly drives the gate of a power MOSFET Q2. Peak currents up to 1.0 A are sourced
and sunk by this pin.
11
Current Sense 2
A voltage proportional to inductor current is connected to this input. PWM 2 uses this information
to terminate conduction of output switch Q2.
12
Compensation 2
This pin is the output of Error Amplifier 2 and is made available for loop compensation.
13
Voltage Feedback 2
This pin is the inverting input of Error Amplifier 2. It is normally connected to the switching power
supply output through a resistor divider.
14
Drive Output 2 Enable
A logic low at this input disables Drive Output 2.
15
Vref
This is the 5.0 V reference output. It can provide bias for any additional system circuitry.
16
VCC
This pin is the positive supply of the control IC. The minimum operating voltage range after startup
is 11 V to 15.5 V.
Figure 1. Timing Resistor versus
Oscillator Frequency
50
14
100 pF
3.3 nF
500 pF
1.0 nF
12
10
2.2 nF
CT =
10 nF
VCC = 15 V
TA = 25°C
4.0
10 k
4
330 pF
5.0 nF
8.0
6.0
220 pF
30 k 50 k
100 k
300 k 500 k
fosc, OSCILLATOR FREQUENCY (Hz)
1.0 M
DCmax , DUTY CYCLE MAXIMUM (%)
R T, TIMING RESISTOR (k Ω )
16
Figure 2. Maximum Output Duty Cycle
versus Oscillator Frequency
48
46
Output 2
44
42
40
38
10 k
Output 1
VCC = 15 V
RT = 4.0 k to 16 k
CL = 15 pF
TA = 25°
30 k 50 k
100 k
300 k 500 k
fosc, OSCILLATOR FREQUENCY (Hz)
1.0 M
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
Figure 3. Error Amp Small–Signal
Transient Response
Figure 4. Error Amp Large–Signal
Transient Response
VCC = 15 V
AV = –1.0
TA = 25°C
2.50 V
200 mV/DIV
3.0 V
20 mV/DIV
2.55 V
VCC = 15 V
AV = –1.0
TA = 25°C
2.5 V
2.0 V
2.45 V
1.0 µs/DIV
1.0 µs/DIV
0
80
VCC = 15 V
VO = 1.5 V to 2.5 V
RL = 100 k
TA = 25°C
Gain
60
40
30
60
90
20
Phase 120
0
150
–20
10
100
1.0 k
10 k
100 k
1.0 M
180
10 M
Vth, CURRENT SENSE INPUT THRESHOLD (V)
100
Figure 6. Current Sense Input Threshold
versus Error Amp Output Voltage
φ, EXCESS PHASE (DEGREES)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
Figure 5. Error Amp Open Loop Gain and
Phase versus Frequency
0.6
VCC = 15 V
0.5
TA = 125°C
0.4
TA = 25°C
0.3
TA = –55°C
0.2
0.1
0
0
1.0
0
VCC = 15 V
–4.0
–8.0
TA = –55°C
–12
TA = 25°C
TA = 125°C
–20
–24
0
20
40
60
80
100
Iref, REFERENCE SOURCE CURRENT (mA)
MOTOROLA ANALOG IC DEVICE DATA
120
I SC, REFERENCE SHORT CIRCUIT CURRENT (mA)
∆Vref, REFERENCE VOLTAGE CHANGE (mV)
Figure 7. Reference Voltage Change
versus Source Current
–16
2.0
3.0
4.0
5.0
6.0
7.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
f, FREQUENCY (Hz)
Figure 8. Reference Short Circuit Current
versus Temperature
120
VCC = 15 V
RL ≤ 0.1 Ω
100
80
60
–55
–25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
5
MC34065 MC33065
VCC = 15 V
IO = 1.0 mA to 10 mA
TA = 25°C
Vsat , OUTPUT SATURATION VOLTAGE (V)
Figure 10. Reference Line Regulation
∆VO, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
∆VO, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Figure 9. Reference Load Regulation
VCC = 11 V to 15 V
TA = 25°C
1.0 ms/DIV
1.0 ms/DIV
Figure 11. Output Saturation Voltage
versus Load Current
Figure 12. Output Waveform
0
VCC
–1.0
Source Saturation
VCC = 15 V
(Load to Ground) 80 µs Pulsed Load
120 Hz Rate
TA = 25°C
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90% –
–2.0
TA = –55°C
Gnd
Sink Saturation
(Load to VCC)
200
400
600
IO, OUTPUT LOAD CURRENT (mA)
800
50 ns/DIV
Figure 14. Supply Current versus Supply Voltage
10 V/DIV
Figure 13. Output Cross Conduction Current
VCC = 15 V
CL = 15 pF
TA = 25°C
10 V/DIV
0
0
VO2, OUTPUT VOLTAGE 2; VO1, OUTPUT VOLTAGE 1
ICC, SUPPLY CURRENT
6
10% –
TA = 25°C
100 ns/DIV
32
ICC , SUPPLY CURRENT (mA)
1.0
TA = –55°C
50 mA/DIV
2.0
24
RT = 8.2 k
CT = 3.3 nF
VFB1,2 = 0 V
Current Sense 1,2 = 0 V
TA = 25°C
16
8.0
0
0
4.0
8.0
12
16
20
VCC, SUPPLY VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
OPERATING DESCRIPTION
The MC34065 series are high performance, fixed
frequency, dual channel current mode controllers specifically
designed for Off–Line and dc–to–dc converter applications.
These devices offer the designer a cost effective solution with
minimal external components where independent regulation
of two power converters is required. The Representative
Block Diagram is shown in Figure 15. Each channel contains
a high gain error amplifier, current sensing comparator, pulse
width modulator latch, and totem pole output driver. The
oscillator, reference regulator, and undervoltage lock–out
circuits are common to both channels.
Oscillator
The unique oscillator configuration employed features
precise frequency and duty cycle control. The frequency is
programmed by the values selected for the timing
components RT and CT. Capacitor CT is charged and
discharged by an equal magnitude internal current source
and sink, generating a symmetrical 50 percent duty cycle
waveform at Pin 2. The oscillator peak and valley thresholds
are 3.5 V and 1.6 V respectively. The source/sink current
magnitude is controlled by resistor RT. For proper operation
over temperature it must be in the range of 4.0 kΩ to 16 kΩ as
shown in Figure 1.
As CT charges and discharges, an internal blanking pulse
is generated that alternately drives the center inputs of the
upper and lower NOR gates high. This, in conjunction with a
precise amount of delay time introduced into each channel,
produces well defined non–overlapping output duty cycles.
Output 2 is enabled while CT is charging, and Output 1 is
enabled during the discharge. Figure 2 shows the Maximum
Output Duty Cycle versus Oscillator Frequency. Note that
even at 500 kHz, each output is capable of approximately
44% on–time, making this controller suitable for high
frequency power conversion applications.
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal as
shown in Figure 17. For reliable locking, the free–running
oscillator frequency should be set about 10% less than the
clock frequency. Referring to the timing diagram shown in
Figure 16, the rising edge of the clock signal applied to the
Sync input, terminates charging of CT and Drive Output 2
conduction. By tailoring the clock waveform symmetry,
accurate duty cycle clamping of either output can be
achieved. A circuit method for this, and multi–unit
synchronization, is shown in Figure 18.
Error Amplifier
Each channel contains a fully–compensated Error
Amplifier with access to the inverting input and output. The
amplifier features a typical dc voltage gain of 100 dB, and a
unity gain bandwidth of 1.0 MHz with 71° of phase margin
(Figure 5). The noninverting input is internally biased at 2.5 V
and is not pinned out. The converter output voltage is
typically divided down and monitored by the inverting input
through a resistor divider. The maximum input bias current is
–1.0 µA which will cause an output voltage error that is equal
to the product of the input bias current and the equivalent
input divider source resistance.
The Error Amp output (Pin 5, 12) is provided for external
loop compensation. The output voltage is offset by two diode
MOTOROLA ANALOG IC DEVICE DATA
drops (≈1.4 V) and divided by three before it connects to the
inverting input of the Current Sense Comparator. This
guarantees that no pulses appear at the Drive Output
(Pin 7, 10) when the error amplifier output is at its lowest
state (VOL). This occurs when the power supply is operating
and the load is removed, or at the beginning of a soft–start
interval (Figures 20, 21).
The minimum allowable Error Amp feedback resistance is
limited by the amplifier’s source current (0.5 mA) and the
output voltage (VOH) required to reach the comparator’s
0.5 V clamp level with the inverting input at ground. This
condition happens during initial system startup or when the
sensed output is shorted:
3.0 (0.5 V)
1.4 V
R
5800 W
f(min)
0.5 mA
)
[
+
Current Sense Comparator and PWM Latch
The MC34065 operates as a current mode controller,
whereby output switch conduction is initiated by the oscillator
and terminated when the peak inductor current reaches the
threshold level established by the Error Amplifier output.
Thus the error signal controls the peak inductor current on a
cycle–by–cycle basis. The Current Sense Comparator–PWM
Latch configuration used ensures that only a single pulse
appears at the Drive Output during any given oscillator cycle.
The inductor current is converted to a voltage by inserting a
ground–referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 6, 11) and compared to a level
derived from the Error Amp output. The peak inductor current
under normal operating conditions is controlled by the
voltage at Pin 5, 12 where:
V
– 1.4 V
(Pin 5, 12)
I
pk
3 R
S
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 0.5 V. Therefore the
maximum peak switch current is:
0.5 V
I
pk(max)
R
S
When designing a high power switching regulator it may
be desirable to reduce the internal clamp voltage in order to
keep the power dissipation of RS to a reasonable level. A
simple method to adjust this voltage is shown in Figure 19.
The two external diodes are used to compensate the internal
diodes, yielding a constant clamp voltage over temperature.
Erratic operation due to noise pickup can result if there is an
excessive reduction of the Ipk(max) clamp voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense input with a
time constant that approximates the spike duration will
usually eliminate the instability, refer to Figure 24.
+
+
7
MC34065 MC33065
Figure 15. Representative Block Diagram
VCC
Vref
15
R
2.5 V
Internal
Bias
R
1
20 k
Sync Input
3.6 V
3
RT
+
–
VCC +
UVLO –
Reference
Regulator
+
–
+
–
16
17 V
14 V
Vref
UVLO
Drive Output 1
Oscillator
CT
2
1.0 mA
Voltage 4
Feedback 1
Compensation 1
5
2R
+
–
Error
Amp 1
Current Sense
Comparator 1
–
+
0.5 V
PWM
Latch 1
S
Q
R
Current Sense 1
R
6
RS
Drive Output 2
14
1.0 mA
Voltage
Feedback 2 13
Compensation 2
Q1
7
250 µA
Drive Enable
Vin = 15 V
+
–
Error
Amp 2
2R
0.5 V
Current Sense
Comparator 2
–
+
R
PWM
Latch 2
S
R Q
R
Current Sense 2
11
12
Gnd
8
Drive Gnd
Q2
10
9
+
–
RS
= Sink Only
Positive True Logic
Figure 16. Timing Diagram
Sync Input
Capacitor CT
Latch 1
“Set” Input
Compensation 1
Current Sense 1
Latch 1
“Reset” Input
Drive Output 1
Drive Output 2
Enable
Latch 2
“Set” Input
Compensation 2
Current Sense 2
Latch 2
“Reset” Input
Drive Output 2
8
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
Undervoltage Lockout
Two Undervoltage Lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stages are enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 14 V and 10 V respectively.
The hysteresis and low startup current makes these devices
ideally suited to off–line converter applications where
efficient bootstrap startup techniques are required
(Figure 28). The Vref comparator disables the Drive Outputs
until the internal circuitry is functional. This comparator has
upper and lower thresholds of 3.6 V and 3.4 V. A 17 V zener
is connected as a shunt regulator from VCC to ground. Its
purpose is to protect the IC and power MOSFET gate from
excessive voltage that can occur during system startup. The
guaranteed minimum operating voltage after turn–on is 11 V.
Drive Outputs and Drive Ground
Each channel contains a single totem–pole output stage
that is specifically designed for direct drive of power
MOSFETs. The Drive Outputs are capable of up to ±1.0 A
peak current with a typical rise and fall time of 28 ns with a
1.0 nF load. Internal circuitry has been added to keep the
outputs in a sinking mode whenever an Undervoltage
Lockout is active. This characteristic eliminates the need for
an external pull–down resistor. Cross–conduction current in
the totem–pole output stage has been minimized for high
speed operation, as shown in Figure 13. The average added
power due to cross–conduction with VCC = 15 V is only
60 mW at 500 kHz.
Although the Drive Outputs were optimized for MOSFETs,
they can easily supply the negative base current required by
bipolar NPN transistors for enhanced turn–off (Figure 25).
The outputs do not contain internal current limiting, therefore
an external series resistor may be required to prevent the
peak output current from exceeding the 1.0 A maximum
rating. The sink saturation (VOL) is less than 0.4 V at 100 mA.
MOTOROLA ANALOG IC DEVICE DATA
A separate Drive Ground pin is provided and, with proper
implementation, will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. Figure 23 shows the proper ground connections
required for current sensing power MOSFET applications.
Drive Output 2 Enable Pin
This input is used to enable Drive Output 2. Drive Output 1
can be used to control circuitry that must run continuously
such as volatile memory and the system clock, or a remote
controlled receiver, while Drive Output 2 controls the high
power circuitry that is occasionally turned off.
Reference
The 5.0 V bandgap reference is trimmed to ±2.0%
tolerance at TJ = 25°C. The reference has short circuit
protection and is capable of providing in excess of 30 mA for
powering any additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout
should contain a ground plane with low current signal and
high current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC and
Vref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and the
converter output voltage–divider should be located close to
the IC and as far as possible from the power switch and
other noise generating components.
9
MC34065 MC33065
Figure 17. External Clock Synchronization
Figure 18. External Duty Cycle Clamp and
Multi–Unit Synchronization
Vref
15
R
15
Bias
8
R
220 pF
External
Sync
Input
6
20 k
1
3
RT
5.0 k
+
–
5
Osc
2
2
CT
4
+
– EA1
4
7
S
5.0 k
MC1455
3
The external diode clamp is required if the negative Sync current
is greater than –5.0 mA.
RB
5.0 Vref
R
Bias
R
20 k
1
5
2R
EA1
0.5 V
R
To additional MC34065’s
R
A
Dmax Drive Output 2 =
R )R
A
B
Figure 20. Soft–Start Circuit
VCC
16
15
+
–
4
Ǔ
Figure 19. Adjustable Reduction of Clamp Level
+
–
Osc
2
ǒ
C
20 k
3
Q
1.08
f+
R )R C
A
B
R
B
Dmax Drive Output 1 =
R )R
A
B
5
Vref
1
R
5.0 k
+
–
R
Bias
R
1
2R
0.5 V
R
RA
Vin
Vref
17 V
15
R
+
_
Bias
R
+
+ –
_
20 k
1
3
3
Osc
2
1.0 mA
+
–
4
R2
2R
0.5 V
R
–
+
PWM
Latch 1
S
Q
R
Clamp
10
[
ǒ )Ǔ
1.67
R2 1
R1
ǒ Ǔ
) 0.33 x 10–3 R1R1R2
) R2
1.0 mA
4
1.0 M
6
I
pk(max)
2
7
5
R1
V
VClamp
EA1
Osc
Q1
[
V
C
RS
+
–
EA1
2R
0.5 V
R
5
tSoft–Start ≈ 2100 C in µF
Clamp
R
S
Where: 0 ≤ VClamp ≤ 0.5 V
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
Figure 21. Adjustable Reduction of Clamp Level
with Soft–Start
Figure 22. MOSFET Parasitic Oscillations
VCC
VCC
Vin
16
16
Vref
15
R
Bias
R
1
+
+–
_
20 k
3
Osc
VClamp
+
–
EA1
R2
C
2R
0.5 V
R
Where: 0 ≤ VClamp ≤ 0.5 V
Clamp
[
ǒ )Ǔ
1.67
R2 1
R1
t
I
[
pk(max)
Soft–Start
V
+ ln
1
V
1–
3V
C
C
)
R1R2
R1 R2
+
+ –
_
–
+
+
–+
_
D1
1N5819
6
RS
RS
Series gate resistor Rg may be needed to damp high frequency
parasitic oscillations caused by the MOSFET input capacitance
and any series wiring inductance in the gate–source circuit. Rg
will decrease the MOSFET switching speed. Schottky diode
D1 is required if circuit ringing drives the output pin below
ground.
Figure 24. Current Waveform Spike Suppression
Vin
VCC
16
16
5.0 Vref
7
Q1
Clamp
Figure 23. Current Sensing Power MOSFET
VCC
Rg
–
+
Clamp
R
S
17 V
PWM
Latch 1
S
Q
R
7
6
MPSA63
+
+ –
–
Q1
5
R1
V
–
+
+
–+
_
5.0 Vref
17 V
PWM
Latch 1
S
Q
R
2
4
+
–+
_
5.0 Vref
Vin
Vin
17 V
5.0 Vref
D SENSEFET
S Power Ground to
G
Input Source Return
K
7
M
Drive Ground
to Pin 9
PWM
Latch 1
S
Q
R
[ RS pk DS(on)
Pin 6
) RS
DM(on)
R
Control Circuitry
Ground to Pin 8
V
6 RS
1/4W
I
R
+
+ –
–
–
+
+
–+
_
17 V
Q1
PWM
Latch 1
S
Q
R
7
R
6
C
RS
If: SENSEFET = MTP10N10M
RS = 200
Then: VPin 6 = 0.075 Ipk
Virtually lossless current sensing can be achieved with the implementation
of a SENSEFET power switch. For proper operation during over current
conditions, a reduction of the Ipk(max) clamp level must be implemented.
Refer to Figures 19 and 21.
MOTOROLA ANALOG IC DEVICE DATA
The addition of the RC filter will eliminate instability caused by
the leading edge spike on the current waveform.
11
MC34065 MC33065
Figure 25. Bipolar Transistor Drive
IB
+
0
–
Figure 26. Isolated MOSFET Drive
VCC
Vin
Vin
16
Base Charge
Removal
+
–+
_
5.0 V Ref
C1
+
17 V
Isolation
Boundary
+ –
–
–
+
RS
I
The totem–pole outputs can furnish negative base current for
enhanced transistor turn–off, with the addition of capacitor C1.
Q1
PWM
Latch 1
S
Q
R
+
pk
V
7
ǒǓ
6
R
NS
C
– 1.4 N
6)
P
N
3R
S
S
(Pin
D1
NP
Figure 27. Dual Charge Pump Converter
VCC = 15 V
+
16
15
2.5 V R
R
Bias
1
2
4
+
_
15 10
Osc
1.0 nF
17 V
+
+ –
_
20 k
3
12 k
+
–
5.0 Vref
47
+
–
1.0 mA
2R
–
+
EA1
R
0.5 V
5
PWM
Latch 1
S
Q
R
1N5819
+
7
47
) V + 2.5
O
15 10
+
250 µA
14
13
1.0 mA
+
–
EA2
2R
–
+
0.5 V
10
R1
ǒ )Ǔ
1N5819
R2
R1
1
–VO ≈ –VCC
47 +
Output Load Regulation
R
11
12
8
R2
Connect to Pin 4 for
closed–loop regulation.
6
PWM
Latch 2
S
R Q
R
+VO ≈ 2.0 VCC
+
9
IO (mA) +VO (V) –VO (V)
–14.7
29.8
0
–13.4
28.3
1.0
–12.9
27.9
5.0
–12.5
27.5
10
–9.5
24.4
50
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor
may be required when using tantalum or other low ESR capacitors. The positive output can provide excellent line and
load regulation by connecting the R2/R1 resistor divider as shown.
12
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
Figure 28. 125 Watt Off–Line Converter
10 Cold
<1 Hot
T
MDA +
970G5
T1
0.22
92 to 138 Vac
270
56 k
0.05
3.0 A
16
100
L1
T2 MUR110
MUR110
+
220
+
10
1N4148
9.0 V
+ 0.1 A
75 k
RTN
+
5.0 Vref
15
R
R
1
20 k
+
_
3
4.7
nF
5.6 k
2
2R
+
–
+
–
16.2 k
1.0 M
EA1
100
pF
T3
+
_
330
pF
+
–
0.5 V
PWM
Latch 1
S
Q
R
R
7
3300
pF
MTD
2N50
6
1N
4937
1.0 k
5
0.001
MUR
440
47 k
14
2R
+
13
–
–
4.7 k
47 k
EA2
180
pF
R
0.5 V
+
PWM
Latch 2
S
R Q
R
10
22
11
1.0 k
470 pF
Test
10
1000
+
1/2
4N35
10
MTH
8N45
12 V
+ 1.0 A
RTN
+
–12 V
1.0 A
L4
0.01
68 k
3.3 k 0.01
TL431A
3.3
12
8
330
L2
MPS
+ A20
0.001
1/2
4N35
330
+
1000
MUR415
100
470
pF
L3
MUR415
10
12 k
22
Osc
4
–
Bias
10 k
51 k
100 V
1.0 A
+
100
1.3 k
RTN
10 k
Output 2
Shutdown
0.082
9
Conditions
Line Regulation
100 V Output
±12 V Outputs
9.0 V Output
Vin = 92 to 138 Vac
IO = 1.0 A
IO = ±1.0 A
IO = 0.1 A
Load Regulation
100 V Output
±12 V Outputs
9.0 V Output
Vin = 115 Vac
IO = 0.25 A to 1.0 A
IO = ±0.25 A to ±1.0 A
IO = 0.08 A to 0.1 A
Output Ripple
100 V Output
±12 V Outputs
9.0 V Output
Vin = 115 Vac
IO = 1.0 A
IO = ±1.0 A
IO = 0.1 A
Short Circuit Current
100 V Output
±12 V Outputs
9.0 V Output
Vin = 115 Vac, RL = 0.1 Ω
Efficiency
Vin = 115 Vac, PO = 125 W
Results
∆ = 40 mV or ±0.02%
∆ = 32 mV or ±0.13%
∆ = 55 mV or ±0.31%
∆ = 50 mV or ±0.025%
∆ = 320 mV or ±1.2%
∆ = 234 mV or ±1.3%
40 mVpp
100 mVpp
60 mVpp
4.3 A
17 A
Output Hiccups
MOTOROLA ANALOG IC DEVICE DATA
T1 – 468 µH per section at 2.5 A,
Coilcraft E3496A.
T2 – Primary: 156 Turns, #34 AWG
Primary Feedback: 19 Turns, #34 AWG
Secondary: 17 Turns, #28 AWG
Core: TDK H7C1EE22–Z
Bobbin: BE22–6H
Gap: ≈0.001″ for a primary
inductance of 6.8 mH
T3 – Primary: 56 Turns, #23 AWG
(2 strands) Bifiliar Wound
Secondary: ±12 V, 4 Turns, #23 AWG
(4 strands) Quadfiliar Wound
Secondary 100 V: 32 Turns, #23 AWG
(2 strands) Bifiliar Wound
Core: Ferroxcube EEC 40–3C8
Bobbin: Ferroxcube 40–1112CP
Gap: ≈0.030″ for a primary
inductance of 212 µH
L1, L3, L4 – 25 µH at 1.0 A, Coilcraft Z7157.
L2 – 10 µH at 3.0 A, Coilcraft PCV–0–010–03.
86%
13
MC34065 MC33065
Figure 29. 125 Watt Off–Line Converter
5 11/16″
4 1/2″
Circuit View
AC Input
*
9.0 V
12 V –12 V
3300
MP5A30
10 k
L3
0.01
3.3 k
3300
L1
T
100 µF
200 V
0.001
1.0 kV
1000 µF
16 V
0.001
1.0 kV
MDA97005
MUR110
MUR415
270 µF
250 V
T3
198
0.05 µF 250 V
1000 µF
16 V
100 µF
200 V
L2
T2
T1
10 µF
16 V
MUR440
1.3 k
MUR110
3AG Fuse
0.22 µF 250 V
10 µF
16 V
.01
6.9 k
51 k
220 µF
16 V
TL431
L4
10 µF
16 V
1N4140
AC Line Input
100 V
4N35
MUR415
4.7 k
470
MTD2N50
MTH8N45
Heat Sink
0.082 Ω 2.0 W
Component View
14
1N4937
330 pF
1.0 kV
12 k 2.0 W
47 k
229
1.0 k
1.0 k
229
470
56 k 5.0 W
3.3 Ω 5.0 W
100
1N4937
10 k 5.0 W
3300 pF 500 V
1.0 M
100 µF
16 V
180
16.2 k
MC34065
4700
5.4 k
47 k
75 k
*100 V and ±12 V Shutdown
MOTOROLA ANALOG IC DEVICE DATA
MC34065 MC33065
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
DW SUFFIX
PLASTIC PACKAGE
CASE 751G–02
(SO–16L)
ISSUE A
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
9
–B–
8X
P
0.010 (0.25)
1
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA ANALOG IC DEVICE DATA
◊
15
*MC34065/D*
MC34065/D