TI1 MSP430F448IPZ Mixed signal microcontroller Datasheet

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
D
D
− Active Mode: 280 µA at 1 MHz, 2.2 V
− Standby Mode: 1.1 µA
− Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
Wake-Up From Standby Mode in Less
Than 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
16-Bit Timer_B With Three† or Seven‡
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1)†
− One USART (USART0)‡
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D Integrated LCD Driver for up to
160 Segments
D Bootstrap Loader
D Family Members Include:
D
− MSP430F435, MSP430F4351§:
16KB+256B Flash Memory,
512B RAM
− MSP430F436, MSP430F4361§:
24KB+256B Flash Memory,
1KB RAM
− MSP430F437, MSP430F4371§:
32KB+256B Flash Memory,
1KB RAM
− MSP430F447:
32KB+256B Flash Memory,
1KB RAM
− MSP430F448, MSP430F4481§:
48KB+256B Flash Memory,
2KB RAM
− MSP430F449, MSP430F4491§:
60KB+256B Flash Memory,
2KB RAM
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
†
MSP430F43x, and MSP430F43x1 devices
MSP430F44x, and MSP430F44x1 devices
§ The MSP430F43x1 and MSP430F44x1 devices are identical to
the MSP430F43x and MSP430F44x devices, respectively − with
the exception that the ADC12 module is not implemented.
‡
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 µs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
description (continued)
The MSP430x43x(1) and the MSP430x44x(1) series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F43x1 and MSP430F44x1 devices), one
or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid
crystal driver (LCD) with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and display it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
AVAILABLE OPTIONS{
PACKAGED DEVICES}
TA
−40°C to 85°C
PLASTIC 80-PIN QFP
(PN)
PLASTIC 100-PIN QFP
(PZ)
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
MSP430F4481IPZ
MSP430F4491IPZ
†
For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at www.ti.com.
‡ Package
drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
D Debugging and Programming Interface
−
MSP-FET430UIF (USB)
−
MSP-FET430PIF (Parallel Port)
D Debugging and Programming Interface with Target Board
−
MSP-FET430U100 (PZ package)
D Stand-Alone Target Board
−
MSP-TS430PZ100 (PZ package)
D Production Programmer
−
2
MSP-GANG430
POST OFFICE BOX 655303
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
AVCC
DVSS1
AVSS
PN PACKAGE
(TOP VIEW)
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
10
11
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
52
51
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P4.0/S9
S10
S11
S12
S13
S14
S15
S16
S17
P2.7/S18
P2.6/CAOUT/S19
S20
S21
S22
S23
P3.7/S24
P3.6/S25
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
pin designation, MSP430x4351IPZ, MSP430x4361IPZ, MSP430x4371IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
4
POST OFFICE BOX 655303
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75
74
73
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71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
AVCC
DVSS1
AVSS
PN PACKAGE
(TOP VIEW)
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
10
11
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
52
51
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P4.0/S9
S10
S11
S12
S13
S14
S15
S16
S17
P2.7/ADC12CLK/S18
P2.6/CAOUT/S19
S20
S21
S22
S23
P3.7/S24
P3.6/S25
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
pin designation, MSP430x4481IPZ, MSP430x4491IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
MSP430F4481IPZ
MSP430F4491IPZ
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
75
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71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x1 functional block diagram
XIN
XT2IN
XT2OUT
DVCC1/2 DVSS1/2
XOUT
AVCC
AVSS
P1
P2
P4
P3
8
8
Port 1
Port 2
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
P5
8
8
P6
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
MCLK
8 MHz
CPU
incl. 16
Registers
32KB
24KB
16KB
RAM
USART0
Port 3
1KB
512B
8 I/O
Port 4
8 I/O
Port 5
8 I/O
Port 6
6 I/O
UART Mode
SPI Mode
MAB
MDB
Emulation
Module
Watchdog
Timer
WDT
POR/
SVS/
Brownout
15/16-Bit
JTAG
Interface
Timer_B3
Timer_A3
3 CC Reg
Shadow
Reg
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
LCD
128/160
Segments
1,2,3,4 MUX
fLCD
RST/NMI
MSP430x43x functional block diagram
XIN
XT2IN
XT2OUT
DVCC1/2 DVSS1/2
XOUT
AVCC
AVSS
P1
P2
P4
P3
8
8
Port 1
Port 2
8
P5
8
P6
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
MCLK
8 MHz
CPU
incl. 16
Registers
Emulation
Module
32KB
24KB
16KB
RAM
1KB
512B
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
ADC12
Watchdog
Timer
WDT
USART0
Port 3
Port 4
Port 5
Port 6
8 I/O
8 I/O
8 I/O
6 I/O
UART Mode
SPI Mode
MAB
MDB
POR/
SVS/
Brownout
JTAG
Interface
12-Bit
8 Channels
<10µs Conv.
15/16-Bit
Timer_B3
Timer_A3
3 CC Reg
Shadow
Reg
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
LCD
128/160
Segments
1,2,3,4 MUX
fLCD
RST/NMI
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x44x1 functional block diagram
XIN
XT2IN
XT2OUT
DVCC1/2 DVSS1/2
XOUT
AVCC
AVSS
P1
P2
P4
P3
8
8
Port 1
Port 2
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
P5
8
8
P6
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
60KB
48KB
MCLK
8 MHz
CPU
incl. 16
Registers
RAM
2KB
Port 3
Port 4
Port 5
Port 6
8 I/O
8 I/O
8 I/O
6 I/O
USART0
USART1
UART Mode
SPI Mode
MAB
MDB
Emulation
Module
Hardware
Multiplier
MPY, MPYS
MAC,MACS
JTAG
Interface
Watchdog
Timer
WDT
POR/
SVS/
Brownout
15/16-Bit
Timer_B7
Timer_A3
7 CC Reg
Shadow
Reg
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
RST/NMI
MSP430x44x functional block diagram
XIN
XT2IN
XT2OUT
DVCC1/2 DVSS1/2
XOUT
AVCC
AVSS
P1
P2
P4
P3
8
8
Port 1
Port 2
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
8
P5
8
P6
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
60KB
48KB
32KB
MCLK
8 MHz
CPU
incl. 16
Registers
Emulation
Module
JTAG
Interface
RAM
2KB
1KB
Port 3
Port 4
Port 5
Port 6
8 I/O
8 I/O
8 I/O
6 I/O
USART0
USART1
UART Mode
SPI Mode
MAB
MDB
Hardware
Multiplier
MPY, MPYS
MAC,MACS
ADC12
POR/
SVS/
Brownout
12-Bit
8 Channels
<10µs Conv.
Watchdog
Timer
WDT
15/16-Bit
Timer_B7
Timer_A3
7 CC Reg
Shadow
Reg
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
RST/NMI
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x1 Terminal Functions
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
DVCC1
1
DVCC1
1
P6.3
2
I/O
P6.3
2
I/O
Digital supply voltage, positive terminal.
General-purpose digital I/O
P6.4
3
I/O
P6.4
3
I/O
General-purpose digital I/O
P6.5
4
I/O
P6.5
4
I/O
General-purpose digital I/O
P6.6
5
I/O
P6.6
5
I/O
General-purpose digital I/O
P6.7/SVSIN
6
I/O
P6.7/SVSIN
6
I/O
General-purpose digital I/O / input to brownout, supply voltage
supervisor
Reserved
7
Reserved
7
XIN
8
I
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT
9
O
XOUT
9
O
Output terminal of crystal oscillator XT1
DVSS
10
I
DVSS
10
I
Connect to DVSS
DVSS
11
I
DVSS
11
I
Connect to DVSS
P5.1/S0
12
I/O
P5.1/S0
12
I/O
General-purpose digital I/O / LCD segment output 0
P5.0/S1
13
I/O
P5.0/S1
13
I/O
General-purpose digital I/O / LCD segment output 1
P4.7/S2
14
I/O
S2
14
O
General-purpose digital I/O / LCD segment output 2
P4.6/S3
15
I/O
S3
15
O
General-purpose digital I/O / LCD segment output 3
P4.5/S4
16
I/O
S4
16
O
General-purpose digital I/O / LCD segment output 4
P4.4/S5
17
I/O
S5
17
O
General-purpose digital I/O / LCD segment output 5
P4.3/S6
18
I/O
S6
18
O
General-purpose digital I/O / LCD segment output 6
P4.2/S7
19
I/O
S7
19
O
General-purpose digital I/O / LCD segment output 7
P4.1/S8
20
I/O
S8
20
O
General-purpose digital I/O / LCD segment output 8
P4.0/S9
21
I/O
S9
21
O
General-purpose digital I/O / LCD segment output 9
S10
22
O
S10
22
O
LCD segment output 10
S11
23
O
S11
23
O
LCD segment output 11
S12
24
O
S12
24
O
LCD segment output 12
S13
25
O
S13
25
O
LCD segment output 13
S14
26
O
S14
26
O
LCD segment output 14
S15
27
O
S15
27
O
LCD segment output 15
S16
28
O
S16
28
O
LCD segment output 16
S17
29
O
S17
29
O
LCD segment output 17
P2.7/S18
30
I/O
S18
30
O
General-purpose digital I/O / LCD segment output 18
P2.6/CAOUT/S19
31
I/O
S19
31
O
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20
32
O
S20
32
O
LCD segment output 20
S21
33
O
S21
33
O
LCD segment output 21
S22
34
O
S22
34
O
LCD segment output 22
S23
35
O
S23
35
O
LCD segment output 23
P3.7/S24
36
I/O
S24
36
O
General-purpose digital I/O / LCD segment output 24
P3.6/S25
37
I/O
S25
37
O
General-purpose digital I/O / LCD segment output 25
P3.5/S26
38
I/O
S26
38
O
General-purpose digital I/O / LCD segment output 26
P3.4/S27
39
I/O
S27
39
O
General-purpose digital I/O / LCD segment output 27
Reserved, do not connect externally
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
NAME
NO.
P3.3/UCLK0/S28
40
I/O
S28
40
O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29
41
I/O
S29
41
O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30
42
I/O
S30
42
O
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31
43
I/O
S31
43
O
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/S36
48
I/O
General-purpose digital I/O / LCD segment output 36
P4.4/S37
49
I/O
General-purpose digital I/O / LCD segment output 37
P4.3/S38
50
I/O
General-purpose digital I/O / LCD segment output 38
P4.2/S39
51
I/O
General-purpose digital I/O / LCD segment output 39
COM0
44
O
COM0
52
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
45
I/O
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2
46
I/O
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3
47
I/O
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
R03
48
I
R03
56
I
P5.5/R13
49
I/O
P5.5/R13
57
I/O
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23
50
I/O
P5.6/R23
58
I/O
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33
51
I/O
P5.7/R33
59
I/O
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2
52
DVCC2
60
DVSS2
53
DVSS2
61
P4.1
62
I/O
General-purpose digital I/O
P4.0
63
I/O
General-purpose digital I/O
P3.7
64
I/O
General-purpose digital I/O
P3.6
65
I/O
General-purpose digital I/O
P3.5
66
I/O
General-purpose digital I/O
P3.4
67
I/O
General-purpose digital I/O
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7
72
I/O
General-purpose digital I/O
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.5/URXD0
12
54
I/O
Input port of fourth positive (lowest) analog LCD level (V5)
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
P2.4/UTXD0
55
I/O
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
56
I/O
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
57
I/O
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
58
I/O
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
59
I/O
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1
60
I/O
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
61
I/O
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.5/TACLK/
ACLK
62
I/O
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
63
I/O
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64
I/O
P1.3/TBOUTH/
SVSOUT
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1
65
I/O
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK
66
I/O
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0
67
I/O
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT
68
O
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
69
I
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI
70
I/O
TDO/TDI
90
I/O
Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK
71
I
TDI/TCLK
91
I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS
72
I
TMS
92
I
Test mode select. TMS is used as an input port for device programming
and test.
TCK
73
I
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
74
I
RST/NMI
94
I
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0
75
I/O
P6.0
95
I/O
General-purpose digital I/O
P6.1
76
I/O
P6.1
96
I/O
General-purpose digital I/O
P6.2
77
I/O
P6.2
97
I/O
General-purpose digital I/O
AVSS
78
AVSS
98
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
DVSS1
79
DVSS1
99
Digital supply voltage, negative terminal.
AVCC
80
AVCC
100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry;
must not power up prior to DVCC1/DVCC2.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x Terminal Functions
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
DVCC1
1
DVCC1
1
P6.3/A3
2
I/O
P6.3/A3
2
I/O
General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4
3
I/O
P6.4/A4
3
I/O
General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5
4
I/O
P6.5/A5
4
I/O
General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6
5
I/O
P6.6/A6
5
I/O
General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN
6
I/O
P6.7/A7/SVSIN
6
I/O
General-purpose digital I/O / analog input a7—12-bit ADC, analog /
input to brownout, supply voltage supervisor
VREF+
7
O
VREF+
7
O
Output of positive terminal of the reference voltage in the ADC
XIN
8
I
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT
9
O
XOUT
9
O
Output terminal of crystal oscillator XT1
VeREF+
10
I
VeREF+
10
I
Input for an external reference voltage to the ADC
VREF−/VeREF−
11
I
VREF−/VeREF−
11
I
Negative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
P5.1/S0
12
I/O
P5.1/S0
12
I/O
General-purpose digital I/O / LCD segment output 0
P5.0/S1
13
I/O
P5.0/S1
13
I/O
General-purpose digital I/O / LCD segment output 1
P4.7/S2
14
I/O
S2
14
O
General-purpose digital I/O / LCD segment output 2
P4.6/S3
15
I/O
S3
15
O
General-purpose digital I/O / LCD segment output 3
P4.5/S4
16
I/O
S4
16
O
General-purpose digital I/O / LCD segment output 4
P4.4/S5
17
I/O
S5
17
O
General-purpose digital I/O / LCD segment output 5
P4.3/S6
18
I/O
S6
18
O
General-purpose digital I/O / LCD segment output 6
P4.2/S7
19
I/O
S7
19
O
General-purpose digital I/O / LCD segment output 7
P4.1/S8
20
I/O
S8
20
O
General-purpose digital I/O / LCD segment output 8
P4.0/S9
21
I/O
S9
21
O
General-purpose digital I/O / LCD segment output 9
S10
22
O
S10
22
O
LCD segment output 10
S11
23
O
S11
23
O
LCD segment output 11
S12
24
O
S12
24
O
LCD segment output 12
S13
25
O
S13
25
O
LCD segment output 13
S14
26
O
S14
26
O
LCD segment output 14
S15
27
O
S15
27
O
LCD segment output 15
S16
28
O
S16
28
O
LCD segment output 16
S17
29
O
S17
29
O
LCD segment output 17
P2.7/ADC12CLK/
S18
30
I/O
S18
30
O
General-purpose digital I/O / conversion clock—12-bit ADC / LCD
segment output 18
P2.6/CAOUT/S19
31
I/O
S19
31
O
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20
32
O
S20
32
O
LCD segment output 20
S21
33
O
S21
33
O
LCD segment output 21
S22
34
O
S22
34
O
LCD segment output 22
S23
35
O
S23
35
O
LCD segment output 23
P3.7/S24
36
I/O
S24
36
O
General-purpose digital I/O / LCD segment output 24
P3.6/S25
37
I/O
S25
37
O
General-purpose digital I/O / LCD segment output 25
P3.5/S26
38
I/O
S26
38
O
General-purpose digital I/O / LCD segment output 26
P3.4/S27
39
I/O
S27
39
O
General-purpose digital I/O / LCD segment output 27
14
Digital supply voltage, positive terminal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
NAME
NO.
P3.3/UCLK0/S28
40
I/O
S28
40
O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29
41
I/O
S29
41
O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30
42
I/O
S30
42
O
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31
43
I/O
S31
43
O
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/S36
48
I/O
General-purpose digital I/O / LCD segment output 36
P4.4/S37
49
I/O
General-purpose digital I/O / LCD segment output 37
P4.3/S38
50
I/O
General-purpose digital I/O / LCD segment output 38
P4.2/S39
51
I/O
General-purpose digital I/O / LCD segment output 39
COM0
44
O
COM0
52
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
45
I/O
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2
46
I/O
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3
47
I/O
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
R03
48
I
R03
56
I
P5.5/R13
49
I/O
P5.5/R13
57
I/O
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23
50
I/O
P5.6/R23
58
I/O
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33
51
I/O
P5.7/R33
59
I/O
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2
52
DVCC2
60
DVSS2
53
DVSS2
61
P4.1
62
I/O
General-purpose digital I/O
P4.0
63
I/O
General-purpose digital I/O
P3.7
64
I/O
General-purpose digital I/O
P3.6
65
I/O
General-purpose digital I/O
P3.5
66
I/O
General-purpose digital I/O
P3.4
67
I/O
General-purpose digital I/O
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7/ADC12CLK
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.5/URXD0
54
I/O
Input port of fourth positive (lowest) analog LCD level (V5)
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
P2.4/UTXD0
55
I/O
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
56
I/O
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
57
I/O
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
58
I/O
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
59
I/O
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1
60
I/O
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
61
I/O
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.5/TACLK/
ACLK
62
I/O
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
63
I/O
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64
I/O
P1.3/TBOUTH/
SVSOUT
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1
65
I/O
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK
66
I/O
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0
67
I/O
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT
68
O
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
69
I
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI
70
I/O
TDO/TDI
90
I/O
Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK
71
I
TDI/TCLK
91
I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS
72
I
TMS
92
I
Test mode select. TMS is used as an input port for device programming
and test.
TCK
73
I
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
74
I
RST/NMI
94
I
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0/A0
75
I/O
P6.0/A0
95
I/O
General-purpose digital I/O / analog input a0 − 12-bit ADC
P6.1/A1
76
I/O
P6.1/A1
96
I/O
General-purpose digital I/O / analog input a1 − 12-bit ADC
P6.2/A2
77
I/O
P6.2/A2
97
I/O
General-purpose digital I/O / analog input a2 − 12-bit ADC
AVSS
78
AVSS
98
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry.
DVSS1
79
DVSS1
99
Digital supply voltage, negative terminal.
AVCC
80
AVCC
100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry; must not power up prior to DVCC1/DVCC2.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x44x1 Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DVCC1
1
P6.3
2
I/O
Digital supply voltage, positive terminal.
General-purpose digital I/O
P6.4
3
I/O
General-purpose digital I/O
P6.5
4
I/O
General-purpose digital I/O
P6.6
5
I/O
General-purpose digital I/O
P6.7/SVSIN
6
I/O
General-purpose digital I/O / analog input to brownout, supply voltage supervisor
Reserved
7
O
Reserved, do not connect externally
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
DVSS
10
I
Connect to DVSS
DVSS
11
I
Connect to DVSS
P5.1/S0
12
I/O
General-purpose digital I/O / LCD segment output 0
P5.0/S1
13
I/O
General-purpose digital I/O / LCD segment output 1
S2
14
O
LCD segment output 2
S3
15
O
LCD segment output 3
S4
16
O
LCD segment output 4
S5
17
O
LCD segment output 5
S6
18
O
LCD segment output 6
S7
19
O
LCD segment output 7
S8
20
O
LCD segment output 8
S9
21
O
LCD segment output 9
S10
22
O
LCD segment output 10
S11
23
O
LCD segment output 11
S12
24
O
LCD segment output 12
S13
25
O
LCD segment output 13
S14
26
O
LCD segment output 14
S15
27
O
LCD segment output 15
S16
28
O
LCD segment output 16
S17
29
O
LCD segment output 17
S18
30
O
LCD segment output 18
S19
31
O
LCD segment output 19
S20
32
O
LCD segment output 20
S21
33
O
LCD segment output 21
S22
34
O
LCD segment output 22
S23
35
O
LCD segment output 23
S24
36
O
LCD segment output 24
S25
37
O
LCD segment output 25
S26
38
O
LCD segment output 26
S27
39
O
LCD segment output 27
S28
40
O
LCD segment output 28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x44x1 Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
S29
41
O
LCD segment output 29
S30
42
O
LCD segment output 30
S31
43
O
LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36
48
I/O
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
49
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38
50
I/O
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39
51
I/O
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0
52
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03
56
I
P5.5/R13
57
I/O
General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
58
I/O
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33
59
I/O
General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DVCC2
60
DVSS2
61
P4.1/URXD1
62
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1
63
I/O
General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6
64
I/O
General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5
65
I/O
General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4
66
I/O
General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3
67
I/O
General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7
72
I/O
General-purpose digital I/O
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
18
Input port of fourth positive (lowest) analog LCD level (V5)
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x44x1 Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
90
I/O
TDI/TCLK
91
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
92
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
94
I
Reset input or nonmaskable interrupt input port
P6.0
95
I/O
General-purpose digital I/O
P6.1
96
I/O
General-purpose digital I/O
P6.2
97
I/O
General-purpose digital I/O
AVSS
98
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and
LCD resistive divider circuitry.
DVSS1
99
Digital supply voltage, negative terminal.
AVCC
100
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and
LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
Test data output port. TDO/TDI data output or programming data input terminal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x44x Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DVCC1
1
P6.3/A3
2
I/O
General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6
5
I/O
General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN
6
I/O
General-purpose digital I/O / analog input a7—12-bit ADC / analog input to brownout, supply voltage
supervisor
VREF+
7
O
Output of positive terminal of the reference voltage in the ADC
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
VeREF+
10
I
Input for an external reference voltage to the ADC
VREF−/VeREF−
11
I
Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
P5.1/S0
12
I/O
General-purpose digital I/O / LCD segment output 0
P5.0/S1
13
I/O
General-purpose digital I/O / LCD segment output 1
S2
14
O
LCD segment output 2
S3
15
O
LCD segment output 3
S4
16
O
LCD segment output 4
S5
17
O
LCD segment output 5
S6
18
O
LCD segment output 6
S7
19
O
LCD segment output 7
S8
20
O
LCD segment output 8
S9
21
O
LCD segment output 9
S10
22
O
LCD segment output 10
S11
23
O
LCD segment output 11
S12
24
O
LCD segment output 12
S13
25
O
LCD segment output 13
S14
26
O
LCD segment output 14
S15
27
O
LCD segment output 15
S16
28
O
LCD segment output 16
S17
29
O
LCD segment output 17
S18
30
O
LCD segment output 18
S19
31
O
LCD segment output 19
S20
32
O
LCD segment output 20
S21
33
O
LCD segment output 21
S22
34
O
LCD segment output 22
S23
35
O
LCD segment output 23
S24
36
O
LCD segment output 24
S25
37
O
LCD segment output 25
S26
38
O
LCD segment output 26
S27
39
O
LCD segment output 27
S28
40
O
LCD segment output 28
20
Digital supply voltage, positive terminal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
S29
41
O
LCD segment output 29
S30
42
O
LCD segment output 30
S31
43
O
LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36
48
I/O
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
49
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38
50
I/O
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39
51
I/O
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0
52
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03
56
I
P5.5/R13
57
I/O
General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
58
I/O
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33
59
I/O
General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DVCC2
60
DVSS2
61
P4.1/URXD1
62
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1
63
I/O
General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6
64
I/O
General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5
65
I/O
General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4
66
I/O
General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3
67
I/O
General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7/ADC12CLK
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
Input port of fourth positive (lowest) analog LCD level (V5)
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
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MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
90
I/O
TDI/TCLK
91
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
92
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
94
I
Reset input or nonmaskable interrupt input port
P6.0/A0
95
I/O
General-purpose digital I/O, analog input a0—12-bit ADC
P6.1/A1
96
I/O
General-purpose digital I/O, analog input a1—12-bit ADC
P6.2/A2
97
I/O
General-purpose digital I/O, analog input a2—12-bit ADC
AVSS
98
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12,
port 1, and LCD resistive divider circuitry.
DVSS1
99
Digital supply voltage, negative terminal.
AVCC
100
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12, port 1,
and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
22
Test data output port. TDO/TDI data output or programming data input terminal
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Indirect
D
D
D
D
D
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
MOV EDE,TONI
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
D
MOV #X,TONI
MOV #45,TONI
#45
−−> M(TONI)
D = destination
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
−
All clocks are active
D Low-power mode 0 (LPM0)
−
CPU is disabled
−
ACLK and SMCLK remain active, MCLK is disabled
−
FLL+ loop control remains active
D Low-power mode 1 (LPM1)
−
CPU is disabled
−
FLL+ loop control is disabled
−
ACLK and SMCLK remain active, MCLK is disabled
D Low-power mode 2 (LPM2)
−
CPU is disabled
−
MCLK, FLL+ loop control, and DCOCLK are disabled
−
DCO’s dc generator remains enabled
−
ACLK remains active
D Low-power mode 3 (LPM3)
−
CPU is disabled
−
MCLK, FLL+ loop control, and DCOCLK are disabled
−
DCO’s dc generator is disabled
−
ACLK remains active
D Low-power mode 4 (LPM4)
24
−
CPU is disabled
−
ACLK is disabled
−
MCLK, FLL+ loop control, and DCOCLK are disabled
−
DCO’s dc generator is disabled
−
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B7†
TBCCR0 CCIFG (see Note 2)
Maskable
0FFFAh
13
Timer_B7†
TBCCR1 to TBCCR6 CCIFGs
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12 (see Note 4)
ADC12IFG (see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFE8h
4
USART1 Receive‡
URXIFG1
Maskable
0FFE6h
3
USART1 Transmit‡
UTXIFG1
Maskable
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
†
’43x(1) uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x(1) uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6
CCIFGs, and TBIFG
‡ USART1 is implemented in ’44x(1) only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
4. ADC12 is not implemented in MSP430x43x1 and MSP430x44x1 devices.
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw–0
URXIE0
rw–0
5
4
ACCVIE
NMIIE
rw–0
3
2
1
OFIE
rw–0
rw–0
0
WDTIE
rw–0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
7
Address
6
BTIE
01h
rw–0
5
4
UTXIE1
URXIE1
rw–0
3
2
1
0
rw–0
URXIE1:
USART1: UART and SPI receive-interrupt enable (MSP430F44x(1) devices only)
UTXIE1:
USART1: UART and SPI transmit-interrupt enable (MSP430F44x(1) devices only)
BTIE:
Basic timer interrupt enable
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw–1
URXIFG0
4
3
2
NMIIFG
rw–0
1
OFIFG
rw–0
rw–1
0
WDTIFG
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0: UART and SPI receive flag
UTXIFG0:
USART0: UART and SPI transmit flag
7
Address
03h
6
BTIFG
rw
26
5
5
4
UTXIFG1
URXIFG1
rw–1
3
2
1
rw–0
URXIFG1:
USART1: UART and SPI receive flag (MSP430F44x(1) devices only)
UTXIFG1:
USART1: UART and SPI transmit flag (MSP430F44x(1) devices only)
BTIFG:
Basic timer flag
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module enable registers 1 and 2
7
UTXE0
Address
04h
rw–0
6
URXE0
USPIE0
5
4
3
1
0
2
1
0
rw–0
URXE0:
USART0: UART mode receive enable
UTXE0:
USART0: UART mode transmit enable
USPIE0:
USART0: SPI mode transmit and receive enable
Address
2
7
6
5
UTXE1
05h
rw–0
4
URXE1
USPIE1
3
rw–0
URXE1:
USART1: UART mode receive enable (MSP430F44x(1) devices only)
UTXE1:
USART1: UART mode transmit enable (MSP430F44x(1) devices only)
USPIE1:
USART1: SPI mode transmit and receive enable (MSP430F44x(1) devices only)
Legend: rw:
rw–0,1:
rw–(0,1):
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430F435
MSP430F4351
MSP430F436
MSP430F4361
MSP430F437
MSP430F4371
MSP430F447
MSP430F448
MSP430F4481
MSP430F449
MSP430F4491
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
24KB
0FFFFh − 0FFE0h
0FFFFh − 0A000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
60KB
0FFFFh − 0FFE0h
0FFFFh − 01100h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
1KB
05FFh − 0200h
2KB
09FFh − 0200h
2KB
09FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s
Guide, literature number SLAU265.
BSL Function
PN Package Pins
PZ Package Pins
Data Transmit
67 - P1.0
87 - P1.0
Data Receive
66 - P1.1
86 - P1.1
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
16KB
24KB
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n
Segment A
Information
Memory
Segment B
28
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peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
oscillator and system clock
The clock system in the MSP430x43x(1) and MSP43x44x(1) family of devices is supported by the FLL+ module,
which includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO),
and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both
low system cost and low power consumption. The FLL+ features a digital frequency-locked loop (FLL) hardware
that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the
watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs.
The FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
hardware multiplier (MSP430x44x(1) only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
watchdog timer (WDT)
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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29
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
USART0
The MSP430x43x(1) and the MSP430x44x(1) have one hardware universal synchronous/asynchronous
receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
USART1 (MSP430x44x(1) only)
The MSP430x44x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Operation of USART1 is identical to USART0.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
PN
PZ
DEVICE INPUT
SIGNAL
62 - P1.5
82 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
62 - P1.5
82 - P1.5
TACLK
INCLK
67 - P1.0
87 - P1.0
TA0
CCI0A
66 - P1.1
86 - P1.1
65 - P1.2
59 - P2.0
‡
MODULE INPUT
NAME
85 - P1.2
79 - P2.0
TA0
CCI0B
DVSS
GND
DVCC
VCC
TA1
CCI1A
CAOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
OUTPUT PIN NUMBER
PN
PZ
67 - P1.0
87 - P1.0
14 - P1.2
85 - P1.2
TA0
ADC12 (internal)‡
CCR1
TA1
15 - P1.3
CCR2
79 - P2.0
TA2
Not implemented in MSP430x43x1 and MSP430x44x1 devices.
Timer_B3 (MSP430x43x(1) only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
30
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
Timer_B7 (MSP430x44x(1) only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3/B7 SIGNAL CONNECTIONS†
INPUT PIN NUMBER
PN
PZ
DEVICE INPUT
SIGNAL
63 - P1.4
83 - P1.4
TBCLK
ACLK
SMCLK
SMCLK
63 - P1.4
83 - P1.4
TBCLK
INCLK
58 - P2.1
78 - P2.1
TB0
CCI0A
58 - P2.1
78 - P2.1
TB0
CCI0B
DVSS
GND
DVCC
VCC
57 - P2.2
77 - P2.2
TB1
CCI1A
57 - P2.2
77 - P2.2
TB1
CCI1B
GND
DVCC
VCC
56 - P2.3
76 - P2.3
TB2
CCI2A
56 - P2.3
76 - P2.3
TB2
CCI2B
DVSS
GND
67 - P3.4
67 - P3.4
DVCC
VCC
TB3
CCI3A
TB3
CCI3B
DVSS
GND
DVCC
VCC
66 - P3.5
TB4
CCI4A
66 - P3.5
TB4
CCI4B
DVSS
GND
65 - P3.6
65 - P3.6
64 - P3.7
‡
TBCLK
ACLK
DVSS
†
MODULE INPUT
NAME
DVCC
VCC
TB5
CCI5A
TB5
CCI5B
DVSS
GND
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0†
OUTPUT PIN NUMBER
PN
PZ
58 - P2.1
78 - P2.1
ADC12 (internal)‡
TB0
57 - P2.2
CCR1†
ADC12 (internal)‡
TB1
56 - P2.3
CCR2†
77 - P2.2
76 - P2.3
TB2
67 - P3.4
CCR3
TB3
66 - P3.5
CCR4
TB4
65 - P3.6
CCR5
TB5
64 - P3.7
CCR6
TB6
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
Not implemented in MSP430x43x1 and MSP430x44x1 devices.
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD driver
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
32
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_B7/
_
Timer_B3
(see Note 1)
Capture/compare register 6
TBCCR6
019Eh
Capture/compare register 5
TBCCR5
019Ch
Capture/compare register 4
TBCCR4
019Ah
Capture/compare register 3
TBCCR3
0198h
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 6
TBCCTL6
018Eh
Capture/compare control 5
TBCCTL5
018Ch
Capture/compare control 4
TBCCTL4
018Ah
Capture/compare control 3
TBCCTL3
0188h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Timer_A3
_
Reserved
017Eh
Reserved
017Ch
Reserved
017Ah
Reserved
0178h
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Reserved
016Eh
Reserved
016Ch
Reserved
016Ah
Reserved
Hardware
Multiplier
(MSP430x44x(1)
only)
0168h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Sum extend
SUMEXT
013Eh
Result high word
RESHI
013Ch
Result low word
RESLO
013Ah
Second operand
OP2
0138h
Multiply signed + accumulate/operand1
MACS
0136h
Multiply + accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
NOTE 1: Timer_B7 in the MSP430x44x(1) family has seven CCRs; Timer_B3 in the MSP430x43x(1) family has three CCRs.
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Flash
34
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
ADC12
Conversion memory 15
(not implemented in Conversion memory 14
MSP430F43x1 and
Conversion memory 13
MSP430F44x1)
Conversion memory 12
ADC12MEM15
015Eh
ADC12MEM14
015Ch
ADC12MEM13
015Ah
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
ADC memory-control register15
ADC12MCTL15
08Fh
ADC memory-control register14
ADC12MCTL14
08Eh
ADC memory-control register13
ADC12MCTL13
08Dh
ADC memory-control register12
ADC12MCTL12
08Ch
ADC memory-control register11
ADC12MCTL11
08Bh
ADC memory-control register10
ADC12MCTL10
08Ah
ADC memory-control register9
ADC12MCTL9
089h
ADC memory-control register8
ADC12MCTL8
088h
ADC memory-control register7
ADC12MCTL7
087h
ADC memory-control register6
ADC12MCTL6
086h
ADC memory-control register5
ADC12MCTL5
085h
ADC memory-control register4
ADC12MCTL4
084h
ADC memory-control register3
ADC12MCTL3
083h
ADC memory-control register2
ADC12MCTL2
082h
ADC memory-control register1
ADC12MCTL1
081h
ADC memory-control register0
ADC12MCTL0
080h
POST OFFICE BOX 655303
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0A4h
:
0A0h
09Fh
:
091h
090h
USART1
(MSP430F44x(1)
only)
Transmit buffer
U1TXBUF
07Fh
Receive buffer
U1RXBUF
07Eh
Baud rate
U1BR1
07Dh
Baud rate
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
USART0
Comparator_A
p
_
Comparator_A control1
CACTL1
059h
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
FLL+ Clock
FLL+ Control1
FLL_CTL1
054h
FLL+ Control0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
Basic Timer1
BT counter2
BT counter1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P5
POST OFFICE BOX 655303
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35
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P4
Port P3
Port P2
Port P1
Special
functions
p
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable2
ME2
005h
SFR module enable1
ME1
004h
SFR interrupt flag2
IFG2
003h
SFR interrupt flag1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
36
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage during program execution
VCC (AVCC = DVCC1 = DVCC2 = VCC) (see Note 1)
MSP430F43x(1),
MSP430F44x(1)
1.8
3.6
V
Supply voltage during program execution, SVS enabled, PORON=1
(see Note 1 and Note 2)
VCC (AVCC = DVCC1 = DVCC2 = VCC)
MSP430F43x(1),
MSP430F44x(1)
2
3.6
V
Supply voltage during flash memory programming
VCC (AVCC = DVCC1 = DVCC2 = VCC) (see Note 1)
MSP430F43x(1),
MSP430F44x(1)
2.7
3.6
V
0
0
V
−40
85
°C
Supply voltage, VSS (AVSS = DVSS1 = DVSS2 = VSS)
MSP430x43x(1),
MSP430x44x(1)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 3)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
32.768
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
VCC = 1.8 V
DC
4.15
VCC = 3.6 V
DC
8
Ceramic resonator
XT2 crystal frequency,
frequency f(XT2)
Crystal
Processor frequency (signal MCLK),
MCLK) f(System)
kHz
kHz
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
fSystem (MHz)
8 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Supply voltage range,
’F43x(1)/’F44x(1), during
program execution
4.15 MHz
1.8
2.7
3
Supply Voltage − V
Supply voltage range, ’F43x(1)/’F44x(1),
during flash memory programming
3.6
Figure 1. Frequency vs Supply Voltage, MSP430F43x(1) or MSP430F44x(1)
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
Active mode (see Note 1),
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32768 Hz
XTS_FLL=0, SELM=(0,1)
TA = −40°C
40°C to 85°C
I(LPM0)
Low power mode, (LPM0)
Low-power
(see Note 1 and Note 4)
TA = −40°C
40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 0
(see Note 2 and Note 4)
TA = −40°C
40°C to 85°C
I(AM)
VCC
TYP
MAX
2.2 V
280
350
3V
420
560
2.2 V
32
45
3V
55
70
2.2 V
11
14
3V
17
22
I(LPM3)
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
MHz
f(ACLK) = 32,768 Hz, SCG0 = 1
((see Note 3 and Note 4))
TA = 60°C
I(LPM4)
1.5
1.5
2
3
3.5
6
1.8
2.2
1.6
1.9
2.5
3.5
TA = 85°C
4.2
7.5
TA = −40°C
0.1
0.5
TA = 25°C
0.1
0.5
0.7
1.1
TA = 60°C
mode (LPM4)
Low-power mode,
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1
(see
Note
Note
(
N
t 2 and
dN
t 4)
22V
2.2
1
1.1
TA = −40°C
TA = 60°C
3V
22V
2.2
TA = 85°C
1.7
3
TA = −40°C
0.1
0.5
0.1
0.5
0.8
1.2
1.9
3.5
TA = 25°C
TA = 60°C
TA = 85°C
µA
A
A
µA
TA = 85°C
TA = 25°C
UNIT
A
µA
TA = −40°C
TA = 25°C
MIN
3V
µA
A
A
µA
µA
A
µA
A
NOTES: 1. Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM3 is measured with
active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified
in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal and OSCCAPx=1h.
4. Current consumption for brownout included.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
38
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6
PARAMETER
VIT+
Positive going input threshold voltage
Positive-going
VIT−
Negative going input threshold voltage
Negative-going
Vhys
Input voltage hysteresis (VIT+ − VIT−)
VCC
MIN
TYP
MAX
2.2 V
1.1
1.5
3V
1.5
1.9
2.2 V
0.4
0.9
3V
0.9
1.3
2.2 V
0.3
1.1
3V
0.5
1
UNIT
V
V
V
standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
PARAMETER
VIL
Low-level input voltage
VIH
High-level input voltage
VCC
MIN
22V/3V
2.2
TYP
MAX
UNIT
VSS
VSS+0.6
V
0.8×VCC
VCC
V
MAX
UNIT
inputs Px.x, TAx, TBx
PARAMETER
t(int)
TEST CONDITIONS
External interrupt
p timing
g
VCC
MIN
2.2 V/3 V
1.5
2.2 V
62
3V
50
2.2 V
62
3V
50
P t P1,
P1 P2:
P2 P1.x
P1 to
t P2.x,
P2 external
t
l trigger
ti
i
l
Port
signal
for the interrupt flag, (see Note 1)
TA0, TA1, TA2
t(cap)
f(TAext)
f(TBext)
f(TAint)
f(TBint)
Timer A Timer
B capture
Timer_A,
Timer_B
timing
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2)
Timer_A, Timer_B clock
frequency externally applied
to pin
TACLK TBCLK
TACLK,
TBCLK, INCLK: t(H) = t(L)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
TYP
cycle
ns
ns
2.2 V
8
3V
10
MHz
2.2 V
8
3V
10
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. Seven capture/compare registers in ’x44x(1) and three capture/compare registers in ’x43x(1).
leakage current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
Ilkg(P1.x)
Port P1
Port 1: V(P1.x)
±50
Ilkg(P2.x)
Port P2
Port 2: V(P2.x)
±50
Ilkg(P3.x)
Port P3
Port 3: V(P3.x)
Port P4
Port 4: V(P4.x)
Ilkg(P5.x)
Port P5
Port 5: V(P5.x)
±50
Ilkg(P6.x)
Port P6
Port 6: V(P6.x)
±50
Ilkg(P4.x)
Leakage
current
2 2 V/3 V
2.2
±50
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, P6
PARAMETER
VOH
VOL
High level output voltage
High-level
Low level output voltage
Low-level
TEST CONDITIONS
VCC
MIN
IOH(max) = −1.5 mA (See Note 1)
2.2 V
VCC−0.25
VCC
IOH(max) = −6 mA (See Note 2)
2.2 V
VCC−0.6
VCC
3V
VCC−0.25
VCC
IOH(max) = −6 mA (See Note 2)
3V
VCC−0.6
VCC
IOL(max) = 1.5 mA (See Note 1)
2.2 V
VSS
VSS+0.25
IOL(max) = 6 mA (See Note 2)
2.2 V
VSS
VSS+0.6
IOL(max) = 1.5 mA (See Note 1)
3V
VSS
VSS+0.25
IOL(max) = 6 mA (See Note 2)
3V
VSS
VSS+0.6
IOH(max) = −1.5 mA (See Note 1)
TYP
MAX
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
f(Px.y)
(1 ≤ x ≤ 6
6, 0 ≤ y ≤ 7)
CL = 20 pF,
IL = ±1.5 mA
f(ACLK)
P1.1/TA0/MCLK,
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
CL = 20 pF
f(MCLK)
f(SMCLK)
t(Xdc)
40
Duty cycle of output frequency
MIN
MAX
DC
5
VCC = 3 V
DC
7.5
f(System)
P1.5/TACLK/ACLK,
CL = 20 pF
VCC = 2.2 V / 3 V
f(ACLK) = f(LFXT1) = f(XT1)
40%
f(ACLK) = f(LFXT1) = f(LF)
30%
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(MCLK) = f(XT1)
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(SMCLK) = f(XT2)
POST OFFICE BOX 655303
TYP
VCC = 2.2 V
f(ACLK) = f(LFXT1)
f(MCLK) = f(DCOCLK)
f(SMCLK) = f(DCOCLK)
• DALLAS, TEXAS 75265
60%
70%
50%
40%
50%−
15 ns
60%
50%
50%+
15 ns
40%
60%
50%−
15 ns
50%
50%+
15 ns
UNIT
MHz
MHz
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
TA = 25°C
VCC = 2.2 V
P2.7
14
12
I OL − Typical Low-level Output Current − mA
I OL − Typical Low-level Output Current − mA
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.7
20
TA = 85°C
15
10
5
0
0.0
2.5
TA = 25°C
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 2
I OL − Typical High-level Output Current − mA
I OL − Typical High-level Output Current − mA
−6
−8
TA = 85°C
−12
TA = 25°C
0.5
3.0
3.5
0
VCC = 2.2 V
P2.7
−4
−14
0.0
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
−10
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−2
1.5
VOL − Low-Level Output Voltage − V
1.0
1.5
2.0
2.5
VCC = 3 V
P2.7
−5
−10
−15
−20
TA = 85°C
−25
−30
0.0
TA = 25°C
0.5
VOH − High-Level Output Voltage − V
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 5
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
f = 1 MHz
td(LPM3)
6
f = 2 MHz
Delay time
UNIT
6
2.2 V/3 V
f = 3 MHz
µs
6
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER
V(33)
V(23)
V(13)
TEST CONDITIONS
Voltage at P5.5/R13
Voltage at R33 to R03
I(R03)
R03 = VSS
Input
p leakage
g
P5.5/R13 = VCC/3
P5.6/R23 = 2 × VCC/3
I(R23)
V(Sxx2)
Segment line
voltage
I(Sxx) = −3
3 µA,
µA
42
POST OFFICE BOX 655303
VCC + 0.2
±20
No load at all
segment and
common lines
lines,
VCC = 3 V
V(Sxx3)
UNIT
V
[V(33)−V(03)] × 1/3 + V(03)
2.5
VCC = 3 V
MAX
VCC + 0.2
[V(33)−V(03)] × 2/3 + V(03)
VCC = 3 V
V(Sxx0)
V(Sxx1)
TYP
2.5
Voltage at P5.6/R23
Analog voltage
V(33) − V(03)
I(R13)
MIN
Voltage at P5.7/R33
±20
nA
±20
V(03)
V(03) − 0.1
V(13)
V(13) − 0.1
V(23)
V(23) − 0.1
V(33)
V(33) + 0.1
• DALLAS, TEXAS 75265
V
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(CC)
CAON 1 CARSEL
CAON=1,
CARSEL=0,
0 CAREF
CAREF=0
0
I(Refladder/RefDiode)
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1.6/CA0 and P1.7/CA1
V(Ref025)
V(Ref050)
Voltage @ 0.25 V
V
CC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
node
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
2.2 V / 3 V
0.23
0.24
0.25
node
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
2.2V / 3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
CC
V
CC
Voltage @ 0.5 V
VCC
CC
PCA0=1, CARSEL=1, CAREF=3,
P1 6/CA0 and P1.7/CA1;
P1 7/CA1;
No load at P1.6/CA0
TA = 85°C
UNIT
µA
A
µA
A
V(RefVT)
See Figure 6 and Figure 7
VIC
Common-mode input
voltage range
CAON=1
2.2 V / 3 V
0
VCC−1
Vp−VS
Offset voltage
See Note 2
2.2 V / 3 V
−30
30
mV
Vhys
Input hysteresis
CAON = 1
2.2 V / 3 V
mV
t(response LH)
t(response HL)
mV
0
0.7
1.4
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V
160
210
300
3V
80
150
240
TA = 25
25°C
C
Overdrive 10 mV, with filter: CAF = 1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
25°C
TA = 25
C
Overdrive 10 mV, without filter: CAF = 0
2.2 V
130
210
300
3V
80
150
240
TA = 25
25°C,
C,
Overdrive 10 mV, with filter: CAF = 1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
V
ns
µss
ns
µss
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
VCC = 2.2 V
600
VREF − Reference Voltage − mV
VREF − Reference Voltage − mV
VCC = 3 V
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
TA − Free-Air Temperature − °C
Figure 6. V(RefVT) vs Temperature
0V
0
−5
15
35
55
Figure 7. V(RefVT) vs Temperature
VCC
CAF
1
CAON
Low-Pass Filter
V+
V−
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
V+
t(response)
Figure 9. Overdrive Definition
44
75
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
95
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
dVCC/dt ≤ 3 V/s (see Figure 10)
VCC(start)
Vhys(B_IT−)
t(reset)
UNIT
2000
µs
0.7 × V(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12)
Brownout
(see Note 2)
V(B_IT−)
MAX
dVCC/dt ≤ 3 V/s (see Figure 10)
70
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V
2
130
V
1.71
V
180
mV
µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+
settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
typical characteristics
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
typical characteristics (Continued)
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
tf = tr
0
0.001
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
supply voltage supervisor/monitor (SVS)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 13)
5
dVCC/dt ≤ 30 V/ms
td(SVSon)
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0‡
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13)
20
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 13)
Vhys(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 13),
external voltage applied on A7
VCC/dt ≤ 3 V/s (see Figure 13)
V(SVS_IT−)
(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 13),
external voltage applied on A7
ICC(SVS)
(see Note 3)
NOM
VLD = 2 to 14
VLD = 15
70
120
MAX
UNIT
150
µs
2000
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT−)
× 0.004
V(SVS_IT−)
× 0.008
4.4
10.4
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61†
VLD = 13
3.24
3.5
3.76†
VLD = 14
3.43
3.7†
3.99†
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V/3 V
†
mV
V
µA
The recommended operating voltage range is limited to 3.6 V.
tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 3: The current consumption of the SVS module is not included in the ICC current consumption data.
‡
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
typical characteristics
Software Sets VLD>0:
SVS is Active
VCC
V(SVS_IT−)
V(SVSstart)
Vhys(SVS_IT−)
Vhys(B_IT−)
V(B_IT−)
VCC(start)
BrownOut
Region
Brownout
Region
Brownout
1
0
td(BOR)
SVSOut
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
VCC(drop) − V
Rectangular Drop
VCC(drop)
1.5
Triangular Drop
1
1 ns
1 ns
VCC
0.5
t pw
3V
0
1
10
100
1000
tpw − Pulse Width − µs
VCC(drop)
tf = tr
tf
tr
t − Pulse Width − µs
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER
MIN
f(DCOCLK)
f(DCO=2)
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS = 1
FN_8=FN_4=FN_3=FN_2=0;
f(DCO=27)
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS = 1
FN_8=FN_4=FN_3=FN_2=0;
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
f(DCO=2)
VCC = 2.2 V/3 V
TYP
MAX
1
VCC = 2.2 V
0.3
0.65
1.25
VCC = 3 V
0.3
0.7
1.3
VCC = 2.2 V
2.5
5.6
10.5
VCC = 3 V
2.7
6.1
11.3
VCC = 2.2 V
0.7
1.3
2.3
VCC = 3 V
0.8
1.5
2.5
VCC = 2.2 V
5.7
10.8
18
VCC = 3 V
6.5
12.1
20
VCC = 2.2 V
1.2
2
3
VCC = 3 V
1.3
2.2
3.5
FN 8 FN 4 FN 3 0 FN
FN_8=FN_4=FN_3=0,
FN_2=1;
2 1; DCOPLUS = 1
f(DCO=2)
FN 8 FN 4 0 FN_3=
FN_8=FN_4=0,
FN 3 1,
1 FN_2=x;
FN 2 x; DCOPLUS = 1
f(DCO=27)
FN 8 FN 4 0 FN_3=
FN_8=FN_4=0,
FN 3 1,
1 FN_2=x;
FN 2 x; DCOPLUS = 1
f(DCO=2)
FN 8 0 FN_4=
FN_8=0,
FN 4 1,
1 FN_3=
FN 3 FN_2=x;
FN 2 x; DCOPLUS = 1
f(DCO=27)
FN 8 0 FN_4=1,
FN 4 1 FN_3=
FN 3 FN_2=x;
FN 2 x; DCOPLUS = 1
FN_8=0,
f(DCO=2)
FN 8 1 FN
FN_8=1,
FN_4=FN_3=FN_2=x;
4 FN 3 FN 2 x; DCOPLUS = 1
f(DCO=27)
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS = 1
FN_8=1,FN_4=FN_3=FN_2=x;
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 16 for taps 21 to 27)
1 < TAP ≤ 20
1.06
Sn
TAP = 27
1.07
Temperature drift, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0
VCC = 2.2 V
–0.2
–0.3
–0.4
VCC = 3 V
–0.2
–0.3
–0.4
0
5
15
15.5
25
17.9
28.5
VCC = 2.2 V
1.8
2.8
4.2
VCC = 3 V
2.1
3.4
5.2
13.5
21.5
33
VCC = 3 V
16
26.6
41
VCC = 2.2 V
2.8
4.2
6.2
VCC = 3 V
4.2
6.3
9.2
VCC = 2.2 V
21
32
46
VCC = 3 V
30
46
70
VCC = 2.2 V
VCC = 2.2 V/3 V
f
(DCO)
f
(DCO3V)
9
10.3
VCC = 3 V
Drift with VCC variation, N(DCO) = 01Eh,
FN_8=FN_4=FN_3=FN_2=0, D= 2; DCOPLUS = 0
DV
f
VCC = 2.2 V
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.11
1.17
%/_C
%/V
(DCO)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC − V
−40
−20
0
20
40
60
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
48
UNIT
MHz
f(DCO=27)
Dt
f
TEST CONDITIONS
N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
fCrystal = 32.768 kHz
POST OFFICE BOX 655303
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85
TA − °C
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 16. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 2 5 in SCFI1 {N (DCO)}
Tolerance at Tap 2
Overlapping DCO Ranges:
uninterrupted frequency range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
POST OFFICE BOX 655303
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49
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
OSCCAPx = 0h
CXIN
CXOUT
VIL
VIH
Integrated input capacitance
Integrated output capacitance
Input levels at XIN
VCC
MIN
TYP
2.2 V / 3 V
2.2 V/3 V
10
OSCCAPx = 2h
2.2 V/3 V
14
OSCCAPx = 3h
2.2 V/3 V
18
OSCCAPx = 0h
2.2 V/3 V
0
OSCCAPx = 1h
2.2 V/3 V
10
OSCCAPx = 2h
2.2 V/3 V
14
OSCCAPx = 3h
2.2 V/3 V
2 2 V/3 V
2.2
UNIT
0
OSCCAPx = 1h
See Note 3
MAX
pF
pF
18
VSS
0.2 × VCC
V
0.8 × VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep the trace between the ’F43x(1)/44x(1) and the crystal as short as possible.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
CXT2IN
Integrated input capacitance
VCC = 2.2 V/3 V
CXT2OUT
Integrated output capacitance
VCC = 2.2 V/3 V
VIL
VIH
Input levels at XT2IN
MIN
NOM
MAX
2
pF
2
VCC = 2
2.2
2 V/3 V (see Note 2)
UNIT
pF
VSS
0.2 × VCC
V
0.8 × VCC
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER
t(τ)
USART0/1: deglitch time
TEST CONDITIONS
MIN
NOM
MAX
VCC = 2.2 V, SYNC = 0, UART mode
200
430
800
VCC = 3 V, SYNC = 0, UART mode
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
50
POST OFFICE BOX 655303
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
range (see Note 2)
All P6.0/A0 to P6.7/A7 terminals.
Analog inputs selected in ADC12MCTLx register
and P6Sel.x=1,
0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
IADC12
Operating supply current
into AVCC terminal
(see Note 3)
fADC12CLK = 5.0 MHz
ADC12ON = 1
1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
IREF+
CI
RI
NOTES: 1.
2.
3.
4.
Operating supply current
i t AVCC tterminal
into
i l
(see Note 4)
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5.0 MHz
ADC12ON = 0
0,
REFON = 1, REF2_5V = 0
VCC
MIN
NOM
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
2.2 V
0.65
1.3
3V
0.8
1.6
3V
0.5
0.8
2.2 V
0.5
0.8
3V
0.5
0.8
mA
mA
mA
Input capacitance
Only one terminal can be selected at one time,
P6.x/Ax
Input MUX ON resistance
0V ≤ VAx ≤ VAVCC
2.2 V
3V
40
pF
2000
Ω
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MAX
UNIT
1.4
VAVCC
V
VeREF+ > VREF−/VeREF− (see Note 3)
0
1.2
V
Differential external
reference voltage input
VeREF+ > VREF−/VeREF− (see Note 4)
1.4
VAVCC
V
IVeREF+
Static input current
0V ≤VeREF+ ≤ VAVCC
2.2 V/3 V
±1
µA
IVREF−/VeREF−
Static input current
0V ≤ VeREF− ≤ VAVCC
2.2 V/3 V
±1
µA
VeREF+
Positive external
reference voltage input
VeREF+ > VREF−/VeREF− (see Note 2)
VREF− /VeREF−
Negative external
reference voltage input
(VeREF+ −
VREF−/VeREF−)
VCC
MIN
NOM
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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51
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
Positive built-in
built in reference voltage
output
VREF+
MIN
REF2_5V = 1 for 2.5 V
IVREF+ ≤ IVREF+max
3V
2.4
2.5
2.6
REF2_5V = 0 for 1.5 V
IVREF+ ≤ IVREF+max
2.2 V/3 V
1.44
1.5
1.56
VREF+ + 0.15
REF2_5V = 1, IVREF+ ≤ 1mA
VREF+ + 0.15
Load current out of VREF+ terminal
IL(VREF)+
UNIT
V
0.01
−0.5
mA
3V
−1
2.2 V
±2
3V
±2
IVREF+ = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
3V
±2
LSB
3V
20
ns
IVREF+ = 500 µA +/− 100 µA
Analog input voltage ~0.75
0 75 V;
REF2_5V = 0
Load current regulation VREF+
Load-current
terminal
MAX
2.2
REF2_5V = 1, IVREF+ ≤ 0.5mA
2.2 V
IVREF+
TYP
V
REF2_5V = 0, IVREF+ ≤ 1mA
AVCC minimum
i i
voltage,
lt
P
Positive
iti
built-in reference active
AVCC(min)
VCC
IDL(VREF) +
Load current regulation VREF+
terminal
IVREF+ =100 µA → 900 µA,
CVREF+=5
5 µF
µF, Ax ~0.5
0 5 x VREF+
Error of conversion result ≤ 1 LSB
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
2.2 V/3 V
TREF+
Temperature coefficient of built-in
reference
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
tREFON
Settle time of internal reference
voltage (see Figure 18 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10µF,
VREF+ = 1.5 V
2.2 V
5
LSB
µF
10
±100
17
ppm/°C
ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 µF
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
tREFON
Figure 18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
52
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
DVCC1/DVCC2
From
Power
Supply
+
−
10 µ F
DVSS1/DVSS2
100 nF
AVCC
+
−
10 µ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
AVSS
10 µ F
VREF+ or VeREF+
100 nF
VREF−/VeREF−
+
−
10 µ F
MSP430F44x
100 nF
+
−
Apply
External
Reference
MSP430F43x
100 nF
Figure 19. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
From
Power
Supply
DVCC1/DVCC2
+
−
10 µ F
DVSS1/DVSS2
100 nF
AVCC
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
10 µ F
AVSS
MSP430F44x
100 nF
VREF+ or VeREF+
+
−
10 µ F
MSP430F43x
100 nF
Reference Is Internally
Switched to AVSS
VREF−/VeREF−
Figure 20. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
POST OFFICE BOX 655303
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53
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
fADC12CLK
fADC12OSC
tCONVERT
Internal ADC12
oscillator
Conversion time
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12
linearity parameters
2.2V/3 V
0.45
5
6.3
MHz
ADC12DIV=0,
fADC12CLK=fADC12OSC
2.2 V/ 3 V
3.7
6.3
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V/ 3 V
2.06
3.51
µs
External fADC12CLK from ACLK, MCLK
or SMCLK: ADC12SSEL ≠ 0
tADC12ON
Turn on settling time of
the ADC
See Note 1
tSample
Sampling time
RS = 400 Ω, RI = 1000 Ω,
CI = 30 pF
τ = [RS + RI] x CI;(see Note 2)
13×ADC12DIV×
1/fADC12CLK
µs
100
3V
1220
2.2 V
1400
ns
ns
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V
EI
Integral linearity error
1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [V(AVCC)]
ED
Differential linearity
error
EO
VCC
MIN
TYP
MAX
±2
UNIT
2 2 V/3 V
2.2
±1.7
LSB
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±1
LSB
Offset error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±2
±4
LSB
EG
Gain error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±1.1
±2
LSB
ET
Total unadjusted
error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±2
±5
LSB
54
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
REFON = 0, INCH = 0Ah,
ADC12ON=NA, TA = 25_C
2.2 V
40
120
3V
60
160
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V
986
986±5%
VSENSOR
3V
986
986±5%
2.2 V
3.55
3.55±3%
TCSENSOR
ADC12ON = 1
1, INCH = 0Ah
3V
3.55
3.55±3%
ISENSOR
Operating supply current into
AVCC terminal (see Note 1)
Sample time required if channel
10 is selected (see Note 2)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V
30
tSENSOR(sample)
3V
30
NA
Current into divider at channel 11
ADC12ON = 1, INCH = 0Bh,
(see Note 3)
2.2 V
IVMID
3V
NA
1.1
1.1±0.04
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC
2.2 V
VMID
3V
1.5
1.50±0.04
tVMID(sample)
Sample time required if channel
11 is selected (see Note 4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
UNIT
µA
A
mV
mV/°C
µss
A
µA
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). Therefore it includes the constant current through the sensor and the reference.
2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
3. No additional current is needed. The VMID is used during sampling.
4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
flash memory
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/
ERASE)
Program and Erase supply voltage
2.7
3.6
V
fFTG
Flash Timing Generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
Supply current from DVCC during erase
2.7 V/ 3.6 V
3
7
mA
tCPT
Cumulative program time
See Note 1
2.7 V/ 3.6 V
10
ms
tCMErase
Cumulative mass erase time
See Note 2
2.7 V/ 3.6 V
200
104
Program/Erase endurance
TJ = 25°C
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
35
tBlock, 0
Block program time for 1st byte or word
30
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
cycles
100
years
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
3V
2.2 V/ 3 V
25
MIN
TYP
MAX
UNIT
0
5
MHz
0
10
MHz
60
90
kΩ
TYP
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow: F versions
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
TEST
CONDITIONS
TA = 25°C
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
56
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MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
input/output schematics
port P1, P1.0 to P1.5, input/output with Schmitt trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
P1OUT.x
1
0
P1.x
1
Module X OUT
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
Set
Interrupt
Edge
Select
P1IES.x
Note: 0 < x< 5
Note: Port function is active if CAPD.x = 0
PnSel.x
PnDIR.x
P1Sel.0
P1DIR.0
P1Sel.1
‡
P1DIR.0
P1DIR.1
P1OUT.0
P1OUT.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
P1Sel.5
†
P1DIR.1
Direction
PnOUT.x
Control
From Module
P1DIR.5
P1DIR.5
P1OUT.5
P1SEL.x
Module X
OUT
Out0 sig.
†
PnIN.x
P1IN.0
P1IN.1
MCLK
†
Module X IN
CCI0A
CCI0B
†
†
†
P1IN.2
CCI1A
SVSOUT
P1IN.3
TBOUTH
SMCLK
P1IN.4
TBCLK
Out1 sig.
ACLK
P1IN.5
TACLK
‡
‡
†
PnIE.x
PnIFG.x
PnIES.x
P1IE.0
P1IFG.0
P1IES.0
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1IE.3
P1IFG.3
P1IES.3
P1IE.4
P1IFG.4
P1IES.4
P1IE.5
P1IFG.5
P1IES.5
Timer_A
Timer_B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P1, P1.6, P1.7, input/output with Schmitt trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
P1.6/
CA0
1
P1DIR.6
0
P1OUT.6
1
DVSS
Bus
Keeper
P1IN.6
EN
D
unused
P1IE.7
P1IRQ.07
EN
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
−
CA1
2
CAREF
Reference Block
Pad Logic
CAPD.7
Note: Port function is active if CAPD.7 = 0
P1SEL.7
0: input
1: output
0
P1DIR.7
P1.7/
CA1
1
P1DIR.7
0
P1OUT.7
1
DVSS
Bus
keeper
P1IN.7
EN
unused
D
P1IE.7
P1IRQ.07
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1IES.7
58
P1SEL.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
Module X IN
D
P2IE.x
P2IRQ.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
P2IES.x
Note:
P2SEL.x
x {0,4,5}
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2 sig. †
P2IN.0
CCI2A †
P2IE.0
P2IFG.0
P2IES.0
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
P2IN.5
URXD0
P2IE.5
P2IFG.5
P2IES.5
P2Sel.4
P2DIR.4
DVCC
P2OUT.4
UTXD0
P2Sel.5
P2DIR.5
DVSS
P2OUT.5
DVSS
‡
‡
PnIES.x
†Timer_A
‡USART0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
59
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P2, P2.1 to P2.3, input/output with Schmitt trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
Keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
D
Module X IN
P2IE.x
P2IRQ.x
Q
P2IFG.x
EN
Interrupt
Edge
Select
Set
P2IES.x
Note:
P2SEL.x
1<x <3
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
Out0 sig. †
P2IN.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
Out1 sig. †
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out2 sig. †
Module X IN
PnIE.x
PnIFG.x
CCI0A †
CCI0B
P2IE.1
P2IFG.1
P2IES.1
P2IN.2
CCI1A †
CCI1B
P2IE.2
P2IFG.2
P2IES.2
P2IN.3
CCI2A †
CCI2B
P2IE.3
P2IFG.3
P2IES.3
†Timer_B
60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PnIES.x
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P2, P2.6 to P2.7, input/output with Schmitt trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD‡
Segment xx‡
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
Keeper
P2.6/CAOUT/S19‡
P2.7/ADC12CLK/S18‡
P2IN.x
‡Segment
function
only available with
MSP430x43x(1)IPN
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
EN
Q
Set
Interrupt
Edge
Select
P2IES.x
Note:
P2SEL.x
6<x <7
‡
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
CAOUT †
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
0: LCDM<40h ‡
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
ADC12CLK§
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
0: LCDM<40h
Port/LCD
‡
†
Comparator_A
signal is 1 only with MSP430xIPN and LCDM ≥40h.
§ ADC12
‡Port/LCD
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
61
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P3, P3.0 to P3.3, input/output with Schmitt trigger
MSP430x43x(1)IPN (80-Pin) Only
0: Port active
1: Segment xx function active
LCDM.5
LCDM.6
LCDM.7
Pad Logic
Segment xx
x43xIPZ and x44xIPZ have no segment
function on Port P3: Both lines are low.
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
1
P3OUT.x
Module X OUT
Bus
Keeper
P3.0/STEO/S31†
P3.1/SIMO0/S30†
P3.2/SOMI0/S29†
P3.3/UCLK0/S28†
P3IN.x
EN
Module X IN
D
Note: 0 ≤ x ≤ 3
†
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P3OUT.0
DVSS
P3IN.0
STE0(in)
DCM_SIMO0 P3OUT.1
SIMO0(out)
P3IN.1
SIMO0(in)
P3DIR.2
DCM_SOMI0 P3OUT.2
SOMIO(out)
P3IN.2
SOMI0(in)
P3DIR.3
DCM_UCLK0 P3OUT.3
UCLK0(out)
P3IN.3
UCLK0(in)
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.1
P3DIR.1
P3Sel.2
P3Sel.3
DVSS
S24 to S31 shared with port function only at MSP430x43x(1)IPN (80-pin QFP)
Direction Control for SIMO0 and UCLK0
SYNC
MM
62
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
SYNC
MM
STC
STC
STE
STE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DCM_SOMI0
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P3, P3.4 to P3.7, input/output with Schmitt trigger
LCDM.7† or DVSS‡
0: Port active
1: Segment xx function active
Pad Logic
Segmentxx† or DVSS‡
TBOUTHiZ# or DVSS§
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
P3OUT.x
1
0
1
Module XOUT
Bus
Keeper
’x43x(1)IPN
80-Pin
’x43x(1)IPZ
’x44x(1)
100-Pin
P3IN.x
P3.4/S27
P3.5/S26
P3.6/S25
P3.7/S24
EN
Module X IN
Note:
D
P3.4
P3.5
P3.6
P3.7
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
4<x <7
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P3DIR.x
P3SEL.x
TBOUTHiZ
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
P3Sel.4
P3DIR.4
P3DIR.4
P3OUT.4
P3Sel.5
P3DIR.5
P3DIR.5
P3OUT.5
P3Sel.6
P3DIR.6
P3DIR.6
P3OUT.6
P3Sel.7
P3DIR.7
P3DIR.7
P3OUT.7
Module X
OUT
DVSS
OUT3
DVSS
OUT4
DVSS
OUT5
DVSS
OUT6
§
#
§
#
§
#
§
#
PnIN.x
P3IN.4
P3IN.5
P3IN.6
P3IN.7
Module X IN
unused §
CCI3A/B#
unused §
CCI4A/B#
unused §
CCI5A/B#
unused §
CCI6A #
†
MSP430x43x(1)IPN
MSP430x43x(1)IPZ, MSP430x44x(1)IPZ
§ MSP430x43x(1)
# MSP430x44x(1)
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
63
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P4, P4.0 to P4.7, input/output with Schmitt trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD§
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
1
0
1
P4OUT.x
Module X OUT
Bus
Keeper
x43x(1)IPN
80-Pin
QFP:
x43x(1)IPZ
100-Pin
QFP:
P4.7/S2
P4.6/S3
P4.5/S4
P4.3/S6
P4.4/S5
P4.2/S7
P4.1/S8
P4.0/S9
P4.7/S34
P4.6/S35
P4.5/S36
P4.3/S37
P4.4/S38
P4.2/S39
P4.0
P4.1
x44x(1)
P4IN.x
EN
Module X IN
Note:
†
‡
D
0<x<7
PnSel.x
PnDIR.x
P4Sel.0
P4DIR.0
Direction
Control
From Module
Module X
PnOUT.x
OUT
PnIN.x
Module X IN
P4OUT.0
DVSS†
UTXD1‡
P4IN.0
unused
DVSS‡
P4OUT.1
DVSS
P4IN.1
URXD1‡
DVSS
P4IN.2
unused†
STE1(in)‡
unused†
SIMO1(in)‡
P4DIR.0†
DVCC‡
P4DIR.1†
unused†
P4Sel.1
P4DIR.1
P4Sel.2
P4DIR.2
P4DIR.2†
DVSS‡
P4OUT.2
P4Sel.3
P4DIR.3
P4DIR3.†
DCM_SIMO1‡
P4OUT.3
DVSS†
SIMO1(out)‡
P4IN.3
P4Sel.4
P4DIR.4
P4DIR4.†
DCM_SOMI1‡
P4OUT.4
DVSS†
SOMI1(out)‡
P4IN.4
unused
SOMI1(in)‡
P4Sel.5
P4DIR.5
P4DIR5.†
DCM_UCLK1‡
P4OUT.5
DVSS†
UCLK1(out)‡
P4IN.5
unused†
UCLK1(in)‡
P4Sel.6
P4DIR.6
P4DIR.6
P4OUT.6
DVSS
P4IN.6
unused
P4Sel.7
P4DIR.7
P4DIR.7
P4OUT.7
DVSS
P4IN.7
unused
Signal at MSP430x43x(1)
Signal at MSP430x44x(1)
64
DEVICE
PORT BITS
PORT FUNCTION
x43x(1)IPN 80-pin QFP
P4.0 . . .P4.7
LCDM < 020h
LCDM ≥ 020h
x43x(1)IPZ 100-pin QFP
P4.2 . . .P4.5
LCDM < 0E0h
LCDM ≥ 0E0h
x44x(1)IPZ 100-pin QFP
P4.6 . . .P4.7
LCDM < 0C0h
LCDM ≥ 0C0h
POST OFFICE BOX 655303
LCD SEG. FUNCTION
• DALLAS, TEXAS 75265
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SMO1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
P4.1/URXD1
P4.0/UTXD1
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P4, P4.0 to P4.7, input/output with Schmitt trigger (continued)
Direction Control for SIMO1 and UCLK1
Direction Control for SOMI1
SYNC
SYNC
MM
DCM_SIMO1
DCM_UCLK1
MM
DCM_SOMI1
STC
STC
STE
STE
port P5, P5.0 to P5.1, input/output with Schmitt trigger
0: Port active
1: Segment function active
Port/LCD
Segment Pad Logic
Segment
Port Pad Logic
P5SEL.x
0
P5DIR.x
Direction Control
From Module
0: Input
1
1: Output
0
P5OUT.x
1
Module X OUT
Bus
Keeper
P5.0/S1
P5.1/S0
P5IN.x
EN
Module X IN
Note:
D
0 <x <1
PnSel.x
PnDIR.x
P5Sel.0
P5DIR.0
P5Sel.1
P5DIR.1
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
Segment
P5DIR.0
P5OUT.0
DVSS
P5IN.0
unused
S1
0: LCDM<20h
P5DIR.1
P5OUT.1
DVSS
P5IN.1
unused
S0
0: LCDM<20h
Dir. Control
from module
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Port/LCD
65
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P5, P5.2 to P5.4, input/output with Schmitt trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
Module X IN
D
Note:
66
2<x <4
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P5Sel.2
P5DIR.2
P5DIR.2
P5OUT.2
DVSS
P5IN.2
unused
COM1
P5SEL.2
P5Sel.3
P5DIR.3
P5DIR.3
P5OUT.3
DVSS
P5IN.3
unused
COM2
P5SEL.3
P5Sel.4
P5DIR.4
P5DIR.4
P5OUT.4
DVSS
P5IN.4
unused
COM3
P5SEL.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
LCD signal
Port/LCD
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P5, P5.5 to P5.7, input/output with Schmitt trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
Module X IN
D
Note:
5<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P5Sel.5
P5DIR.5
P5DIR.5
P5OUT.5
DVSS
P5IN.5
unused
R13
P5SEL.5
P5Sel.6
P5DIR.6
P5DIR.6
P5OUT.6
DVSS
P5IN.6
unused
R23
P5SEL.6
P5Sel.7
P5DIR.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
unused
R33
P5SEL.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
LCD signal
Port/LCD
67
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P6, P6.0 to P6.6, input/output with Schmitt trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
1
0: Input
1: Output
Pad Logic
P6.0/A0 ..
P6.6/A6
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
Note: Not implemented in the MSP430x43x1 and MSP430x44x1 devices
From ADC
To ADC
x: Bit Identifier, 0 to 6 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
68
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
port P6, P6.7, input/output with Schmitt trigger
P6SEL.x
VLP(SVS)=15
0
P6DIR.x
Direction Control
From Module
1
0: Input
1: Output
Pad Logic
P6.7/A7/SVSIN
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
Note: Not implemented in the MSP430x43x1 and MSP430x44x1 devices
From ADC
To ADC
To Brownout/SVS Module
x: Bit Identifier, 7 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
69
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
70
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
D
U
S
G
D
U
S
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
ITDI/TCLK
I(TF)
Figure 21. Fuse Check Mode Current MSP430x43x(1), MSP430x44x(1)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
71
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
Data Sheet Revision History
Literature
Number
Summary
SLAS344E
Added MSP430F43x1 devices
Updated functional block diagram (page 6)
Clarified test conditions in recommended operating conditions table (page 27)
Clarified test conditions in electrical characteristics table (page 28)
Added Port 2 through Port 5 to leakage current table (page 29)
Corrected y-axis unit on Figures 6 and 7; changed from V to mV (page 34)
Clarified test conditions in USART0/USART1 table (page 40)
Changed tCPT maximum value from 4 ms to 10 ms in Flash memory table (page 46)
SLAS344F
Added MSP430F43x1 devices in PZ (100 pin) package
SLAS344G
Added MSP430F44x1 devices
NOTE: Page and figure numbers refer to the respective document revision.
72
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Manual Update Sheet
SLAZ555 – December 2013
Corrections to MSP430x43x, MSP430x43x1, MSP430x44x
Data Sheet (SLAS344J)
Document Being Updated: MSP430x43x, MSP430x43x1, MSP430x44x Mixed Signal Microcontroller
Literature Number Being Updated: SLAS344J
Page Change or Add
61
In both entries in the "Port/LCD" column of the table:
0: LCDM < 40h should be changed to 0: LCDPx < 02h.
In note ‡:
LCDM ≥ 40h should be changed to LCDPx ≥ 02h.
62
In top left of the figure:
LCDM.5 should be changed to bit 0 of LCDPx, which is bit 5 of the LCDCTL register.
LCDM.6 should be changed to bit 1 of LCDPx, which is bit 6 of the LCDCTL register.
LCDM.7 should be changed to bit 2 of LCDPx, which is bit 7 of the LCDCTL register.
63
In top left of the figure:
LCDM.7 should be changed to bit 2 of LCDPx, which is bit 7 of the LCDCTL register.
64
In the table at the bottom of the page:
LCDM < 020h should be changed to LCDPx < 01h.
LCDM ≥ 020h should be changed to LCDPx ≥ 01h.
LCDM < 0E0h should be changed to LCDPx < 07h.
LCDM ≥ 0E0h should be changed to LCDPx ≥ 07h.
LCDM < 0C0h should be changed to LCDPx < 06h.
LCDM ≥ 0C0h should be changed to LCDPx ≥ 06h.
65
In both entries in the "Port/LCD" column of the table:
0: LCDM < 20h should be changed to 0: LCDPx < 01h.
SLAZ555 – December 2013
Submit Documentation Feedback
Corrections to MSP430x43x, MSP430x43x1, MSP430x44x Data Sheet
(SLAS344J)
Copyright © 2013, Texas Instruments Incorporated
1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430A046IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F449
REV #
MSP430A047IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F437
MSP430A062IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F448
MSP430A066IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F437-80
MSP430F4351IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4351
MSP430F4351IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4351
MSP430F4351IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4351
MSP430F4351IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4351
MSP430F435IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F435-80
MSP430F435IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F435-80
MSP430F435IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F435
MSP430F435IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F435
MSP430F4361IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4361
MSP430F4361IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4361
MSP430F4361IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4361
MSP430F436IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F436-80
MSP430F436IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F436-80
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430F436IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F436
MSP430F436IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F436
MSP430F4371IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4371
MSP430F4371IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4371
MSP430F4371IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4371
MSP430F4371IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4371
MSP430F437IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F437-80
MSP430F437IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F437-80
MSP430F437IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F437
MSP430F437IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F437
MSP430F447IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F447
MSP430F447IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F447
MSP430F4481IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4481
MSP430F4481IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4481
MSP430F448IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F448
MSP430F448IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F448
MSP430F4491IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4491
MSP430F4491IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F4491
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430F449IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F449
MSP430F449IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F449
REV #
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
MSP430F4351IPNR
LQFP
MSP430F4351IPZR
MSP430F435IPNR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430F435IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F4361IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430F4361IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F436IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430F436IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F4371IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430F4371IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F437IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430F437IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F447IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F4481IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F448IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F4491IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430F449IPZR
LQFP
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F4351IPNR
LQFP
MSP430F4351IPZR
LQFP
PN
80
1000
367.0
367.0
45.0
PZ
100
1000
367.0
367.0
45.0
MSP430F435IPNR
LQFP
MSP430F435IPZR
LQFP
PN
80
1000
367.0
367.0
45.0
PZ
100
1000
367.0
367.0
MSP430F4361IPNR
LQFP
45.0
PN
80
1000
367.0
367.0
45.0
MSP430F4361IPZR
MSP430F436IPNR
LQFP
PZ
100
1000
367.0
367.0
45.0
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F436IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F4371IPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F4371IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F437IPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430F437IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F447IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F4481IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F448IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F4491IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430F449IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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