TI1 OPA4377AQPWRQ1 Low-noise, low quiescent current, precision automotive grade operational precision automotive grade operational Datasheet

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OPA377-Q1, OPA2377-Q1, OPA4377-Q1
SBOS797A – MAY 2016 – REVISED MAY 2016
OPAx377-Q1 Low-Noise, Low Quiescent Current, Precision Automotive Grade Operational
Amplifier
1 Features
3 Description
•
•
The OPAx377-Q1 family of operational amplifiers are
wide-bandwidth CMOS amplifiers that provide very
low noise, low input bias current, and low offset
voltage while operating on a low quiescent current of
0.76 mA (typical).
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
Low Noise: 7.5 nV/√Hz at 1 kHz
0.1-Hz to 10-Hz Noise: 0.8 μVPP
Quiescent Current: 760 μA (typical)
Low Offset Voltage: 250 μV (typical)
Gain Bandwidth Product: 5.5 MHz
Rail-to-Rail Input and Output
Single-Supply Operation
Supply Voltage: 2.2 V to 5.5 V
Space-Saving Packages:
– SOT-23, VSSOP, TSSOP
The OPAx377-Q1 op amps are optimized for lowvoltage, single-supply applications. The exceptional
combination of ac and dc performance make them
ideal for a wide range of applications, including small
signal conditioning, audio, and active filters. In
addition, these parts have a wide supply range with
excellent PSRR, making them attractive for
applications that run directly from batteries without
regulation.
The OPA377-Q1 is available in the SOT23-5
package. The dual, OPA2377-Q1, is offered in the
MSOP-8 package and the quad OPA4377-Q1 is
offered in the TSSOP-14 package. All versions are
specified for operation from –40°C to +125°C.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
Active Cruise Control
Park Assist
Tire Pressure Monitoring
Infotainment
Active Filtering
Sensor Signal Conditioning
PACKAGE
BODY SIZE (NOM)
OPA377-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
OPA2377-Q1
VSSOP (8)
3.00 mm × 3.00 mm
OPA4377-Q1
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Low-Side Current Sense Amplifier
Load
VS
VBAT
+
VOUT = ISHUNT x RSHUNT x (1 + RF/RG)
ISHUNT
RSHUNT
RG
±
RF
Copyright © 2016, Texas
Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
SBOS797A – MAY 2016 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6
6
6
6
6
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA377-Q1 ............................
Thermal Information: OPA2377-Q1 ..........................
Thermal Information: OPA4377-Q1 ..........................
Electrical Characteristics: VS = 2.2 V to 5.5 V ..........
Typical Characteristics .............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Original (May 2016) to Revision A
•
2
Page
Changed device status from Product Preview to Production Data ....................................................................................... 1
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SBOS797A – MAY 2016 – REVISED MAY 2016
5 Pin Configuration and Functions
OPA377-Q1: DBV Package
5-Pin SOT23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Pin Functions: OPA377-Q1
PIN
NAME
+IN
NO.
I/O
DESCRIPTION
DBV
3
I
Noninverting input
Inverting input
–IN
4
I
NC
—
—
No internal connection (can be left floating)
OUT
1
O
Output
V–
2
—
Negative (lowest) power supply
V+
5
—
Positive (highest) power supply
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SBOS797A – MAY 2016 – REVISED MAY 2016
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OPA2377-Q1: DGK Package
8-Pin VSSOP and SOIC
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions: OPA2377-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
DGK
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
4
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SBOS797A – MAY 2016 – REVISED MAY 2016
OPA4377-Q1: PW Package
14-Pin TSSOP
Top View
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Pin Functions: OPA4377-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
PW
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) power supply
V+
4
—
Positive (highest) power supply
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SBOS797A – MAY 2016 – REVISED MAY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS = (V+) – (V–)
Supply voltage
Signal input terminal voltage
(2)
Signal input terminal current (2)
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
7
V
(V–) – 0.5
(V+) + 0.5
V
–10
10
mA
Output short-circuit current (3)
TA
MAX
Continuous
–40
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TA
MIN
MAX
Supply voltage
2.2
5.5
UNIT
V
Operating temperature
–40
150
°C
6.4 Thermal Information: OPA377-Q1
OPA377-Q1
THERMAL METRIC (1)
DBV (SOT23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
273.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
126.8
°C/W
RθJB
Junction-to-board thermal resistance
85.9
°C/W
ψJT
Junction-to-top characterization parameter
10.9
°C/W
ψJB
Junction-to-board characterization parameter
84.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2377-Q1
OPA2377-Q1
THERMAL METRIC
(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
171.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
63.9
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS797A – MAY 2016 – REVISED MAY 2016
Thermal Information: OPA2377-Q1 (continued)
OPA2377-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJB
Junction-to-board thermal resistance
92.8
°C/W
ψJT
Junction-to-top characterization parameter
9.2
°C/W
ψJB
Junction-to-board characterization parameter
91.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
6.6 Thermal Information: OPA4377-Q1
OPA4377-Q1
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
107.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.6
°C/W
RθJB
Junction-to-board thermal resistance
52.6
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
51.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics: VS = 2.2 V to 5.5 V
At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.25
1
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V
Input offset voltage
versus temperature
At TA = –40°C to +125°C, VS = 2.2 V to 5.5 V,
VCM < (V+) – 1.3 V
dVOS/dT
Input offset voltage
versus drift
At TA = –40°C to +125°C
PSRR
Input offset voltage
versus power supply
At TA = 25°C, VS = 2.2 V to 5.5 V,
VCM < (V+) – 1.3 V
5
Channel separation, dc (dual, quad)
mV
µV/V
0.32
2
μV/°C
5
28
μV/V
0.5
µV/V
INPUT BIAS CURRENT
IIB
Input bias current
±0.2
Input bias current
versus temperature
IOS
±10
pA
See Typical Characteristics
Input offset current
±0.2
pA
±10
pA
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
0.8
μVPP
en
Input voltage noise density
f = 1 kHz
7.5
nV/√Hz
in
Input current noise density
f = 1 kHz
2
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V–) < VCM < (V+) – 1.3 V
70
(V+) + 0.1
V
90
dB
Differential
6.5
pF
Common-mode
13
pF
134
dB
126
dB
INPUT CAPACITANCE
OPEN-LOOP GAIN
AOL
50 mV < VO < (V+) – 50 mV, RL = 10 kΩ
Open-loop voltage gain
112
100 mV < VO < (V+) – 100 mV, RL = 2 kΩ
FREQUENCY RESPONSE, VS = 5.5 V
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Electrical Characteristics: VS = 2.2 V to 5.5 V (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETER
GBW
Gain-bandwidth product
SR
Slew rate
tS
TEST CONDITIONS
G = +1
At 0.1%, 2-V step, G = +1
Settling time
THD+N
MIN
At 0.01%, 2-V step, G = +1
Overload recovery time
VIN × Gain > VS
Total harmonic distortion + noise
VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ
TYP
MAX
UNIT
5.5
MHz
2
V/μs
1.6
μs
2
μs
0.33
μs
0.00027%
OUTPUT
Voltage output swing from rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output impedance
At TA = 25°C, RL = 10 kΩ
10
At TA = –40°C to +125°C, RL = 10 kΩ
20
mV
40
mV
+30/–50
mA
See Typical Characteristics
Ω
150
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current
(per amplifier)
2.2
At TA = 25°C, IO = 0, VS = 5.5 V
0.76
At TA = –40°C to +125°C
5.5
V
1.05
mA
1.2
mA
+125
°C
TEMPERATURE
Specified temperature
8
–40
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6.8 Typical Characteristics
0
140
-20
120
-40
Gain
100
-60
Phase
80
-80
60
-100
40
-120
20
-140
0
-160
-20
0.1
1
10
100
120
1k
10k
100k
1M
Power-Supply Rejection Ratio (dB)
160
Phase Margin (°)
Open-Loop Gain (dB)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
V(+) Power-Supply Rejection Ratio
100
80
Common-Mode
Rejection Ratio
60
40
V(-) Power-Supply Rejection Ratio
20
0
-180
10M
100
10
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 2. Power-Supply and Common-Mode
Rejection Ratio vs Frequency
Figure 1. Open-Loop Gain and Phase vs Frequency
Open-Loop Gain (RL = 10kW)
140
120
500nV/div
Open-Loop Gain and PSRR (dB)
160
Power-Supply Rejection Ratio
(VS = 2.2V to 5.5V)
100
80
-50
0
-25
25
50
75
100
125
1s/div
150
Temperature (°C)
Figure 4. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 3. Open-Loop Gain and Power-Supply
Rejection Ratio vs Temperature
1
Total Harmonic Distortion + Noise (%)
Voltage Noise (nV/ÖHz)
100
10
1
VS = 5V, VCM = 2V, VOUT = 1VRMS
0.1
0.01
Gain = 10V/V
0.001
Gain = 1V/V
0.0001
1
10
100
1k
10k
100k
10
100
1k
Frequency (Hz)
Figure 5. Input Voltage Noise Spectral Density
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10k
100k
Frequency (Hz)
Figure 6. Total Harmonic Distortion and Noise
vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
1000
100
900
Quiescent Current (mA)
Common-Mode Rejection Ratio (dB)
110
90
80
70
800
700
600
60
50
500
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 7. Common-Mode Rejection Ratio
vs Temperature
Figure 8. Quiescent Current
vs Temperature
150
125
150
75
50
1000
125
VS = ±2.75V
Quiescent Current (mA)
ISC+
30
800
IQ
700
20
10
600
0
500
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Short-Circuit Current (mA)
40
900
Short-Circuit Current (mA)
50
ISC+
25
0
-25
ISC-
-50
-75
-100
-50
5.5
-25
0
25
50
75
100
Temperature (°C)
Supply Voltage (V)
Figure 10. Short-Circuit Current
vs Temperature
Figure 9. Quiescent and Short-Circuit Current
vs Supply Voltage
3
1000
VS = ±2.75
2
800
Output Voltage (V)
Input Bias Current (pA)
900
700
600
500
400
300
200
1
+150°C
+125°C
+25°C
-40°C
0
-1
-2
100
-3
0
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 11. Input Bias Current vs Temperature
10
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150
0
10
20
30
40
50
60
70
80
Output Current (mA)
Figure 12. Output Voltage vs Output Current
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
6
VS = 5.5V
VS = 5V
Population
Output Voltage (VPP)
5
4
3
VS = 2.5V
2
1
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
0
1k
10k
Offset Voltage (mV)
10M
Figure 14. Maximum Output Voltage vs Frequency
Figure 13. Offset Voltage
Production Distribution
50
G = +1
RL = 10kW
CL = 50pF
G = +1V/V
40
50mV/div
Small-Signal Overshoot (%)
1M
100k
Frequency (Hz)
30
20
10
0
10
100
1k
Time (400ns/div)
Load Capacitance (pF)
Figure 16.
Small-Signal Pulse Response
Figure 15.
Small-Signal Overshoot vs Load Capacitance
100
1V/div
Settling Time (ms)
G = +1
RL = 2kW
CL = 50pF
10
0.01%
1
0.1%
0.1
Time (2ms/div)
10
1
100
Closed-Loop Gain (V/V)
Figure 17. Large-Signal Pulse Response
Figure 18. Settling Time vs Closed-Loop Gain
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
140
Open-Loop Output Resistance (W)
1k
Channel Separation (dB)
120
100
80
60
40
20
0
100
10
400mA Load
2mA Load
1
0.1
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 19. Channel Separation vs Frequency
Figure 20. Open-Loop Output Resistance vs Frequency
2
T = 25°C
T = 85°C
T = 125°C
1.5
VOS (mV)
1
0.5
VCM = –2.75 V
VCM = 1.45 V
0
–0.5
–1
–1.5
–2
–3
–2.8 –2.6 –2.4 –2.2 –2 1.4 1.6
VCM (V)
1.8
2
2.2
2.4
C013
Figure 21. Input Offset Voltage vs Common-Mode Voltage
12
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SBOS797A – MAY 2016 – REVISED MAY 2016
7 Detailed Description
7.1 Overview
The OPAx377-Q1 family belongs to a new generation of low-noise operational amplifiers, giving customers
outstanding dc precision and ac performance. Low noise, rail-to-rail input and output, and low offset, drawing a
low quiescent current, make these devices ideal for a variety of precision and portable applications. In addition,
this device has a wide supply range with excellent PSRR, making it a suitable option for applications that are
battery-powered without regulation.
7.2 Functional Block Diagram
+V
NCH Input
Stage
+IN
Output
Stage
OUT
± IN
PCH Input
Stage
t
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±V
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7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx377-Q1 family of amplifiers has parameters that are fully specified from 2.2 V to 5.5 V (±1.1 V to ±2.75
V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with
regard to operating voltage or temperature are presented in the Typical Characteristics section.
7.3.2 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx377-Q1 series extends 100 mV beyond the supply rails. The
offset voltage of the amplifier is low, from approximately (V–) to (V+) – 1 V, as shown in Figure 22. The offset
voltage increases as common-mode voltage exceeds (V+) – 1 V. Common-mode rejection is specified from (V–)
to (V+) – 1.3 V.
Input Offset Voltage (mV)
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
Figure 22. Offset and Common-Mode Voltage
7.3.3 Input and ESD Protection
The OPAx377-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current steering diodes connected between the
input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table.
Figure 23 shows how a series input resistor may be added to the driven input to limit the input current. The
added resistor contributes thermal noise at the amplifier input and its value must be kept to a minimum in noisesensitive applications.
V+
IOVERLOAD
10 mA max
OPA377-Q1
VOUT
VIN
5 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Input Current Protection
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Feature Description (continued)
7.3.4 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
operational amplifier, the dc offset observed at the amplifier output may shift from the nominal value while the
EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions.
While all amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The
OPAx377-Q1 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier
response to EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is
designed for a cutoff frequency of approximately 75 MHz (–3 dB), with a roll-off of 20 dB per decade.
7.3.5 Capacitive Load and Stability
The OPAx377-Q1 series of amplifiers may be used in applications where driving a capacitive load is required. As
with all op amps, there may be specific instances where the OPAx377-Q1 can become unstable, leading to
oscillation. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to
consider when establishing whether an amplifier will be stable in operation. An op amp in the unity-gain (1 V/V)
buffer configuration and driving a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a
pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases
as the capacitive loading increases.
The OPAx377-Q1 in a unity-gain configuration can directly drive up to 250-pF pure capacitive load. Increasing
the gain enhances the ability of the amplifier to drive greater capacitive loads; see the typical characteristic plot,
Figure 15. In unity-gain configurations, capacitive load drive can be improved by inserting a small (10-Ω to 20-Ω)
resistor, RS, in series with the output, as shown in Figure 24. This resistor significantly reduces ringing while
maintaining dc performance for purely capacitive loads. However, if there is a resistive load in parallel with the
capacitive load, a voltage divider is created, introducing a gain error at the output and slightly reducing the output
swing. The error introduced is proportional to the ratio RS/RL, and is generally negligible at low output current
levels.
V+
RS
VOUT
OPA377-Q1
VIN
10 W to
20 W
RL
CL
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Improving Capacitive Load Drive
7.4 Device Functional Modes
The OPAx377-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.2 V (±1.1 V). The maximum power supply voltage for the OPAx376-Q1 is 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx377-Q1 family of operational amplifiers is built on a precision analog CMOS technology featuring low
noise and low offset voltage. The OPAx377-Q1 family delivers excellent offset voltage (250 μV, typical).
Additionally, the amplifier boasts a fast slew rate, low drift, low noise, and excellent PSRR and AOL. These 5.5MHz CMOS op amps operate on 760 μA (typical) quiescent current.
8.2 Typical Application
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA377-Q1 is ideally suited to construct high-speed, high-precision active filters. Figure 25 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
±
Output
+
C2
39 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Typical Application Schematic
8.2.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 25. Use Equation 1
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
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Typical Application (continued)
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 26. Low-Pass Filter Transfer Function
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9 Power Supply Recommendations
The OPAx377-Q1 family of devices is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices,
including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and mosteffective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted
to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds paying attention to the flow of the ground current. For
more detailed information refer to the application report, Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces
as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is
much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 28, keeping
RF and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the
most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process.
A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN
+
VOUT
±
RG
RF
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Texas Instruments Incorporated
Figure 27. Typical Schematic for PCB Layout Example
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Layout Example (continued)
VS+
VOUT
VS±
V+
OUT
GND
V±
Use a low-ESR,
ceramic bypass
capacitor.
Use a low-ESR,
ceramic bypass
capacitor.
RG
+IN
VIN
GND
±IN
GND
Run the input traces
as far away from
the supply lines
as possible.
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Typical PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5 and
SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP and SOT23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
20
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Circuit Board Layout Techniques, SLOA089
• Operational Amplifier Gain stability, Part 3: AC Gain-Error Analysis, SLYT383
• Operational Amplifier Gain Stability, Part 2: DC Gain-Error Analysis, SLYT374
• Op Amp Performance Analysis, SBOS054
• Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046
• Single-Supply Operation of Operational Amplifiers, SBOA059
• Tuning in Amplifiers, SBOA067
• Using Infinite-Gain, MFB Filter Topology in Fully Differential Active Filters, SLYT343
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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20-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2377QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2377
OPA377QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
377Q
OPA4377AQPWRQ1
PREVIEW
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
4377Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2377-Q1, OPA377-Q1 :
• Catalog: OPA2377, OPA377
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2377QDGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA377QDBVRQ1
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2377QDGKRQ1
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA377QDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
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