Power DI-40 2.5 v, 20 w dc-dc converter with synchronous rectification Datasheet

®
Design Idea DI-40
DPA-Switch 2.5 V, 20 W DC-DC
Converter with Synchronous Rectification
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
DC-DC Converter
DPA424R
20 W
36-75 VDC
2.5 V
Forward
Design Highlights
•
•
•
•
•
•
Capacitor C8 and the gate capacitance of Q1 reset T1 during
DPA-Switch off-time. Zener VR1 provides a hard voltage
clamp to limit DRAIN voltage under output transient and
overload conditions.
Extremely low component count
High efficiency - 86% using synchronous rectification
No current sense resistor or current transformer required
Output overload, open loop and thermal protection
Accurate input under/overvoltage meets ETSI standards
300 kHz switching frequency - optimizes efficiency when
simple self-driven synchronous rectification is used
Since the output voltage is low, the U2 LED is supplied with
a higher voltage derived from a winding on output choke L2.
The DPA-Switch bias supply is derived from a forward
winding on transformer T1. Flyback windings are not
recommended for this purpose, since the bias capacitor C4
would create high capacitive loading during DPA-Switch
off- time, preventing the transformer from efficiently resetting.
Operation
DPA-Switch greatly simplifies the design compared to a discrete
implementation. Resistor R1 programs the input UV/OV
thresholds. The tight tolerance of the UV/OV thresholds limits
the range of gate drive voltages applied to MOSFETs Q1 and
Q2, eliminating the need for gate voltage clamp circuitry. The
self-driven synchronous rectification configuration is therefore
very simple, with R13 filtering voltage spikes at the gate of Q2,
and D3 preventing the body diode of Q1 from conducting.
C7
1 nF
1.5 kV
Key Design Points
• For nominal under-voltage set point V UV :
R1=(VUV- 2.35 V)/50 µA. VOV = (R1 x 135 µA)+2.5 V.
• Locate C5, C6, and R4 close to U1 CONTROL pin, with
ground connected to SOURCE pin.
• Minimize primary and secondary layout loop area to
reduce parasitic inductance.
R14
10 Ω
L2
D3
3.3 µH
12CWQ03FM 8 A
+ VIN
T1
36 - 75 VDC
1
L1
1 µH 2.5 A
1
R13
10 Ω
Q2
SI4842DY
R5
C8
2.2 nF 1.0 Ω
4
2
3
L
D
C
X
D1
BAV19WS
D4
BAV19WS
U1
DPA424R
F
R3
15 kΩ
1%
R4
1.0 Ω
C5
0.22 µF
C6
68 µF
10 V
RTN
C12
4.7 µF
20 V
U2
R7
10 kΩ
D3
BAV19WS
R6
150 Ω
C15
10 µF
10 V
U3
LMV431
AIM5X
VIN
Figure 1. DPA-Switch 20 W DC to DC Converter.
.
DI-40
C11
1 µF
10 V
L3
2.2 mH
40 mA
C4
1 µF
U2
PC357
N1T
DPA-Switch
CONTROL
S
C9, C10
100 µF
10 V
6, 7
C3
1 µF
100 V
VR1
SMBJ150
2.5 V, 8 A
5, 6
2
D2
BAV19WS
Q1
SI4842DY
R1
619 kΩ
C1, C2
1 µF
100 V
7, 8
9, 10
www.powerint.com
R10
10.2 kΩ
1%
C13
100 nF
R12
5.1 Ω
R9
220 Ω
C14
1 µF
R11
10.0 kΩ
1%
PI-3264-051303
May 2003
DI-40
• Optocoupler U2 should have controlled CTR of 100-200%
for optimum loop stability.
• Size transformer reset components C8 and R5, and the Q1
gate capacitance to assure transformer reset at minimum
operating voltage without exceeding 170 V drain voltage
at high line.
• Set Zener VR1 clamp voltage to 150 V to guarantee both
transformer reset and limit DRAIN voltage below BVDSS.
• Scale primary side forward bias winding to provide
12 V to 15 V at minimum input voltage, nominal load.
• Secondary choke winding provides 5 V at nominal load.
• Main primary power return should be connected to the
DPA-Switch tab, not to the SOURCE pin.
• Consult AN-31 for additional design tips.
PI-3378-091702
95
90
Core Material
PR1408
EPCOS N87 material ungapped
Bobbin
P1408 8 pin
(B&B B-096 or equivalent)
Turns
Bias: 6T, 32 AWG
Primary: 7T + 7T, 2 x 28 AWG
Secondary: 2T, 4 x 26 AWG
Winding Order
(Pin Numbers)
Bias: (3-2), Tape
Primary: (4-FL), Tape
Secondary: (6, 7-9, 10), Tape
Primary: (FL-10), Tape
Primary Inductance
392 µH ± 25%
Primary Resonant
Frequency
3 MHz (minimum)
Leakage Inductance
1 µH (maximum)
Table 1. Transformer Construction Information.
85
Efficiency (%)
TRANSFORMER PARAMETERS
80
OUTPUT INDUCTOR PARAMETERS
75
Core
EPCOS N87 material
Gap for AL of 206 nH/T2
Bobbin
P1408 8 pin
(B&B B-096 or equivalent)
Winding Details
Bias: 10T, 32 AWG
Main: 4T, 4 x 26 AWG
Winding Order
(Pin Numbers)
Bias: (1-2), Tape
Main: (7,8-5,6), Tape
Inductance Pins 5,6-7,8
3.3 µH ± 10%
VIN = 36 VDC
VIN = 48 VDC
VIN = 60 VDC
VIN = 72 VDC
70
65
60
0
5
10
15
20
Output Power (W)
Figure 2. Efficiency vs. Output Power.
Table 2. Output Inductor Construction Information.
For the latest updates, visit our Web site: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license
under its patent rights or the rights of others. The products and applications illustrated herein (including circuits external to the products and
transformer construction) may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent
applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com.
The PI Logo, TOPSwitch, TinySwitch, LinkSwitch and EcoSmart are registered trademarks of Power Integrations, Inc.
PI Expert and DPA-Switch are trademarks of Power Integrations, Inc. ©Copyright 2003, Power Integrations, Inc.
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