CET CED3423 P-channel enhancement mode field effect transistor Datasheet

CED3423/CEU3423
P-Channel Enhancement Mode Field Effect Transistor
FEATURES
-30V, -18A, RDS(ON) = 45mΩ @VGS = -10V.
RDS(ON) = 80mΩ @VGS = -4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability.
D
Lead free product is acquired.
TO-251 & TO-252 package.
G
D
G
S
CEU SERIES
TO-252(D-PAK)
ABSOLUTE MAXIMUM RATINGS
Parameter
G
D
S
CED SERIES
TO-251(I-PAK)
Tc = 25 C unless otherwise noted
Symbol
Limit
-30
Units
V
VGS
±20
V
ID
-18
A
IDM
-72
A
31
W
Drain-Source Voltage
VDS
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
S
a
Maximum Power Dissipation @ TC = 25 C
PD
- Derate above 25 C
Operating and Store Temperature Range
0.25
W/ C
TJ,Tstg
-55 to 150
C
Thermal Characteristics
Symbol
Limit
Units
Thermal Resistance, Junction-to-Case
Parameter
RθJC
4
C/W
Thermal Resistance, Junction-to-Ambient
RθJA
50
C/W
Rev 2. 2006.Sep
http://www.cetsemi.com
Details are subject to change without notice .
1
CED3423/CEU3423
Electrical Characteristics
Parameter
TA = 25 C unless otherwise noted
Symbol
Test Condition
Min
Drain-Source Breakdown Voltage
BVDSS
VGS = 0V, ID = -250µA
-30
Zero Gate Voltage Drain Current
IDSS
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
Typ
Max
Units
VDS = -24V, VGS = 0V
-1
µA
IGSSF
VGS = 20V, VDS = 0V
100
nA
IGSSR
VGS = -20V, VDS = 0V
-100
nA
Off Characteristics
V
On Characteristics c
Gate Threshold Voltage
VGS(th)
Static Drain-Source
RDS(on)
On-Resistance
Forward Transconductance
Dynamic Characteristics
gFS
VGS = VDS, ID = -250µA
-3
V
37
45
mΩ
VGS = -4.5V, ID = -5A
62
80
mΩ
VDS = -15V, ID = -10A
4.5
S
840
pF
170
pF
100
pF
VGS = -10V, ID = -10A
-1
d
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VDS = -15V, VGS = 0V,
f = 1.0 MHz
Switching Characteristics d
Turn-On Delay Time
td(on)
Turn-On Rise Time
tr
Turn-Off Delay Time
td(off)
VDD = -15V, ID = -1A,
VGS = -10V, RGEN = 6Ω
10
20
ns
6
12
ns
40
80
ns
Turn-Off Fall Time
tf
23
45
ns
Total Gate Charge
Qg
12.5
16
nC
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = -15V, ID = -10A,
VGS = -10V
2
nC
2.4
nC
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current b
IS
Drain-Source Diode Forward Voltage c
VSD
VGS = 0V, IS = -10A
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.
2
-10
A
-1.3
V
CED3423/CEU3423
50
25
-ID, Drain Current (A)
-ID, Drain Current (A)
-VGS=10,8,6V
40
30
20
10
20
15
10
TJ=125 C
-VGS=3V
25 C
0
0
2
4
6
8
10
0
4
5
Figure 2. Transfer Characteristics
RDS(ON), Normalized
RDS(ON), On-Resistance(Ohms)
C, Capacitance (pF)
3
Figure 1. Output Characteristics
Ciss
800
600
400
Coss
200
Crss
0
0
5
10
15
20
25
2.2
1.9
ID=-10A
VGS=-10V
1.6
1.3
1.0
0.7
0.4
-100
-50
0
50
100
150
200
-VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
VDS=VGS
-IS, Source-drain current (A)
VTH, Normalized
Gate-Source Threshold Voltage
2
-VGS, Gate-to-Source Voltage (V)
1000
ID=-250µA
1.1
1.0
0.9
0.8
0.7
0.6
-50
1
-VDS, Drain-to-Source Voltage (V)
1200
1.2
-55 C
5
0
1.3
5
VGS=0V
10
10
10
-25
0
25
50
75
100
125
150
1
0
-1
0.4
0.6
0.8
1.0
1.2
1.4
TJ, Junction Temperature( C)
-VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
10
10 V =-15V
DS
ID=-10A
8
6
4
2
4
8
12
16
10ms
100ms
10
1
1s
DC
10
10
0
0
2
RDS(ON)Limit
-ID, Drain Current (A)
-VGS, Gate to Source Voltage (V)
CED3423/CEU3423
0
TC=25 C
TJ=150 C
Single Pulse
-1
10
-1
10
0
10
1
10
Qg, Total Gate Charge (nC)
-VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
t on
RL
V IN
D
td(off)
tf
90%
90%
VOUT
VOUT
VGS
RGEN
toff
tr
td(on)
10%
INVERTED
10%
G
90%
S
VIN
50%
50%
10%
PULSE WIDTH
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
Figure 9. Switching Test Circuit
10
0
D=0.5
0.2
10
-1
PDM
0.1
t1
0.05
t2
0.02
0.01
1. RθJC (t)=r (t) * RθJC
2. RθJC=See Datasheet
3. TJM-TC = P* RθJC (t)
4. Duty Cycle, D=t1/t2
Single Pulse
10
-2
10
-2
10
-1
10
0
10
1
10
2
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
10
3
10
4
2
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