¡ Semiconductor
¡ Semiconductor
MSM518121A
This version:
Jan. 1998
MSM518121A
Previous version: Dec. 1996
131,072-Word ¥ 8-Bit Multiport DRAM
DESCRIPTION
The MSM518121A is an 1-Mbit CMOS multiport memory composed of a 131,072-words by 8-bit
dynamic random access memory, RAM port, and a 256-word by 8-bit static serial access memory,
SAM port. The RAM port and SAM port operate independently and asynchronously.
The MSM518121A supports three types of operation: random access to and from the RAM port,
high speed serial access to and from the SAM port and bidirectional transfer of data between any
selected row in the RAM port and the SAM port. The RAM port and the SAM port can be accessed
independently except when data is being transferred between them internally.
FEATURES
• Single power supply of 5 V ±10% with a built-in VBB generator
• All inputs and outputs :TTL compatible
• Multiport organization
RAM port : 128K word ¥ 8 bits
SAM port : 256 word ¥ 8 bits
• RAM port
Fast page mode, Read modify write
CAS before RAS refresh, Hidden refresh
RAS only refresh, Standard write-per-bit
• SAM port
High speed serial
Read / Write capabillity
Fully static register
256 tap location
• RAM-SAM bidirectional, Read / Write / Pseudo write, Real time read transfer
• Package options:
40-pin 475 mil plastic ZIP
(ZIP40-P-475-1.27)
(Product : MSM518121A-xxZS)
40-pin 400 mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM518121A-xxJS)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time
Cycle Time
Power Dissipation
RAM
SAM
RAM
SAM
Operating
Standby
MSM518121A-70
70 ns
25 ns
140 ns
30 ns
120 mA
8 mA
MSM518121A-80
80 ns
25 ns
150 ns
30 ns
110 mA
8 mA
MSM518121A-10
100 ns
25 ns
180 ns
30 ns
100 mA
8 mA
1/33
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
W5/IO5
1
W7/IO7
3
SE
5
SIO6
7
SIO8
9
SC 11
SIO2 13
SIO4 15
W1/IO1 17
W3/IO3 19
W4/IO4 21
WB/WE 23
A8 25
VSS2 27
A5 29
NC 31
A7 33
A2 35
A0 37
CAS 39
2
W6/IO6
4
W8/IO8
6
SIO5
8
SIO7
10 VSS1
12 SIO1
14 SIO3
SC 1
40 VSS1
SIO1 2
39 SIO8
SIO2 3
38 SIO7
SIO3 4
37 SIO6
SIO4 5
36 SIO5
DT/OE 6
16 DT/OE
18 W2/IO2
34 W8/IO8
W2/IO2 8
33 W7/IO7
W3/IO3 9
32 W6/IO6
W4/IO4 10
31 W5/IO5
VCC1 11
24 RAS
30 VSS2
WB/WE 12
29 NC
NC 13
28 NC
RAS 14
27 CAS
NC 15
26 NC
A8 16
25 A0
A6 17
24 A1
A5 18
23 A2
A4 19
22 A3
VCC2 20
21 A7
26 A6
28 NC
30 A4
32 VCC2
34 A3
36 A1
38 NC
40 NC
40-Pin Plastic ZIP
40-Pin Plastic SOJ
Pin Name
A0 - A8
Function
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DT / OE
Data Transfer / Output Enable
WB / WE
Write per Bit / Write Enable
W1/IO1 - W8/IO8
Write Mask / Data IN, OUT
SC
Serial Clock
SE
Serial Enable
SIO1 - SIO8
VCC / VSS
NC
Note:
35 SE
W1/IO1 7
20 NC
22 VCC1
MSM518121A
Serial Input / Output
Power Supply (5 V) / Ground (0 V)
No Connection
The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
2/33
¡ Semiconductor
MSM518121A
I/O Buffer
(RAM)
SIO1
- SIO8
SE
SC
WB/WE
DT/OE
CAS
RAS
W1/IO1
- W8/IO8
BLOCK DIAGRAM
I/O Buffer
(SAM)
Timing Generator
Mask Register
SAM
512 ¥ 256 ¥ 8
Cell Array
Column
Address
Buffer
Row
Address
Buffer
Serial
Address
Counter
Row Decoder
Selector
Sense Amplifier
Column Decoder
Write/WPB Control
Refresh
Counter
VCC
A0 - A8
VSS
3/33
¡ Semiconductor
MSM518121A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
(Note : 16)
Unit
Symbol
Condition
Rating
Input Output Voltage
VT
Ta = 25°C
–1.0 to 7.0
V
Output Current
lOS
Ta = 25°C
50
mA
Power Dissipation
PD
Ta = 25°C
1
W
Operating Temperature
Topr
—
0 to 70
°C
Storage Temperature
Tstg
—
–55 to 150
°C
Recommended Operating Conditions
Parameter
(Ta = 0°C to 70°C) (Note : 17)
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
(VCC = 5 V ±10%, f = 1 MHz, Ta = 25°C)
Symbol
Min.
Max.
Unit
CI
—
7
pF
CI/O
—
9
pF
Input Capacitance
Input / Output Capacitance
Note :
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Symbol
Condition
Min.
Max.
Output "H" Level Voltage
VOH
IOH = –2 mA
2.4
—
Output "L" Level Voltage
VOL
IOL = 2 mA
—
0.4
Input Leakage Current
ILI
0 £ VIN £ VCC
All other pins
not under test = 0 V
–10
10
0 £ VOUT £ 5.5 V
Output Disable
–10
Parameter
Output Leakage Current
ILO
Unit
V
mA
10
4/33
¡ Semiconductor
MSM518121A
DC Characteristics 2
Item (RAM)
Operating Current
(RAS, CAS Cycling, tRC = tRC min.)
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
SAM
Symbol
-70
-80
-10
Max. Max. Max.
Unit Note
Standby
ICC1
85
75
65
1, 2
Active
ICC1A
120
110
100
1, 2
Standby Current
Standby
ICC2
8
8
8
3
(RAS, CAS = VIH)
Active
ICC2A
50
45
40
1, 2
RAS Only Refresh Current
(RAS Cycling, CAS = VIH, tRC = tRC min.)
Page Mode Current
(RAS = VIL, CAS Cycling, tPC = tPC min.)
CAS before RAS Refresh Current
(RAS Cycling, CAS before RAS, tRC = tRC min.)
Data Transfer Current
(RAS, CAS Cycling, tRC = tRC min.)
Standby
ICC3
85
75
65
1, 2
Active
ICC3A
120
110
100
1, 2
Standby
ICC4
70
65
60
Active
ICC4A
120
110
100
1, 2
Standby
ICC5
85
75
65
1, 2
mA
1, 2
Active
ICC5A
120
110
100
1, 2
Standby
ICC6
85
75
65
1, 2
Active
ICC6A
120
110
100
1, 2
5/33
¡ Semiconductor
MSM518121A
AC Characteristics (1/3)
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
Symbol
-70
-80
-10
Min. Max. Min. Max. Min. Max.
Unit Note
tRC
140
—
150
—
180
—
ns
tRWC
195
—
195
—
235
—
ns
tPC
45
—
50
—
55
—
ns
tPRWC
90
—
90
—
100
—
ns
tRAC
—
70
—
80
—
100
ns
7, 13
Access Time from Column Address
tAA
—
35
—
40
—
55
ns
7, 13
Access Time from CAS
tCAC
—
20
—
25
—
25
ns
7, 14
Access Time from CAS Precharge
tCPA
—
40
—
45
—
50
ns
7, 14
Output Buffer Turn-off Delay
tOFF
0
20
0
20
0
20
ns
9
6
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
Transition Time (Rise and Fall)
tT
3
35
3
35
3
35
ns
RAS Precharge Time
tRP
60
—
60
—
70
—
ns
100
RAS Pulse Width
tRAS
70
10k
80
10k
10k
ns
RAS Pulse Width (Fast Page Mode Only)
tRASP
70
100k
80
100k 100 100k
ns
RAS Hold Time
tRSH
20
—
25
CAS Hold Time
tCSH
70
—
CAS Pulse Width
tCAS
20
10k
RAS to CAS Delay Time
tRCD
20
50
RAS to Column Address Delay Time
tRAD
15
35
—
25
—
ns
80
—
100
—
ns
25
10k
25
10k
ns
20
55
20
75
ns
13
15
40
20
50
ns
13
Column Address to RAS Lead Time
tRAL
35
—
40
—
55
—
ns
CAS to RAS Precharge Time
tCRP
10
—
10
—
10
—
ns
CAS Precharge Time
tCPN
10
—
10
—
10
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
ns
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
15
—
15
—
15
—
ns
Column Address Hold Time referenced to RAS
tAR
55
—
55
—
70
—
ns
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
10
10
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
Write Command Hold Time
tWCH
15
—
15
—
15
—
ns
Write Command Hold Time referenced to RAS
tWCR
55
—
55
—
70
—
ns
Write Command Pulse Width
tWP
15
—
15
—
15
—
ns
Write Command to RAS Lead Time
tRWL
20
—
20
—
25
—
ns
Write Command to CAS Lead Time
tCWL
20
—
20
—
25
—
ns
6/33
¡ Semiconductor
MSM518121A
AC Characteristics (2/3)
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
Symbol
-70
-80
-10
Min. Max. Min. Max. Min. Max.
Unit Note
Data Set-up Time
tDS
0
—
0
—
0
—
ns
11
Data Hold Time
tDH
15
—
15
—
15
—
ns
11
Data Hold Time referenced to RAS
tDHR
55
—
55
—
70
—
ns
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
12
RAS to WE Delay Time
tRWD
100
—
100
—
130
—
ns
12
Column Address to WE Delay Time
tAWD
65
—
65
—
80
—
ns
12
CAS to WE Delay Time
tCWD
45
—
45
—
55
—
ns
12
Data to CAS Delay Time
tDZC
0
—
0
—
0
—
ns
Data to OE Delay Time
tDZO
0
—
0
—
0
—
ns
Access Time from OE
tOEA
—
20
—
20
—
25
ns
7
9
Output Buffer Turn-off Delay from OE
tOEZ
0
10
0
10
0
20
ns
OE to Data Delay Time
tOED
10
—
10
—
20
—
ns
OE Command Hold Time
tOEH
10
—
10
—
20
—
ns
RAS Hold Time referenced to OE
tROH
15
—
15
—
15
—
ns
CAS Set-up Time for CAS before RAS Cycle
tCSR
10
—
10
—
10
—
ns
CAS Hold Time for CAS before RAS Cycle
tCHR
10
—
10
—
10
—
ns
RAS Precharge to CAS Active Time
tRPC
0
—
0
—
0
—
ns
Refresh Period
tREF
—
8
—
8
—
8
ms
WB Set-up Time
tWSR
0
—
0
—
0
—
ns
WB Hold Time
tRWH
15
—
15
—
15
—
ns
Write Per Bit Mask Data Set-up Time
tMS
0
—
0
—
0
—
ns
Write Per Bit Mask Data Hold Time
tMH
15
—
15
—
15
—
ns
DT High Set-up Time
tTHS
0
—
0
—
0
—
ns
DT High Hold Time
tTHH
15
—
15
—
15
—
ns
DT Low Set-up Time
tTLS
0
—
0
—
0
—
ns
DT Low Hold Time
tTLH
15
10k
15
10k
15
10k
ns
tRTH
60
10k
65
10k
80
10k
ns
tATH
25
—
30
—
30
—
ns
tCTH
20
—
25
—
25
—
ns
DT Low Hold Time referenced to RAS
(Real Time Read Transfer)
DT Low Hold Time referenced to Column Address
(Real Time Read Transfer)
DT Low Hold Time referenced to CAS
(Real Time Read Transfer)
SE Set-up Time referenced to RAS
tESR
0
—
0
—
0
—
ns
SE Hold Time referenced to RAS
tREH
15
—
15
—
15
—
ns
DT to RAS Precharge Time
tTRP
60
—
60
—
70
—
ns
DT Precharge Time
tTP
20
—
20
—
30
—
ns
RAS to First SC Delay Time (Read Transfer)
tRSD
70
—
80
—
100
—
ns
Column Address to First SC Delay Time (Read Transfer)
tASD
45
—
45
—
50
—
ns
CAS to First SC Delay Time (Read Transfer)
tCSD
20
—
25
—
25
—
ns
Last SC to DT Lead Time (Real Time Read Transfer)
tTSL
5
—
5
—
5
—
ns
7/33
¡ Semiconductor
MSM518121A
AC Characteristics (3/3)
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
Symbol
-70
-80
-10
Min. Max. Min. Max. Min. Max.
Unit Note
DT to First SC Delay Time (Read Transfer)
tTSD
15
—
15
—
15
—
ns
Last SC to RAS Set-up Time (Serial Input)
tSRS
25
—
25
—
30
—
ns
RAS to First SC Delay Time (Serial Input)
tSRD
20
—
20
—
25
—
ns
RAS to Serial Input Delay Time
tSDD
40
—
40
—
50
—
ns
tSDZ
10
40
10
40
10
50
ns
tSCC
30
—
30
—
30
—
ns
SC Pulse Width (SC High Time)
tSC
10
—
10
—
10
—
ns
SC Precharge Time (SC Low Time)
tSCP
10
—
10
—
10
—
ns
Access Time from SC
tSCA
—
25
—
25
—
25
ns
Serial Output Hold Time from SC
tSOH
5
—
5
—
5
—
ns
Serial Output Buffer Turn-off Delay from RAS
(Pseudo Write Transfer)
SC Cycle Time
Serial Input Set-up Time
tSDS
0
—
0
—
0
—
ns
Serial Input Hold Time
tSDH
15
—
15
—
15
—
ns
Access Time from SE
tSEA
—
25
—
25
—
25
ns
SE Pulse Width
tSE
25
—
25
—
25
—
ns
SE Precharge Time
tSEP
25
—
25
—
25
—
ns
Serial Output Buffer Turn-off Delay from SE
tSEZ
0
20
0
20
0
20
ns
Serial Input to SE Delay Time
tSZE
0
—
0
—
0
—
ns
Serial Input to First SC Delay Time
tSZS
0
—
0
—
0
—
ns
Serial Write Enable Set-up Time
tSWS
5
—
5
—
5
—
ns
Serial Write Enable Hold Time
tSWH
15
—
15
—
15
—
ns
Serial Write Disable Set-up Time
tSWIS
5
—
5
—
5
—
ns
Serial Write Disable Hold Time
tSWIH
15
—
15
—
15
—
ns
9
8
8
9
8/33
¡ Semiconductor
Notes:
MSM518121A
1. These parameters depend on output loading. Specified values are obtained with the
output open.
2. These parameters are masured at minimum cycle test.
3. ICC2 (Max.) are mesured under the condition of TTL input level.
4. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between VIH and VIL.
5. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles
(DT/OE “high”) and any 8 SC cycles before proper divice operation is achieved. In
the case of using an internal refresh counter, a minimum of 8 CAS before RAS
initialization cycles in stead of 8 RAS cycles are required.
6. AC measurements assume tT = 5 ns.
7. RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF.
Output reference levels are VOH/VOL = 2.4 V/0.8 V.
8. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are VOH/VOL = 2.0 V/0.8 V.
9. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) difine the time at which the
outputs achieve the open circuit condition and are not reference to output voltage
levels.
10. Either tRCH or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to CAS leading edge of early write cycles and to
WB/WE leading edge in OE controlled write cycles and read modify write cycles.
12. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only.
If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will
remain open circuit (high impedance) throughout the entire cycle : If tRWD ≥ tRWD
(Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.) the cycle is a read-write cycle
and the data out will contain data read from the selected cell : If neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is
indterminate.
13. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD
(Max.) is specified as a reference point only : If tRCD is greater than the specified tRCD
(Max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD
(Max.) is specified as a reference point only : If tRAD is greater than the specified tRAD
(Max.) limit, then access time is controlled by tAA.
15. Input levels at the AC parameter measurement are 3.0 V/0 V.
16. Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permenent damege to the device.
17. All voltages are referenced to VSS.
9/33
¡ Semiconductor
MSM518121A
,,,
,
TIMING WAVEFORM
Read Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
CAS
tRSH
VIH –
VIL –
VIH –
VIL –
tCPN
tCAS
tASR
A0 - A8
tRCD
tRAD
tRAH
Row Address
tRAL
tCAH
tASC
Column Address
tRCH
tRRH
tRCS
WB/WE
VIH –
VIL –
tTHS
tROH
tTHH
VIH –
DT/OE V
IL –
tOEA
tDZO
IN
VIH –
VIL –
W1/IO1 W8/IO8
OUT
tCAC
tAA
tRAC
VOH –
VOL –
Open
tOFF
tOEZ
Valid Data-out
"H" or "L"
10/33
,,,
,
,,
¡ Semiconductor
MSM518121A
Write Cycle (Early Write)
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
tRCD
tRSH
tRAD
tASR
VIH –
A0 - A8
VIL –
tRAH
tRAL
tASC
tRWH
VIH –
VIL –
tCAH
Column Address
Row Address
tWSR
WB/WE
tCPN
tCAS
VIH –
CAS
VIL –
tWCS
tWCH
tWP
*1
tWCR
tTHS
tTHH
tMS
tMH
tCWL
tRWL
VIH –
DT/OE V
IL –
IN
VIH –
VIL –
WM1 Data
tDH
Valid Data-in
tDHR
W1/IO1 W8/IO8
OUT
tDS
VOH –
VOL –
Open
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
11/33
¡ Semiconductor
MSM518121A
Write Cycle (OE Controlled Write)
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
CAS
tRCD
VIH –
VIL –
tRAD
tRAH
tCPN
tRSH
tCAS
tRAL
,,
,
tASR
VIH –
A0 - A8
VIL –
Row Address
tASC
tCAH
Column Address
tCWL
tWSR
VIH –
WB/WE
VIL –
tRWH
tRWL
tWP
*1
tWCR
tTHS
tOEH
VIH –
DT/OE V
IL –
tMS
IN
VIH –
VIL –
WM1 Data
tDH
Valid Data-in
tDHR
W1/IO1 W8/IO8
OUT
tDS
tMH
VOH–
VOL –
Open
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
12/33
¡ Semiconductor
MSM518121A
Read Modify Write Cycle
tRWC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
tRCD
tRSH
VIH –
CAS
VIL –
tCPN
tCAS
tRAD
,
,
tASR
VIH –
A0 - A8
VIL –
tASC
tRAH
tCAH
Column Address
Row Address
tCWL
tWSR
VIH –
WB/WE
VIL –
tRWH
tRCS
tCWD
*1
tRWL
tWP
tAWD
tRWD
tTHH
tTHS
tOEH
VIH –
DT/OE
VIL –
tMS
IN
VIH –
VIL –
tOED
WM1 Data
W1/IO1 W8/IO8
OUT
tDS
tDZC
tDZO
tMH
Valid
Data-in
tOEA
tRAC
VOH–
VOL –
tAA
tDH
tCAC
Open
tOEZ
Valid
Data-out
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
13/33
¡ Semiconductor
MSM518121A
Fast Page Mode Read Cycle
tRASP
RAS
tAR
VIH –
VIL –
tRP
tPC
tRSH
tCRP
CAS
VIH –
VIL –
tCP
tRCD
tCP
tCAS
tRAD
tCSH
tRAH tASC
tCPN
tCAS
tCAS
tRAL
,,,
tASR
A0 - A8
VIH –
VIL –
Row
Address
tASC
tCAH
Column
Address 1
tCAH
tASC
Column
Address 2
tRCH
tCAH
Column
Address n
tRCH
tRCH
tRCS
tRCS
tRRH
tRCS
VIH –
WB/WE
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tDZO
tCPA
VIH –
IN
VIL –
W1/IO1 W8/IO8
OUT
tOEA
tCAC
VOH –
VOL –
tRAC
Open
tAA
tCPA
tOEA
tOFF
tOEZ
Data-out 1
tCAC
tAA
tOFF
tOEZ
Data-out 2
tOEA
tCAC
tAA
tOFF
tOEZ
Data-out n
"H" or "L"
14/33
¡ Semiconductor
MSM518121A
Fast Page Mode Write Cycle (Early Write)
tRASP
RAS
tAR
VIH –
VIL –
tRP
tPC
tRSH
tCRP
CAS
VIH –
VIL –
tRCD
tCP
tCP
tCAS
tRAD
tCSH
tRAH tASC
tCAS
tCPN
tCAS
tRAL
,
,,
,,,
tASR
A0 - A8
VIH –
VIL –
Row
Address
tCAH
tCAH
tASC
Column
Address 1
Column
Address 2
tWCR
tWSR
WB/WE
tRWH
tWCS
VIH –
VIL –
tCAH
Column
Address n
tWCH
tWCH
tWCH
tWCS
tWCS
tWP
tWP
tCWL
tTHS
tASC
tWP
tCWL
tRWL
tCWL
tTHH
VIH –
DT/OE V
IL –
tMH
tDS
tMS
IN
VIH –
VIL –
Data-in 1
tDH
tDS
tDH
tDS
Data-in 2
Data-in n
tDHR
W1/IO1 W8/IO8
OUT
WM1
Data
tDH
VOH –
VOL –
Open
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
15/33
¡ Semiconductor
MSM518121A
Fast Page Mode Read Modify Write Cycle
tRASP
tRP
tAR
RAS
VIH –
VIL –
tCSH
tPRWC
tRCD
tCAS
VIH –
CAS
VIL –
tRSH
tCP
tCP
tCAS
tCAS
tASC
tASC
tCWL
tASC
,
,
tASR tRAH
A0 - A8
WB/WE
VIH –
VIL –
Row
Address
tWSR
VIH –
VIL –
tTHS
VIH –
DT/OE V
IL –
W1/IO1 W8/IO8
VOH –
OUT V
OL –
Column
Address 1
tCWL
tCAH
Column
Address 2
tRWL
Column
Address n
tWP
tWP
tWP
tCWD
tCWD
tRWD
*1
tCWD
tTHH
tRFH
tMH
VIH –
VIL –
tCAH
tCWL
tRWH
tMS
IN
tCAH
tDS
tDZO
tDZC
tOED
WM1
Data
tDH
Datain 1
tOEA
tCAC
tOEZ
tAA
tRAC
tDS
tDZO
tDZC
tOED
tDH
Datain 2
tOEA
tCAC
tAA
Dataout 1
tOEZ
tDS
tDZO
tDZC
tOED
Datain n
tOEA
tCAC
tAA
Dataout 2
tDH
tOEZ
Dataout n
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
16/33
¡ Semiconductor
MSM518121A
RAS Only Refresh Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tRPC
tCRP
CAS
tCRP
VIH –
VIL –
,,,
,
tASR
A0 - A8
VIH –
VIL –
WB/WE
VIH –
VIL –
Row Address
tTHS
DT/OE
tRAH
tTHH
VIH –
VIL –
W1/IO1 - VOH–
W8/IO8 VOL –
Open
"H" or "L"
17/33
,
,
¡ Semiconductor
MSM518121A
CAS before RAS Refresh Cycle
tRC
tRP
VIH –
RAS
VIL –
tRP
tRAS
tRPC
tCSR
tCPN
tCHR
VIH –
CAS
VIL –
WB/WE
VIH –
VIL –
VIH –
DT/OE V
IL –
tOFF
W1/IO1 - VOH–
W8/IO8 VOL –
Open
Note: A0 - A8 = Don't care ("H" or "L")
"H" or "L"
18/33
¡ Semiconductor
MSM518121A
Hidden Refresh Cycle
tRC
tRC
tRAS
RAS
tRAS
tRP
tRP
tAR
VIH –
VIL –
tCRP
tRSH
tRCD
tCHR
tCPN
VIH –
CAS
VIL –
,
,
tRAD
tASR
VIH –
A0 - A8
VIL –
tASC
tRAH
tRAL
tCAH
Column
Address
Row Address
tWSR
tRCS
WB/WE
tRWH
VIH –
VIL –
tTHS
DT/OE
tRRH
tROH
tTHH
VIH –
VIL –
tOEZ
tOFF
W1/IO1 - VOH–
W8/IO8 VOL –
tAA
tOEA
tCAC
tOFF
tOEZ
Valid Data-out
"H" or "L"
19/33
¡ Semiconductor
MSM518121A
,
Read Transfer Cycle (Previous Transfer is Write Transfer Cycle)
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
tRCD
tRAD
tASR
VIH –
A0 - A8
VIL –
WB/WE
tCPN
tRSH
tCAS
VIH –
CAS
VIL –
tRAH
Row Address
tRAL
tASC
tCAH
SAM Start Address
A0 - A7: TAP
tWSR
tRWH
tTLS
tTLH
VIH –
VIL –
tTRP
tTP
VIH –
DT/OE V
IL –
tASD
tCSD
tOFF
tRSD
W1/IO1 - VOH –
W8/IO8 VOL –
tTSD
tSRS
SC
VIH –
VIL –
VIH –
VIL –
tSCP
Inhibit Rising Transient
tSDH
tSZS
Valid Data-in
SIO1 SIO8
OUT
tSCC
tSC
tSC
tSDS
IN
tSCP
tSCA
VOH –
VOL –
tSOH
Valid
Data-out
Note: SE = VIL
"H" or "L"
20/33
¡ Semiconductor
MSM518121A
,,,
,
Real Time Read Transfer Cycle
tRC
tRAS
tRP
tAR
VIH –
RAS
VIL –
tCSH
tCRP
tRCD
tCAS
tRAL
tRAD
tASR
VIH –
A0 - A8
VIL –
tCPN
tRSH
VIH –
CAS
VIL –
tASC
tRAH
Row Address
tCAH
SAM Start Address
A0 - A7: TAP
tWSR
WB/WE
tRWH
tATH
VIH –
VIL –
tCTH
tTLS
tTRP
tRTH
tTP
VIH –
DT/OE V
IL –
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
tSCC
tSC
SC
IN
tTSL
tSCP
tTSD
VIH –
VIL –
VIH –
VIL –
SIO1 SIO8
Open
tSCA
tSCA
tSOH
OUT
VOH –
VOL –
Valid
Data-out
tSOH
Valid
Data-out
Valid
Data-out
Valid
Data-out
Valid
Data-out
Previous Row Data
New Row Data
Note: SE = VIL
"H" or "L"
21/33
¡ Semiconductor
MSM518121A
,
,
,
Pseudo Write Transfer Cycle
tRC
tRAS
tRP
tAR
VIH –
RAS
VIL –
tCSH
tCRP
CAS
tRCD
tRSH
tCAS
VIH –
VIL –
tRAL
tRAD
tASR
VIH –
A0 - A8
VIL –
tCPN
tASC
tRAH
Row Address
tCAH
SAM Start Address
A0 - A7: TAP
WB/WE
tWSR
tRWH
tTLS
tTLH
VIH –
VIL –
VIH –
DT/OE V
IL –
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
Open
tSRD
tSRS
SC
tSCP
VIH –
VIL –
Inhibit Rising Transient
tESR
SIO1 SIO8
VIH –
VIL –
VOH –
OUT V –
OL
tSCP
tSC
tSWS
tREH
VIH –
SE
VIL –
IN
tSCC
tSC
tSDD
tSDZ
tSDS
tSEZ
Valid
Data-in
tSCA
Valid Data-out
Valid
Data-out
tSDH
Open
tSOH
Serial Output Data
Serial Input Data
"H" or "L"
22/33
¡ Semiconductor
MSM518121A
,
,
,
Write Transfer Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tRCD
tCRP
CAS
tRSH
tCAS
VIH –
VIL –
tRAL
tRAD
tASR
VIH –
A0 - A8
VIL –
tRAH
Row Address
tCPN
tASC
tCAH
SAM Start Address
A0 - A7: TAP
WB/WE
tWSR
tRWH
tTLS
tTLH
VIH –
VIL –
VIH –
DT/OE V
IL –
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
Open
tSRD
tSRS
SC
VIH –
VIL –
tSCP
tSC
SIO1 SIO8
tSWS
tREH
VIH –
VIL –
tSDS
IN
tSCP
Inhibit Rising Transient
tESR
SE
tSCC
tSC
VIH –
VIL –
tSDS
tSDH
Valid
Data-in
Valid Data-in
VOH –
OUT V –
OL
tSDH
Valid
Data-in
Open
Previous
Row Data
New Row Data
"H" or "L"
23/33
,
,,
,,
,
,
¡ Semiconductor
MSM518121A
Serial Read Cycle (SE = VIL)
RAS
VIH –
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tSCC
tSCC
tSC
SC
tSCC
tSC
tSCC
tSC
tSCC
tSC
tSC
VIH –
VIL –
tSCP
tSCA
tSCP
tSOH
SIO1 - VOH –
SIO8 VOL –
tSCP
tSCA
tSCA
tSOH
Valid
Data-out
tSCP
tSOH
Valid
Data-out
tSCA
tSCP
tSOH
Valid
Data-out
tSCA
tSCP
tSOH
Valid
Data-out
Valid
Data-out
Valid
Data-out
Note: SE = VIL
"H" or "L"
Serial Read Cycle (SE Controlled Outputs)
RAS
VIH –
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tSCC
tSCC
tSC
tSCC
tSC
tSCC
tSC
tSCC
tSC
tSC
VIH –
SC
VIL –
tSCP
SE
tSCP
tSEP
tSCP
tSCP
tSCP
tSCP
VIH –
VIL –
tSZE
IN
VIH –
VIL –
SIO1 SIO8
tSOH
OUT
VOH –
VOL –
tSEA
tSCA
Valid
Data-out
tSEZ
Valid
Data-out
tSCA
Open
tSCA
tSOH
Valid
Data-out
tSCA
tSOH
Valid
Data-out
Valid
Data-out
"H" or "L"
24/33
,
,
,,
,
,
¡ Semiconductor
MSM518121A
Serial Write Cycle (SE = VIL)
RAS
VIH –
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tSCC
tSCC
tSC
VIH –
SC
VIL –
tSC
tSDH
tSDS
tSCC
tSC
tSDH
tSCP
SIO1 - VIH –
SIO8 VIL –
tSCC
tSCC
tSC
tSDH
tSC
tSDH
tSDH
tSCP
tSCP
tSCP
tSCP
tSDS
tSDS
tSDS
tSDS
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
tSCP
Valid
Data-in
Note: SE = VIL
"H" or "L"
Serial Write Cycle (SE Controlled Inputs)
RAS
VIH –
VIL –
tTHS
tTHH
VIH –
DT/OE
VIL –
tSCC
tSC
VIH –
SC
VIL –
tSCP
tSWIH
tSEP
tSDS
IN
VIH –
VIL –
tSE
tSDH
Valid
Data-in
tSC
tSCP
tSWH
VIH –
VIL –
tSCC
tSC
tSCP
tSWS
SE
tSCC
tSWS
tSWH
tSE
tSDH
Valid
Data-in
tSCC
tSC
tSCP
tSWIS
tSDS
tSCC
tSC
tSCP
tSWIH
tSEP
tSWIS
tSDS
tSCP
tSWS
tSWH
tSE
tSDH
Valid
Data-in
SIO1 SIO8
VOH –
OUT V
OL –
Open
"H" or "L"
25/33
¡ Semiconductor
MSM518121A
Address Input : A0 - A8
The 17 address bits decode an 8-bit location out of the 131,072 locations in the MSM518121A
memory array. The address bits are multiplexed to 9 address input pins (A0 to A8) as standard
DRAM. Nine row address bits are latched at the falling edge of RAS. The following eight column
address bits are latched at the falling edge of CAS.
Row Address Strobe : RAS
RAS is a basic a RAM control input signal. The RAM port is in standby mode when the RAS level
is “high”. As the standard DRAM’s RAS signal function, RAS is the control input that latches the
row address bits are a random access cycle begins at the falling edge of RAS.
In addition to the conventional RAM signal functions, the level of the input signals, CAS, DT/
OE, WB/WE, and SE, at the falling edge of RAS, determines the MSM518121A operation modes.
Column Address Strobe : CAS
As the standard DRAM’s CAS signal function, CAS is the control input signal that latches the
column address input and acts as an RAM port output enable signal.
Data Transfer / Output Enable : DT / OE
DT/OE is also a control input signal having multiple functions. As the standard DRAM’s OE
signal function, DT/OE is used as an output enable control when DT/OE is “high” at the falling
edge of RAS.
In addition to the conventional OE signal function, a data transfer operation is started between
the RAM port and the SAM port when the DT/OE is “low” at the falling edge of RAS.
Write-per-Bit / Write Enable : WB / WE
WB/WE is a control input signal having multiple functions. As the standard DRAM’s WE signal
function, it is used to write data into the memory array on the RAM port when WB/WE is “high”
at the falling edge of RAS.
In addition to the conventional WE signal function, the WB/WE determines the write-per-bit
function when WB /WE is “low” at the falling edge of RAS, during RAM port operations. The
WB/WE also determines the direction of data transfer between the RAM and SAM. When WB/
WE is “high” at the falling edge of RAS, the data is transferred from RAM to SAM (Read transfer).
When WB/WE is “low” at the falling edge of RAS, the data is transferred from SAM to RAM
(Write transfer).
26/33
¡ Semiconductor
MSM518121A
Write Mask Data / Data Input and Mask Data : W1 / IO1 - W8 / IO8
W1/ IO1 to W8 / IO8 have the functions of both Input/Output and a control input signal. As the
standard DRAM’s I/O pins, input data on the W1/IO1 to W8/IO8 are written into the RAM port
during the write cycle. The input data is latched at the falling edge of either CAS or WB/WE,
whichever occurs later. The RAM data out buffers, which will output read data from the W1/IO1
to W8 /IO8 pins, become low impedance state after the specified access times from RAS, CAS,
DT / OE and column address are satisfied and the output data will remain vaild as long as CAS
and DT/OE are kept “low”. The outputs will return to the high-impedance state at the rising edge
of either CAS or DT/OE, whichever occurs earlier.
In addition to the conventional I/O functions, the W1/IO1 to W8/IO8 have the funnction to set
the mask data, which select mask input pins out of eight input pins, W1/ IO1 to W8/IO8, at the
falling edge of RAS. Data is written in to the DRAM on data lines where the write-mask data is
a logic “1”. Writing is inhibited on data lines where the write-mask data is a logic “0”. The writemask data is valid for only one cycle.
Serial Clock : SC
SC is a main serial cycle contorol input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In
a serial read, the output data becomes valid on the SIO pins after the maximum specified serial
access time tSCA from the rising edge of SC.
The serial lock SC also increments the 8 bits serial pointer which is used to select the SAM address.
The pointer address is incremented in a wrap-around mode to select sequential locations after
the setting location which is determined by the column address in the read transfer cycle. When
the pointer reaches the most significant address location (Decimal 255), the next SC clock will
place it at the least significant address location (Decimal 0).
The serial clock SC must be held data constant VIH or VIL level during read/pseudo write/write
transfer operations and should not be clocked while the SAM port is in the standby mode to
prevent the SAM pointer from being incremented.
Serial Enable : SE
The SE is a serial access enable control and serial read/write control input signal. In a serial read
cycle, SE is used as an output control. In a serial write cycle, SE is used as a write enable control.
When SE is “high”, serial access is disable, however, the serial address pointer location is still
incremented when SC is clocked even when SE is “high”.
Serial Input / Output : SIO1 - SIO8
Serial input/output mode is determined by the most recent read, write or pseudo write transfer
cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write
or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input
mode.
27/33
¡ Semiconductor
MSM518121A
Fast Page Mode Cycle
Fast page mode allows data to be transferred into or out multiple column locations of the same
row by performing multiple CAS cycle during a single active RAS cycle.
During a fast page cycle, the RAS signal may be maintained active for a period up to 100µ
seconds.
For the initial fast page mode access, the output data is valid after the specified access times from
RAS, CAS, column address and DT/OE.
For all subsequent fast page mode read operations, the output data is valid after the specified
access times from CAS, column address and DT/OE. When the write-per-bit function is enabled,
the mask data latched at the falling edge of RAS is maintained throughout the fast page mode
write or Read-Modify-Write cycle.
RAS-Only Refresh
The data is the DRAM requires periodic refreshing to prevent data loss. Refreshing is accomplished
by performing a memory cycle at each of the 512 rows in the DRAM array within the specified
8 ms refresh period.
Although any normal memory cycle will perform the refresh operation, this function is most
easily accomplished with “RAS-Only” cycle.
CAS before RAS Refresh
The MSM518121A also offers an internal-refresh function. When CAS is held “low” for a
specified period (tCSR) before RAS goes “low”, an internal refresh address counter and on-chip
refresh control clock generators are enabled and an internal refresh operation takes place.
When the refresh operation is completed, the internal refresh address counter is automatically
incremented in preparation for the next CAS-before-RAS cycle. For successive CAS-before-RAS
refresh cycle, CAS can remain “low” while cycling RAS.
Hidden Refresh
A hidden refresh is a CAS-before-RAS refresh performed by holding CAS “low” from a previous
read cycle. This allows for the output data from the previous memory cycle to remain valid while
performing a refresh.
The internal refresh address counter provides the address and the refresh is accomplished by
cycling RAS after the specified RAS-precharge period.
Write-per-Bit Function
The Write-Per-Bit selectively controls the internal write-enable circuits of the RAM port. WritePer-Bit is enabled when WB/WE held “low” at the falling edge of RAS in a random write
operation. Also, at the falling edge of RAS, the mask data on the Wi/IOi pins are latched into a
write mask register. The write mask data must be presented at the Wi/IOi pins at every falling
edge of RAS. A “0” on any of the Wi/IOi pins will disable the corresponding write circuits and
new data will not be written into the RAM. A “1” on any of the Wi/IOi pins will enable the
corresponding write circuits and new data will be written into the RAM.
28/33
¡ Semiconductor
MSM518121A
DATA TRANSFER OPERATION
The MSM518121A features an internal data transfer capability between RAM and the SAM.
During a transfer cycle, 256 words by 8 bits of data can be loaded from RAM to SAM (Read
Transfer) or from SAM to RAM (Write Trasfer).
The MSM518121A supports three types of transfer operations: Read transfer, Write Transfer and
pseudo write transfer. Data transfer operations between RAM and SAM are invoked by holding
the DT/OE signal “low” at the falling edge of RAS, the type of data transfer operation is
determined by the state of CAS, WB/WE and SE latched at the falling edge of RAS.
During data transfer operations, the SAM port is switched from input to output mode (Read
Transfer) or output to input mode (Write Transfer/Pseudo Write Trasfer).
During a data transfer cycle, the row A0-A8 select one of the 512 rows of the memory array to or
from which data will be transferred and the column address A0-A8 select one of the tap locations
in the serial register. The selected tap location is the start position in the SAM port from which
the first serial data will be read out during the subsequent serial read cycle or the start position
in the SAM port into which the first serial data will be written during the subsequent serial write
cycle.
Read Transfer Cycle
A read transfer consists of loading a selected row of data from the RAM array into the SAM
register. A read transfer is invoked by holding CAS “high”, DT/OE “low” and WB/WE “high”
at the falling edge of RAS. The row address selected at the falling edge of RAS determines the
RAM row to be transferred into the SAM.
The transfer cycle is completed at the rising edge of DT/OE. When the transfer is completed, the
SAM port is set into the output mode.
In a read/real time read transfer of a new row of data is completed at the rising edge of DT/OE
and this data becomes valid on the SIO lines after the specified access time tSCA from the rising
edge of the subsequent serial clock (SC) cycle. The start address of the serial pointer of the SAM
is determined by the column address selected at the falling edge of CAS.
In a read transfer cycle preceded by a write transfer cycle, the SC clock must be held at a constant
VIL or VIH, after the SC high time has been satisfied. A rising edge of the SC clock must not occur
until after the specified delay tTSD from the rising edge of DT/OE.
In a real time read transfer cycle (which is perceded by another read transfer cycle), the previous
row data appears on the SIO lines until the DT/OE signal goes “high” and the serial access time
tSCA for the following serial clock is satisfied.
This feature allows for the first bit of the new row of data to appear on the serial output as soon
as the last bit of the previous row has been strobed without any timing loss. To make this
continuous data flow possible, the rising edge of DT/OE must be synchronized with RAS, CAS
and the subsequent rising edge of SC (tRTH, tCTH, and tTSL/tTSD must be satisfied). The timing
restriction tTSL/tTSD are 5 ns min./10 ns min..
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MSM518121A
Write Transfer Cycle
A write transfer cycle transfers the contents of the SAM register into a selected row of the RAM
array. If the SAM data to be transferred must first be loaded through the SAM port, a pseudo
write transfer operation must precede the write transfer cycles.
Data transferred to SAM by read transfer cycle can be written to other address of RAM by write
transfer cycle.
A write transfer is invoked by holding CAS “low”, WB/WE “low” and SE “low” at the falling
edge of RAS.
The row address selected at the falling edge of RAS determines the RAM row address into which
the data will be transferred. The column address selected at the falling edge of CAS determines
the start address of the serial pointer of the SAM.
After the writetransfer is completed, the SIO lines are set in the input mode so that serial data
synchronized with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the RAS cycle of the preceding write transfer is completed.
Consequently, the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising
edge of the SC clock is only allowed after the specified delay tSRD from the rising edge of RAS,
at which time a new row of data can be written in the serial register.
Pseudo Write Transfer Cycle
A pseudo write transfer cycle must be performed before loading data into the serial register after
a read transfer operation has been excuted. The only purpose of a pseudo write transfer is to
change the SAM port mode from output mode to input mode (A data transfer from SAM to RAM
does not occur).
After the serial register is loaded with new data, a write transfer cycle must be performed to
transfer the data from SAM to RAM. A pseudo write transfer is invoked by holding CAS “high”,
DT/OE “low”, WB/WE “low” and SE “high” at the falling edge of RAS. The timing conditions
are the same as the one for the write transfer cycle except for the state of SE at the falling edge of
RAS.
Transfer Operation Without CAS
During all transfer cycles, the CAS input clock must be cycled, so that the column address are
latched at the falling edge of CAS, to set the SAM tap location. If CAS was maintained at a
constant “high” level during a transfer cycle, the SAM pointer location would be undifined.
Therefore a transfer cycle with CAS held “high” is not allowed.
Normal Read Transfer Cycle After Normal Read Transfer Cycle
Another read transfer may be performed following the read transfer provided that a minimum
delay of 30 ns from the rising edge of the first clock SC is satisfied.
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MSM518121A
POWER-UP
Power must be applied to the RAS and DT/OE input signals to pull them “high” before or at the
same time as the VCC supply is turned on. After power-up, a pause of 200µ seconds (minimum)
is required with RAS and DT/OE held “high”.
After the pause, a minimum of 8 RAS and 8 SC dummy cycles must be performed to stabilize the
internal circuitry, before valid read, write or transfer operations can begin. During the initialization
period, the DT/OE signal must be held “high”. If the internal refresh counter is used, a minimum
8 CAS-before-RAS initialization cycles are required instead of 8 RAS cycle.
Initial State After Power-up
When power is achieved with RAS, CAS, DT/OE and WB/WE held “high” the internal state of
the MSM518121A is automatically set as follows.
SAM port
Write mask register
TAP pointer
——> Input mode
——> Write mode
——> Invalid
However, the initial state can not be guaranteed for various power-up conditions and input
signal levels. Therefore, it is recommended that the initial state be set after the initialization of the
device is performed (200µ seconds pause followed by a minimum of 8 RAS cycles and 8 SC cycles)
and before valid operations begin.
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MSM518121A
PACKAGE DIMENSIONS
(Unit : mm)
ZIP40-P-475-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
3.46 TYP.
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MSM518121A
(Unit : mm)
SOJ40-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.70 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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