ON NCP6915AFCCLT1G 6 channels pmic Datasheet

NCP6915
6 Channels PMIC with One
DCDC Converter and 5
LDOs
The NCP6915 integrated circuit is part of the ON Semiconductor
mini power management IC family. It is optimized to supply battery
powered portable application sub−systems such as camera function,
microprocessors ... etc. This device integrates one high efficiency
600 mA Step−down DCDC converter with DVS (Dynamic Voltage
Scaling) and 5 low dropout (LDO) voltage regulators in WLCSP16
package.
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MARKING
DIAGRAM*
Features
6915A
ALYWW
G
WLCSP16
CASE 567GF
• One DCDC Converter:
♦
Peak Efficiency 96%
Programmable Output Voltage from 0.8 V to 2.3 V by 50 mV Steps
♦ 600 mA Output Current Capability
Five Low Noise − Low Dropout Regulators
♦ Programmable Output Voltage from 1.7 V to 3.3 V for LDOs
1,2,3
♦ Programmable Output Voltage from 1.2 V to 2.85 V for LDO 4 & 5
♦ 200 mA Output Current Capability: LDO’s 1,2,3 & 4
♦ 300 mA Output Current Capability: LDO 5
♦ 45 mVrms Low Output Noise
Control
♦ 400 kHz / 3.4 MHz I2C Control Interface
♦ Hardware Enable Pin
♦ Customizable Power up Sequencer
Extended Input Voltage Range 2.5 V to 5.5 V
♦ Support of Newest Battery Technologies
Optimized Power Efficiency
♦ 82 mA Very Low Quiescent Current at no Load
♦ Dynamic Voltage Scaling on DCDC Converter
♦ Regulators can be Supplied from DCDC Converter Output
Small footprint
♦ Package WLCSP16 1.56 x 1.56 mm2
♦ DCDC Converter runs at 3.0 MHz using a 1 mH Inductor and
10 mF Capacitor or 2.2 mH Inductor and 4.7 mF Capacitor
This is a Pb−Free Device
A
L
Y
WW
G
♦
•
•
•
•
•
•
August, 2014 − Rev. 3
1
2
3
4
A
VOUT2
VOUT1
FB
PVIN
B
VIN1
SCL
HWEN
SW
C
AGND
VBG
SDA
PGND
D
VOUT3
VOUT4
VIN2
VOUT5
(Top View)
See detailed ordering and shipping information on page 23 of
this data sheet.
Cellular Phones
Digital Cameras
Personal Digital Assistant and Portable Media Player
GPS
© Semiconductor Components Industries, LLC, 2014
*Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
ORDERING INFORMATION
Typical Applications
•
•
•
•
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
Publication Order Number:
NCP6915/D
NCP6915
NCP6915
2 .2uF
PVIN
VBG
100 nF
AGND
DCDC1
600 mA
Core
System Supply
DCDC1 Out
SW
1 uH
FB
10 uF
PGND
1uF
System Supply
System Supply
Or
DCDC Out
VIN1
1.0 uF
LDO1
200 mA
VOUT1
LDO2
200 mA
VOUT2
LDO3
200 mA
VOUT3
Power Up/
Down
Sequencer
LDO4
200 mA
VOUT4
VOUT5
I2C
LDO5
300 mA
VIN2
1.0 uF
1uF
Thermal
Protection
Enabling
HWEN
1.0 uF
1.0 uF
1.0 uF
SDA
Processor I2C
SCL
Figure 1. Functional Block Diagram
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NCP6915
Table 1. PIN OUT DESCRIPTION
Pin
Name
Type
Description
VIN1
Power Input
Analog Supply. This pin is the device analog, digital and LDO 1, 2 & 3 supply. A 1.0 mF ceramic
capacitor or larger must bypass this input to ground. This capacitor should be placed as close a
possible to this pin.
C2
VBG
Analog Input
Reference Voltage. A 0.1 mF ceramic capacitor must bypass this pin to the ground
C1
AGND
Analog
Ground
POWER
B1
Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
CONTROL AND SERIAL INTERFACE
B3
HWEN
Digital Input
Hardware Enable. Active high will enable the part; there is internal pull down resistor on this pin.
B2
SCL
Digital Input
I2C interface Clock
C3
SDA
Digital
Input/Output
I2C interface Data
DCDC Power Supply. This pin must be decoupled to ground by a 2.2 mF ceramic capacitor. This
capacitor should be placed as close a possible to this pin.
DCDC CONVERTER
A4
PVIN
Power Input
B4
SW
Power Output
DCDC Switch Power pin connects power transistors to one end of the inductor. Typical
application uses 1.0 mH inductor; refer to application section for more information.
A3
FB
Analog Input
DCDC Feedback Voltage. Must be connected to the output capacitor. This is the input to the error
amplifier.
C4
PGND
Power
Ground
DCDC Power Ground. This pin is the power ground and carries the high switching current. High
quality ground must be provided to prevent noise spikes. To avoid high−density current flow in a
limited PCB track, a local ground plane is recommended.
LDO REGULATORS
B1
VIN1
Power Input
LDO 1,2 & 3 Power and Core supply (see Power table)
D3
VIN2
Power Input
LDO 4&5 Power Supply This pin requires a 1 mF decoupling capacitor.
A2
VOUT1
Power Output
LDO 1 Output Power. This pin requires a 1 mF decoupling capacitor.
A1
VOUT2
Power Output
LDO 2 Output Power. This pin requires a 1 mF decoupling capacitor.
D1
VOUT3
Power Output
LDO 3 Output Power. This pin requires a 1 mF decoupling capacitor.
D2
VOUT4
Power Output
LDO 4 Output Power. This pin requires a 1 mF decoupling capacitor.
D4
VOUT5
Power Output
LDO 5 Output Power. This pin requires a 1 mF decoupling capacitor.
Table 2. MAXIMUM RATINGS
Symbol
Rating
Analog and power pins: AVIN, PVIN, SW, VIN1, VIN2, VOUT1, VOUT2, VOUT3,
VOUT4, VOUT5, FB, VBG Pins
Value
Unit
VA
−0.3 to +6.0
V
VDG
IDG
−0.3 to VA +0.3 ≤ 6.0
10
V
mA
Storage Temperature Range
TSTG
−65 to + 150
°C
Maximum Junction Temperature
TJMAX
−40 to +150
°C
MSL
Level 1
Digital pins: SCL, SDA, HWEN Pin:
Input Voltage
Input Current
Moisture Sensitivity (Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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NCP6915
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VIN1
PVIN
Core Power Supply, DCDC power supply and LDOs 1,
2&3
Conditions
VIN2
Min
Typ
2.5
Max
Unit
5.5
V
LDOs 4 & 5 Input Voltage range
1.7
5.5
V
TA
Ambient Temperature Range
−40
25
+85
°C
TJ
Junction Temperature Range (Note 3)
−40
25
+125
°C
RqJA
Thermal Resistance Junction to Case
−
80
−
°C/W
TA = 25°C
−
1250
−
mW
TA = 85°C
−
500
−
mW
2.2
mH
PD
L
Power Dissipation Rating (Note 5)
Inductor for DCDC converter (Note 2)
1
10
mF
1
mF
Output Capacitors for VBG
100
nF
Cpvin
Input Capacitor for DCDC Converter (Note 2)
2.2
mF
Cvin1
Input Capacitor for Vin1 (Note 2)
1
mF
Cvin2
Input Capacitor for Vin2 (Note 2)
1
mF
Co
Output Capacitor for DCDC Converter (Note 2)
Output Capacitors for LDO (Note 2)
CBG
0.65
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Refer to the Application Information section of this data sheet for more details.
3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. The RqCA is dependent of the PCB heat dissipation. Board used to drive this data was a 2” x 2” NCPXXXEVB board. It is a multilayer board
with 1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
5. The maximum power dissipation (PD) is dependent by input voltage, maximum output current and external components selected.
R qCA +
125 * T A
PD
* R qJC with ǒR qJA + R qJC ) R qCAǓ
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified.
PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical
values are referenced to TJ = + 25°C and default configuration (Note 7).
Symbol
Parameter
Conditions
Min
Typ
Max
−
32
−
Unit
SUPPLY CURRENT: PINS VIN1, VIN2, PVIN
DCDC on – no load – no switching
LDOs off
TA = up to +85°C
IQ
ISLEEP
Operating quiescent current
Product sleep mode current
mA
DCDC on – no load – no switching
LDOs on – no load
TA = up to +85°C
−
82
−
DCDC Off
LDOs on – no load
TA = up to +85°C
−
65
−
HWEN on
All DCDC and LDOs off
VIN = 2.5 V to 5.5 V
TA = up to +85°C
−
7
−
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels
to the VDD voltage to which the pull−up resistors RP are connected.
7. Refer to the Application Information section of this data sheet for more details.
8. Guaranteed by design and characterized.
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NCP6915
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified.
PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical
values are referenced to TJ = + 25°C and default configuration (Note 7).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−
0.3
−
mA
2.5
−
5.5
V
SUPPLY CURRENT: PINS VIN1, VIN2, PVIN
IOFF
Product off current
HWEN off
I2C interface disabled
VIN = 2.5 V to 5.5 V
TA = up to +85°C
DCDC CONVERTER
PVIN
Input Voltage Range
IOUTMAX
Maximum Output Current
(Note 8)
0.6
−
−
A
DVOUT
Output Voltage DC Error
Io = 300 mA, PWM mode
−1.5
0
1.5
%
DCOUT
DCDC Output voltage
Programmable 50 mV steps
(Note 8)
0.8
2.3
V
FSW
Switching Frequency
IPK
Peak Inductor Current
Open loop
2.5 V ≤ PVIN ≤ 5.5 V
Load Regulation
Line Regulation
D
2.7
3
3.3
MHz
1.0
1.3
1.6
A
IOUT from 300 mA to IOUTMAX
−
−0.5
−
%/A
IOUT = 300 mA
2.5 V ≤ VIN ≤ 5.5 V
−
0
−
%/V
−
100
−
%
−
128
−
8
−
W
LDO1, LDO2, LDO3 input voltage
Range
2.5
−
5.5
V
Maximum Output Current
200
−
−
mA
−
500
mA
130
mA
Maximum Duty Cycle
I2C
tSTART
RDISDCDC
Soft−Start Time
Time from
command ACK to
90% of Output Voltage, Vout =
1.2 V.
DCDC Active Output Discharge
ms
LDO1, LDO2, LDO3
VIN1
IOUTMAX1,2, 3
ISC1,2, 3
Short Circuit Protection
Foldback Current
Vout1, 2, 3
tSTART1
DVOUT1,2, 3
Output voltage
Programmable, see table. (Note 8)
1.7
Soft−Start Time
Time from I2C command ACK to 90%
of Output Voltage.
−
128
IOUT1,2, 3 = 150 mA
−2
VNOM
+2
%
Load Regulation
IOUT1,2, 3 = 0 mA to 200 mA
−
0.4
−
%
Line Regulation
VIN1 = (Vout + Drop) to 5.5 V
VOUT1,2 = 2.8 V, VOUT3 = 1.8 V
IOUT1,2,3 = 200 mA
−
0.3
−
Output Voltage Accuracy DC
IOUT1,2,3 = 200 mA, VOUT = 3.3 V −
2%
VDROP
Dropout Voltage
IOUT1,23 = 200 mA, VOUT = 2.8 V −
2%
3.3
V
ms
%
160
mV
−
185
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels
to the VDD voltage to which the pull−up resistors RP are connected.
7. Refer to the Application Information section of this data sheet for more details.
8. Guaranteed by design and characterized.
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NCP6915
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified.
PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical
values are referenced to TJ = + 25°C and default configuration (Note 7).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
F = 1 kHz, 100 mV peak to peak
VOUT1,2 = 2.8 V, VOUT3 = 1.8 V
IOUT1,2,3 = 5 mA
−
−70
−
F = 10 kHz, 100 mV peak to peak
VOUT1,2 = 2.8 V, VOUT3 = 1.8 V
IOUT1,2,3 = 5 mA
−
−60
−
10 Hz ³ 100 kHz, 5 mA
VOUT1,2,3 = 2.8 V
−
45
−
mV
−
25
−
W
LDO4 and LDO5 Input Voltage
1.7
−
5.5
V
IOUTMAX4
Maximum Output Current
200
−
−
mA
IOUTMAX5
Maximum Output Current
300
−
−
mA
LDO1, LDO2, LDO3
PSRR
Ripple Rejection
Noise
RDISLDO1,2, 3
LDO Active Output Discharge
dB
LDO4 and LDO5
VIN2
ISC4
Short Circuit Protection
−
500
−
mA
ISC5
Short Circuit Protection
−
600
−
mA
ISC4
Foldback Protection
130
−
mA
ISC5
Foldback Protection
190
−
mA
2.85
V
Vout4,5
LDO 4&5 Output voltage
tSTART2
Soft−Start Time
DVOUT4
DVOUT5
VDROP
Programmable, see table. (Note 8)
1.2
−
Time from I2C command ACK to 90%
of Output Voltage.
−
128
Output Voltage Accuracy
IOUT4 = 200 mA
−2
VNOM
+2
%
Output Voltage Accuracy
IOUT5 = 300 mA
−2
VNOM
+2
%
Load Regulation
IOUT4 = 0 mA to 200 mA
IOUT5 = 0 mA to 300 mA
−
0.4
−
%
Line Regulation
VIN2 = (Vout + Drop) to 5.5 V
VOUT4 = 2.8 V, VOUT5 = 1.8 V
IOUT4 = 200 mA, IOUT5 = 300 mA
−
0.3
−
%
IOUT4,5 = 200 mA
VOUT4,5 = 2.8 V − 2%
−
165
Dropout Voltage
mV
IOUT5 = 300 mA
VOUT5 = 1.8 V − 2%
PSRR
Ripple Rejection
Noise
RDISLDO4,5
ms
290
F = 1 kHz, 100 mV peak to peak
IOUT4= 5 mA, IOUT5 = 5 mA
−
−70
−
F = 10 kHz, 100 mV peak to peak
IOUT4,5 = 5 mA
−
−60
−
10 Hz ³ 100 kHz, 5 mA
VOUT4,5 = 2.8 V
−
45
−
mV
−
25
−
W
LDO 4&5 Active Output Discharge
dB
HWEN
VIH
High level input Voltage Threshold
1.1
−
−
V
VIL
Low level Voltage Threshold
−
−
0.4
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels
to the VDD voltage to which the pull−up resistors RP are connected.
7. Refer to the Application Information section of this data sheet for more details.
8. Guaranteed by design and characterized.
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NCP6915
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified.
PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical
values are referenced to TJ = + 25°C and default configuration (Note 7).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.1
1
mA
1.7
−
5.0
V
HWEN
IEN
I2C
VI2C
Voltage at SCL and SDA line
VI2CIL
SCL, SDA low input voltage
SCL, SDA pin (Note 6)
−
−
0.5
V
VI2CIH
SCL, SDA high input voltage
SCL, SDA pin (Note 6)
0.8 x
VI2CC
−
−
V
VI2COL
SCL, SDA low output voltage
ISINK = 3 mA (Note 8)
−
−
0.4
V
FSCL
I2C clock frequency
(Note 8)
−
−
3.4
MHz
VUVLO
Under Voltage Lockout
VIN falling
−
−
2.3
V
VUVLOH
Under Voltage Lockout Hysteresis
VIN rising
60
−
200
mV
TSD
Thermal Shut Down Protection
−
150
−
°C
TWARNING
Warning Rising Edge
−
135
−
°C
TSDR
Thermal Shut Down Rearming
−
110
−
°C
TOTAL DEVICE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels
to the VDD voltage to which the pull−up resistors RP are connected.
7. Refer to the Application Information section of this data sheet for more details.
8. Guaranteed by design and characterized.
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NCP6915
DETAILED DESCRIPTION
capabilities of the device can be exceeded. A thermal
protection circuit is therefore implemented to prevent the
part from damage. This protection circuit is only activated
when the core is in active mode (at least one output channel
is enabled). During thermal shutdown, all outputs of
NCP6915 are off.
When NCP6915 returns from thermal shutdown, it can
re−start in two different configurations depending on
REARM[7:6] bits ($09 register). If REARM[7:6] = 00 then
NCP6915 re−starts with default register values, otherwise it
re−starts with register values set prior to thermal shutdown.
In addition, a thermal warning is implemented which can
inform the processor through an interrupt that NCP6915 is
close to its thermal shutdown so that preventive action can
be taken by software.
The NCP6915 is optimized to supply the different sub
systems of battery powered portable applications. The IC
can be supplied directly from the latest technology single
cell batteries such as Lithium−Polymer as well as from triple
alkaline cells. Alternatively, the IC can be supplied from a
pre−regulated supply rail in case of multi−cell or mains
powered applications.
The output voltage range, current capabilities and
performance of the switched mode DCDC converter are
well suited to supply the different peripherals in the system
as well as to supply processor cores. To reduce overall power
consumption of the application, Dynamic Voltage Scaling
(DVS) is supported on the DCDC converter. For PWM
operation, the converter runs on a local 3 MHz clock. A low
power PFM mode is provided that ensures that even at low
loads high efficiency can be obtained. All the switching
components are integrated including the compensation
networks and synchronous rectifier. Small sized 1 uH
inductor and 10 uF bypass capacitor are required for typical
applications.
The general purpose low dropout regulators can be used
to supply the lower power rails in the application. To
improve on overall application standby current, the bias
current of these regulators are made very low. The regulators
have two separated input supply pin to be able to connect
them independently to either the system supply voltage or to
the output of the DCDC converter in the application. The
regulators are bypassed with a small size 1.0 uF capacitor.
The IC is controlled through the I2C interface that allows
to program amongst others the output voltages of the
different supply rails as well as to configure its behavior. In
addition to this bus, a digital hardware enable control pin
(HWEN) is provided.
Active Output Discharge
By default, to prevent any disturbances on power−up
sequence, output discharge is activated as soon as the input
voltage is valid (upper than UVLO+ hyst).
After power up sequence and during ON state, output
discharge can be independently enabled / disabled by
appropriate settings in the DIS register (refer to the register
definition section).
If a power down sequence, UVLO or thermal shutdown
events occur, the output discharge paths are activated until
the next PUS and ON state.
When the IC is turned off when VIN1 drops down below
UVLO threshold, no shut down sequence is expected, all
supplies are disabled and outputs turn to high impedance.
Enabling
The HWEN pin controls the device start up. If HWEN is
raised, this starts the power up sequencer (PUS). If HWEN
is made low, device enters in shutdown mode and all
regulators will be turned off with inverted PUS of power up.
A built−in pull−down resistor disables the device if this
pin is left unconnected.
When HWEN is high, the different power rails can be
independently enabled / disabled by writing the appropriate
bit in the ENABLE register.
Under Voltage Lockout
The core does not operate for voltages below the under
voltage lockout (UVLO) threshold and all internal circuitry,
both analog and digital, is held in reset.
NCP6915 functionality is guaranteed down to VUVLO
when the battery is falling. A hysteresis is implemented to
avoid erratic on / off behavior of the IC. Due to its 200 mV
hysteresis, when the battery is rising, re−start is guaranteed
at 2.5 V.
Power Up Sequence and HWEN
When enabling part with HWEN pin, the part will be set
with the default configuration factory programmed in the
registers, if no I2C programming has been done as described
in the below table.
Thermal Shutdown
Given the output power capabilities of the on chip step
down converters and low drop out regulators the thermal
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NCP6915
Table 5. DEFAULT POWER UP SEQUENCER
Delay (in ms) from Tstart
Sequence
Default Assignment
Default Vprog
Default Mode and
ON/OFF
128
To: 000
DCDC
1.20 V
Auto PFM/PWM OFF
256
T1: 001
LDO1
2.80 V
OFF
512
T2: 011
LDO2
2.80 V
OFF
640
T3: 100
LDO3
1.80 V
OFF
768
T4: 101
LDO4
2.80 V
OFF
896
T5: 110
LDO5
1.80 V
OFF
NOTE:
Additional power sequence are available. Please contact your ON Semiconductor representative for further information.
VIN1, VIN2
UVLO
POR
HWEN
VOUT DCDC
O
F
F
600 us
typ
(DCDC_T[2:0] + 1) x
128 ms *
M
O
DVS ramp
Time
VOUT LDOx D
E
(LDOx_T[2:0] + 1) x
128 ms *
Bias
Time
128 us
Soft start 90%
I@C
Figure 3. IPUS
Figure 2. IPUS
In order to power up the circuit, the input voltage VIN1
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up including:
Internal references
Core circuitry “Wake Up Time”
DCDC “Bias Time”
These delays are internals and cannot be bypassed.
The initial power up sequence (IPUS) is described in
Figure 2.
Remark 1: T2 – T1 = 2x 128 ms in the default configuration.
Can be reprogrammed at 128 ms by I2C.
Remark 2: LDOs must be turned on sequentially to avoid
inrush current on Vin source. So it’s strongly recommended
to turn them one by one, even if the default PUS sequence
is changed by I2C.
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NCP6915
As the default configuration factory is programmed with
disable state for the DCDC and LDOs, an I2C access must
be done at the end of the bias time to enable the supplies.
In addition a user programmable delay will also take place
between end of Core circuitry turn on (Bias time) and Start
up time: The PowerSupplies_T[2..0] bits of TIME register
will set this user programmable delay with a 128 ms
resolution (note: please contact your ON Semiconductor
representative for additional resolution options). The output
discharge of the DCDC and LDOs are done during this time
slot. NOTE: During the Bias time, the I2C interface is not
active during the first 50 ms. Any I2C request to the IC during
this time period will result in a NACK reply.
However, I2C registers can be read and written while
HWEN pin is still low (except blanking time of 50 ms
typical). By programming the appropriate registers (see
registers description section), the power up sequence default
can be modified and set upon requirements (please contact
your ON representative for additional PUS options)
VIN1, VIN2
UVLO
POR
HWEN
VOUT DCDC
Bias time
32ms
VOUT LDOx
Soft start 90%
128 us
I@C
LDOx,
DCDC
OFF/
ON
Figure 5. ON Mode PUS (OPUS)
Shutdown by HWEN
VIN1, VIN2
When HWEN is tied low, all supplies are disabled with
reverted turn on sequence detailed in default Power Up
Sequencer table. If different turn off sequence is required, a
different programming can be done by I2C.
UVLO
POR
HWEN
(DCDC _T[2:0] + 1) x
128 ms*
S
L
E
E
P
VOUT DCDC
O
F
F
VOUT LDOx
M
O
D
E
M
O
D
E
70
us
typ
600ms Bias
min Time
I@C
DVS ramp
Time
Ì
Ì
DCDC Converter
The converter can operate in two modes: PWM mode and
PFM mode. In PWM mode the converter operates at a fixed
frequency and adapts its duty cycle to regulate to the desired
output voltage. The advantage of this mode is that the EMI
noise is predictable. However, at lower loadings the
efficiency is degraded. In PFM mode some switching pulses
are skipped to control the output voltage. This allows
maintaining high efficiency even at low loadings. In
addition, no high frequency clock is required which
provides additional current savings. The switchover point
between both modes is chosen depending on the supply
conditions such that highest efficiency is obtained over the
entire load range.
The switch over between PWM/PFM modes can occur
automatically but the switcher can be set in auto switching
mode PFM / PWM by I2C programming.
A soft start is provided to limit inrush currents when
enabling the converters. The soft start consists of ramping
gradually the reference to the switcher.
Additional current limitation is provided by a peak current
limiter that monitors and limits the current through the
inductor.
DCDC converter output voltage can be set by I2C
MODEDCDC bit is used to program switcher mode
control
DVS ramp
Time
(LDOx_T[2:0] + 1) x
128 ms*
128 us
Soft start 90%
Figure 4. Sleep Mode PUS (SMPUS)
A third turn on sequence is also available by I2C. Indeed
each power supply can be turn off/on through I2C register.
In this case no biasing time is required except for DCDC bias
time (32 ms typical).
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NCP6915
DCDC Step Down Converter and LDOs End of Turn on
Sequence
Table 6. MODEDCDC BIT DESCRIPTION
MODEDCDC
DCDC Mode Control
0
Mode is auto switching PFM / PWM
(default)
1
Mode is PWM only
To indicate the end of the power up sequence, a power
good sense bit is available at the $0A address. (SEN_PG).
Sense bit is set to 0 during power up sequence and 16 x
digital clock (128 ms by default). The Power good sense bit
is released to 1 after this sequence and trig ACK_PG
interrupt. The interrupt is reset by a read or HWEN.
Dynamic Voltage Scaling (DVS)
Step down converters support dynamic voltage scaling
(DVS). This means the output voltage can be reprogrammed
based upon I2C commands to provide the different voltages
required by the processor. The change between set points is
managed in a smooth manner without disturbing the
operation of the processor.
When programming a higher voltage, the reference of the
switcher and therefore the output is raised in 50 mV/ 2.67 ms
(default) steps such that the dV/dt is controlled. When
programming a lower voltage the output voltage will
decrease based on the output capacitor value and the load.
The DVS system makes sure that the voltage ramp down will
not exceed the steps settings.
V2
Internal
Reference
Output
Voltage
Figure 7. Power good behavior
DV
Interrupt
Dt
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual edge monitoring).
The interrupt sources include:
Figure 6. Dynamic Voltage Scaling Effect Timing
Programmability
DCDC converter has two different output voltages
programmed by default in the DCDC_V1 and V2 bank. The
DCDC output voltage can be changed from V1 to V2 with
the DCDC_V2/V1 bit in $08 register.
Table 9. INTERRUPT SOURCES
Register
UVLO
PUS
Table 7. DCDC_V2/1 BIT DESCRIPTION
DCDC_V2/1
WNRG
TSD
Bit Description
0
Output voltage is set to DCDC_V2
1
Output voltage is set to DCDC_V1(Default)
1
10.67 ms per step
Thermal shutdown
The I2C registers are reset when the part is in Off Mode:
• Vin<UVLO or
• I2C and HWEN not present or
• Restart from TSD event (REARM_ TSD[7:6]=00,
register $09)
Bit Description
2.67 ms per step (default)
Thermal warning
Force Register Reset
Table 8. DVS BIT DESCRIPTION
0
End of power up sequence
Individual bits generating interrupts will be set to 1 in the
INT_ACK register (I2C read only register), indicating the
interrupt source. INT_ACK register is reset by an I2C read.
INT_SEN registers (read only registers) are real time
indicators of interrupt sources.
The two DVS bits in register TIME determine ramp up
time per each voltage step.
DVS [0]
$0B
Under voltage threshold
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NCP6915
TYPICAL OPERATING CHARACTERISTICS
100
25°C
90
90
80
80
EFF (%)
EFF (%)
100
70
70
60
60
50
50
40
0.1
1.0
10
IOUT (mA)
100
25°C
40
0.1
1000
Figure 8. Efficiency versus Iout (Auto Mode)
L= 1 mH (TOKO DFE2016), Vin = 5 V, Vout 1.2 V,
Cin 2.2 mF, Cout 10 mF
1.0
10
IOUT (mA)
100
1000
Figure 9. Efficiency versus Iout (Auto Mode)
L= 1 mH (TOKO DFE2016), Vin = 3.6 V, Vout
1.2 V, Cin 2.2 mF, Cout 10 mF
100
100
90
90
80
80
EFF (%)
EFF (%)
25°C
70
70
60
60
50
50
40
0.1
1.0
10
IOUT (mA)
100
40
0.1
1000
Figure 10. Efficiency versus Iout (Auto Mode)
L= 1 mH (TOKO DFE2016), Vin = 2.9 V, Vout
1.2 V, Cin 2.2 mF, Cout 10 mF
1.0
10
IOUT (mA)
100
1000
Figure 11. Efficiency versus Iout (auto mode)
L= 1 mH (TOKO DFE2016), , Vout 2.3 V, Cin
2.2 mF, Cout 10 mF
100
95
95
IQ (mA)
100
IQ (mA)
VIN = 5.5 V
VIN = 3.2 V
VIN = 5 V
VIN = 2.9 V
VIN = 4.2 V
VIN = 2.5 V
VIN = 3.6 V
90
85
90
VIN = 5.5 V
VIN = 3.6 V
85
VIN = 2.5 V
80
−50
−25
0
25
50
(°C)
75
100
80
−50
125
Figure 12. Quiescent current versus Vinx and
PVIN Tied Together HWEN high, LDOs on,
DCDC on, No Switching
−25
0
25
50
(°C)
75
100
Figure 13. Quiescent Current versus
Temperature, Vinx and PVIN Tied Together
HWEN High, LDOs on, DCDC On, No
Switching
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125
NCP6915
TYPICAL OPERATING CHARACTERISTICS
0
−10
−20
10k
NOISE (nV/√Hz)
−30
PSRR (dB)
VOUT = 1.8 V
VOUT = 2.8 V
VIN = 5 V
VIN = 3.6 V
VIN = 1.7 V
−40
−50
−60
−70
1k
100
−80
−90
−100
100
1k
10k
FREQUENCY (Hz)
100k
1M
10
0.1
Figure 14. LDO4 PSRR
1
100
1k
10
FREQUENCY (Hz)
10k
Figure 15. LDO1 Output Noise versus
Frequency and Vout, Vin 3.6 V
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100k
NCP6915
I2C Compatible Interface
I2C Communication Description
NCP6915 can support a subset of I2C protocol, below are
detailed introduction for I2C programming.
ON Semiconductor communication protocol is a subset
of I2C protocol.
Figure 16. General Protocol Description
The first byte transmitted is the Chip address (with LSB
bit sets to 1 for a read operation, or sets to 0 for a Write
operation). Then the following data will be:
• In case of a Write operation, the register address
(@REG) we want to write in followed by the data we
will write in the chip. The writing process is
incremental. So the first data will be written in @REG,
the second one in @REG + 1 .... The data are optional.
• In case of read operation, the NCP6915 will output the
data out from the last register that has been accessed by
the last write operation. Like writing process, reading
process is an incremental process.
Read out from Part
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
then start or a Repeated Start will initiate the read transaction
from the register address the initial write transaction has set:
Figure 17. Read Out from Part
The first WRITE sequence will set the internal pointer on
the register we want access to. Then the read transaction will
start at the address the write transaction has initiated.
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NCP6915
Transaction with Real Write then Read
1. With Stop Then Start
Figure 18. Write Followed by Read Transaction
Write in Part
Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register
we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2, ...., Reg +n.
Write n Registers:
Figure 19. Write in n Registers
I2C Address
NCP6915 has fixed I2C but different I2C address (by default $10, 7 bit address, see below table A7~A1), NCP6915 supports
7−bit address only.
Table 10. NCP6915 I2C AdDRESS
I2C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0 (Default)
W $20 /R $21
0
0
1
0
0
0
0
X
ADDRESS
$10
0
0
1
0
0
0
0
−
Different default address is available upon request
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NCP6915
Register Map
Following register map describes I2C registers.
Registers can be:
R
Read only register
RC
Read then Clear
RW
Read and Write register
RWM
Read, Write and can be modified by the IC
Reserved
Address is reserved and register is not physically designed
Spare
Address is reserved and register is physically designed
Table 11. REGISTERS SUMMARY
Address
Register Name
Type
Default
Function
$00
GENERAL_SETTINGS
RW
$00
DVS control Settings
$01
LDO1_SETTINGS
RW
$39
LDO1 register settings
$02
LDO2_SETTINGS
RW
$79
LDO2 register settings
$03
LDO3_SETTINGS
RW
$8C
LDO3 register settings
$04
LDO4_SETTINGS
RW
$BE
LDO4 register settings
$05
LDO5_SETTINGS
RW
$D1
LDO5 register settings
$06
DCDC_SETTINGS1
RW
$15
DCDC register settings 1
$07
DCDC_SETTINGS2
RW
$13
DCDC register settings 2
$08
ENABLE
RW
$80
Enable and DVS register settings
$09
PULLDOWN
RW
$3F
Active discharge and rearming register
$0A
STATUS
R
$04
Status or sense register
$0B
INTERRUPT_ACK
RC
$00
Interrupt register
$0C to $FF
−
−
−
Reserved. Do not access to those registers
Details of the registers are in the following section.
Registers Description
Table 12. GENERAL_SETTINGS REGISTER
Name: GENERAL_SETTINGS
Address: $00
Type: RW
Default: $00
D7
D6
D5
D4
D3
D2
D1
D0
spare = 0
spare = 0
spare = 0
DVS
spare = 0
spare = 0
spare = 0
spare = 0
D1
D0
Table 13. BIT DESCRIPTION OF GENERAL_SETTINGS REGISTER
Bit
Bit Description
DVS[0]
Ramp up time per voltage step
Table 14. LDO1_SETTINGS REGISTER
Name: LDO1_SETTINGS
Address: $01
Type: RW
Default: $39
D7
D6
D5
D4
D3
LDO1_T [2:0]
D2
LDO1_V[4:0]
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NCP6915
Table 15. BIT DESCRIPTION OF LDO1_SETTINGS REGISTER
Bit
Bit Description
LDO1_V[4:0]
LDO1 output voltage setting, refer to Table 16
LDO1_T[2:0]
LDO1 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO1
startup
Delay time = (LDO1_T[2:0] + 1) * 128 ms
Remark: it’s not recommended to use same LDOx_T for two consecutives LDOs.
64 ms, 128 ms, 1 ms, 2 ms OTP options (128 ms default value)
Table 16. LDO2_SETTINGS REGISTER
Name: LDO2_SETTINGS
Address: $02
Type: RW
Default: $79
D7
D6
D5
D4
D3
D2
LDO2_T [2:0]
D1
D0
LDO2_V[4:0]
Table 17. BIT DESCRIPTION OF LDO2_SETTINGS REGISTER
Bit
Bit Description
LDO2_V[4:0]
LDO2 output voltage setting, refer to Table 16
LDO2_T[2:0]
LDO2 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO2
startup
Delay time = (LDO2_T[2:0] + 1) * 128 ms
Remark: it’s not recommended to use same LDOx_T for two consecutives LDOs.
Table 18. LDO3_SETTINGS REGISTER
Name: LDO3_SETTINGS
Address: $03
Type: RW
Default: $8C
D7
D6
D5
D4
D3
LDO3_T [2:0]
D2
D1
D0
LDO3_V[4:0]
Table 19. BIT DESCRIPTION OF LDO3_SETTINGS REGISTER
Bit
Bit Description
LDO3_V[4:0]
LDO3 output voltage setting, refer to Table 16
LDO3_T[2:0]
LDO3 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO3
startup
Delay time = (LDO3_T[2:0] + 1) * 128 ms
Remark: it’s not recommended to use same LDOx_T for two consecutives LDOs.
Table 20. LDO1_V[4:0], LDO2_V[4:0], LDO3_V[4:0] SETTING TABLE
Register
Vout (V)
Register
Vout (V)
Register
Vout (V)
Register
Vout (V)
00000
1.70
01000
1.70
10000
2.10
11000
2.75
00001
1.70
01001
1.70
10001
2.20
11001
2.80
00010
1.70
01010
1.70
10010
2.30
11010
2.85
00011
1.70
01011
1.75
10011
2.40
11011
2.90
00100
1.70
01100
1.80
10100
2.50
11100
2.95
00101
1.70
01101
1.85
10101
2.60
11101
3.00
00110
1.70
01110
1.90
10110
2.65
11110
3.10
00111
1.70
01111
2.00
10111
2.70
11111
3.30
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NCP6915
Table 21. LDO4_SETTINGS REGISTER
Name: LDO4_SETTINGS
Address: $04
Type: RW
Default: $BE
D7
D6
D5
D4
D3
LDO4_T [2:0]
D2
D1
D0
LDO4_V[4:0]
Table 22. BIT DESCRIPTION OF LDO4_SETTINGS REGISTER
Bit
Bit Description
LDO4_V[4:0]
LDO4 output voltage setting, refer to Table 21
LDO4_T[2:0]
LDO4 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO4
startup
Delay time = (LDO4_T[2:0] + 1) * 128 ms
Remark: it’s not recommended to use same LDOx_T for two consecutives LDOs.
Table 23. LDO5_SETTINGS REGISTER
Name: LDO5_SETTINGS
Address: $05
Type: RW
Default: $D1
D7
D6
D5
D4
D3
LDO5_T [2:0]
D2
D1
D0
LDO5_V[4:0]
Table 24. BIT DESCRIPTION OF LDO5_SETTINGS REGISTER
Bit
Bit Description
LDO5_V[4:0]
LDO5 output voltage setting, refer to Table 21
LDO5_T[2:0]
LDO5 startup delay time setting (delay time between HWEN transitions from LOW to High and LDO5
startup
Delay time = (LDO5_T[2:0] + 1) * 128 ms
Remark: it’s not recommended to use same LDOx_T for two consecutives LDOs.
Table 25. LDO4_V[4:0], LDO5_V[4:0] SETTING TABLE
Register
Vout (V)
Register
Vout (V)
Register
Vout (V)
Register
Vout (V)
00000
1.20
01000
1.35
10000
1.75
11000
2.40
00001
1.20
01001
1.40
10001
1.80
11001
2.50
00010
1.20
01010
1.45
10010
1.85
11010
2.60
00011
1.20
01011
1.50
10011
1.90
11011
2.65
00100
1.20
01100
1.55
10100
2.00
11100
2.70
00101
1.20
01101
1.60
10101
2.10
11101
2.75
00110
1.25
01110
1.65
10110
2.20
11110
2.80
00111
1.30
01111
1.70
10111
2.30
11111
2.85
D1
D0
Table 26. DCDC_SETTINGS1 REGISTER
Name: DCDC_SETTINGS1
Address: $06
Type: RW
Default: $15
D7
D6
D5
D4
D3
DCDC_T[2:0]
D2
DCDC_V1[4:0]
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NCP6915
Table 27. BIT DESCRIPTION OF DCDC_SETTINGS1 REGISTER
Bit
Bit Description
DCDC_V1[4:0]
DCDC output voltage setting 1, refer to Table 25
DCDC_T[2:0]
DCDC startup delay time setting (delay time between HWEN transitions from LOW to High and DCDC
startup
Delay time = (DCDC_T[2:0] + 1) * 128ms
Table 28. DCDC_SETTINGS2 REGISTER
Name: DCDC_SETTINGS2
Address: $07
Type: RW
Default: $13
D7
D6
D5
spare = 0
spare = 0
MODEDCDC
D4
D3
D2
D1
D0
DCDC_V2[4:0]
Table 29. BIT DESCRIPTION OF DCDC_SETTINGS2 REGISTER
Bit
Bit Description
DCDC_V2[4:0]
DCDC output voltage setting 2, refer to Table 25
MODEDCDC
DCDC Operating Mode
0: Auto switching PFM / PWM (default)
1: Forced PWM
Table 30. DCDC_Vx[4:0] SETTING TABLE
DCDC_V1/2
Vout (V)
DCDC_V1/2
Vout (V)
DCDC_V1/2
Vout (V)
DCDC_V1/2
Vout (V)
00000
0.80 V
01000
1.15 V
10000
1.55 V
11000
1.95 V
00001
0.80 V
01001 (V1)*
1.20 V
10001
1.60 V
11001
2.00 V
00010
0.85 V
01010
1.25 V
10010
1.65 V
11010
2.05 V
00011
0.90 V
01011
1.30 V
10011
1.70 V
11011
2.10 V
00100
0.95 V
01100
1.35 V
10100
1.75 V
11100
2.15 V
00101
1.00 V
01101
1.40 V
10101
1.80 V
11101
2.20 V
00110
1.05 V
01110
1.45 V
10110
1.85 V
11110
2.25 V
00111 (V2)
1.10 V
01111
1.50 V
10111
1.90 V
11111
2.30 V
*Default value: V1
Table 31. ENABLE REGISTER
Name: ENABLE
Address: $08
Type: RW
Default: $80
D7
D6
D5
D4
D3
D2
D1
D0
DCDC_V2/V1
spare = 0
DCDC_ EN
LDO5_ EN
LDO4_ EN
LDO3_ EN
LDO2_ EN
LDO1_ EN
Table 32. BIT DESCRIPTION OF ENABLE REGISTER
Bit
DCDC_V2/V1
DCDC_ EN
Bit Description
DCDC output voltage setting
0: DCDC converter output voltage is set to DCDC_V2
1: DCDC converter output voltage is set to DCDC_V1
DCDC Enabling
0: Disabled
1: Enabled
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NCP6915
Table 32. BIT DESCRIPTION OF ENABLE REGISTER
Bit
Bit Description
LDO5_ EN
LDO5 Enabling
0: Disabled
1: Enabled
LDO4_ EN
LDO4 Enabling
0: Disabled
1: Enabled
LDO3_ EN
LDO3 Enabling
0: Disabled
1: Enabled
LDO2_ EN
LDO2 Enabling
0: Disabled
1: Enabled
LDO1_ EN
LDO1 Enabling
0: Disabled
1: Enabled
Table 33. PULLDOWN REGISTER
Name: PULLDOWN
Address: $09
Type: RW
Default: $3F
D7
D6
D5
D4
D3
D2
D1
D0
REARM_ TSD[7]
REARM_
TSD[6]
DCDC_
PULLDOWN
LDO5_
PULLDOWN
LDO4_
PULLDOWN
LDO3_
PULLDOWN
LDO2_
PULLDOWN
LDO1_
PULLDOWN
Table 34. BIT DESCRIPTION OF PULLDOWN REGISTER
Bit
Bit Description
REARM_ TSD[7:6]
Device Rearming after Thermal Shut Down
11: N/A
10: No re−arming after TSD
01: Re-arming active after TSD with no reset of I2C registers: new power-up sequence is initiated with I2C
registers values.
00: Re-arming active after TSD with reset of I2C registers: new power-up sequence is initiated with default
I2C registers values (default).
DCDC_ PULLDOWN
DCDC active output discharge
0: Disabled
1: Enabled
LDO5_ PULLDOWN
LDO5 active output discharge
0: Disabled
1: Enabled
LDO4_ PULLDOWN
LDO4 active output discharge
0: Disabled
1: Enabled
LDO3_ PULLDOWN
LDO3 active output discharge
0: Disabled
1: Enabled
LDO2_ PULLDOWN
LDO2 active output discharge
0: Disabled
1: Enabled
LDO1_ PULLDOWN
LDO1 active output discharge
0: Disabled
1: Enabled
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NCP6915
Table 35. STATUS REGISTER
Name: STATUS
Address: $0A
Type: R
Default: $04
D7
D6
D5
D4
D3
D2
D1
D0
spare = 0
spare = 0
spare = 0
spare = 0
SEN_UVLO
SEN_/PUS
SEN_TSD
SEN_WNRG
Table 36. BIT DESCRIPTION OF STATUS REGISTER
Bit
Bit Description
SEN_UVLO
UVLO sense
0: Input voltage is higher than (UVLO + hyst) threshold.
1: Input voltage is lower than (UVLO) threshold.
SEN_PUS
Power up sequence
0: Power up sequence on going
1: Power up sequence finished or HWEN is low
SEN_TSD
Thermal Shut Down sense
0: IC temperature is below TSD threshold
1: IC temperature is over TSD threshold
SEN_WNRG
Thermal warning sense
0: IC temperature is below Thermal Warning threshold
1: IC temperature is over Thermal Warning threshold
Table 37. INTERRUPT_ACK REGISTER
Name: INTERRUPT_ACK
Address: $0B
Type: RC
Default: $00
D7
D6
D5
D4
D3
D2
D1
D0
spare = 0
spare = 0
spare = 0
spare = 0
ACK_UVLO
ACK_PUS
ACK_TSD
ACK_WNRG
Table 38. BIT DESCRIPTION OF INTERRUPT_ACK REGISTER
Bit
ACK_UVLO
UVLO sense acknowledge
0: Cleared
1: SEN_UVLO Dual edge triggered interrupt
ACK_PUS
Power up sequence sense acknowledge
0: Cleared
1: SEN_PUS Rising edge triggered interrupt
ACK_TSD
Thermal Shut Down sense acknowledge
0: Cleared
1: SEN_TSD Dual edge triggered interrupt
ACK_WNRG
NOTE:
Bit Description
Thermal warning sense acknowledge
0: Cleared
1: SEN_WNRG Dual edge triggered interrupt
SEN_PUS rising edge appears (16 ) x 128ms (default) after HWEN rising edge.
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21
NCP6915
DEMOBOARD INFORMATIONS
Figure 20. Demoboard Schematic
COMPONENTS SELECTION
Inductor Selection
The inductance of the inductor is determined by given peak−to−peak ripple current IL_PP of approximately 20% to 50% of
the maximum output current IOUT_MAX for a trade−off between transient response and output ripple. The inductance
corresponding to the given current ripple is:
L+
ǒVIN * VOUTǓ @ VOUT
V IN @ f SW @ I L_PP
The selected inductor must have high enough saturation current rating to be higher than the maximum peak current that is
I L_MAX + I OUT_MAX )
I L_PP
2
The inductor also needs to have high enough current rating based on temperature rise concern. Low DCR is good for
efficiency improvement and temperature rise reduction. Table 39 shows recommended.
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22
NCP6915
Table 39. INDUCTOR SELECTION
Supplier
TOKO
TOKO
Murata
Murata
Cyntec
Part
DFE201610R-H-1R0N
MDT2012-CLR1R0AM
LQM21PN1R0NGR
LQM2MPN1R0NG0
PIFE2016T-1R0
Value (mH)
1
1
1
1
1
Size (mm) DC Rated Current (A) DCR Max at 25°C (mW)
2.0x1.6 mm
2.2
48
2.0x1.2 mm
2.15
80
2.0x1.2 mm
1.3
66
2.0x1.6 mm
1.4
85
2.0x1.6 mm
2
80
Table 40. BOARD COMPONENTS DESCRIPTION
Quantity
1
1
3
2
2
1
5
2
1
1
1
1
2
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reference schem
B1
B2
C1,C3,C5
C7,C8
C9,C11
C10
C12,C13,C14,C15,C16
GND2,GND
J1
L1
Q3
Q4
R1,R2
S1,S2,S3,S11
TP2
S12
TP1
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
U1
Part description
HEADER200 4
HEADER200_12
100uF
2.2uF
10uF
100nF
1uF
GND JUMPER
CON26A
1uH
Nmos
Nmos
50 Ohms
STRAP 2pins
HWEN
LOGIC_SUPPLY
VBAT
SDA
SCL
VIN1
VIN2
DCDC_VOUT
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
FB1
SMB4
SMB3
PMIC
Part number
SL 5.08/4/90B
2.54 mm, 77313-101-06LF
GRM31CR60J107ME39#
GRM188R60J225KE19#
GRM188R60J106ME47#
GRM033C801J104KE84B
GRM155R70J105KA12#
D3082F05
N2526-5002RB
DFE201610R-H-1R0N
BSS138LT1
NTD4969NT4G
FC0603E50R0BTBST1
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
77311-401-36LF
NCP6915
Manufacturer
Weidmuller
FC
Murata
Murata
Murata
Murata
Murata
Harvin
3M
Toko
ON Semiconductor
ON Semiconductor
Vishay
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
FCI
ON Semiconductor
ORDERING INFORMATION
Device
NCP6915AFCCLT1G
Marking
Package
Shipping†
6915A
WLCSP 1.56x1.56 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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23
NCP6915
PACKAGE DIMENSIONS
WLCSP16, 1.56x1.56
CASE 567GF
ISSUE D
ÈÈ
PIN A1
REFERENCE
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
A3
A2
DIM
A
A1
A2
A3
b
D
E
e
E
0.10 C
2X
0.10 C
2X
DETAIL A
TOP VIEW
A2
DETAIL A
MILLIMETERS
MIN
MAX
−−−
0.60
0.17
0.23
0.33
0.39
0.04 BSC
0.24
0.29
1.56 BSC
1.56 BSC
0.40 BSC
0.10 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05 C
NOTE 3
A1
C
SIDE VIEW
SEATING
PLANE
PACKAGE
OUTLINE
A1
e/2
16X
b
e
0.05 C A B
0.03 C
e
D
0.40
PITCH
e/2
C
16X
0.40
PITCH
B
0.25
DIMENSIONS: MILLIMETERS
A
1
2
3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
4
BOTTOM VIEW
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NCP6915/D