Maxim MAX9880A Low-power, high-performance dual i2s stereo audio codec Datasheet

19-5139; Rev 0; 7/10
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
PART
TEMP RANGE
PIN-PACKAGE
MAX9880AEWM+
-40°C to +85°C
48 WLP
MAX9880AETM+
-40°C to +85°C
48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Simplified Block Diagram
RIGHT
I2C
INTERFACE
LEFT
DAC
DIGITAL
FILTERING
RIGHT
DAC
JACK SENSE/
MEASUREMENT
ADC
MIX
LEFT
DIGITAL
DIGITAL
AUDIO
AUDIO
INTERFACE INTERFACE
1
2
MIX
MASTER
CLOCK
MIC
BIAS
MIX
The MAX9880A prevents click and pop during volume
changes and during power-up and power-down. Audio
quality is further enhanced with user-configurable digital
filters for voice and audio data. Voiceband filters provide extra attenuation at the GSM packet frequency and
greater than 70dB stopband attenuation at fS/2. An I2C
or SPI™ serial interface provides control for volume levels, signal mixing, and general operating modes.
The MAX9880A is available in space-saving, 48-bump,
2.7mm x 3.5mm, 0.4mm-pitch WLP and 48-pin, 6mm x
6mm TQFN packages.
Ordering Information
MIX
The MAX9880A is a high-performance, stereo audio
codec designed for portable consumer applications
such as smartphones and tablets. Operating from a single 1.8V supply to ensure low-power consumption, the
MAX9880A offers a variety of input and output configurations for design flexibility. The MAX9880A can be
combined with an audio subsystem, such as the
MAX9877 or MAX9879, for a complete audio solution
for portable applications.
The MAX9880A’s stereo differential microphone inputs
can support either analog or digital microphones. A
stereo single-ended line input, with a configurable preamplifier, can either be recorded by the ADC or routed
directly to the headphone or line output amplifiers. The
stereo headphone amplifiers can be configured as differential, single ended, or capacitorless. The stereo line
outputs have dedicated level adjustment.
There are two digital audio interfaces. The primary
interface is intended for voiceband applications, while
the secondary interface can be used for high performance stereo audio data. Two digital input streams can
be processed simultaneously and both digital interfaces support TDM and I2S data formats.
The flexible clocking circuitry utilizes any available
10MHz to 60MHz system clock, eliminating the need for
an external PLL and multiple crystal oscillators. Both
the ADC and DAC can be operated synchronously or
asynchronously in master or slave mode. The ADC can
be operated from 8kHz to 48kHz sample rates, while
the DAC can be operated up to 96kHz.
Features
♦ 1.8V Single-Supply Operation
♦ 10.6mW Playback Power Consumption
♦ 8kHz to 96kHz Stereo DAC with 96dB Dynamic
Range
♦ 8kHz to 48kHz Stereo ADC with 82dB Dynamic
Range
♦ Support for Any Master Clock Between 10MHz to
60MHz
♦ Stereo Microphone Inputs Support Digital
Microphones
♦ Stereo Headphone Amplifiers: Differential
(30mW), Single-Ended, or Capacitorless (10mW)
♦ Stereo Line Inputs and Stereo Line Outputs
♦ Voiceband Filters with Stopband Attenuation
Greater than 70dB
♦ Battery-Measurement Auxiliary ADC
♦ Comprehensive Headset Detection
♦ Dual I2S- and TDM-Compatible Digital Audio
Interfaces
♦ I2C- or SPI-Compatible Control Bus with 3.6V
Tolerant Inputs
Cellular Phones
Tablet PCs
MAX9880A
MIX
MIX
Applications
Portable Gaming Devices
Portable Multimedia Players
SPI is a trademark of Motorola, Inc.
Functional Diagram/Typical Operating and Pin
Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX9880A
General Description
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.)
DVDD, AVDD and PVDD ..........................................-0.3V to +2V
DVDDS1, JACKSNS, MICVDD ..............................-0.3V to +3.6V
DGND and PGND..................................................-0.1V to +0.1V
PREG, REF, REG ....................................-0.3V to (VAVDD + 0.3V)
MICBIAS .............................................-0.3V to (VMICVDD + 0.3V)
MCLK, LRCLKS1, BCLKS1,
SDINS1, SDOUTS1..........................-0.3V to (VDVDDS1 + 0.3V)
X1, X2, LRCLKS2, BCLKS2, SDINS2,
SDOUTS2, DOUT, MODE ...................-0.3V to (VDVDD + 0.3V)
SDA/DIN, SCL/SCLK, CS, IRQ ..............................-0.3V to +3.6V
LOUTP, LOUTN, ROUTP, ROUTN,
LOUTL, LOUTR ....................(VPGND - 0.3V) to (VPVDD + 0.3V)
LINL, LINR, MICLP/DIGMICDATA,
MICLN/DIGMICCLK, MICRP/SPDMDATA,
MICRN/SPDMCLK ...............................-0.3V to (VAVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
48-Bump WLP (derate 12.5mW/°C above +70°C) .....1000mW
48-Pin TQFN (derate 37mW/°C above +70°C) ..........2963mW
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
48-Bump WLP ...............................................................80°C/W
48-Pin TQFN..................................................................29°C/W
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Supply Voltage Range
CONDITIONS
1.65
1.8
1.95
1.65
1.8
3.6
Analog (AVDD + PVDD +
MICVDD)
5.33
8
Digital (DVDD + DVDDS1)
1.4
2
Analog (AVDD + PVDD +
MICVDD)
3.5
6
Digital (DVDD + DVDDS1)
2.5
4
Analog (AVDD + PVDD +
MICVDD)
8.4
12
Digital (DVDD + DVDDS1)
3.0
5
I VDD
Full-duplex 48kHz
stereo (Note 3)
Shutdown to Full
Operation
2
MAX
DVDDS1, MICVDD
DAC playback
48kHz stereo
(Note 3)
Shutdown Supply
Current
TYP
PVDD, DVDD, AVDD
Full-duplex 8kHz
mono (Note 3)
Total Supply Current
MIN
Stereo line-in to
line-out only,
TA = +25°C
Analog (AVDD + PVDD +
MICVDD)
4.9
8
Digital (DVDD + DVDDS1)
0.012
0.05
TA = +25°C
Analog (AVDD + PVDD +
MICVDD)
0.3
2
Digital (DVDD + DVDDS1)
2.6
8
Excludes PLL lock time
10
_______________________________________________________________________________________
UNITS
V
mA
μA
ms
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC (Note 4)
Dynamic Range
(Note 5)
DR
fS = 48kHz, AVVOL = +0dB,
TA = +25°C
Master or slave mode
Slave mode
96
Differential mode
Full-Scale Output
1
Capacitorless and single-ended modes
Gain Error
DC accuracy, measured with respect to full-scale
output
Voice Path Phase Delay
1kHz, 0dB input, highpass
filter disabled measured from
digital input to analog output;
MODE = 0 (IIR voice)
Total Harmonic
Distortion
PDLY
THD
AVDAC
VDACA/SDACA = 0xF to 0x0
DAC Gain Adjust
AV GAIN
VDACG = 00 to 11
Power-Supply Rejection
Ratio
PSRR
1
f S = 8kHz
1.2
f S = 16kHz
0.59
f PLP
Passband Ripple
Stopband Cutoff
f SLP
-75
dB
0
dB
0
+18
dB
85
f = 1kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
80
85
dB
74
With respect to f S within ripple; f S = 8kHz to 48kHz
0.448 x f S
-3dB cutoff
f < f PLP
0.451 x f S
±0.1
With respect to f S; f S = 8kHz to 48kHz
0.476 x f S
f > f SLP, f = 20Hz to 20kHz
DAC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
fDHPPB
%
-15
VAVDD = VPVDD = 1.65V to 1.95V
f = 217Hz, VRIPPLE = 100mVP-P, AV VOL = 0dB
Stopband Attenuation
5th-Order Passband
Cutoff
(-3dB from Peak,
I2C Register
Programmable)
5
ms
f = 10kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
DAC VOICE MODE DIGITAL IIR LOWPASS FILTER (6x Interpolation)
Passband Cutoff
VRMS
0.56
fMCLK = 12.288MHz, f S = 48kHz, 0dBFS, measured
at headphone outputs
DAC Attenuation Range
dB
88
75
Hz
dB
Hz
dB
DVFLT = 0x1
(Elliptical tuned for 16kHz GSM + 217Hz notch)
0.0161 x
fS
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312 x
fS
DVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0321 x
fS
DVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0625 x
fS
DVFLT = 0x5
(fS/240 Butterworth)
0.0042 x
fS
Hz
_______________________________________________________________________________________
3
MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
5th-Order Stopband
Cutoff
(-30dB from Peak,
I2C Register
Programmable)
DC Attenuation
SYMBOL
fDHPSB
CONDITIONS
MIN
TYP
DVFLT = 0x1
(Elliptical tuned for 16kHz GSM + 217Hz notch)
0.0139 x
fS
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0156 x
fS
DVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0279 x
fS
DVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0312 x
fS
DVFLT = 0x5
(fS/240 Butterworth)
0.0021 x
fS
DCATTEN DVFLT not equal to 000
MAX
UNITS
Hz
90
dB
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 0, fLRCLK < 50kHz)
Passband Cutoff
f PLP
With respect to f S within ripple; f S = 8kHz to 48kHz
0.43 x f S
-3dB cutoff
0.47 x f S
0.50 x f S
Hz
±0.1
dB
0.58 x f S
Hz
-6.02dB cutoff
Passband Ripple
f < f PLP
Stopband Cutoff
With respect to f S; f S = 8kHz to 48kHz; f S = 0.5f S to
3.5f S
f SLP
Stopband Attenuation
f > f SLP
60
dB
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 1 for fLRCLK > 50kHz)
Passband Cutoff
f PLP
Passband Ripple
Stopband Cutoff
Ripple limit cutoff
-3dB cutoff
f < f PLP
f SLP
Stopband Attenuation
With respect to f S; f S = 0.5 f S to 3.5 f S
f > f SLP
0.24 x f S
0.33 x f S
Hz
±0.1
dB
0.5 x f S
Hz
60
dB
DAC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak)
DC Attenuation
fDHPPB
DVFLT = 0x1 (DAI1), DCB = 1 (DAI2)
DCATTEN DVFLT = 0x1 (DAI1), DCB = 1 (DAI2)
0.000625 x
fS
Hz
90
dB
ADC (Note 6)
Dynamic Range
(Note 5)
DR
f S = 8kHz, MODE = 0 (IIR voice), TA = +25°C
fS = 8kHz to 48kHz, MODE = 1 (FIR audio) (Note 7)
72
82
Full-Scale Input
Differential MIC input or stereo line inputs,
AV PRE = 0dB, AV PGA = 0dB
1
Gain Error (Note 7)
DC accuracy, measured with respect to 80% of fullscale output
1
Voice Path Phase Delay
1kHz, 0dB input, highpass
filter disabled measured from
analog input to digital output;
MODE = 0 (IIR voice)
4
dB
84
f S = 8kHz
1.2
f S = 16kHz
0.61
VP-P
5
%
ms
_______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Total Harmonic
Distortion
THD
ADC Level Adjust
AVADC
Power-Supply Rejection
Ratio
PSRR
CONDITIONS
MIN
f = 1kHz, f S = 8kHz, TA = +25°C, -20dB input
AVL/AVR = 0xF to 0x0
-12
VAVDD = 1.65V to 1.95V, input referred
60
TYP
MAX
UNITS
-80
-70
dB
+3
dB
80
f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred
80
f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input
referred
78
f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred
72
dB
ADC VOICE MODE DIGITAL IIR LOWPASS FILTER
Passband Cutoff
f PLP
Passband Ripple
Stopband Cutoff
f SLP
Stopband Attenuation
With respect to f S within ripple; f S = 8kHz to 48kHz
0.445 x f S
-3dB cutoff
0.449 x f S
f < f PLP
With respect to f S; f S = 8kHz to 48kHz
f > f SLP, f = 20Hz to 20kHz
±0.1
0.469 x f S
74
Hz
dB
Hz
dB
ADC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak)
fAHPPB
AVFLT = 0x1
(Elliptical tuned for 16kHz GSM + 217Hz notch)
0.0161 x
fS
AVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312 x
fS
AVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0321 x
fS
AVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0625 x
fS
AVFLT = 0x5 (f S/240 Butterworth)
AVFLT = 0x1 (Elliptical tuned for 16kHz GSM +
217Hz notch)
AVFLT = 0x2 (500Hz Butterworth tuned for 16kHz)
Stopband Cutoff
(-30dB from Peak)
fAHPSB
AVFLT = 0x3 (Elliptical tuned for 8kHz GSM +
217Hz notch)
AVFLT = 0x4 (500Hz Butterworth tuned for 8kHz)
AVFLT = 0x5 (f S/240 Butterworth)
DC Attenuation
DCATTEN AVFLT 000
Hz
0.0042 x f S
0.0139 x
fS
0.0156 x f S
0.0279 x
fS
Hz
0.0312 x f S
0.0021 x f S
90
dB
ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
Passband Cutoff
f PLP
With respect to f S within ripple; f S = 8kHz to 48kHz
0.43 x f S
-3dB cutoff
0.48 x f S
-6.02dB cutoff
Hz
0.5 x f S
_______________________________________________________________________________________
5
MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Passband Ripple
Stopband Cutoff
CONDITIONS
MIN
With respect to f S; f S = 8kHz to 48kHz
Stopband Attenuation
f > f SLP, f = 20Hz to 20kHz
ADC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak)
DC Attenuation
fAHPPB
MAX
±0.1
f < f PLP
f SLP
TYP
AVFLT = 0x1
DCATTEN AVFLT = 0x1
UNITS
dB
0.58 x f S
Hz
60
dB
0.000625
x fS
Hz
90
dB
OUTPUT VOLUME CONTROL
Output Volume Control
(Note 8)
Output Volume Control
Step Size
Output Volume Control
Mute Attenuation
VOLL/VOLR = 0x00
8.1
8.6
9.2
VOLL/VOLR = 0x01
7.6
8.1
8.6
VOLL/VOLR = 0x02
7.1
7.6
8.1
VOLL/VOLR = 0x04
6.1
6.6
7.2
VOLL/VOLR = 0x08
3.1
3.6
4.3
VOLL/VOLR = 0x10
-5.9
-5.4
-4.9
VOLL/VOLR = 0x20
-60
-55.1
-52
VOLL/VOLR = 0x27
-94
-84
-81
VOLL/VOLR = 00x00 to 0x06 (+9dB to +6dB)
0.5
VOLL/VOLR = 00x06 to 0x0F (+6dB to +3dB)
1
VOLL/VOLR = 00x0F to 0x17 (-3dB to -19dB)
2
VOLL/VOLR = 00x17 to 0x27 (-19dB to -81dB)
4
f = 1kHz
dB
dB
100
dB
HEADPHONE AMPLIFIER (Note 9)
RL = 16
25
48
Output Power
(Differential Mode)
POUT
f = 1kHz, 0dBFS input,
THD < 1%, TA = +25°C
RL = 32
30
Output Power
(Capacitorless Mode)
POUT
f = 1kHz, 0dBFS input,
THD < 1%, TA = +25°C
RL = 16
17
RL = 32
10
Total Harmonic
Distortion + Noise
(Differential Mode)
f = 1kHz, -3dBFS input
RL = 16
-78
THD+N
RL = 32
-79
Total Harmonic
Distortion + Noise
(Capacitorless Mode)
RL = 16
-73
THD+N
RL = 32
-75
Total Harmonic
Distortion + Noise
(Single-Ended Mode)
RL = 16
-70
THD+N
RL = 32
-70
Dynamic Range
(Notes 5, 7)
6
DR
f = 1kHz, -3dBFS input
f = 1kHz, -3dBFS input
AV VOL = +6dB
mW
mW
-67
dB
-60
dB
-60
dB
77
90
_______________________________________________________________________________________
dB
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
VAVDD = VPVDD = 1.65V to 1.95V
Power-Supply Rejection
Ratio (Note 7)
Output Offset Voltage
Crosstalk
PSRR
VOS
XTALK
Capacitive Drive
Capability
60
TYP
MAX
UNITS
80
f = 217Hz, VRIPPLE = 100mVP-P, AV VOL = 0dB
80
f = 1kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
f = 10kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
78
dB
72
AV VOL = -81dB
differential mode
LOUTP to LOUTN, ROUTP to
ROUTN, TA = +25°C
±0.2
AV VOL = -81dB,
capacitorless mode
LOUTP to LOUTN, ROUTP to
LOUTN, TA = +25°C
±0.6
mV
Differential, P OUT = 5mW, f = 1kHz
90
Capacitorless mode, P OUT = 5mW, f = 1kHz
RL = 32
No sustained oscillations
RL = 45
dB
500
pF
100
Click-and-Pop Level
(Differential,
Capacitorless Modes)
Peak voltage, A-weighted,
32 samples per second
Into shutdown
-70
Out of shutdown
-70
Click-and-Pop Level
(Single-Ended Mode)
Peak voltage, A-weighted,
32 samples per second
Into shutdown
-70
Out of shutdown
-70
dBV
dBV
LINE OUTPUTS (Note 7)
Full-Scale Output
0.5
Line Output Level
Adjust
AVLO
Line Output Mute
Attenuation
Total Harmonic
Distortion + Noise
THD+N
Signal-to-Noise Ratio
Power-Supply Rejection
Ratio
Capacitive Drive
Capability
PSRR
VRMS
LOGL/LOGR = 0x00
-0.7
-0.1
+0.6
LOGL/LOGR = 0x01
LOGL/LOGR = 0x02
-2.6
-4.6
-2.1
-4.1
-1.6
-3.6
LOGL/LOGR = 0x04
-8.6
-8.1
-7.6
LOGL/LOGR = 0x08
-16.6
-16
-15.6
LOGL/LOGR = 0x0F
-31.1
-29.9
-29.1
f = 1kHz
90
RL = 1k, f = 1kHz, VOUT = 1.4V P-P (Note 9)
-67
RL = 1k, LINL/LINR = 20Hz < f < 20kHz
1μF to GND
A-weighted
86
90
VAVDD = VPVDD = 1.65V to 1.95V
46
f = 217Hz, VRIPPLE = 100mVP-P, AV VOL = 0dB
78
f = 1kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
f = 10kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
80
RL = 10k, no sustained oscillations
dB
dB
-59
dB
dB
dB
76
100
pF
_______________________________________________________________________________________
7
MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MICROPHONE AMPLIFIER
Preamplifier Gain
AV PRE
MIC PGA Gain
AV PGAM
Common-Mode
Rejection Ratio
CMRR
MIC Input Resistance
Total Harmonic
Distortion + Noise
PALEN/PAREN = 01
-0.5
0
+0.5
PALEN/PAREN = 10
19.5
20
20.5
PALEN/PAREN = 11
29.3
30
30.5
PGAML/PGAMR = 0x1F
-0.5
0
+0.6
PGAML/PGAMR = 0x00
19.3
19.9
20.4
VIN = 100mVP-P, f = 217Hz
RIN_MIC All gain settings
THD+N
30
Power-Supply Rejection
Ratio
PSRR
dB
50
dB
50
k
AV PRE = 0dB
VIN = 1VP-P, f = 1kHz, A-weighted
-80
AV PRE = +30dB
VIN = 32mV P-P, f = 1kHz, A-weighted
-65
VAVDD = 1.65V to 1.95V, input referred
dB
dB
60
80
f = 217Hz, VRIPPLE = 100mV, AVADC = 0dB, input
referred
80
f = 1kHz, VRIPPLE = 100mV, AVADC = 0dB, input
referred
78
f = 10kHz, VRIPPLE = 100mV, AVADC = 0dB, input
referred
72
dB
MICROPHONE BIAS
MICBIAS Output Voltage VMICBIAS ILOAD = 1mA
VMICVDD = 1.8V, MBIAS = 0
1.48
1.52
1.56
VMICVDD = 3V, MBIAS = 0
2.15
2.2
2.25
10
Load Regulation
ILOAD = 1mA to 2MA, MBIAS = 0
0.6
Line Regulation
VAVDD =1.8V, VMICVDD =1.65V to 1.95V, MBIAS = 0
1.55
f = 217Hz, VRIPPLE = 100mVP-P
f = 10kHz, VRIPPLE = 100mVP-P
100
A-weighted
9.5
Power-Supply Rejection
Ratio
PSRR
Noise Voltage
V
V/A
mV/V
dB
90
μVRMS
LINE INPUT
Full-Scale Input
Line Input Level Adjust
8
VIN
AVLINE
AVLINE = 0dB
1.0
VP-P
LIGL/LIGR = 0x00
22.8
23.9
24.9
LIGL/LIGR = 0x01
20.7
21.9
22.9
LIGL/LIGR = 0x02
18.9
20
20.9
LIGL/LIGR = 0x04
14.9
16
16.9
LIGL/LIGR = 0x08
6.9
8
8.9
_______________________________________________________________________________________
dB
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Line Input Mute
Attenuation
CONDITIONS
MIN
f = 1kHz
Input Resistance
RIN_LINE
AVLINE = +24dB
Total Harmonic
Distortion + Noise
THD+N
VIN = 0.1VP-P, f = 1kHz
TYP
MAX
100
UNITS
dB
20
k
-74
dB
AUXIN INPUT
Input DC Voltage Range
AUXIN Input Resistance
RIN
AUXEN = 1
0
AUXEN = 1, 0V VAUXIN 0.738
10
0.738
40
V
M
JACK DETECT
JACKSNS High
Threshold
SHDN = 1
0.92 x
0.95 x
0.98 x
VMICBIAS VMICBIAS VMICBIAS
SHDN = 0
0.95 x
VMICVD
VTH1
JACKSNS Low
Threshold
0.06 x
D
SHDN = 1
0.17 x
VMICBIAS VMICBIAS VMICBIAS
SHDN = 0
0.08 x
VMICVDD
VMICVDD
VTH2
JACKSNS Sense
Voltage
VSENSE
SHDN = 0
JACKSNS Sense
Resistance
RSENSE
SHDN = 0
JACKSNS Deglitch
Period
t GLITCH
1.9
0.10 x
2.3
12
Headphone Sense
Threshold
V
V
V
3.1
k
300
ms
8
90
dB
1-BIT SPDM OUTPUT
Dynamic Range
(Note 5)
DR
Output Operational
Range
f S = 48kHz, A-weighted, 0kHz to 20kHz,
AV VOL = +0dB; master or slave mode, TA = +25°C
0dB signal 1’s density
25
75
%
-60
0
dB
DIGITAL SIDETONE (MODE = 1 IIR Voice Mode Only)
Sidetone Gain Adjust
Range
Voice Path Phase Delay
AV STGA
PDLY
Differential output mode
MIC input to headphone
output, f = 1kHz, HP filter
disabled
f S = 8kHz
2.2
f S = 16kHz
1.1
ms
_______________________________________________________________________________________
9
MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
fMCLK
MCLK Input Duty Cycle
Maximum MCLK Input
Jitter
For any LRCLK sample rate
10
60
Prescaler = /1 mode
40
60
/2 or /4 modes
30
70
Maximum allowable RMS for performance limits
100
ps
LRCLK Sample Rate
(Note 10)
DHF = 0
8
48
DHF = 1
48
96
LRCLK Average
Frequency Error (Master
and Slave Modes)
(Note 11)
FREQ1 mode = 0x8 to 0xF
0
0
PCLK = 192x, 256x, 384x, 512x, 768x, and 1024x
0
0
-0.025
+0.025
FREQ1 mode = Any clock other than above
Rapid lock mode
2
7
Nonrapid lock mode
12
25
LRCLK PLL Lock Time
Any allowable LRCLK and
PCLK rate, slave mode
LRCLK Acceptable
Jitter for Maintaining
PLL Lock
Allowable LRCLK period change from nominal for
slave PLL mode at any allowable LRCLK and PCLK
rates
±100
Soft-Start/Stop Time
%
kHz
%
ms
ns
10
ms
12.288
MHz
CRYSTAL OSCILLATOR
Frequency
Fundamental mode only
Maximum Crystal ESR
Input Leakage Current
100
I IH, I IL
X1, TA = +25°C
-1
+1
μA
Input Capacitance
CX1, C X2
4
pF
Maximum Load
Capacitor
CL1, CL2
45
pF
DIGITAL INPUT (MCLK)
Input High Voltage
Input Low Voltage
Input Leakage Current
VIH
1.2
V
VIL
I IH, I IL
TA = +25°C
-1
Input Capacitance
0.6
V
+1
μA
10
pF
DIGITAL INPUTS (SDINS1, BCLKS1, LRCLKS1)
Input High Voltage
VIH
Input Low Voltage
VIL
0.7
x VDVDDS1
0.3
x VDVDDS1
Input Hysteresis
Input Leakage Current
Input Capacitance
10
V
200
I IH, I IL
TA = +25°C
-1
mV
+1
10
______________________________________________________________________________________
V
μA
pF
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SDA, SCL, DIN, SCLK, CS, MODE, SDINS2, BCLKS2, LRCLKS2)
Input High Voltage
VIH
Input Low Voltage
VIL
0.7
x VDVDD
V
0.3
x VDVDD
Input Hysteresis
200
Input Leakage Current
I IH, I IL
TA = +25°C
-1
Input Capacitance
V
mV
+1
10
μA
pF
DIGITAL INPUTS (DIGMICDATA)
Input High Voltage
VIH
Input Low Voltage
VIL
0.65
x VDVDD
V
0.35
x VDVDD
Input Hysteresis
100
Input Leakage Current
I IH, I IL
TA = +25°C
-35
Input Capacitance
V
mV
+35
10
μA
pF
CMOS DIGITAL OUTPUTS (BCLKS1, LRCLKS1, SDOUTS1)
Output Low Voltage
VOL
Output High Voltage
VOH
I OL = 3mA
I OH = 3mA
0.4
V
VDVDDS1
- 0.4
V
CMOS DIGITAL OUTPUTS (BCLKS2, LRCLKS2, SDOUTS2)
Output Low Voltage
VOL
Output High Voltage
VOH
I OL = 3mA
I OH = 3mA
0.4
V
VDVDD
- 0.4
V
CMOS DIGITAL OUTPUTS (DOUT)
Output Low Voltage
VOL
I OL = 1mA, CS = DVDD
Output High Voltage
VOH
I OH = 1mA, CS = DVDD
0.4
V
VDVDD
- 0.4
V
Output Low Current
I OL
MODE = DVDD, DOUT = 0, TA = +25°C
-1
+1
μA
Output High Current
IOH
MODE = DVDD, DOUT = DVDD, TA = +25°C
-1
+1
μA
0.4
V
CMOS DIGITAL OUTPUTS (DIGMICCLK, SPDMDATA, SPDMCLK)
Output Low Voltage
VOL
I OL = 1mA
Output High Voltage
VOH
I OH = 1mA
VDVDD
- 0.4
V
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Current
IOH
VOUT = VDVDD, TA = +25°C
Output Low Voltage
VOL
I OL = 3mA
-1
+1
μA
0.2
x VDVDD
V
______________________________________________________________________________________
11
MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL MICROPHONE TIMING CHARACTERISTICS (VDVDD = 1.8V)
DIGMICCLK Frequency
fMICCLK
fMCLK = 12.288MHz
MICCLK = 00
1.536
MICCLK = 01
2.048
MICCLK = 10
64f S
MHz
DIGMICDATA to
DIGMICCLK Setup Time
t SU,MIC
Either clock edge
20
ns
DIGMICDATA to
DIGMICCLK Hold Time
tHD,MIC
Either clock edge
0
ns
SPDM TIMING CHARACTERISTICS
SPDMCLK Frequency
SPDMCLK to
SPDMDATA Delay Time
f SPDMCLK fMCLK = 12.288MHz
SPDMCLK = 00
1.536
SPDMCLK = 01
2.048
SPDMCLK = 10
3.072
Rising edge SPDMCLK
Minimum, fMCLK = 20MHz
to right-channel valid
SPDMDATA and falling
tDLY,SPDM
edge SPDMCLK to leftchannel valid
Maximum, fMCLK = 10MHz
SPDMDATA
MHz
15
ns
65
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 0, VDVDD = 1.8V)
BCLK Cycle Time
tBCLKS
75
ns
BCLK High Time
tBCLKH
TA = +25°C
30
ns
BCLK Low Time
tBCLKL
TA = +25°C
30
ns
BCLK or LRCLK Rise
and Fall Time
tR, tF
Master operation, CL = 15pF
7
ns
SDIN or LRCLK to BCLK
Setup Time
t SU
20
ns
SDIN or LRCLK to BCLK
Hold Time
tHD
5
ns
SDOUT Delay Time from
BCLK Rising Edge
tDLY
CL = 30pF
0
40
ns
2048
kHz
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 1, Figure 3, VDVDD = 1.8V)
TDM Clock Frequency
1/tCLK
TDM mode (TDM = 1)
128
TDM Clock Time High
tCLKH
TDM mode (TDM = 1), TA = +25°C
220
ns
TDM Clock Time Low
tCLKL
TDM mode (TDM = 1), TA = +25°C
220
ns
TDM Short-Sync Setup
Time
12
t SYNCSET
Short TDM mode (TDM = 1, FSW = 0), master mode
(MAS = 1)
Short TDM mode (TDM = 1, FSW = 0), slave mode
(MAS = 0)
200
ns
20
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
TDM Short Sync Hold
Time
TDM Short Sync Tx Data
Delay
CONDITIONS
MIN
Short TDM mode (TDM = 1, FSW = 0), master mode
(MAS = 1)
tSYNCHOLD
t SYNCTX
TYP
MAX
UNITS
200
ns
Short TDM mode (TDM = 1, FSW = 0), slave mode
(MAS = 0)
20
Short TDM mode (TDM = 1, FSW = 0)
12
ns
TDM Long Sync Start
Delay
tCLKSYNC Long TDM mode (TDM = 1, FSW = 1)
3.4
ns
TDM Long Sync End
Time Setup
t ENDSYNC Long TDM mode (TDM = 1, FSW = 1)
51
ns
TDM Data Delay from
Clock
tCLKTX
TDM mode (TDM = 1)
TDM High-Impedance
State Setup from Data
tHIZOUT
TDM mode (TDM = 1)
TDM Rx Data Setup
Time
t SETUP
TDM mode (TDM = 1)
20
ns
TDM Rx Data Hold Time
tHOLD
TDM mode (TDM = 1)
20
ns
40
ns
120
ns
I2C TIMING CHARACTERISTICS (VDVDD = 1.65V)
Serial-Clock Frequency
f SCL
0
Bus Free Time Between
STOP and START
Conditions
tBUF
1.3
μs
tHD,STA
0.6
μs
Hold Time (Repeated)
START Condition
400
kHz
SCL Pulse-Width Low
tLOW
1.3
μs
SCL Pulse-Width High
tHIGH
0.6
μs
Setup Time for a
Repeated START
Condition
t SU,STA
0.6
μs
Data Hold Time
tHD,DAT
Data Setup Time
RPU,SDA = 475
0
900
ns
t SU,DAT
100
SDA and SCL Receiving
Rise Time
tR
(Note 12)
20 +
0.1CB
ns
300
ns
SDA and SCL Receiving
Fall Time
tF
(Note 12)
20 +
0.1CB
300
ns
SDA Transmitting Fall
Time
tF
RPU,SDA = 475 (Note 12)
20 +
0.1CB
250
ns
Setup Time for STOP
Condition
t SU,STO
0.6
______________________________________________________________________________________
μs
13
MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Bus Capacitance
CB
Pulse Width of
Suppressed Spike
t SP
CONDITIONS
MIN
TYP
0
MAX
UNITS
400
pF
50
ns
SPI TIMING CHARACTERISTICS
Minimum SCLK Clock
Period
tCP
40
ns
Minimum SCLK PulseWidth Low
tCL
18
ns
Minimum SCLK PulseWidth High
tCH
18
ns
Minimum CS Setup
Time
tCSS
20
ns
Minimum CS Hold Time
tCSH
20
ns
Minimum CS PulseWidth High
tCSW
20
ns
Minimum DIN Setup Time
tDS
5
ns
Minimum DIN Hold Time
tDH
5
ns
Minimum Output Data
Propagation Delay
tDO
9
ns
Minimum Output Data
Enable Time
tDEN
5
ns
Minimum Output Data
Disable Time
tDZ
5
ns
CL = 50pF
The MAX9880A is 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by
design.
Note 3: Clocking all zeros into the DAC. Master mode. Differential headphone mode.
Note 4: DAC performance measured at headphone outputs.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 6: Performance measured using microphone inputs, unless otherwise stated.
Note 7: Performance measured using line inputs.
Note 8: Performance measured using line inputs to line outputs.
Note 9: Performance measured using DAC. fMCLK = 12.288MHz, fLRCLK = 48kHz, unless otherwise stated.
Note 10: LRCLK can be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios can exhibit some fullscale performance degradation compared to synchronous integer-related MCLK/LRCLK ratios.
Note 11: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock
rate.
Note 12: CB is in pF.
Note 2:
14
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
-20
3kHz
1kHz
-60
-30
-40
-50
3kHz
-60
-40
-50
-70
-70
-80
-80
-90
-90
-100
-100
10
20
30
20Hz
-90
-100
0
50
40
20Hz
1kHz
6kHz
-60
-80
20Hz
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
-20
-70
10
20
30
40
50
60
0
10
20
30
50
40
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
-20
-30
-20
-30
1kHz
-60
6kHz
-70
THD+N (dB)
THD+N (dB)
-50
-40
1kHz
-50
-60
6kHz
-80
20Hz
-90
-100
0
10
20
30
40
50
-40
-50
6kHz
-80
20Hz
-90
-90
-100
-100
60
1kHz
-60
-70
-70
-80
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 16Ω
BTL MODE
-10
-30
-40
MAX9880A toc06
-20
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
-10
0
MAX9880A toc05
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
-10
0
MAX9880A toc04
0
0
10
20
30
40
20Hz
0
50
10
20
30
40
50
60
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
-72
-74
-70
-74
-76
-80
-82
-84
20mW
-85
5mW
-78
THD+N (dB)
THD+N (dB)
-80
-90
100
1000
FREQUENCY (Hz)
10,000
-78
-80
5mW
-82
-84
20mW
-86
-86
-88
-88
20mW
-90
-90
10
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
-72
-76
5mW
MAX9880A toc09
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
-75
-70
MAX9880A toc07
-70
MAX9880A toc08
THD+N (dB)
1kHz
THD+N (dB)
THD+N (dB)
THD+N (dB)
-40
0
THD+N (dB)
0
-10
-30
-30
-50
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 16Ω
BTL MODE
-10
MAX9880A toc02
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
DIFFERENTIAL MODE
-20
0
MAX9880A toc01
0
-10
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc03
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
10
100
1000
FREQUENCY (Hz)
10,000
10
100
1k
10k
100k
FREQUENCY (Hz)
______________________________________________________________________________________
15
MAX9880A
Typical Operating Characteristics
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
-74
-74
-80
-82
-84
-76
-78
-80
5mW
-82
20mW
20mW
-86
-88
100
1k
10k
100k
-82
20mW
-86
-90
-90
10
5mW
-80
-88
-88
-90
-78
-84
-84
-86
10
100
1k
10k
10
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
-20
-20
-30
3kHz
-50
1kHz
-60
-70
THD+N (dB)
-40
-40
-50
6kHz
1kHz
-60
-80
20Hz
-90
10
15
6kHz
-60
20Hz
-90
-100
-100
5
0
1kHz
-50
-80
20Hz
-90
-100
-40
-70
-70
-80
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
CAPACITORLESS MODE
-10
-30
THD+N (dB)
-30
MAX9880A toc15
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
CAPACITORLESS MODE
-10
0
MAX9880A toc14
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
CAPACITORLESS MODE
-20
0
MAX9880A toc13
0
-10
5
0
10
5
0
15
10
15
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
1mW
-70
THD+N (dB)
THD+N (dB)
-75
1mW
-75
-80
-80
-85
-80
20mW
-85
-90
-85
-90
100
5mW
-75
5mW
5mW
10
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
CAPACITORLESS MODE
-65
-70
-70
1000
FREQUENCY (Hz)
10,000
MAX9880A toc18
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 32Ω
CAPACITORLESS MODE
-65
-60
MAX9880A toc17
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
CAPACITORLESS MODE
-65
-60
MAX9880A toc16
-60
16
-74
THD+N (dB)
5mW
-78
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
-72
-76
THD+N (dB)
THD+N (dB)
-76
THD+N (dB)
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
-72
-70
MAX9880A toc11
fMCLK = 12.288MHz
fLRCLK = 48kHz
RLOAD = 16Ω
DIFFERENTIAL MODE
-72
-70
MAX9880A toc10
-70
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc12
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
THD+N (dB)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
-90
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
______________________________________________________________________________________
10k
100k
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
-50
-45
-50
1kHz
-65
-70
20Hz
3kHz
-75
-30
-60
-65
-70
20Hz
6kHz
-75
-40
-60
-80
-80
-85
-90
-90
2
4
6
8
10
12
6kHz
-70
-85
0
1kHz
-50
-80
-90
20Hz
-100
0
2
4
6
8
10
12
0
3
6
9
15
12
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
-74
-75
-80
-70
THD+N (dB)
THD+N (dB)
1mW
-78
-80
5mW
-82
-86
-85
5mW
-75
-80
-84
5mW
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
-65
-76
-70
MAX9880A toc24
1mW
-72
-60
MAX9880A toc23
fMCLK = 13MHz
fLRCLK = 8kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
-65
-70
MAX9880A toc22
-60
THD+N (dB)
-20
THD+N (dB)
-60
fMCLK = 12.288MHz
fLRCLK = 96kHz
RLOAD = 32Ω
SINGLE-ENDED MODE
-10
1kHz
-55
THD+N (%)
-55
0
MAX9880A toc20
-45
THD+N (%)
-40
MAX9880A toc19
-40
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc21
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
20mW
-85
-88
-90
1000
10,000
10
100
1k
10k
10
100k
100
1k
100k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE-IN TO HEADPHONE)
1kHz
-20
-30
-40
-50
1kHz
6kHz
20Hz
-60
-40
-50
-60
-80
-80
-90
-90
10
20
30
POWER OUT (mW)
40
50
5mW
0.1
0.01
20mW
0.001
-100
0
1
20Hz
-70
-70
LINE-IN PREAMP = +18dB
RLOAD = 32I
BTL MODE
6kHz
THD+N (%)
THD+N (dB)
-30
10
MAX9880A toc27
-20
-10
MAX9880A toc26
LINE IN PREAMP = +18dB
RLOAD = 32Ω
DIFFERENTIAL MODE
-10
0
MAX9880A toc25
0
THD+N (dB)
-90
-90
100
10
0
10
20
30
POWER OUT (mW)
40
50
10
100
1000
10,000
100,000
FREQUENCY (Hz)
______________________________________________________________________________________
17
MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
THD+N (dB)
0.1
5mW
40
IIR
-60
-70
100
1000
10,000
100,000
5
0
10
100
1000
10,000
1
10
1000
100
FREQUENCY (Hz)
HEADPHONE LOAD (Ω)
POWER OUT vs. HEADPHONE LOAD
POWER OUT vs. HEADPHONE LOAD
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
10
5
10
0
10
100
1000
0.1
0.01
5
0
fMCLK = 13MHz
fLRCLK = 8kHz
MICPRE = 0dB
VIN = 1VP-P
1
15
MAX9880A toc33
10
THD+N (%)
15
fMCLK = 12.288MHz
fLRCLK = 48kHz
THD+N = < 0.1%
SINGLE-ENDED MODE
20
POWER OUT (mW)
20
25
MAX9880A toc32
fMCLK = 12.288MHz
fLRCLK = 48kHz
THD+N = < 0.1%
CAPACITORLESS MODE
1
20
FREQUENCY (Hz)
25
0.001
1
10
100
1000
10
100
1000
10,000
HEADPHONE LOAD (Ω)
HEADPHONE LOAD (Ω)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
10
THD+N (%)
0.1
fMCLK = 13MHz
fLRCLK = 8kHz
MICPRE = +30dB
VIN = 32mVP-P
0
VRIPPLE = 100mV
-20
-40
1
PSRR (dB)
fMCLK = 13MHz
fLRCLK = 8kHz
MICPRE = +20dB
VIN = 100VP-P
1
100
MAX9880A toc34
10
MAX9880A toc35
POWER OUT (mW)
FIR
-90
MAX9880A toc31
10
25
10
-80
20mW
30
15
0.01
0.001
35
MAX9880A toc36
THD+N (%)
-50
fMCLK = 12.288MHz
fLRCLK = 48kHz
THD+N = < 0.1%
DIFFERENTIAL MODE
45
POWER OUT (mW)
fMCLK = 13MHz
fLRCLK = 8kHz
0dBFS
-40
POWER OUT vs. HEADPHONE LOAD
50
MAX9880A toc29
LINE-IN PREAMP = +0dB
RLOAD = 32I
BTL MODE
1
-30
MAX9880A toc28
10
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO LINE OUT)
MAX9880A toc30
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE-IN TO HEADPHONE)
THD+N (%)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
0.1
-60
-80
0.01
0.01
0.001
10
100
1000
FREQUENCY (Hz)
18
10,000
-100
-120
0.001
10
100
1000
FREQUENCY (Hz)
10,000
1
10
100
1k
FREQUENCY (Hz)
______________________________________________________________________________________
10k
100k
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
-20
20
0
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-40
PSRR (dB)
-60
-80
-70
-100
-80
-120
-90
-100
-120
1
10
100
1k
10k
100k
-140
1
10
100
1k
10k
100k
5k
0
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
0
0
NI = 6000
0
-20
-40
-60
-80
AMPLITUDE (dB)
-20
AMPLITUDE (dB)
-20
20
-40
-60
-80
-40
-60
-80
-100
-100
-100
-120
-120
-120
-140
-140
-140
0
5k
10k
15k
20k
MAX9880A toc42
FREQ1 = 0xA
MAX9880A toc41
20
MAX9880A toc40
20
5k
0
10k
15k
0
20k
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 12.288MHz, fLRCLK = 96kHz
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 12.288MHz, fLRCLK = 96kHz
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
20
MAX9880A toc43
20
0
NI = 6000
0
0
-20
-40
-60
-80
AMPLITUDE (dB)
-20
AMPLITUDE (dB)
-20
20
MAX9880A toc44
AMPLITUDE (dB)
-60
-100
-80
AMPLITUDE (dB)
-40
-40
-60
-80
-40
-60
-80
-100
-100
-100
-120
-120
-120
-140
-140
-140
0
5k
10k
FREQUENCY (Hz)
15k
20k
MAX9880A toc45
PSRR (dB)
FFT, DAC TO HEADPHONE,
0dBFS, MCLK = 13MHz, LRCLK = 8kHz
MAX9880A toc38
VRIPPLE = 100mV
fMCLK = 12.288MHz
fLRCLK = 48kHz
-20
0
MAX9880A toc37
0
-10
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICBIAS)
MAX9880A toc39
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MIC TO ADC)
0
5k
10k
FREQUENCY (Hz)
15k
20k
0
5k
10k
15k
20k
FREQUENCY (Hz)
______________________________________________________________________________________
19
MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
PLL MODE
0
0
-60
-80
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
-120
-140
-140
-140
0
5k
10k
15k
20k
0
5k
10k
15k
0
20k
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, MICROPHONE TO ADC,
0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
FFT, MICROPHONE TO ADC,
-60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
FFT, MICROPHONE TO ADC,
0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
AMPLITUDE (dB)
-40
-60
-80
-60
-80
-100
-120
-120
-140
0
-20
-40
-100
1000
2000
3000
4000
-40
-60
-80
-100
-120
-140
-140
0
MAX9880A toc51
-20
AMPLITUDE (dB)
-20
20
MAX9880A toc50
0
MAX9880A toc49
0
0
1000
2000
3000
0
4000
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, MICROPHONE TO ADC,
-60dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
FFT, MICROPHONE TO ADC,
0dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
FFT, MICROPHONE TO ADC,
-60dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
0
20
0
-20
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
-140
AMPLITUDE (dB)
-20
AMPLITUDE (dB)
-20
0
5k
10k
FREQUENCY (Hz)
15k
20k
-40
-60
-80
-100
-120
-140
-140
0
MAX9880A toc54
NI = 6000
MAX9880A toc52
20
MAX9880A toc53
AMPLITUDE (dB)
-20
AMPLITUDE (dB)
-40
-100
20
PLL MODE
0
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
-20
20
MAX9880A toc47
20
MAX9880A toc46
20
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
MAX9880A toc48
FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
AMPLITUDE (dB)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
0
5k
10k
FREQUENCY (Hz)
15k
20k
0
5k
10k
FREQUENCY (Hz)
______________________________________________________________________________________
15k
20k
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
-20
AMPLITUDE (dB)
-40
-60
-80
-60
-80
-140
40k
60k
80k
100k
120k
-40
-60
DVFLT = 4
-140
20k
0
-20
-80
-120
-120
fLRCLK = 8kHz
0
-100
-100
DVFLT = 0
DVFLT = 3
-40
-100
0
20k
40k
60k
80k
100k
120k
0
100
200
300
400
500
600
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
ADC IIR HIGHPASS FILTER FREQUENCY
RESPONSE, MODE = 0
DAC IIR/FIR LOWPASS FILTER FREQUENCY
RESPONSE (8kHz)
DAC FIR LOWPASS FILTER FREQUENCY
RESPONSE (96kHz)
fLRCLK = 8kHz
0
20
MODE = 1
20
0
MAX9880A toc60
AVFLT = 0
MAX9880A toc58
20
MAX9880A toc59
AMPLITUDE (dB)
-20
20
AMPLITUDE (dB)
FREQ1 = 0xA
0
DAC IIR HIGHPASS FILTER FREQUENCY
RESPONSE, MODE = 0
MAX9880A toc56
0
MAX9880A toc55
20
WIDEBAND FFT, DAC TO HEADPHONE,
-60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc57
WIDEBAND FFT, DAC TO HEADPHONE,
0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
0
-40
-60
-20
AMPLITUDE (dB)
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
AVFLT = 3
MODE = 0
-40
-60
-20
-40
-60
AVFLT = 4
-80
-100
-100
-100
0
100
200
300
400
500
600
3000
3200
3400
3600
3800
20k
4000
24k
28k
32k
36k
40k
44k
FREQUENCY (Hz)
ADC IIR/FIR LOWPASS FILTER FREQUENCY
RESPONSE (8kHz)
SHUTDOWN TO FULL OPERATION
(DIFFERENTIAL)
SHUTDOWN TO FULL OPERATION
(SE CLICKLESS)
-20
SCL (1V/div)
SCL (1V/div)
MAX9880A toc61
MODE = 1
0
48k
MAX9880A toc63
FREQUENCY (Hz)
MAX9880A toc62
FREQUENCY (Hz)
20
SPKLP (500mV/div)
MODE = 0
-40
SPKL (500mV/div)
AMPLITUDE (dB)
-80
-80
-60
-80
-100
3000
3200
3400
3600
3800
4000
TIME (4ms/div)
TIME (40ms/div)
FREQUENCY (Hz)
______________________________________________________________________________________
21
MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN,
CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB,
AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
SHUTDOWN TO FULL OPERATION
(SE FAST TURN ON)
SOFT-START ADC
TIME (4ms/div)
TIME (1ms/div)
TIME (200μs/div)
TOTAL HARMONIC DISTORTION + NOISE
vs. MCLK FREQUENCY, 0dBFS
DYNAMIC RANGE vs. MCLK FREQUENCY
-40
-50
-60
-70
VIN = -60dBFS
fLRCLK = 48kHz
PLL MODE
110
DYNAMIC RANGE (dB)
-30
-80
MAX9880A toc68
fLRCLK = 48kHz
PLL MODE
-20
THD+N (dB)
120
MAX9880A toc67
0
-10
MAX9880A toc66
SPKL-R (500mV/div)
SCL (1V/div)
MAX9880A toc65
SCL (1V/div)
SPKL/R (500mV/div)
SCL (1V/div)
MAX9880A toc64
FULL OPERATION TO SHUTDOWN
SPKLP (500mV/div)
100
90
80
70
-90
-100
60
10
100
10
100
MCLK FREQUENCY (MHz)
MCLK FREQUENCY (MHz)
LINE INPUT RESISTANCE
vs. GAIN SETTING
AUX CODE vs. INPUT VOLTAGE
200
150
100
50
25,000
20,000
15,000
10,000
5000
0
-5000
0
-10
-5
0
5
10
15
GAIN SETTING (dB)
22
MAX9880A toc70
250
30,000
AUX CODE (SIGNED DECIMAL)
MAX9880A toc69
300
INPUT RESISTANCE (kΩ)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
20
25
-0.4 -0.2
0
0.2
0.4
0.6
0.8
1.0
INPUT VOLTAGE (V)
______________________________________________________________________________________
1.2
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
TOP VIEW
(BUMP SIDE DOWN)
+
MAX9880A
1
2
3
4
5
6
7
8
DGND
X1
X2
IRQ
MODE
AVDD
PREG
AGND
DVDD
SDA/DIN
SCL/SCLK
CS
DOUT
REF
MICVDD
MICBIAS
SDINS2
LRCLKS2
BCLKS2
N.C.
N.C.
REG
MICLN/
DIGMICCLK
MICRP/
SPDMDATA
MCLK
SDOUTS2
SDINS1
N.C.
JACKSNS/
AUX
N.C.
MICLP/
DIGMICDATA
MICRN/
SPDMCLK
LRCLKS1
BCLKS1
PVDD
LOUTP
ROUTP
PGND
LOUTL
LINL
SDOUTS1
DVDDS1
PVDD
LOUTN
ROUTN
PGND
LOUTR
LINR
A
B
C
D
E
F
LOUTR
LOUTL
PGND
N.C.
ROUTP
ROUTN
LOUTN
LOUTP
N.C.
N.C.
PVDD
TOP VIEW
DVDDS1
WLP
36 35 34 33 32 31 30 29 28 27 26 25
SDOUTS1 37
24 LINR
SDINS1 38
23 LINL
LRCLKS1 39
22 JACKSNS/AUX
BCLKS1 40
21 MICRN/SPDMCLK
MCLK 41
20 MICRP/SPDMDATA
MAX9880A
SDOUTS2 42
19 MICLP/DIGMICDATA
SDINS2 43
18 MICLN/DIGMICCLK
LRCLKS2 44
17 MICBIAS
BCLKS2 45
16 MICVDD
DVDD 46
15 AGND
*EP
+
DGND 47
14 N.C.
N.C. 48
10 11 12
N.C.
9
PREG
8
REF
X2
7
AVDD
X1
6
IRQ
SCL/SCLK
*EP = EXPOSED PAD
5
MODE
4
DOUT
3
CS
2
SDA/DIN
13 REG
1
THIN QFN
(6mm × 6mm)
______________________________________________________________________________________
23
MAX9880A
Pin Configurations
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Pin Description
PIN
NAME
FUNCTION
TQFN-EP
WLP
1
B2
SDA/DIN
I2C Serial-Data Input/Output (MODE = 0). Connect a pullup resistor to DVDD for
full output swing. SPI (MODE = 0) compatible serial-data input (MODE = 1).
2
B3
SCL/SCLK
I2C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing.
SPI-compatible serial clock input (MODE = 1).
3
A2
X1
Crystal Oscillator Input. Connect load capacitor and one terminal of the crystal
to this pin. Acceptable input frequency range: 10MHz to 30MHz.
4
A3
X2
Crystal Oscillator Output. Connect load capacitor and second terminal of the
crystal to this pin.
5
B4
CS
SPI-Compatible, Active-Low Chip-Select Input
24
6
B5
DOUT
SPI-Compatible Serial-Data Output
7
A5
MODE
I2C/SPI Mode Select Input (MODE = 0 for I2C mode, MODE = 1 for SPI mode)
8
A4
IRQ
9
A6
AVDD
Hardware Interrupt Output. IRQ can be programmed to go low when bits in the
status register 0x00 are set. Read status register 0x00 to clear IRQ once set.
Repeat faults have no effect on IRQ until it is cleared by reading the I2C status
register 0x00. Connect a 10k pullup resistor to DVDD for full output swing.
Analog Power Supply. Bypass to AGND with a 1μF capacitor.
10
B6
REF
Converter Reference. Bypass to AGND with a 2.2μF capacitor (1.23V nominal).
11, 14,
28, 33,
35, 48
C4, D4,
C5, D6
N.C.
No Connection. Connect to GND.
12
A7
PREG
13
C6
REG
Positive Internal Regulated Supply. Bypass to AGND with a 1μF capacitor (1.6V
nominal).
PREG/2 Voltage Reference. Bypass to AGND with a 1μF capacitor (0.8V
nominal)
15
A8
AGND
16
B7
MICVDD
Microphone Bias Power Supply. Bypass to AGND with a 1μF capacitor.
Analog Ground
17
B8
MICBIAS
Low-Noise Microphone Bias. Connect a 2.2k to 470 resistor to the positive
output of the microphone.
18
C7
MICLN/
DIGMICCLK
19
D7
MICLP/
DIGMICDATA
20
C8
MICRP/
SPDMDATA
21
D8
MICRN/
SPDMCLK
22
D5
JACKSNS/AUX
Left Negative Differential Microphone Input. AC-couple a microphone with a series
1μF capacitor. Also digital microphone clock output. Selectable through I2C.
Left Positive Differential Microphone Input. AC-couple a microphone with a
series 1μF capacitor. Also digital microphone data input. Selectable through
I2C.
Right Positive Differential Microphone Input or SPDM Data Output. AC-couple a
microphone with a series 1μF capacitor. Selectable through I2C.
Right Negative Differential Microphone Input. AC-couple a microphone with a
series 1μF capacitor. Selectable through I2C.
Jack Sense. Detects the presence or absence of a jack. See the Headset
Detection section. When used as an auxiliary ADC input, AUX is used to
measure DC voltages.
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
PIN
NAME
FUNCTION
TQFN-EP
WLP
23
E8
LINL
Left-Line Input. AC-couple analog audio signal to LINL with a 1μF capacitor.
24
F8
LINR
Right-Line Input. AC-couple analog audio signal to LINR with a 1μF capacitor.
25
F7
LOUTR
Right-Line Output
26
E7
LOUTL
Left-Line Output
27
E6, F6
PGND
Headphone Power Ground
29
E5
ROUTP
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
30
F5
ROUTN
Negative Right-Channel Headphone Output. Unused in capacitorless and
single-ended mode.
31
F4
LOUTN
Negative Left-Channel Headphone Output. Common headphone return in
Capacitorless mode. Unused in single-ended mode.
32
E4
LOUTP
Positive Left-Channel Headphone Output
34
E3, F3
PVDD
Headphone Power Supply. Bypass to PGND with a 1μF capacitor.
36
F2
DVDDS1
37
F1
SDOUTS1
38
D3
SDINS1
39
E1
LRCLKS1
40
E2
BCLKS1
41
D1
MCLK
42
D2
SDOUTS2
43
C1
SDINS2
44
C2
LRCLKS2
45
C3
BCLKS2
46
B1
DVDD
47
A1
DGND
—
—
EP
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1μF
capacitor.
S1 Digital Audio Serial-Data ADC Output
S1 Digital Audio Serial-Data DAC Input
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample
rate clock and determines whether the audio data on SDINS1 is routed to the left
or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the
MAX9880A is in slave mode and an output when in master mode.
Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
S2 Digital Audio Serial-Data ADC Output
S2 Digital Audio Serial-Data DAC Input
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample
rate clock and determines whether the audio data on SDINS2 is routed to the left
or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the
MAX9880A is in slave mode and an output when in master mode.
Digital Power Supply. Supply for the digital core and I2C/SPI interface. Bypass to
DGND with a 1.0μF capacitor.
Digital Ground
Exposed Pad. Connect the exposed thermal pad to AGND.
______________________________________________________________________________________
25
MAX9880A
Pin Description (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Detailed Description
The MAX9880A is a low-power stereo audio codec
designed for portable applications requiring minimum
power consumption.
The stereo playback path accepts digital audio through
flexible digital audio interfaces compatible with I2S,
TDM, and left-justified audio signals. The MAX9880A
can process two simultaneous digital input streams that
can be mixed digitally. The primary interface is intended for voiceband applications, while the secondary
interface can be used for stereo audio data. An oversampling sigma-delta DAC converts the mixed incoming digital data stream to analog audio and outputs
through the stereo headphone amplifier and stereo-line
outputs. The headphone amplifier can be configured in
differential, single-ended, and capacitorless output
modes.
The stereo record path has two differential analog
microphone inputs with selectable gain. The microphones are powered by an integrated microphone bias.
The MAX9880A can retask the left analog microphone
input to accept data from up to two digital microphones. An oversampling sigma-delta ADC converts
the microphone signals and outputs the digital bit
stream over the digital audio interface. An auxiliary
ADC allows accurate measurements of DC voltages by
retasking the right audio ADC. DC voltages can be
read through the registers.
The MAX9880A also includes two line inputs. These
inputs allow a stereo single-ended signal to be gain
adjusted and then recorded by the ADCs and output by
the headphone amplifier and line output amplifiers. A
jack detection function allows the detection of headphone, microphone, and headset jacks. Insertion and
removal events can be programmed to trigger a hardware interrupt and flag a register bit.
The MAX9880A’s flexible clock circuitry utilizes a programmable clock divider and a digital PLL to allow the
DAC and ADC to operate at maximum dynamic range
for all combinations of master clock (MCLK) and sample rate (LRCLK) without consuming extra supply current. Any master clock between 10MHz and 60MHz is
supported as are all sample rates from 8kHz to 48kHz
for the record path and 8kHz to 96kHz for the playback
path. Master and slave modes are supported for maximum flexibility.
The right analog microphone input can be retasked to
output SPDM data. Integrated digital filtering provides a
range of notch and highpass filters for both the playback and record paths to limit undesirable low-frequency signals and GSM transmission noise. The digital
filtering provides attenuation of out-of-band energy by
over 70dB, eliminating audible aliasing. A digital
sidetone function allows audio from the record path to
be summed into the playback path after digital filtering.
I2C/SPI Registers
Forty internal registers program and report the status of
the MAX9880A. Table 1 lists all of the registers, their
addresses, and power-on-reset states. Registers
0x00–0x03 are read-only while all of the other registers
are read/write. Write zeros to all unused bits in the register table when updating the register, unless otherwise
noted. All bits in the read-only registers are not programmable. Read operations of unused bits return zero.
I2C Slave Address
The MAX9880A is preprogrammed with a slave
address of 0x20 or 0010000. The address is defined as
the 7 most significant bits (MSBs) followed by the
read/write bit. Set the read/write bit to 1 to configure the
MAX9880A to read mode. Set the read/write bit to zero
to configure the MAX9880A to write mode. The address
is the first byte of information sent to the MAX9880A
after the START (S) condition.
Table 1. Register Map
REGISTER
B7
B6
B5
B4
CLD
SLD
ULK
—
—
—
B3
REGISTER
POR
ADDRESS
STATE
(SEE NOTE)
B2
B1
B0
*
*
JDET
—
0x00
—
R
—
—
—
—
0x01
—
R
R/W
STATUS
Status
Jack Status
JKSNS[1:0]
AUX High
AUX[15:8]
0x02
—
R
AUX Low
AUX[7:0]
0x03
—
R
0x04
0x00
R/W
0x05
0x00
R/W
Interrupt Enable
ICLD
ISLD
0
0
IULK
0
0*
0*
IJDET
0
SYSTEM CLOCK CONTROL
System Clock
26
PSCLK
FREQ1
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
POR
ADDRESS
STATE
(SEE NOTE)
R/W
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High
PLL1
NI1[14:8]
Stereo Audio Clock Control Low
NI1[7:1]
RLK1/NI1[0]
0x06
0x00
R/W
0x07
0x00
R/W
DAI1 CONFIGURATION
Interface Mode A
MAS1
WCI1
BCI1
Interface Mode B
DL1
SEL1
SDOEN1
Time-Division Multiplex
SLOTL1
DLY1
HIZOFF1
TDM1
FSW1
SDIEN1 DMONO1
SLOTR1
0
BSEL1
SLOTDLY1[3:0]
0x08
0x00
R/W
0x09
0x00
R/W
0x0A
0x00
R/W
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High
PLL2
NI2[14:8]
Stereo Audio Clock Control Low
0x0B
0x00
R/W
RLK2/NI2[0]
0x0C
0x00
R/W
WS2
0x0D
0x00
R/W
0x0E
0x00
R/W
SLOTDLY2[3:0]
0x0F
0x00
R/W
MIXDAR
0x10
0x00
R/W
0x11
0x00
R/W
0x12
0x00
R/W
0x13
0x00
R/W
0x14
0x42
R/W
R/W
NI2[7:1]
DAI2 CONFIGURATION
Interface Mode A
MAS2
WCI2
BCI2
DLY2
HIZOFF2
Interface Mode B
DL2
SEL2
SDOEN2
SDIEN2
DHF
Time-Division Multiplex
SLOTL2
SLOTR2
TDM2
FSW2
BSEL2
DIGITAL MIXERS
DAC-L/R Mixer
MIXDAL
DIGITAL FILTERING
Codec Filters
MODE
AVFLT
DCB
DVFLT
SPDM OUTPUTS
Configuration
SPDMCLK
Input
SPDML
SPDMR
0
0
MIXSPDML
0
0
MIXSPDMR
REVISION ID
Rev ID location (replicated for
SPI mode)
REV
LEVEL CONTROL
Sidetone
DSTS
0
DVST
0x15
0x00
SDACA
0x16
0x00
R/W
VDACA
0x17
0x00
R/W
AVLG
AVL
0x18
0x00
R/W
AVRG
AVR
0x19
0x00
R/W
LIGL
0x1A
0x00
R/W
Stereo DAC Level
0
SDACM
0
0
Voice DAC Level
0
VDACM
Left ADC Level
0
0
Right ADC Level
0
0
Left-Line Input Level
0
LILM
0
0
Right-Line Input Level
0
LIRM
0
0
Left Volume Control
0
VOLLM
Right Volume Control
0
VOLRM
Left-Line Output Level
0
LOLM
0
0
Right-Line Output Level
0
LORM
0
0
0x1F
0x00
R/W
Left Microphone Gain
0
PALEN
PGAML
0x20
0x00
R/W
Right Microphone Gain
0
PAREN
PGAMR
0x21
0x00
R/W
VDACG
LIGR
VOLL
VOLR
LOGL
LOGR
0x1B
0x00
R/W
0x1C
0x00
R/W
0x1D
0x00
R/W
0x1E
0x00
R/W
CONFIGURATION
Input
Microphone
MXINL
MXINR
MICCLK
DIGMICL DIGMICR
AUXCAP AUXGAIN AUXCAL
0
Mode
DSLEW
VSEN
ZDEN
0
0
Jack Detect
JDETEN
0
JDWK
0
0
0
0
AUXEN
0x22
0x00
R/W
MBIAS
0x23
0x00
R/W
HPMODE
0
JDEB
0x24
0x00
R/W
0x25
0x00
R/W
______________________________________________________________________________________
27
MAX9880A
Table 1. Register Map (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 1. Register Map (continued)
REGISTER
REGISTER
POR
ADDRESS
STATE
(SEE NOTE)
B7
B6
B5
B4
B3
B2
B1
B0
R/W
Enable
LNLEN
LNREN
LOLEN
LOREN
DALEN
DAREN
ADLEN
ADREN
0x26
0x00
R/W
System Shutdown
SHDN
0
0
0
XTEN
XTOSC
0
0
0x27
0x00
R/W
0xFF
0x42
R/W
POWER MANAGEMENT
REVISION ID
Revision ID
REV
*Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Device Status
Bits in status register 0x00 are set when an alert condition exists. All bits in status register 0x00 are automatically cleared upon a read operation of the register and
are set again if the condition remains or occurs following the read of this register.
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon reading the status
register and are set the next time the event occurs.
Registers 0x02 and 0x03 report the DC level applied to
AUX. See the ADC section for more details.
Table 2. Status Register
REGISTER
Status
Jack Status
B7
B6
B5
B4
CLD
SLD
ULK
—
—
—
JKSNS[1:0]
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
*
*
JDET
—
0x00
—
—
—
—
B3
0x01
AUX High
AUX[15:8]
0x02
AUX Low
AUX[7:0]
0x03
*Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
28
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
FUNCTION
CLD
Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC. To resolve a clip condition in
the signal path, the DAC gain settings and analog input gain settings should be lowered. As the CLD bit does
not indicate where the overload has occurred, identify the source by lowering gains individually.
SLD
Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through
all intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final
value. SLD is also set when soft start or stop is complete.
ULK
Digital PLL Unlock Flag. Indicates that the digital audio PLL has become unlocked and digital signal data is not
reliable.
JDET
Headset Configuration Change Flag. JDET reports changes in JKSNS[1:0]. Changes to JKSNS[1:0] are
debounced before setting JDET. The debounce period is programmable using the JDEB bits.
JKSNS reports the status of the JACKSNS pin when JDETEN = 1. JKSNS is not debounced and should be
interpreted according to the following information.
JKSNS[1:0]
JKSNS[1:0]
DESCRIPTION
00
JACKSNS is below VTH2.
01
JACKSNS is between VTH1 and VTH2.
10
Invalid.
11
JACKSNS is above VTH1.
DESCRIPTION
JKMONO
1
Headphone impedance < 8.
Auxiliary Input Measurement. AUX is a 16-bit signed two’s complement number representing the voltage
measured at JACKSNS/AUX. Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After
reading the value, set AUXCAP to 0.
AUX
Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
AUX Voltage = 0.738V k k = AUX value when AUXGAIN = 1. See AUXGAIN for details on determining the value of k, the calibration
constant.
______________________________________________________________________________________
29
MAX9880A
Table 3. Status Register Bits
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Hardware Interrupts
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00.
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
Table 4. Interrupt Enable
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
ICLD
ISLD
IULK
0
0*
0*
IJDET
0
0x04
REGISTER
Interrupt Enable
*Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Clock Control
flexibility in both the MCLK and LRCLK frequencies
and can be used in either master or slave mode.
• Exact integer mode: Common MCLK frequencies
(12MHz, 13MHz, 16MHz, and 19.2MHz) can be programmed to operate in exact integer mode for both
8kHz and 16kHz sample rates. In these modes, the
MCLK and LRCLK rates are selected by using the
FREQ1 bits instead of the NI high, NI low, and PLL control bits.
• PLL mode: When operating in slave mode, a PLL
can be enabled to lock onto externally generated
LRCLK signals that are not integer related to PCLK.
Prior to enabling the interface, program NI to the
nearest desired ratio and set the NI[0] = 1 to enable
the PLL’s rapid lock mode. If NI[0] = 0, then NI is
ignored and PLL lock time is slower.
The MAX9880A can work with a master clock (MCLK)
supplied from any system clock within the 10MHz to
60MHz range. Internally the MAX9880A requires a
10MHz to 20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9880A.
The MAX9880A can support any sample rate from 8kHz
to 48kHz for the digital audio path DAI1 (DAC and
ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity
DAC path), including all common sample rates (8kHz,
16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To
accommodate a wide range of system architectures,
the MAX9880A supports three main clocking modes:
• Normal mode: This mode uses a 15-bit clock
divider coefficient to set the sample rate relative to
the prescaled MCLK input (PCLK). This allows high
Table 5. System and Audio Clock Registers
REGISTER
B7
B6
0
0
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
SYSTEM CLOCK CONTROL
System Clock
PSCLK
FREQ1
0x05
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High
PLL1
Stereo Audio Clock Control Low
NI1[14:8]
NI1[7:1]
0x06
RLK1/NI1[0]
0x07
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
PLL2
NI2[14:8]
NI2[7:1]
0x0B
RLK2/NI2[0]
0x0C
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
30
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
PSCLK
MAX9880A
Table 5. System and Audio Clock Registers (continued)
FUNCTION
MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz.
10 = Select if MCLK is between 20MHz and 40MHz.
11 = Select if MCLK is greater than 40MHz.
Exact Integer Modes. Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or
16kHz sample rates.
FREQ1
FREQ1[3:0]
0x00
PCLK (MHz)
LRCLK (kHz)
PCLK/LRCLK
0x1–0x7
Reserved
Reserved
Reserved
0x8
0x9
12
12
8
16
1500
750
0xA
0xB
13
13
8
16
1625
812.5
0xC
0xD
16
16
8
16
2000
1000
0xE
0xF
19.2
19.2
8
16
2400
1200
Normal or PLL mode
Modes 0x8 to 0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK
ratio cannot be guaranteed, use PLL mode instead.
PLL1/PLL2
PLL Mode Enable
0 = (Valid for slave and master mode) The frequency of LRCLK is set by the NI divider bits. In master mode,
the MAX9880A generates LRCLK using the specified divide ratio. In slave mode, the MAX9880A expects
an LRCLK as specified by the divide ratio.
1 = (Valid for slave mode only) A digital PLL locks on to any externally supplied LRCLK signal.
RLK1/RLK2
Rapid Lock Mode. To enable rapid lock mode set NI_ to the nearest desired ratio and set RLK_ = 1 before
enabling the interface.
NI1/NI2
Normal Mode LRCLK Divider. When PLL = 0, the frequency of LRCLK is determined by NI. See Table 6 for
common NI values.
For LRCLK = 8kHz to 48kHz operation (DHF = 0 for DAI2):
NI = (65,536 x 96 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
f PCLK = Prescaled internal MCLK frequency (PCLK)
For LRCLK > 50kHz operation (DHF = 1 for DAI2):
NI = (65,536 x 48 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
f PCLK = Prescaled internal MCLK frequency (PCLK)
______________________________________________________________________________________
31
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 6. Common NI Values
(DAI1, DAI2 for DHF = 0)
LRCLK (kHz)
PCLK
(MHz):
(Note: Any
PCLK from
10MHz to
20MHz
with any
LRCLK
7.8kHz to
50kHz
can be
used.)
(DAI2 for DHF = 1)
8
11.025
12
16
22.05
24
32
44.1
48
64
88.2
96
10
13A9
1B18
1D7E
2752
3631
3AFB
4EA5
6C61
75F7
4EA5
6C61
75F7
11
11E0
18A2
1ACF
23BF
3144
359F
477E
6287
6B3E
477E
6287
6B3E
11.2896
116A
1800
1A1F
22D4
3000
343F
45A9
6000
687D
45A9
6000
687D
12
1062
1694
1893
20C5
2D29
3127
4189
5A51
624E
4189
5A51
624E
12.288
1000
160D
1800
2000
2C1A
3000
4000
5833
6000
4000
5833
6000
13
F20
14D8
16AF
1E3F
29AF
2D5F
3C7F
535F
5ABE
3C7F
535F
5ABE
14
E0B
135B
1511
1C16
26B5
2A21
382C
4D6A
5443
382C
4D6A
5443
15
D1B
1210
13A9
1A37
2420
2752
346E
4841
4EA5
346E
4841
4EA5
16
C4A
10EF
126F
1893
21DE
24DD
3127
43BD
49BA
3127
43BD
49BA
16.9344
B9C
1000
116A
1738
2000
22D4
2E71
4000
45A9
2E71
4000
45A9
17
B91
FF0
1159
1721
1FE0
22B2
2E43
3FC1
4564
2E43
3FC1
4564
18
AEC
F0E
1062
15D8
1E1B
20C5
2BB1
3C36
4189
2BB1
3C36
4189
18.432
AAB
EB3
1000
1555
1D66
2000
2AAB
3ACD
4000
2AAB
3ACD
4000
19
A59
E43
F86
14B2
1C85
1F0B
2964
390B
3E16
2964
390B
3E16
20
9D5
D8C
EBF
13A9
1B18
1D7E
2752
3631
3AFB
2752
3631
3AFB
Note: Values in bold and underline are exact integers that provide maximum full-scale performance.
Digital Audio Interface
The MAX9880A’s dual digital audio interface supports a
wide range of operating modes to ensure maximum
compatibility. See Figures 1 to 5 for timing diagrams. In
master mode, the MAX9880A outputs LRCLK and
BCLK, while in slave mode they are inputs. When operating in master mode, BCLK can be configured in a
number of ways to ensure compatiblity with other audio
devices.
The MAX9880A has two sets of digital audio interface
pins, S1 and S2, that can be connected to one of two
digital audio paths, DAI1 or DAI2.
DAI1: Digital Audio Path 1 Operation
• DAC path with DR of 90dB and ADC path with DR of
82dB
32
• DAC path connectable to either S1 or S2
• ADC path connectable to either S1 or S2
• 8kHz to 48kHz sample rates
• I2S and TDM-compatible modes
• Voice filters or audio filter modes
DAI2: Digital Audio Path 2 Operation
•
•
•
•
High-fidelity DAC path with DR of 96dB
DAC path connectable to either S1 or S2
8kHz to 96kHz sample rates
I2S and TDM-compatible modes
• Audio FIR filters
• No ADC clock control from DAI2 sample clock and
no voice filter modes available in DAI2
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
REGISTER
B7
B6
Interface Mode A
MAS1
WCI1
Interface Mode B
DL1
SEL1
B5
B4
B3
B2
BCI1
DLY1
HIZOFF1
TDM1
SDOEN1
SDIEN1
DMONO1
B1
B0
FSW1
0
REGISTER
ADDRESS
(SEE NOTE)
DAI1 CONFIGURATION
Time-Division Multiplex
SLOTL1
SLOTR1
BSEL1
0x08
0x09
SLOTDLY1[3:0]
0x0A
DAI2 CONFIGURATION
Interface Mode A
MAS2
WCI2
BCI2
DLY2
HIZOFF2
Interface Mode B
DL2
SEL2
SDOEN2
SDIEN2
DHF
Time-Division Multiplex
SLOTL2
SLOTR2
TDM2
FSW2
BSEL2
SLOTDLY2[3:0]
WS2
0x0D
0x0E
0x0F
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
MAS1/2
Master Mode
0 = The MAX9880A operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9880A operates in master mode with LRCLK and BCLK configured as outputs.
WCI1/2
LRCLK Invert (TDM1/2 = 0)
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
BCI1/2
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK. SDOUT transitions immediately after the rising edge
of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK. SDOUT transitions immediately after the falling
edge of BCLK.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
DLY1/2
Delay Mode. DLY1/2 have two different functions in TDM and non-TDM mode.
In Non-TDM Mode (TDM1/TDM2 = 0): The functionality is as follows:
1 = The most significant bit of an audio word is latched at the second BCLK edge after the LRCLK transition.
0 = The most significant bit of an audio word is latched at the first BCLK edge after the LRCLK transition.
In TDM Mode (TDM1/TDM2 = 1): The functionality is as follows:
1 = The HOLD time on the SDOUT output is increased to be greater than 150ns.
0 = The HOLD time on the SDOUT output is the default (greater than 20ns but less than 150ns).
HIZOFF1/2
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9880A,
allowing SDOUT to be shared by other devices.
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9880A.
Note: High-impedance mode is intended for use when TDM = 1.
______________________________________________________________________________________
33
MAX9880A
Table 7. Digital Audio Interface Registers
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 7. Digital Audio Interface Registers (continued)
BITS
FUNCTION
TDM1/2
TDM Mode Select
1 = Enables time-division multiplex mode and configures the audio interface to accept PCM data.
0 = Disables time-division multiplex mode. LRCLK signal polarity indicates left and right audio.
FSW1/2
Frame Sync Width
1 = Frame sync pulse extended to the width of the entire 16-bit first slot 0 data word (TDM1/TDM2 = 1 only;
SLOTDLY[0] must be 0 when FSW is set to 1).
0 = Frame sync pulse is 1 bit wide.
WS2
Word Size
0 = The number of bits per input data word sample is 16 bits, and at least 16 BCLKs per input word are required.
1 = The number of bits per input data word sample is 18 bits, and at least 18 BCLKs per input word transfer is
required. These control bits are only recognized when TDM1/TDM2 are cleared to 0.
Data Loop. Enabling of these bits provides a bridge from one DAI interface to the other. Data format looping could
occur in both directions simultaneously.
BIT
DL1/2
DESCRIPTION
DL1 = 0
Normal operation
DL1 = 1, SEL2 = 1
Enables SDINS1 to SDOUTS2.
DL2 = 0
Normal operation
DL2 = 1, SEL1 = 0
Enables SDINS2 to SDOUTS1.
Note: The LRCLKS1 and LRCLKS2 interfaces must be identical.
Set the SEL1/2, SDOEN1/2, and SDIEN1/2 bits as shown in the table below to connect the S1 and S2 pins to the
DAI1 and DAI2 paths in the MAX9880A.
SETTING
SEL1/SEL2
SEL1
SEL2
SDIEN1
SDOEN1
SDIEN2
SDOEN2
Connect S1 pins to DAI1 (DAC and ADC)
0
X
1
1
0
0
Connect S2 pins to DAI1 (DAC and ADC)
1
0
1
0
0
1
Connect S1 pins (DAC only) to DAI2
1
0
0
0
1
0
Connect S2 pins (DAC only) to DAI2
X
1
0
0
1
0
Connect S1 pins (DAC and ADC) to DAI1,
connect S2 to DAI2 (DAC only)
0
1
1
1
1
0
Connect S2 pins (DAC and ADC) to DAI1,
connect S1 to DAI2 (DAC only)
1
0
1
0
1
1
SDOEN1/2
SDOUT Enable
1 = Serial-data output enabled on S1/S2 pins.
0 = Serial-data output disabled on S1/S2 pins.
SDIEN1/2
SDIN Enable
1 = Serial-data input to DAI1/2 audio path enabled.
0 = Serial-data input to DAI1/2 audio path disabled.
DMONO1
Mono Playback Mode
0 = Stereo data input on DAI1 path is processed separately.
1 = Stereo data input on DAI1 path is mixed to a single channel and routed to both the left and right DAC.
When operating in mono voice mode (MODE = 1), stereo data may still be input through DAI1 path and optionally
mixed using DMONO = 1.
34
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
FUNCTION
BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL =
010, unless sharing the bus with multiple devices.
BSEL
BSEL1/2
DESCRIPTION
000
Off (BCLK output held low)
001
64x LRCLK (192x internal clock divided by 3)
010
48x LRCLK (192x internal clock divided by 4)
011
128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.)
100
PCLK/2
101
PCLK/4
110
PCLK/8
111
PCLK/16
TDM Slot Select. Selects the time slot to use for left/right data according to the following information when
operating in time-division multiplex mode.
SLOT
SLOTL1/2
SLOTR1/2
DESCRIPTION
00
Time slot 1
01
Time slot 2
10
Time slot 3
11
Time slot 4
Slot Data Delay (SLOTDLY1/SLOTDLY2)
In TDM Mode: Configures the data delay for each slot in TDM mode of operation according to the following
information.
In Non-TDM Mode (TDM = 0): SLOTDLY[1:0] does not have any effect.
SLOTDLY1/2[3:0]
0xxx
SLOTDLY1/2
DHF
DESCRIPTION
Data for slot 4 begins immediately.
1xxx
Data for slot 4 delayed 1 BCLK cycle.
x0xx
Data for slot 3 begins immediately.
x1xx
Data for slot 3 delayed 1 BCLK cycle.
xx0x
Data for slot 2 begins immediately.
xx1x
Data for slot 2 delayed 1 BCLK cycle.
xxx0
Data for slot 1 begins immediately.
xxx1
Data for slot 1 delayed 1 BCLK cycle (not valid when FSW = 1).
DAC High Sample Rate Mode (DHF) (Valid only for DAI2 audio path)
1 = LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
0 = LRCLK is less than 50kHz. 8x FIR interpolation filter used.
______________________________________________________________________________________
35
MAX9880A
Table 7. Digital Audio Interface Registers (continued)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
AUDIO MASTER MODES:
LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
LRCLK
RIGHT
LEFT
1/fS
RELATIVE TO PCLK (SEE NOTE)
D15
SDOUT
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ)
BCLK
20ns (min)
CONFIGURED BY BSEL
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
RIGHT
LEFT
LRCLK
1/fS
RELATIVE TO PCLK (SEE NOTE)
D15
SDOUT
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ)
BCLK
20ns (min)
CONFIGURED BY BSEL
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
RIGHT
LEFT
LRCLK
1/fS
RELATIVE TO PCLK (SEE NOTE)
SDIN
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ)
BCLK
20ns (min)
CONFIGURED BY BSEL
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2S: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
RIGHT
LEFT
LRCLK
1/fS
RELATIVE TO PCLK (SEE NOTE)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
BCLK
20ns (min)
CONFIGURED BY BSEL
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
7ns (typ)
7ns (typ)
RIGHT
LEFT
LRCLK
1/fS
RELATIVE TO PCLK (SEE NOTE)
D15
SDOUT
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ)
BCLK
20ns (min)
SDIN
5ns (min)
CONFIGURED BY BSEL
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED-DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) PERIOD OF MCLK PLUS THE
INTERNAL DELAY. FOR EXAMPLE: IF fPCLK = 12.288MHz, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode
36
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MAX9880A
AUDIO SLAVE MODES:
LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0
LEFT
LRCLK
RIGHT
1/fS
20ns (min)
D15
SDOUT
0ns (min)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30ns (min)
BCLK
20ns (min)
75ns (min)
5ns (min)
SDIN
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
LEFT
LRCLK
RIGHT
1/fS
0ns (min)
20ns (min)
D15
SDOUT
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30ns (min)
BCLK
20ns (min)
75ns (min)
5ns (min)
SDIN
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
LEFT
LRCLK
RIGHT
1/fS
0ns (min)
20ns (min)
SDIN
D15
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30ns (min)
BCLK
20ns (min)
75ns (min)
5ns (min)
SDIN
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2S: TDM = 0, WCI = 0, BCI = 0, DLY = 1, SLOTDLY = 0
RIGHT
LEFT
LRCLK
1/fS
0ns (min)
20ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
30ns (min)
BCLK
20ns (min)
75ns (min)
5ns (min)
SDIN
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
RIGHT
LEFT
LRCLK
1/fS
20ns (min)
D15
SDOUT
0ns (min)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30ns (min)
BCLK
20ns (min)
SDIN
5ns (min)
75ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. Digital Audio Interface Audio Slave Mode
______________________________________________________________________________________
37
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
VOICE (TDM/PCM) MASTER MODES:
TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
7ns (typ)
7ns (typ)
LRCLK
1/fS
200ns
SDOUT
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
BCLK
20ns (min)
SDIN
0ns (min)
CONFIGURED BY BSEL
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00
7ns (typ)
7ns (typ)
LRCLK
1/fS
200ns
SDOUT
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
BCLK
20ns (min)
SDIN
0ns (min)
CONFIGURED BY BSEL
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0
7ns (typ)
7ns (typ)
LRCLK
1/fS
200ns
SDOUT
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
BCLK
20ns (min)
SDIN
0ns (min)
CONFIGURED BY BSEL
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 3. Digital Audio Interface Voice Master Mode
38
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MAX9880A
VOICE (TDM/PCM) SLAVE MODES:
TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
LRCLK
1/fS
20ns
SDOUT
0ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
7ns (typ)
BCLK
20ns (min)
SDIN
75ns (min)
0ns (min)
30ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
LRCLK
1/fS
20ns
SDOUT
0ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
7ns (typ)
BCLK
20ns (min)
SDIN
75ns (min)
0ns (min)
30ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0
LRCLK
1/fS
20ns
SDOUT
0ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
BCLK
20ns (min)
SDIN
75ns (min)
0ns (min)
30ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 4. Digital Audio Interface Voice Slave Mode
Table 8. Digital Mixers
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
DIGITAL MIXERS
DAC-L/R Mixer
MIXDAL
MIXDAR
0x10
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Digital Mixers (MIXDAL/MIXDAR). Selects and mixes the audio source(s) for the DACs according to the
information below.
MIXDAL/MIXDAR
MIXDAL/
MIXDAR
SOURCE
1xxx
DAI1 left-channel data
x1xx
DAI1 right-channel data
xx1x
DAI2 left-channel data
xxx1
DAI2 right-channel data
______________________________________________________________________________________
39
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Digital Filtering
The MAX9880A incorporates both IIR (voice) and FIR
(audio) digital filters to accomodate a wide range of
audio sources. The IIR fiilters provide over 70dB of
stopband attenuation as well as selectable highpass filters. The FIR filters provide low power consumption and
are linear phase to maintain stereo imaging.
Table 9. Digital Filtering Register
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
DIGITAL FILTERING
Codec Filters
MODE
AVFLT
DCB
DVFLT
0x11
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
MODE
Digital Audio Filter Mode. Selects the filtering mode for the DAI1 DAC and ADC signal paths.
0 = IIR voice filters
1 = FIR audio filters
AVFLT
ADC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
DCB
DVFLT
1 = DC-blocking filter for DAI2 enabled.
0 = DC-blocking filter for DAI2 disabled.
DAC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
Table 10. IIR Highpass Digital Filters
FILTER TYPE
VALID SAMPLE
RATE (kHz)
0x1
Elliptical
16
256Hz
0x2
Butterworth
16
500Hz
No
0x3
Elliptical
8
256Hz
Yes
0x4
Butterworth
8
500Hz
No
0x5
Butterworth
8 to 24
f S/240
No
CODE
0x0
0x6 to 0x7
40
HIGHPASS CORNER FREQUENCY
217Hz NOTCH
Disabled
Reserved
______________________________________________________________________________________
Yes
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
REGISTER
B7
Configuration
SPDMCLK
Input
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
SPDML
SPDMR
0
0
0
0
0x12
B6
MIXSPDML
MIXSPDMR
0x13
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
The MAX9880A supports stereo PDM outputs. The PDM
signals consist of PDM data outputs (SPDMDATA) and a
clock output (SPDMCLK). The mixer at the input to the
PDM modulators allows a mix/mux of the audio digital data
stream from the digital audio ports SDINS1 and SDINS2.
Figure 5 shows the SPDM interface timing diagram.
SPDMCLK
tDLY, DSD
tDLY, DSD
SPDMDATA
LEFT CH
RIGHT CH
LEFT CH
RIGHT CH
Figure 5. SPDM Timing Diagram
BITS
SPDMCLK
SPDML/SPDMR
FUNCTION
SPDM Clock Rate (SPDMCLK)
00 = SPDMCLK is set to PCLK/8.
01 = SPDMCLK is set to PCLK6.
10 = SPDMCLK is set to PCLK/4.
11 = Reserved
0 = Disables SPDM data.
1 = Enables SPDM data.
SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following
information.
MIXDSPDM/
MIXSPDMR
MIXSPDML/MIXSPDMR
SOURCE
1xxx
DAI1 left-channel data
x1xx
DAI1 right-channel data
xx1x
DAI2 left-channel data
xxx1
DAI2 right-channel data
______________________________________________________________________________________
41
MAX9880A
Table 11. SPDM Output Registers
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Digital Gain Control
The MAX9880A includes gain adjustment for the playback and record paths. Independent gain adjustment is
provided for the two record channels. Sidetone gain
adjustment is also provided to set the sidetone level relative to the playback level.
Table 12. Digital Gain Registers
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
LEVEL CONTROL
Sidetone
DSTS
0
DVST
0
0
0x15
Stereo DAC Level
0
SDACM
SDACA
0x16
Voice DAC Level
0
VDACM
VDACG
VDACA
0x17
Left ADC Level
0
0
AVLG
AVL
0x18
Right ADC Level
0
0
AVRG
AVR
0x19
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
42
FUNCTION
DSTS
Digital Sidetone Source Mixer
00 = No sidetone selected.
01 = Left ADC
10 = Right ADC
11 = Left and right ADC
DVST
Digital Sidetone Level Control. All gain settings are relative to the ADC input voltage.
Differential Headphone Output Mode
SETTING
GAIN (dB)
SETTING
GAIN (dB)
SETTING
0x00
Off
0x0B
-20
0x16
0x01
0
0x0C
-22
0x17
0x02
-2
0x0D
-24
0x18
0x03
-4
0x0E
-26
0x19
0x04
-6
0x0F
-28
0x1A
0x05
-8
0x10
-30
0x1B
0x06
-10
0x11
-32
0x1C
0x07
-12
0x12
-34
0x1D
0x08
-14
0x13
-36
0x1E
0x09
-16
0x14
-38
0x1F
0x0A
-18
0x15
-40
—
Capacitorless and Single-Ended Headphone Output Mode
SETTING
GAIN (dB)
SETTING
GAIN (dB)
SETTING
0x00
Off
0x0B
-25
0x16
0x01
-5
0x0C
-27
0x17
0x02
-7
0x0D
-29
0x18
0x03
-9
0x0E
-31
0x19
0x04
-11
0x0F
-33
0x1A
0x05
-13
0x10
-35
0x1B
0x06
-15
0x11
-37
0x1C
0x07
-17
0x12
-39
0x1D
0x08
-19
0x13
-41
0x1E
0x09
-21
0x14
-43
0x1F
0x0A
-23
0x15
-45
—
______________________________________________________________________________________
GAIN (dB)
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
—
GAIN (dB)
-47
-49
-51
-53
-55
-57
-59
-61
-63
-65
—
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
MAX9880A
Table 12. Digital Gain Registers (continued)
FUNCTION
SDACM/
VDACM
DAC Mute Enable
0 = No mute
1 = Mute
VDACG
DAC Gain
00 = 0dB
01 = +6dB
10 = +12dB
11 = +18dB
Note: VDACG is only used when MODE = 0. If MODE = 1, then the DAC gain is always 0dB.
DAC Level Control. VDACA/SDACA works in all modes.
VDACA/SDACA
SETTING
GAIN (dB)
SETTING
0x0
0
0x8
GAIN (dB)
-8
0x1
-1
0x9
-9
0x2
-2
0xA
-10
0x3
-3
0xB
-11
0x4
-4
0xC
-12
0x5
-5
0xD
-13
0x6
-6
0xE
-14
0x7
-7
0xF
-15
ADC Gain Control. Applies the specified gain to the digital ADC paths according to the following
information.
SETTING
AVLG/AVRG
GAIN (dB)
0x0
0
0x1
+6
0x2
+12
0x3
+18
ADC Left/Right Level Control
AVL/AVR
SETTING
GAIN (dB)
SETTING
GAIN (dB)
0x0
+3
0x8
-5
0x1
+2
0x9
-6
0x2
+1
0xA
-7
0x3
0
0xB
-8
0x4
-1
0xC
-9
0x5
-2
0xD
-10
0x6
-3
0xE
-11
0x7
-4
0xF
-12
______________________________________________________________________________________
43
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Line Inputs
Playback Volume
The MAX9880A include one pair of single-ended line
inputs. When enabled the line inputs connect directly to
the headphone amplifier and line outputs and can be
optionally connected to the ADC for recording.
The MAX9880A incorporates volume and mute control to
allow level control for the playback audio path. Program
registers 0x1C and 0x1D to set the desired volume.
Line Output Level
The MAX9880A incorporates gain and mute control to
allow level control for the line outputs.
Table 13. Line Input Registers
REGISTER
B3
B2
B1
REGISTER
ADDRESS
(SEE NOTE)
B7
B6
B5
B4
B0
Left-Line Input Level
0
LILM
0
0
LIGL
0x1A
Right-Line Input Level
0
LIRM
0
0
LIGR
0x1B
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
LILM/LIRM
FUNCTION
Line Input Left/Right Playback Mute
0 = Line input is connected to the headphone amplifiers.
1 = Line input is disconnected from the headphone amplifiers.
Line Input Left/Right Gain
LIGL/LIGR
SETTING
GAIN (dB)
SETTING
GAIN (dB)
0x0
+24
0x8
+8
0x1
+22
0x9
+6
0x2
+20
0xA
+4
0x3
+18
0xB
+2
0x4
+16
0xC
0
0x5
+14
0xD
-2
0x6
+12
0xE
-4
0x7
+10
0xF
-6
Table 14. Playback Volume Registers
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
Left Volume Control
0
VOLLM
VOLL
0x1C
Right Volume Control
0
VOLRM
VOLR
0x1D
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
VOLLM/
VOLRM
44
FUNCTION
Left/Right Playback Mute. VOLLM and VOLRM mute both the DAC and line input audio signals.
0 = Audio playback is unmuted.
1 = Audio playback is muted.
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
MAX9880A
Table 14. Playback Volume Registers (continued)
FUNCTION
Left/Right Playback Volume. VOLL and VOLR control the playback volume for both the DAC and line input
audio signals.
VOLL/VOLR
SETTING
GAIN (dB)
SETTING
GAIN (dB)
SETTING
GAIN (dB)
0x00
+9
0x0E
-2
0x1C
-39
0x01
+8.5
0x0F
-3
0x1D
-43
0x02
+8
0x10
-5
0x1E
-47
0x03
+7.5
0x11
-7
0x1F
-51
0x04
+7
0x12
-9
0x20
-55
0x05
+6.5
0x13
-11
0x21
-59
0x06
+6
0x14
-13
0x22
-63
0x07
+5
0x15
-15
0x23
-67
0x08
+4
0x16
-17
0x24
-71
0x09
+3
0x17
-19
0x25
-75
0x0A
+2
0x18
-23
0x26
-79
0x0B
+1
0x19
-27
0x27
-81
0x0C
0
0x1A
-31
0x28 to 0x3F
MUTE
0x0D
-1
0x1B
-35
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the singleended and capacitorless modes, the actual gain is 5dB lower. Assuming LOGL/LOGR = 0dB, line output
gain is 6dB lower.
Table 15. Output Line-Level Registers
REGISTER
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
B7
B6
B5
B4
Left-Line Output Level
0
LOLM
0
0
LOGL
0x1E
Right-Line Output Level
0
LORM
0
0
LOGR
0x1F
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
LOLM/LORM
FUNCTION
Left/Right Line Output Mute. LOLM and LORM mute both the DAC and line input audio signals.
0 = Line output is unmuted.
1 = Line output is muted.
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Left/Right Line Output Gain. LOGL and LOGR set the line output gain according to the following information.
LOGL/LOGR
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
GAIN (dB)
0
-2
-4
-6
-8
-10
-12
-14
SETTING
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
GAIN (dB)
-16
-18
-20
-22
-24
-26
-28
-30
______________________________________________________________________________________
45
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Microphone Inputs
microphone signals are amplified by two stages of gain
and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable gain amplifier (PGA)
adjustable from 0dB to 20dB in 1dB steps. Zero-crossing detection is included on the PGA to minimize zipper
noise while making gain changes. See Figure 6 for a
detailed diagram of the microphone input structure.
Two differential microphone inputs and a low noise 1.5V
microphone bias for powering the microphones are
provided by the MAX9880A. In typical applications, the
left microphone records a voice signal and the right
microphone records a background noise signal. In
applications that require only one microphone, use the
left microphone input and disable the right ADC. The
MAX9880A
MICBIAS
1.5V
0/20/30dB
VREG
MICLP
PREAMP
MICLN
ADC
L
PGA
0dB TO +20dB
-
0/20/30dB
VREG
MICRP
PREAMP
MICRN
ADC
R
PGA
0dB TO +20dB
Figure 6. Microphone Input Block Diagram
Table 16. Microphone Input Register
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
Left Microphone Gain
0
PALEN
PGAML
0x20
Right Microphone Gain
0
PAREN
PGAMR
0x21
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
PALEN/
PAREN
46
FUNCTION
Left/Right Microphone Preamplifier Gain. Enables the microphone circuitry and sets the preamplifier gain.
00 = Disabled
01 = 0dB
10 = +20dB
11 = +30dB
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
MAX9880A
Table 16. Microphone Input Register (continued)
FUNCTION
Left/Right Microphone Programmable Gain Amplifier
PGAML/
PGAMR
SETTING
GAIN (dB)
SETTING
GAIN (dB)
0x00
+20
0x0B
+9
0x01
+19
0x0C
+8
0x02
+18
0x0D
+7
0x03
+17
0x0E
+6
0x04
+16
0x0F
+5
0x05
+15
0x10
+4
0x06
+14
0x11
+3
0x07
+13
0x12
+2
0x08
+12
0x13
+1
0x09
+11
0x14 to 0x1F
0
0x0A
+10
ADC
The MAX9880A includes 2-bit ADCs. The first ADC is
used to record left-channel microphone and line-input
audio signals. The second ADC can be used to record
right-channel microphone and line-input signals or it
can be configured to accurately measure DC voltages.
When measuring DC voltages both the left and right ADC
must be enabled by setting ADLEN and ADREN in register 0x26. The input to the second ADC is JACKSNS/
AUX and the output is reported in AUX (registers 0x02
and 0x03). Since the audio ADC is used to perform the
measurement, the digital audio interface must be properly configured. If the left ADC is being used to convert
audio, then the DC measurement is performed at the
same sample rate. When not using the left ADC, configure the digital interface for a 48kHz sample rate to
ensure the fastest possible settling time.
To ensure accurate results, the MAX9880A includes
two calibration routines. Calibrate the ADC each time
the MAX9880A is powered on. Calibration settings are
not lost if the MAX9880A is placed in shutdown. When
making a measurement, set AUXCAP to 1 to prevent
AUX from changing while reading the registers.
Setup Procedure
1) Ensure a valid MCLK signal is provided and configure PSCLK appropriately.
2) Choose a clocking mode. The following options are
possible:
a. Slave mode with LRCLK and BCLK signals
provided. The measurement sample rate is
determined by the external clocks.
b. Slave mode with no LRCLK and BCLK signals
provided. Configure the device for normal clock
mode using the NI ratio. Select fS = 48kHz to
allow for the fastest settling times.
c. Master mode with audio. Configure the device
in normal mode using the NI ratio or exact integer mode using FREQ1 as required by the audio
signal.
d. Master mode without audio. Configure the
device in normal mode using the NI ratio. Select
fS = 48kHz to allow for the fastest settling times.
3) Ensure jack sense is disabled.
4) Enable the left and right ADC; take the MAX9880A
out of shutdown.
______________________________________________________________________________________
47
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Offset Calibration Procedure
Perform before the first DC measurement is taken after
applying power to the MAX9880A.
1) Enable the AUX input (AUXEN = 1).
2) Enable the offset calibration (AUXCAL = 1).
3) Wait the appropriate time (see Table 17).
4) Complete calibration (AUXCAL = 0).
Gain Calibration Procedure
Perform the first time a DC measurement is taken after
applying power to the MAX9880A or if the temperature
changes significantly.
1) Enable the AUX input (AUXEN = 1).
2) Start gain calibration (AUXGAIN = 1).
3) Wait the appropriate time (see Table 17).
4) Freeze the measurement results (AUXCAP = 1).
5) Read AUX and store the value in memory to correct
all future measurements (k = (AUX[15:0], k is typically 19,500).
6) Complete calibration (AUXGAIN = AUXCAP = 0).
DC Measurement Procedure
Perform after offset and gain calibration are complete.
1) Enable the AUX input (AUXEN = 1).
2) Wait the appropriate time (see Table 17).
Complete DC Measurement Example
fMCLK = 13MHz, slave mode, BCLK, and LRCLK are
not externally supplied.
1) Configure the digital audio interface for fs = 48kHz
(PSCLK = 01, FREQ1 = 0x0, PLL = 0, NI = 0x5ABE,
MAS = 0).
2) Disable jack sense (JDETEN = 0).
3) Enable the left and right ADC; take the MAX9880A
out of shutdown (ADLEN = ADREN = SHDN = 1).
4) Calibrate the offset:
a. Enable the AUX input (AUXEN = 1).
b. Enable the offset calibration (AUXCAL = 1).
c. Wait 40ms.
d. Complete calibration (AUXCAL = 0).
5) Calibrate the gain:
a. Start gain calibration (AUXGAIN = 1).
b. Wait 40ms.
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and store the value in memory to correct all future measurements (k = (AUX[15:0]).
e. Complete calibration (AUXGAIN = AUXCAP =
AUXEN = 0).
6) Measure the voltage on JACKSNS/AUX.
3) Freeze the measurement results (AUXCAP = 1).
a. Enable the AUX input (AUXEN = 1).
4) Read AUX and correct with the gain calibration value
b. Wait 40ms.
⎛
⎛ AUX[15 : 0] ⎞ ⎞
⎟⎠ ⎟ .
⎜ V AUX = 0. 738 ⎜⎝
k
⎝
⎠
5) Complete measurement (AUXCAP = 0).
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and correct with the gain calibration
value.
e. Complete measurement (AUXCAP = 0).
7) DC measurement is complete.
Table 17. AUX ADC Wait Times
LRCLK (kHz)
48
WAIT TIME (ms)
48
40
44.1
44
32
60
24
80
22.05
90
16
120
12
160
11.025
175
8
240
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
REGISTER
B7
Input
B6
MXINL
B5
B4
MXINR
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
AUXCAP
AUXGAIN
AUXCAL
AUXEN
0x22
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
MXINL/MXINR
FUNCTION
Left/Right ADC Audio Input Mixer
00 = No input selected
01 = Left/right analog microphone
10 = Left/right line input
11 = Left/right analog microphone + line input
Note: If the right line input is disabled, then the left line input is connected to both mixers. Enabling the left
and right digital microphones disables the left and right audio mixer, respectively. See the DIGMICL/
DIGMICR bit description for more details.
AUXCAP
Auxiliary Input Capture
0 = Update AUX with the voltage at JACKSNS/AUX.
1 = Hold AUX for reading.
AUXGAIN
Auxiliary Input Gain Calibration
0 = Normal operation
1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference.
While in this mode, read the AUX register and store the value. Use the stored value as a gain
calibration factor, k, on subsequent readings.
AUXCAL
Auxiliary Input Offset Calibration
0 = Normal operation
1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal
offsets. AUXCAL must remain set for time indicated in Table 17 to guarantee an accurate offset
calibration.
AUXEN
Auxiliary Input Enable
0 = Use JACKSNS/AUX for jack detection.
1 = Use JACKSNS/AUX for DC measurements.
Note: Set MXINR = 00, ADLEN = 1, and ADREN = 1 when AUXEN = 1.
______________________________________________________________________________________
49
MAX9880A
Table 18. ADC Input Register
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Digital Microphone Input
microphone input. The right analog microphone input is
still available to allow a combination of analog and digital microphones to be used. Figure 7 shows the digital
microphone interface timing diagram.
The MAX9880A can accept audio from up to two digital microphones. When using digital microphones, the
left analog microphone input is retasked as a digital
1/fMICCLK
DIGMICCLK
tHD, MIC
tSU, MIC
LEFT
DIGMICDATA
tHD, MIC
tSU, MIC
RIGHT
LEFT
RIGHT
Figure 7. Digital Microphone Timing Diagram
Table 19. Digital Microphone Input Register
REGISTER
B7
Microphone
Grayed boxes = Not used.
B6
MICCLK
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
DIGMICL
DIGMICR
0
0
0
MBIAS
0x23
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
MICCLK
FUNCTION
Digital Microphone Clock
00 = PCLK/8
01 = PCLK/6
10 = 64f S (high jitter clock)
11 = Reserved
Digital Left/Right Microphone Enable
DIGMICL/
DIGMICR
DIGMICL
DIGMICR
LEFT ADC INPUT
RIGHT ADC INPUT
0
0
ADC input mixer
ADC input mixer
0
1
Line input (left analog
microphone unavailable)
Right digital microphone
1
0
Left digital microphone
ADC input mixer
1
1
Left digital microphone
Right digital microphone
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.
MBIAS
50
Microphone Bias Output Voltage
Set MBIAS = 0 for nominal output of 1.52V (VMICVDD = 1.8V)
Set MBIAS = 1 for nominal output of 2.2V (VMICVDD = 3V)
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
and providing information to assist the system controller
in determining the configuration of an inserted plug. If
programmed to do so, upon insertion or removal of a
plug, the IRQ output is asserted (pulled low).
Table 20 shows the registers associated with the jack
detect function in MAX9880A.
Table 20. Jack-Detect Registers
REGISTER
Status
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
POR STATE
R/W
CLD
SLD
ULK
—
—
—
JDET
—
0x00
—
R
Jack Status
JKSNS[1:0]
Interrupt Enable
Jack Detect
—
—
—
—
—
—
0x01
—
R
ICLD
ISLD
IULK
0
0
0
IJDET
0
0x04
0x00
R/W
JDETEN
0
JDWK
0
0
0
0x25
0x00
R/W
JDEB
Grayed boxes = Not used.
Jack Configuration Change Flag (JDET)
1 = Jack configuration has changed.
0 = No change in jack configuration.
JDET reports changes in JKSNS[1:0]. Changes to
JKSNS[1:0] are debounced before setting JDET. The
debounce period is programmable using the JDEB bits.
Jack status register 0x01 is a read-only register that reports
the status of the jack-detect circuitry when enabled.
Jack Sense (JKSNS)
JKSNS[1:0] reports the status of the JACKSNS pin
when JDETEN = 1. JKSNS[1:0] should be interpreted
according to Table 21.
Jack-Detect Interrupt Enable (IJDET)
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. So IJDET must be set to
enable interrupts for jack detect.
Jack-Detect Enable (JDETEN)
Enables the jack-detect circuitry.
Jack-Sense Weak Pullup (JDWK)
Enables a weak internal pullup current for reduced
power loss when the chip is in shutdown or the
MICBIAS is disabled.
JDWK = 0 enables a 2.2kΩ pullup to obtain full jackdetect operation. This mode can be used to detect
insertion and removal of a plug as well as distinguish
between headphone and headset accessories.
JDWK = 1 enables a 4µA pullup current source when
SHDN = 0 or MICBIAS disabled. In this power-saving
configuration, the circuit can detect insertion and
removal of a plug but cannot distinguish between headphone and headset accessories.
The recommended usage follows: Set JDWK = 0 (or set
any bit in the microphone preamplifier gain registers
PALEN[1:0] or PAREN[1:0]). This enables the 2.2kΩ
pullup. Once the jack has been inserted and the type of
accessory determined, set JDWK = 1 to save power.
Once the plug is removed, set JDWK = 0.
Table 21. Jack Sense (JKSNS)
JKSNS[1:0]
DESCRIPTION
00
JACKSNS is below VTH2 (low).
01
JACKSNS is between VTH1 and VTH2 (mid).
10
Invalid.
11
JACKSNS is above VTH1 (high).
______________________________________________________________________________________
51
MAX9880A
Mode Configuration
The MAX9880A includes circuitry to minimize click-andpop during volume changes, detect headsets, and configure the headphone amplifier mode. Both volume
slewing and zero-crossing detection are included to
ensure click-and-pop free volume transitions.
Headset Detection Overview
The MAX9880A contains headset detect circuitry that is
capable of detecting the insertion or removal of a plug
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
LOUTP
GND
MIC
HPR
MICBIAS
HPL
JACKSNS/AUX
ROUTP
MICLP
LOUTN
Figure 8. Typical Configuration for Headset Detection
Table 22. Debounce Time
JDEB
DEBOUNCE (ms)
00
25
01
50
10
100
11
200
Debounce (JDEB)
Configures the JDET debounce time for changes to
JKSNS[1:0] according to Table 22.
For jack plug insertion/removal, the sequence of events
is as follows:
Jack insertion: No jack is present. The MAX9880A has
a power supply and is in low-power sleep mode
(LOUTP/ROUTP are high impedance). When the
JDETEN I 2 C bit is set, the JACKSNS pin has weak
pullups to MICVDD. When a jack is subsequently inserted, JACKSNS should change state (indicated by I2C
bits JKSNS[1:0]), and this causes the IRQ pin to be
pulled low, which can trigger a system wakeup.
Jack present: After an interrupt has been sent to the
system controller, the I2C must indicate unambiguously
that a jack is present when the I2C registers are read.
This is done with the JDET I2C bit, which goes high
when there is a change of state of the JKSNS[1:0] bits.
The MAX9880A jack-detect system monitors the
JACKSNS pin and reports the voltage level as high
52
(> 95% x MICBIAS), mid, or low (< 10% x MICBIAS).
When connected to the microphone pin of the headset
jack, this window comparator allows detection of:
• No headset (high)
• Cellular headset with microphone (high → mid)
• Stereo headset without microphone (high → low)
• Cellular headset button press (mid → low → mid)
• Headset removal (low or mid → high)
Jack removal: A jack is present. All output poles
(headphones/line outs) are assumed driven by a low
impedance amplifier. All input poles (microphones) are
assumed to be biased with a voltage above ground but
below 95% of the MICBIAS voltage. For the MAX9880A
to sense when a jack is removed, the JACKSNS pin
must be connected to the jack in such a way as to
ensure either the JACKSNS pin gets pulled above 95%
of MICBIAS (as would happen if JACKSNS is hooked to
a microphone pole) or it changes state from low to high
or vice versa (as would happen if JACKSNS is hooked
to a ground pole which goes high impedance when the
jack is removed, or is hooked to a regular jack insertion
tab that shorts to ground when the jack is removed).
Subsequently, IRQ is pulled low.
Jack absent: After an interrupt has been sent to the
system controller, the I2C must indicate unambiguously
that a jack is not present when the I2C registers are
read. This is indicated by reading the status of the
JKSNS[1:0] I2C read bits.
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
SHDN
MICBIAS
JDWK
0
—
0
0
—
0
—
0
—
JACK ACTION
IRQ TOGGLES?
JKSNS
FROM
TO
FROM
TO
IJDET = 1
IJDET = 0
None
Headset
11
01
Yes
No
0
None
Headphone
11
00
Yes
No
0
Headset
None
01
11
Yes
No
0
Headphone
None
00
11
Yes
No
0
—
1
None
Headset
11
00
Yes
No
0
—
1
None
Headphone
11
00
Yes
No
0
—
1
Headset
None
00
11
Yes
No
0
—
1
Headphone
None
00
11
Yes
No
1
0
0
None
Headset
11
01
Yes
No
1
0
0
None
Headphone
11
00
Yes
No
1
0
0
Headset
None
01
11
Yes
No
1
0
0
Headphone
None
00
11
Yes
No
1
0
1
None
Headset
11
00
Yes
No
1
0
1
None
Headphone
11
00
Yes
No
1
0
1
Headset
None
00
11
Yes
No
1
0
1
Headphone
None
00
11
Yes
No
1
1
—
None
Headset
11
01
Yes
No
1
1
—
None
Headphone
11
00
Yes
No
1
1
—
Headset
None
01
11
Yes
No
1
1
—
Headphone
None
00
11
Yes
No
Note: JDETEN = 1; MICBIAS enable; any bit of PALEN/PAREN set.
______________________________________________________________________________________
53
MAX9880A
Table 23. Headset Detect Configuration
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Headphone Modes
The MAX9880A’s headphone amplifier supports differential, single-ended, and capacitorless output modes, as
shown in Figure 9. In each mode, the amplifier can be
configured for stereo or mono operation. The single-
DIFFERENTIAL
ended mode optionally includes click-and-pop reduction to eliminate the click-and-pop that would normally
be caused by the output coupling capacitor. When
click-and-pop reduction is not required leave LOUTN
and ROUTN unconnected.
SINGLE-ENDED
CAPACITORLESS
220μF
LOUTP
LOUTP
LOUTP
LOUTN
LOUTN
LOUTN
1μF
220μF
ROUTP
ROUTP
ROUTP
ROUTN
ROUTN
ROUTN
1μF
OPTIONAL COMPONENTS REQUIRED FOR CLICK-AND-POP SUPPRESSION ONLY.
Figure 9. Headphone Amplifier Modes
Table 24. Mode Configuration Register
REGISTER
B7
B6
B5
B4
B3
Mode
DSLEW
VSEN
ZDEN
0
0
Jack Detect
JDETEN
0
JDWK
0
0
B2
B1
B0
HPMODE
0
JDEB
REGISTER
ADDRESS
(SEE NOTE)
0x24
0x25
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
DSLEW
54
FUNCTION
Digital Volume Slew Speed
0 = Digital volume changes are slewed over 10ms.
1 = Digital volume changes are slewed over 80ms.
VSEN
Volume Change Smoothing
0 = Volume changes slew through all intermediate values.
1 = Volume changes occur in one step.
ZDEN
Line Input Zero-Crossing Detection
0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero
crossing occurs.
1 = Line input volume changes occur immediately.
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
BITS
MAX9880A
Table 24. Mode Configuration Register (continued)
FUNCTION
Headphone Amplifier Mode
HPMODE
MODE
000
HPMODE
Stereo differential
001
Mono (left) differential
010
Stereo capacitorless
011
Mono (left) capacitorless
100
Stereo single-ended (clickless)
101
Mono (left) single-ended (clickless)
110
Stereo single-ended (fast turn-on)
111
Mono (left) single-ended (fast turn-on)
Note: In mono operation, the right amplifier is disabled.
JDETEN
JDWK
Jack-Detection Enable
SHDN = 0: Sleep Mode. Enables pullups on JACKSNS/AUX to detect jack insertion.
SHDN = 1: Normal Mode. Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes.
Note: AUXEN must be set to 0 for jack detection to function.
Jack-Sense Weak Pullup. Enables an internal pullup. Set JDWK = 1 to enable an internal 5μA current
source. Set JDWK = 0 for external pullup.
Jack Detect Debounce. Configures the JDET debounce time for changes to JKSNS[1:0] according to
information below.
JDEB
JDEB
DEBOUNCE TIME (ms)
00
25
01
50
10
100
11
200
Power Management
Revision Code
The MAX9880A includes complete power management
control to minimize power usage. The DAC and both
ADCs can be independently enabled so that only the
required circuitry is active.
The MAX9880A includes a revision code to allow easy
identification of the device revision. Revision code at
register address 0xFF is not accessible through the SPI
interface and so the revision code is accessible
through SPI at an additional address of 0x14 (0x14–SPI
address). The current revision code is 0x42.
______________________________________________________________________________________
55
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 25. Power Management Register
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
Enable
LNLEN
LNREN
LOLEN
LOREN
DALEN
DAREN
ADLEN
ADREN
0x26
System Shutdown
SHDN
0
0
0
XTEN
XTOSC
0
0
0x27
REGISTER
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
LNLEN
Left-Line Input Enable. Enables the left-line input preamp and automatically enables the left and right
headphone amplifiers. If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and
right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LNREN
Right-Line Input Enable. Enables the right-line input preamp and automatically enables the right headphone
amplifiers.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LOLEN
Left-Line Output Enable. Enables the left-line output.
LOREN
Right-Line Output Enable. Enables the right-line output.
DALEN
Left DAC Enable. Enables the left DAC and automatically enables the left and right headphone amplifiers. If
DAREN = 0, the left DAC signal is also routed to the right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
DAREN
Right DAC Enable. Right DAC operation requires DALEN = 1.
ADLEN
Left ADC Enable.
ADREN
Right ADC Enable. Enabling the right ADC must be done in the same I2C write operation that enables the left
ADC. The right ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must
be toggled to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
SHDN
Shutdown. Places the device in low power shutdown mode.
XTEN
Crystal Clock Enable
1 = Output of crystal oscillator and buffer routed to the clock prescaler. MCLK input disabled.
0 = MCLK input routed to the clock prescaler. Crystal oscillator and buffer disabled.
XTOSC
Crystal Clock Source
1 = Disables the internal crystal oscillator. Provide an external clock on X1.
0 = Enables the internal crystal oscillator. Attach a crystal between X1 and X2. XTOSC is ignored if XTEN = 0.
Table 26. Revision Code Register
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
Revision ID
REV
0x14
Revision ID
REV
0xFF
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
56
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MAX9880A
tCSS
tCSH
CS
tCP
tCSW
tCL
SCLK
tDO
tDEN
tCH
DIN
tDS
tDZ
tDH
DOUT
Figure 10. SPI Interface Timing Diagram
CS
SCLK
DIN
DOUT
R/W
ADDR9
ADDR0
UNUSED4
HIGH-Z
UNUSED0
D7
D0
1 DATA BYTE
Figure 11. Writing 1 Byte of Data to the MAX9880A
Serial Peripheral Interface (SPI)
Chip Select (CS)
The MAX9880A SPI interface is active only when CS is
low. When CS is high, the MAX9880A three-states the
DOUT output and resets the internal SPI logic. If CS
goes high in the middle of an SPI transfer, all the data is
discarded. When CS is low, unless the register address
is correctly decoded by the MAX9880A, the DOUT output is three-stated.
Serial Clock (SCLK)
The SPI master provides the SCLK signal to clock the
SPI interface. SCLK has an upper frequency limit of
25MHz. The MAX9880A samples the DIN input data on
the falling edge of SCLK and changes the output data
on the rising edge of SCLK. The MAX9880A ignores
SCLK transitions when CS is high.
Serial-Data In (DIN) and Serial-Data Out (DOUT)
The SPI frame is organized into 24 bits. The first 16 bits
consist of the R/W enable bit, followed by the 10 register address bits and 5 unused bits. The next 8 bits are
data bits, sent most significant bit first.
For an SPI write transfer, write a 1 to the R/W bit, followed by the 10 register address bits, 5 unused bits,
then the 8 data bits.
Figure 11 illustrates the proper frame format for writing
one byte of data to the MAX9880A. Additional 24-bit
frames can be sent while CS remains low. The DOUT
output is three-stated during a write operation.
For an SPI read transfer, write a zero to the R/W bit, followed by the 10 register address bits and 5 unused
bits. Any data sent after the register address bits are
ignored. The internal contents of the register being read
______________________________________________________________________________________
57
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
CS
SCLK
DIN
R/W
ADDR9
ADDR0
UNUSED4
UNUSED0
HIGH-Z
DOUT
D7
D0
1 DATA BYTE
Figure 12. Reading 1 Byte of Data from the MAX9880A
CS
SCLK
DIN
DOUT
R/W
ADDR9
ADDR0
UNUSED4
HIGH-Z
UNUSED0
D7
D0
D7
1 DATA BYTE
D0
1 DATA BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Reading n Bytes of Data from the MAX9880A
do not change until the transfer is complete. The DOUT
output is three-stated when writing the register address
bits. If the correct register address is decoded, DOUT
is driven low at the first rising clock edge after the first
unused bit.
Figure 12 illustrates the proper frame format for reading
1 byte of data from the MAX9880A.
When reading data from the MAX9880A, the address
pointer autoincrements by one register address if CS is
held low after reading the first 8 data bits. For each
subsequent eight clock cycles, a byte of data is read.
This autoincrement feature allows a master to read
sequential registers within one continuous SPI register
address range from 0x200 to 0x227. The register
address does not autoincrement if a read is initiated at
a register address lower than 0x200. If the register
address increments beyond 0x227, the DOUT output is
three-stated. Figure 13 illustrates the proper format for
reading multiple bytes of data.
I2C Serial Interface
The MAX9880A features an I2C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9880A and
the master at clock rates up to 400kHz. Figure 14
shows the 2-wire interface timing diagram. The master
generates SCL and initiates data transfer on the bus.
The master device writes data to the MAX9880A by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or repeated
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9880A is 8 bits long and is
followed by an acknowledge clock pulse. A master
reading data from the MAX9880A transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX9880A transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read
SMBus is a trademark of Intel Corp.
58
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MAX9880A
SDA
tBUF
tSU,STA
tSU,DAT
tLOW
tHD,STA
tSP
tHD,DAT
tSU,STO
tHIGH
SCL
tHD,STA
tR
tF
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 14. 2-Wire Interface Timing Diagram
S
Sr
P
SCL
SDA
Figure 15. START, STOP, and Repeated START Conditions
sequence is framed by a START (S) or repeated START
(Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an opendrain output. A pullup resistor, typically greater than
500Ω, is required on SDA. SCL operates only as an
input. A pullup resistor, typically greater than 500Ω, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the
MAX9880A from high voltage spikes on the bus lines
and minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 15). A
START condition from the master signals the beginning
of a transmission to the MAX9880A. The master terminates transmission and frees the bus by issuing a STOP
condition. The bus remains active if a repeated START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9880A recognizes a STOP condition at any
point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
______________________________________________________________________________________
59
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
28
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 16. Acknowledge
ACKNOWLEDGE FROM MAX9880A
B7
ACKNOWLEDGE FROM MAX9880A
S
SLAVE ADDRESS
0
B6
B5
B4
B3
B2
B1
B0
ACKNOWLEDGE FROM MAX9880A
A
REGISTER ADDRESS
R/W
A
A
DATA BYTE
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 17. Writing 1 Byte of Data
Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the
MAX9880A, the seven most significant bits are
0011000. Setting the read/write bit to 1 (slave address
= 0x31) configures the MAX9880A for read mode.
Setting the read/write bit to 0 (slave address = 0x30)
configures the MAX9880A for write mode. The address
is the first byte of information sent to the MAX9880A
after the START (S) condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9880A uses to handshake receipt each byte of
data when in write mode (see Figure 16). The
MAX9880A pulls down SDA during the entire mastergenerated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful
data transfer, the bus master retries communication.
60
The master pulls down SDA during the 9th clock cycle
to acknowledge receipt of data when the MAX9880A is
in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue.
A not acknowledge is sent when the master reads the
final byte of data from the MAX9880A, followed by a
STOP (P) condition.
Write Data Format
A write to the MAX9880A includes transmission of a
START condition, the slave address with the R/W bit set
to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
condition. Figure 17 illustrates the proper frame format
for writing 1 byte of data to the MAX9880A. Figure 18
illustrates the frame format for writing n bytes of data to
the MAX9880A.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9880A.
The MAX9880A acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condition is issued followed by another read operation, the
first data byte to be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9880A’s
slave address with the R/W bit set to 0 followed by the
register address. A repeated START (Sr) condition is
then sent followed by the slave address with the R/W bit
set to 1. The MAX9880A then transmits the contents of
the specified register. The address pointer autoincrements after transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condition. Figure 19 illustrates the frame format for reading 1
byte from the MAX9880A. Figure 20 illustrates the frame
format for reading multiple bytes from the MAX9880A.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9880A acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START (S) command followed by a read command resets the address pointer
to register 0x00.
The first byte transmitted from the MAX9880A is the
contents of register 0x00. Transmitted data is valid on
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
S
SLAVE ADDRESS
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9880A
0
A
REGISTER ADDRESS
A
A
DATA BYTE 1
R/W
DATA BYTE n
1 BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 18. Writing n Bytes of Data
NOT ACKNOWLEDGE FROM MASTER
S
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
SLAVE ADDRESS
REGISTER ADDRESS
0
R/W
ACKNOWLEDGE FROM MAX9880A
A
REPEATED START
Sr
SLAVE ADDRESS
1
R/W
A
DATA BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 19. Reading 1 Byte of Data
______________________________________________________________________________________
61
MAX9880A
The second byte transmitted from the master configures the MAX9880A’s internal register address pointer.
The pointer tells the MAX9880A where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9880A upon receipt of the address pointer data.
The third byte sent to the MAX9880A contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9880A signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This
autoincrement feature allows a master to write to
sequential registers within one continuous frame. The
master signals the end of transmission by issuing a
STOP (P) condition. Register addresses greater than
0x17 are reserved. Do not write to these addresses.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ACKNOWLEDGE FROM MAX9880A
S
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9880A
0
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9880A
A
Sr
SLAVE ADDRESS
REPEATED START
R/W
1
R/W
A
DATA BYTE
A
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 20. Reading n Bytes of Data
Applications Information
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the
MAX9880A, partition the circuitry so that the analog
sections of the MAX9880A are separated from the digital sections. This ensures that the analog audio traces
are not routed near digital traces.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect
AGND and DGND directly to the ground plane using
the shortest trace length possible. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any digital noise from
coupling into the analog audio signals.
Ground the bypass capacitors on MICBIAS, REG,
PREG, and REF directly to the ground plane with minimum trace length. Also be sure to minimize the path
length to AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD and
DVDDS1 directly to DGND.
Route microphone signals from the microphone to the
MAX9880A as a differential pair, ensuring that the positive and negative signals follow the same path as
closely as possible with equal trace length. When using
single-ended microphones or other single-ended audio
sources, ground the negative microphone input as
close to the audio source as possible and then treat the
positive and negative traces as differential pairs.
The MAX9880A TQFN package features an exposed
thermal pad on its underside. Connect the exposed
thermal pad to AGND.
An evaluation kit (EV kit) is available to provide an
example layout for the MAX9880A. The EV kit allows
quick setup of the MAX9880A and includes easy-to-use
software allowing all internal registers to be controlled.
Startup Sequences
Table 27. Clock Initialization (Perform Before Any Playback or Record Setup)
SEQUENCE
DESCRIPTION
1
SHDN = 0
2
Configure clocks
3
Configure digital audio interface
REGISTERS
0x27
0x05, 0x06, 0x07, 0x0B, 0x0C
0x08, 0x09, 0x0A, 0x0D, 0x0E, 0x0F
Table 28. Music Playback
SEQUENCE
1
2
3
4
5
6
7
8
9
62
DESCRIPTION
Select DAC audio source
Select music filters
Set output volume
Set line output volume
Select headphone mode
Enable line outputs and DAC as required
Enable LRCLK and BCLK (if operating in slave mode)
Enable MAX9880A
Enable external amplifier (if using)
REGISTERS
0x10
0x11
0x1C, 0x1D
0x1E, 0x1F
0x24
0x26
N/A
0x27
N/A
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
SEQUENCE
DESCRIPTION
MAX9880A
Table 29. Line Input Playback
REGISTERS
1
Set line input gain
0x1A, 0x1B
2
Set volume
0x1C, 0x1D
3
Set line output volume (if using)
0x1E, 0x1F
4
Select headphone mode
5
Enable line outputs and line inputs as required
0x24
0x26
6
Enable MAX9880A
0x27
7
Enable external amplifier (if using)
N/A
Table 30. Line Input Playback with Record
SEQUENCE
DESCRIPTION
REGISTERS
1
Select music filters
0x11
2
Set line input gain
0x1A, 0x1B
3
Set volume
0x1C, 0x1D
4
Set line output volume (if using)
0x1E, 0x1F
5
Configure ADC input mixer
0x22
6
Select headphone mode
0x24
7
Enable line outputs, line inputs, and ADC as required
0x26
8
Enable LRCLK and BCLK (if operating in slave mode)
N/A
9
Enable MAX9880A
0x27
10
Enable external amplifier (if using)
N/A
Table 31. Voice Playback
SEQUENCE
DESCRIPTION
REGISTERS
1
Select DAC audio source
0x10
2
Select voice filters
0x11
3
Set volume
0x1C, 0x1D
4
Set line output volume (if using)
0x1E, 0x1F
5
Select headphone mode
0x24
6
Enable line outputs and DAC as required
0x26
7
Enable LRCLK and BCLK (if operating in slave mode)
N/A
8
Enable MAX9880A
0x27
9
Enable external amplifier (if using)
N/A
______________________________________________________________________________________
63
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 32. Voice Microphone Record
SEQUENCE
DESCRIPTION
REGISTERS
1
Select voice filters
2
Set ADC level to 0dB
0x18, 0x19
0x11
3
Configure microphone gain
0x20, 0x21
4
Set line output volume (if using)
0x1E, 0x1F
5
Configure ADC input mixer
0x22
6
Configure MICBIAS voltage
0x23
7
Enable ADC
0x26
8
Enable LRCLK and BCLK (if operating in slave mode)
N/A
9
Enable MAX9880A
0x27
Table 33. Voice Playback with Record
SEQUENCE
64
DESCRIPTION
REGISTERS
1
Select voice filters
0x11
2
Set ADC level to 0dB
0x18, 0x19
3
Configure microphone gain
0x20, 0x21
4
Set line output volume (if using)
0x1E, 0x1F
5
Configure ADC input mixer
0x22
6
Configure MICBIAS voltage
0x23
7
Enable ADCs and DACs as required
0x26
8
Enable LRCLK and BCLK (if operating in slave mode)
N/A
9
Enable MAX9880A
0x27
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Music Playback
fMCLK = 12.288MHz (master clock supplied to codec),
fLRCLK = 48kHz, standard I2S format, codec in slave
mode, music source connected through S2 pins to
DAI2 audio path, and output on headphone amplifiers
(output capacitorless mode).
Table 34. Music Playback
SEQUENCE
DESCRIPTION
REGISTER ADDRESS
REGISTER VALUE
1
SHDN = 0
0x27
04h
2
Configure system clock
0x05
10h
3
Configure DAI2 clock
0x0B
60h
4
Configure DAI2 clock
0x0C
00h
5
Configure DAI2 audio path
0x0D
11h
6
Configure DAI2 audio path
0x0E
50h
7
Select DAC audio source
0x10
21h
8
Select music filters
0x11
80h
9
Set output volume (0dB)
0x1C, 0x1D
09h
10
Set line output volume (muted)
0x1E, 0x1F
40h
11
Select headphone mode (output capacitorless mode)
0x24
02h
12
Enable line outputs and DAC as required
0x26
0Ch
13
Enable MAX9880A
0x27
84h
Voice Duplex
f MCLK = 13MHz (master clock supplied to codec),
f LRCLK = 8kHz, TDM/PCM format, codec in slave
mode, voice signals on S1 pins to DAI1 audio path and
output on headphone amplifier left (differential mode).
Table 35. Voice Duplex
SEQUENCE
DESCRIPTION
REGISTER ADDRESS
REGISTER VALUE
1
SHDN = 0
0x27
04h
2
Configure system clock
0x05
10h
3
Configure DAI1 clock
0x0B
0Fh
4
Configure DAI1 clock
0x0C
1Fh
5
Configure DAI1 audio path
0x0D
04h
6
Configure DAI2 audio path
0x0E
30h
7
Select DAC audio source
0x10
21h
8
Select voice GSM filters
0x11
33h
03h
9
Set ADC level to 0dB
0x18, 0x19
10
Configure microphone gain (20dB preamp gain)
0x20, 0x21
54h
11
Set headphone volume
0x1C, 0x1D
09h
12
Set line output volume (if using)
0x1E, 0x1F
40h
13
Configure ADC input mixer
0x22
50h
14
Configure MICBIAS voltage (2.2V)
0x23
01h
15
Select headphone mode
0x24
01h
16
Enable line outputs, ADC and DAC as required
0x26
0Bh
18
Enable MAX9880A
0x27
84h
______________________________________________________________________________________
65
MAX9880A
Example of Register Settings for Music
Playback and Voice Duplex Senarios
1μF
FM
RECEIVER
18
(C7)
20
(C8)
21
(D8)
23
(E8)
MICLN/
DIGMICCLK
MICRP/
SPDMDATA
MICRN/
SPDMCLK
LINL
LINR
19
(D7)
MICLP/
DIGMICDATA
24
(F8)
17
(B8)
1μF
MICBIAS
10
(B6)
13
(C6)
REF
REG
2.2μF
REF
16
(B7)
DVDDS1
36
(F2)
PGAMR:
+20dB TO 0dB
LNREN
LIGR:
+30dB TO 0dB
LNLEN
LIGL:
+30dB TO 0dB
SPDMCLK
PAREN:
0/20/30dB
SPDMDATA
IRQ
PREG
8
(A4)
1μF
PGAML:
+20dB TO 0dB
VCM
MICVDD
PALEN:
0/20/30dB
MICBIAS
1μF
1.8V
SCL/SCLK
I2C/SPI
5
(B4)
CS
1
(B2)
MIXINR
ADREN
ADCR
AVFLT
VOICE/AUDIO
FILTER
MODE
AVFLT
MODE
SDA/DIN
VOICE/AUDIO
FILTER
DOUT
ADLEN
6
(B5)
CLOCK
GEN
41
(D1)
40
(E2)
39
(E1)
MICDG:
0/6/12/18dB
AVR:
+4dB TO -11dB
38
(D3)
37
(F1)
LRCLKS1
DSTS
PLL1, NI1,
REGS 08-OA
DGND
47
(A1)
45
(C3)
44
(C2)
LRCLKS2
BCLKS2
43
(C1)
SDINS2
42
(D2)
VDACG:
_DACA:
0/6/12/18dB 0dB TO -15dB
VDACG:
_DACA:
0/6/12/18dB 0dB TO -15dB
DVST:
-9dB TO -69dB
PLL2, NI2,
REGS 0D-0F
DIGITAL AUDIO PATH 2
(8kHz TO 96kHz)
AUDIO SOURCE SELECTION
SDINS1
DIGITAL AUDIO PATH 1
(8kHz TO 48kHz)
BCLKS1
MICDG:
0/6/12/18dB
AVL:
+4dB TO -11dB
SPDMCLK
ADCL
MAX9880A
2
(B3)
MXINL
7
(A5)
FREQ1
1.8V
MODE
MIX
MIX
MCLK
PSCLK
SDOUTS2
MIX/MUX
SDOUTS1
MIX/MUX
MIX/MUX
1.8V
DVDD
9
(A6)
AVDD
AGND
15
(A8)
VOLR:
+6dB TO -84dB
VOLL:
+6dB TO -84dB
_DACA:
VOLR:
0dB TO -15dB +6dB TO -84dB
_DACA:
VOLL:
0dB TO -15dB +6dB TO -84dB
SEL1, SEL2
46
(B1)
1μF
AUDIO
FILTER
DCB
AUDIO
FILTER
DCB
LINEAR
REG
1μF
MODE, DVFLT
VOICE/AUDIO
FILTER
MODE, DVFLT
VOICE/AUDIO
FILTER
1.8V
PREG
12
(A7)
MIXSPDML
1μF
MIXDAL
MIXDAR
1.8V
DAC
SPDMR
DAREN
DAC
PGND
1b
I/F
1μF
27
(E6, F6)
34
(E3, F3)
SPDML
DALEN
MIXSPDMR
MIX
MIX
MIX
PVDD
66
MIX
31
(F4)
22
(D5)
25
(F7)
26
(E7)
30
(F5)
29
HPMODE (E5)
LOGR:
0dB TO -30dB LOREN
HEADPHONE
SENSE
AUXEN
4
(A3)
3
(A2)
32
HPMODE (E4)
XTAL
OSC
LOGL:
0dB TO -30dB LOLEN
SPDMDATA
XTEN,
XTOSC
JACKSNS/
AUX
LOUTR
LOUTL
ROUTN
ROUTP
LOUTN
LOUTP
X2
X1
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Functional Diagram/Typical Operating Circuit
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
48 WLP
W482A3+1
21-0230
48 TQFN-EP
T4866+1
21-0141
______________________________________________________________________________________
67
MAX9880A
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
QFN THIN.EPS
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
68
______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
69
MAX9880A
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.