Etron EM639165TS-75L 8mega x 16bits sdram Datasheet

EtronTech
EM639165
8Mega x 16bits SDRAM
Preliminary (Rev 1.0, 2/2001)
Features
Pin Assignment (Top View)
• Single 3.3 ± 0.3V power supply
• Fast clock rate
- PC133: 133 MHz (CL3)
- PC100: 100 MHz (CL2)
• Fully synchronous operation referenced to clock
rising edge
• 4-bank operation controlled by BA0, BA1 (Bank
Address)
• Programmable Mode registers
- /CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8 or full page
- Burst Type: interleaved or linear burst
• Byte Control – DQML and DQMU
• Random column access
• Auto precharge / All banks precharge controlled
by A10
• Auto and self-refresh
• Self-refresh mode: standard and low power
• 4096 refresh cycles/64ms
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Ordering Information
Part Number
Speed
Grade
Self refresh
current (Max.)
- 75/8
EM639165TS-75
PC133/CL3
2 mA
Clock Cycle time (min., CL=2)
10/10 ns
EM639165TS-75L
PC133/CL3
800 µA
Clock Cycle time (min., CL=3)
7.5/8 ns
EM639165TS-8
PC100/CL2
2 mA
EM639165TS-8L
PC100/CL2
800 µA
Key Specifications
EM639165
tCK2
tCK3
tAC2
tAC3
tRAS
tRC
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
Access time (max., CL=2)
6/6 ns
Access time (max., CL=3)
5.4/6 ns
Row Active time (max.)
45/48 ns
Row Cycle time(min.)
67.5/70 ns
Overview
EM639165 is a high-speed Synchronous Dynamic
Random Access Memory (SDRAM), organized as 4
banks x 2,097,152 words x 16 bits. All inputs and
outputs are referenced to the rising edge of CLK.
It achieves very high-speed data rates up to
133MHz, and is suitable for main memories or graphic
memories in computer systems. For handheld device
application, we also provide a low power option, with
self-refresh current under 800 µA.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EM639165
BLOCK DIAGRAM
DQ0-15
I/O Buffer
Memory Array
Memory Array
Memory Array
Memory Array
4096 x512x16
Cell Array
4096 x512x16
Cell Array
4096 x512x16
Cell Array
4096 x512x16
Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
A0-11
Preliminary
BA0,1
CLK
/CS
CKE
2
/RAS
/CAS
/WE
DQM
Rev 1.0
Feb. 2001
EM639165
PIN FUNCTION
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
CKE
Input
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
/CS
Input
Chip Select:
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified byA0-8.
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
CLK
DQ0-15
Input / Output Data In and Data out are referenced to the rising edge of CLK.
DQMU/L
Input
VDD,VSS
Power Supply
VDDQ,VSSQ
Preliminary
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
Power Supply VDDQ and VSSQ are supplied to the Output Buffers only.
3
Rev 1.0
Feb. 2001
EM639165
BASIC FUNCTIONS
The EM639165 provides basic functions, bank (row)
activate, burst read / write, bank (row) precharge, and auto
/ self refresh.
Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /CS
,CKE and A10 are used as chip select, refresh opt ion, and
precharge option, respectively .
To know the detailed definition of commands, please see
the command truth table.
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @ refresh command
A10
Precharge Option @ precharge or read/write command
define basic command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output
data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, all banks
are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
Preliminary
4
Rev 1.0
Feb. 2001
EM639165
COMMAND TRUTH TABLE
MNEMONIC
CKE
n-1
CKE
n
/CS
DESEL
H
X
H
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
Row Address Entry &
Bank Active
ACT
H
X
L
L
H
Single Bank Precharge
PRE
H
X
L
L
PREA
H
X
L
WRITE
H
X
WRITE A
H
READ
COMMAND
A1 0
A0-9
X
X
X
X
X
X
X
H
V
V
V
V
H
L
V
X
L
X
L
H
L
X
X
H
X
L
H
L
L
V
V
L
V
X
L
H
L
L
V
V
H
V
H
X
L
H
L
H
V
V
L
V
READA
H
X
L
H
L
H
V
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
X
L
H
H
X
X
X
X
X
X
X
Self-Refresh Exit
REFSX
L
H
L
H
H
H
X
X
X
X
TBST
H
X
L
H
H
L
X
X
X
X
MRS
H
X
L
L
L
L
L
L
L
V*1
Deselect
Precharge All Banks
Column Address Entry
&Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Burst Terminate
Mode Register Set
/RAS /CAS
/WE BA0,1 A1 1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
Preliminary
5
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
IDLE
ROW
ACTIVE
Preliminary
Command Action
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE /
PREA
NOP*4
L
L
L
H
X
REFA
Auto-Refresh*5
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set*5
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE /
PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
6
READ /
READA
WRITE /
WRITEA
Bank Active, Latch RA
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Bank Active / ILLEGAL*2
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State
/CS
READ
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
L
H
L
H
BA, CA, A10
READ
/READA
Terminate Burst, Latch CA,Begin
Read, Determine Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE /
PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE /
PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE
Preliminary
/RAS /CAS /WE Address
Command Action
TBST
TBST
7
READ /
READA
WRITE /
WRITEA
Terminate Burst
Terminate Burst, Latch CA,Begin
Terminate Burst, Latch CA,Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
Preliminary
/CS
/RAS /CAS /WE
Address
Command
Action
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ /
READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITE A
ILLEGAL
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE /
PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE /
PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
TBST
8
Bank Active / ILLEGAL*2
ILLEGAL
READ /
ILLEGAL
READA
WRITE /
ILLEGAL
WRITEA
Bank Active / ILLEGAL*2
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State
/CS
PRE CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE /
PREA
NOP*4 (Idle after tRP)
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
BA
L
H
L
X
BA, CA, A10
L
L
H
H
L
L
H
L
L
L
L
ROW
ACTIVATING
Preliminary
/RAS /CAS /WE
Address
Command
Action
TBST
ILLEGAL*2
READ /
WRITE
ILLEGAL*2
BA, RA
ACT
ILLEGAL*2
L
BA, A10
PRE /
PREA
ILLEGAL*2
L
H
X
REFA
ILLEGAL
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
9
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State
WRITE
RECOVERING
REFRESHING
Preliminary
/CS
/RAS /CAS /WE
Address
Command
Action
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE /
PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE /
PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
10
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State
/CS
MODE
REGISTER
SETTING
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE /
PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Preliminary
/RAS /CAS /WE Address
11
Command
Action
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE for CKE
Current State
SELFREFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
ANY STATE
other than
listed above
CKE
n-1
CKE
n
/CS
H
X
X
X
L
H
H
L
H
L
/RAS /CAS
/WE
Add
Action
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Susspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Susspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Preliminary
12
Rev 1.0
Feb. 2001
EM639165
POWER ON SEQUENCE
MODE REGISTER
Before starting normal operation, the following power on
Burst Length, Burst Type and /CAS Latency can be pro-
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
grammed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
1. Apply power and start clock. Attempt to maintain CKE
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input con-
command.
ditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
CLK
After these sequence, the SDRAM is idle state and ready
/RAS
for normal operation.
/CAS
/CS
/WE
V
BA0,1 A11-A0
BA0 BA1 A1 1 A1 0 A9
0
0
0
CL
LATENCY
MODE
0
0
A7
0
0
A6
A5
A4
LTMODE
/CAS LATENCY
000
001
R
R
0
0
1
1
1
1
2
3
R
R
R
R
1
1
0
0
1
1
A8
0
1
0
1
0
1
A3
A2
BT
A1
BL
BURST
LENGTH
BURST
TYPE
A0
BL
BT= 0
BT= 1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
R
1
2
4
8
R
101
110
111
R
R
FP
R
R
R
0
0
0
0
1
0
1
SEQUENTIAL
INTERLEAVED
R: Reserved for Future Use
FP: Full Page
Preliminary
13
Rev 1.0
Feb. 2001
EM639165
CLK
Command
Read
Write
Address
Y
Y
Q0
DQ
CL= 3
BL= 4
/CAS Latency
Q1
Q2
Q3
D0
Burst Length
D1
D2
D3
Burst Length
Burst Type
Initial Address
BL
Column Addressing
A2
A1 A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
Preliminary
-
1
14
Rev 1.0
Feb. 2001
EM639165
OPERATIONAL DESCRIPTION
BANK ACTIVATE
READ
The SDRAM has four independent banks. Each bank is activated by
the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval
between one bank and the other bank is tRRD. Maximum 2 ACT
commands are allowed within tRC , although the number of banks
which are active concurrently is not limited.
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the /CAS Latency from the
READ, followed by (BL -1) consecutive data when the Burst Length
is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8),
A0-8(X16) , and the address sequence of burst data is defined by
the Burst Type. A READ command may be applied to any active
bank, so the row precharge time (tRP) can be hidden behind
continuous output data by interleaving the multiple banks. When
A10 is high at a READ command, the auto-precharge (READA) is
performed. Any command (READ, WRITE, PRE, TBST, ACT) to
the same bank is inhibited till the internal precharge is complete.
The internal precharge starts at BL after READA. (Need to keep
tRAS min.) The next ACT command can be issued after (BL +
tRP) from the previous READA.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When
multiple banks are active, the precharge all command (PREA, PRE
+ A10=H) is available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the same bank
can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2 ACT command / tRCmin
tRCmin
Command
ACT
ACT READ
PRE
ACT
tRAS
tRRD
A0-9
Xa
Xb
tRCD
Y
A10
Xa
Xb
0
A11
Xa
Xb
BA0,1
00
01
tRP
Xb
Xb
1
Xb
00
01
DQ
Qa0
Qa1
Qa2
Qa3
Precharge all
Preliminary
15
Rev 1.0
Feb. 2001
EM639165
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
Command
ACT
READ ACT
READ PRE
tRCD
A0-9
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
A11
Xa
BA0,1
00
10
00
Qa1
Qa2
Xb
00
10
DQ
Qa0
Qa3
Qb0
Qb1
Qb2
/CAS latency
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK
BL + tRP
Command
ACT
ACT
READ
tRCD
tRP
BL
A0-9
Xa
Y
Xa
A10
Xa
1
Xa
A11
Xa
BA0,1
00
Xa
00
00
Qa0
DQ
Qa1
Qa2
Qa3
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK
Command
AC T
READ
BL
CL=3
DQ
CL=2
DQ
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal Precharge Start Timing
Preliminary
16
Rev 1.0
Feb. 2001
EM639165
WRITE
After tRCD from the bank activation, a WRITE command
can be issued. 1st input data is set at the same cycle as the
WRITE. Following (BL -1) data are written into the RAM,
when the Burst Length is BL. The start address is specified
by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address
sequence of burst data is defined by the Burst Type. A
WRITE command may be applied to any active bank, so
the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From
the last input data to the PRE command, the write recovery
time (tWR) is required. When A10 is high at a WRITE
command, the autoprecharge (WRITEA) is performed. Any
command (READ, WRITE, PRE, TBST, ACT) to the same
bank is inhibited till the internal precharge is complete. The
internal precharge begins at tWR after the last input data
cycle. (Need to keep tRAS min.) The next ACT command
can be issued after tRP from the internal precharge timing.
WRITE with Auto-Precharge (BL=4)
CLK
Command
ACT
Write
PRE
PRE
0
0
0
0
10
00
10
Db0
Db1
Write
ACT
tRCD
tRCD
A0-9
Xa
Y
Xb
A10
Xa
Xa
0
Xb
A11
Xa
Xa
BA0,1
00
Y
0
Xb
DQ
00
10
Da0
Da1
Da2
Da3
Db2
Db3
Multi Bank Interleaving WRITE (BL=4)
CLK
Command
Write
ACT
ACT
tRCD
tRP
A0-9
Xa
Y
Xa
A10
Xa
1
Xa
A11
Xa
BA0,1
00
Xa
00
00
tWR
DQ
Da0
Da1
Da2
Da3
Internal precharge starts
Preliminary
17
Rev 1.0
Feb. 2001
EM639165
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval
is minimum 1 CLK..
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
READ READ
READ
READ
Yl
A0-9
Yi
Yj
Yk
A10
0
0
0
00
00
10
0
A11
BA0,1
Qai0
DQ
01
Qaj0
Qaj1 Qbk0 Qbk1 Qbk2
Qal0
Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ
should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1
cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
READ
Write
A0-9
Yi
Yj
A10
0
0
00
00
A11
BA0,1
DQM
Q
Qai0
D
Daj0
Daj1
Daj2
Daj3
DQM control Write control
Preliminary
18
Rev 1.0
Feb. 2001
EM639165
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the
same bank . READ to PRE interval is minimum 1 CLK. A PRE
command to output disable latency is equivalent to the /CAS
Latency. As a result, READ to PRE interval determines valid
data length to be output. The figure below shows examples of
BL=4.
Read Interrupted by Precharge (BL=4)
CLK
Command
PRE
READ
DQ
Command
CL=3
READ
CL=2
READ
DQ
Preliminary
PRE
Q0
READ
Q1
Q2
PRE
Q0
DQ
Command
Q1
Q0
DQ
Command
Q0
Q2
READ PRE
DQ
Command
Q1
PRE
DQ
Command
Q0
Q1
READ PRE
Q0
19
Rev 1.0
Feb. 2001
EM639165
[Read Interrupted by Burst Terminate]
READ to TBST interval is minimum 1 CLK. A TBST command to
Similarly to the precharge, a burst terminate command can inter- output disable latency is equivalent to the /CAS Latency.
rupt the burst read operation and disable the data output. The
terminated bank remains active.
Read Interrupted by Terminate (BL=4)
CLK
Command
TBST
READ
DQ
Command
CL=3
READ
CL=2
READ
DQ
Preliminary
TBST
Q0
READ
Q1
Q2
TBST
Q0
DQ
Command
Q1
Q0
DQ
Command
Q0
Q2
READ TBST
DQ
Command
Q1
TBST
DQ
Command
Q0
Q1
READ TBST
Q0
20
Rev 1.0
Feb. 2001
EM639165
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE
interval is minimum 1 CLK.
Write Interrupted by Write (CL=3,BL=4)
CLK
Command
Write Write
Write
Write
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
00
00
10
00
DQ
Dai0
Daj0
A11
Daj1
Dbk0 Dbk1 Dbk2
Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE
to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (CL=3,BL=4)
CLK
Command
Write READ
Write
READ
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
00
00
10
00
A11
BA0,1
DQM
DQ
Preliminary
Dai0
Qaj0
21
Qaj1
Dbk0 Dbk1
Qal0
Rev 1.0
Feb. 2001
EM639165
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data
to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK
Command
ACT
Write
PRE
ACT
tRP
A0-9,11
Xa
Ya
Xa
A10
0
0
0
0
BA0-1
00
00
00
00
DQM
tWR
DQ
Da 0
Da 1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the
bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Terminate (BL=4)
CLK
Command
ACT
Write
A0-9,11
Xa
Ya
Yb
A10
0
0
0
BA0-1
00
00
00
DQ
Preliminary
Da 0
TBST
Da 1
Write
Db 0
22
Db 1
Db 2
Db 3
Rev 1.0
Feb. 2001
EM639165
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after
tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Write Interrupted by WRITE to another bank (BL=4)
CLK
Command
Write
ACT
Write
BL
A0-9,11
Ya
tRP
Xa
Yb
tWR
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da 0
Da 1
auto-precharge
Db 0
Db 1
Db 2
Db 3
interrupted
activate
Write Interrupted by READ to another bank (CL=2,BL=4)
CLK
Command
Write
ACT
Read
BL
A0-9,11
Ya
tRP
Xa
Yb
tWR
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da 0
Da 1
auto-precharge
Preliminary
Qb0
interrupted
Qb1
Qb2
Qb3
activate
23
Rev 1.0
Feb. 2001
EM639165
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after
tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Read Interrupted by Read to another bank (CL=2,BL=4)
CLK
Command
Read
Read
ACT
BL
A0-9,11
tRP
Ya
Yb
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Qa0
auto-precharge
Qa1
Qb0
interrupted
Qb1
Qb2
Qb3
activate
[Full Page Burst]
Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge
or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
Preliminary
24
Rev 1.0
Feb. 2001
EM639165
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /
banks must be in the idle state. Auto-refresh to auto-refresh
CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh
interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command.
128M bit memory cells. The auto-refresh is performed on 4
banks concurrently. Before performing an auto-refresh, all
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
Preliminary
25
Rev 1.0
Feb. 2001
EM639165
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command
(/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the selfrefresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and
the only enabled input ,all other inputs including CLK are
synchronous inputs is saved. To exit the self-refresh, supplying
stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE=H. After tRC from the 1st CLK egde following
CKE=H, all banks are in the idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
disabled and ignored, so that power consumption due to
Self-Refresh
CLK
Stable CLK
/CS
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
X
BA0,1
00
Self Refresh Exit
Self Refresh Entry
Preliminary
26
minimum tRFC
for recovery
Rev 1.0
Feb. 2001
EM639165
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure
synchronous input except during the self-refresh mode. CLK
below shows how CKE works. By negating CKE, the next
internal CLK is suspended. The purpose of CLK suspend is
suspend can be performed either when the banks are active
or idle. A command at the suspended cycle is ignored.
power down, output suspend or input suspend. CKE is a
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CLK
Standby Power Down
CKE
Command
PRE
NOP
NOP
NOP
Active Power Down
CKE
Command
ACT
NOP
NOP
NOP
DQ Suspend by CKE (CL=2)
CLK
CKE
Command
DQ
Preliminary
Write
D0
Read
D1
D2
D3
27
Q0
Q1
Q2
Rev 1.0
Q3
Feb. 2001
EM639165
DQM CONTROL
DQM is a dual function signal defined as the data mask for
writes and the output disable for reads. During writes, DQM(U,L)
masks input data word by word. DQM(U,L) to write mask latency
is 0. During reads, DQM(U,L) forces output to Hi-Z word by word.
DQM(U,L) to output Hi-Z latency is 2.
DQM Function(CL=3)
CLK
Command
Write
READ
DQM
DQ
D0
D2
D3
Q0
Q3
disabled by DQM(U,L)=H
masked by DQM(U,L)=H
Preliminary
Q1
28
Rev 1.0
Feb. 2001
EM639165
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Rating
Unit
VDD
Supply Voltage
with respect to VSS
-0.5 - 4.6
V
VDDQ
Supply Voltage for Output
with respect to VSSQ
-0.5 - 4.6
V
VI
Input Voltage
with respect to VSS
-0.5 - 4.6
V
VO
Output Voltage
with respect to VSSQ
-0.5 - 4.6
V
IO
Output Current
Pd
Power Dissipation
Topr
Operating Temperature
Tstg
Storage Temperature
Ta = 25˚C
50
mA
1000
mW
0 - 70
˚C
-65 - 150
˚C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70 ˚C ,unless otherwise noted)
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.6
V
VDD
Supply Voltage
3.0
3.3
VSS
Supply Voltage
0
0
V
VDDQ
Supply Voltage for output
3.0
3.3
3.6
V
VSSQ
Supply Voltage for output
0
0
0
V
VIH*1
High-Level Input Voltage all inputs
VIL*2
Low-level Input Voltage all inputs
VDDQ +0.3
2.0
-0.3
0.8
V
V
NOTES:
1. VIH(max)=5.5V for pulse width less than 10ns.
2. VIL(min)=-1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 -70˚C,VDD=VDDQ=3.3± 0 . 3 V , V S S = V S S Q = 0 V , u n l e s s o t h e r w i s e n o t e d )
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, contorl pin
CI(K)
Input Capacitance, CLK pin
CI/O
Input Capacitance, I/O pin
Preliminary
Test Condition
@ 1MHz
1.4V bias
200mV swing
Vcc=3.3V
29
Min.
Max.
Unit
2.5
5.0
pF
2.5
5.0
pF
2.5
4.0
pF
4.0
6.5
pF
Rev 1.0
Feb. 2001
EM639165
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70˚C, VDD=VDDQ=3.3±0.3V,VSS=VSSQ=0V, unless otherwise noted)
Max.
ITEM
Test Condition
Symbol
Operating current
-8
100
95
mA
110
100
mA
130
120
mA
Icc2N
CKE=VILmax
tCLK=15ns
20
20
mA
Icc2NS
CKE=VIHmin
CLK=VILmax(fixed)
15
15
mA
Icc2P
CKE=VIHmin
tCLK=15ns(Note)
2
2
mA
Icc2PS
CKE=VIHmin
tCLK=VILmax(fixed)
1
1
mA
Icc3N
CKE=/CS=VIHmin
tCLK=15ns(Note)
30
30
Icc3NS
CKE=VIHmin
tCLK=VILmax(fixed)
20
20
All Bank Active
tCLK = min
BL=4, CL=3, IOL=0mA
160
130
mA
160
160
mA
Standard
2
2
mA
Low-Power
800
800
µA
Icc1
Precharge Standby
current in Non-Power
down mode
Precharge Standby
current in Power down
mode
Unit
-75
Active Standby current
Burst current
Icc4
Auto-refresh current
Icc5
Self-refresh current
Icc6
tRC=min, tCLK=min
BL=1,IOL=0mA
tRC=min, tCLK=min
mA
CKE < 0.2V
NOTE:
1. Icc(max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 - 70˚C, VDD=VSSQ=3.3±0.3V,VSS=VSSQ=0V, unless otherwise noted)
Symbol
Parameter
Test Conditions
VOH (DC)
High-Level Output Voltage (DC)
IOH=-2mA
VOL (DC)
Low-level Output Voltage (DC)
IOL= 2mA
IOZ
Off-state Output Current
Q floating VO= 0 -- VDDQ
II
Input Current
VIH = 0 -- VDDQ +0.3V
Preliminary
30
Min.
Max.
Unit
V
2.4
0.4
V
-10
10
µA
-10
10
µA
Rev 1.0
Feb. 2001
EM639165
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, VDD=VDDQ=3.3±0.3V,VSS=VSSQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Symbol
-75
Parameter
Max.
Min.
tCLK
CLK cycle time
-8
Min.
Unit
Max.
CL=2
10
10
ns
CL=3
7.5
8
ns
tCH
CLK High pulse width
2.5
3
ns
tCL
CLK Low pulse width
2.5
3
ns
tT
Transition time of CLK
1
tIS
Input Setup time
(all inputs)
1.8
2
ns
tIH
Input Hold time
(all inputs)
1
1
ns
tRC
Row Cycle time
67.5
70
ns
tRFC
tRCD
Refresh Cycle Time
Row to Column Delay
75
80
ns
20
20
ns
tRAS
Row Active time
45
tRP
Row Precharge time
20
20
ns
tWR
Write Recovery time
15
20
ns
tRRD
Act to Act Delay time
15
20
ns
tRSC
Mode Register Set Cycle time
15
20
ns
tREF
Refresh Interval time
10
100K
64
CLK
1.4V
DQ
1.4V
1
48
10
100K
64
ns
ns
ms
Any AC timing is referenced
to the input signal passing
through 1.4V.
Preliminary
31
Rev 1.0
Feb. 2001
EM639165
SWITCHING CHARACTERISTICS
(Ta=0 - 70˚C, VDD=VDDQ=3.3±0.3V,VSS=VSSQ=0V, unless otherwise noted)
-75
Symbol
-8
Parameter
Unit
Max.
Min.
tAC
tOH
Min.
Note
Max.
CL=2
6
6
ns
CL=3
5.4
6
ns
Access time from CLK
Output Hold time
from CLK
CL=2
3
3
ns
CL=3
3
3
ns
0
ns
tOLZ
Delay time , output lowimpedance from CLK
0
tOHZ
Delay time , output highimpedance from CLK
3
5.4
6
3
*1
ns
NOTE:
1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Output Load Condition
CLK
VOUT
1.4V
50pF
1.4V
DQ
Output Timing Measurement
Reference Point
1.4V
CLK
tOLZ
DQ
1.4V
tAC
Preliminary
tOHZ
tOH
32
Rev 1.0
Feb. 2001
EM639165
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
DQ
X
0
D0
ACT#0
Preliminary
Y
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
33
ACT # 0
0
D0
D0
D0
WRITE#0
PRE#0
Rev 1.0
Feb. 2001
EM639165
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRAS
tRP
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
DQ
Y
X
0
1
D0
D0
Y
D0
ACT#0 WRITE#0
ACT#1
Preliminary
D0
X
1
0
D1
D1
PRE#0
D1
34
0
0
D1
D0
ACT# 0
WRITEA#1
(Auto-Precharge)
Y
X
1
D0
D0
0
D0
WRITE#0
PRE#0
ACT#1
Rev 1.0
Feb. 2001
EM639165
Burst Read (single bank) @BL=4 CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS
tRP
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
Y
0
DQ
0
Q0
ACT#0
Preliminary
X
READ# 0
Q0
0
Q0
Y
0
Q0
PRE#0
35
ACT# 0
0
Q0
READ# 0
Q0
Q0
Q0
PRE#0
Rev 1.0
Feb. 2001
EM639165
Burst Read (multiple bank) @BL=4 CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRRD
tRAS
/RAS
tRCD
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
Y
X
0
Y
1
DQ
X
1
Q0
Q0
Q0
0
Q0
ACT#0 READA# 0
ACT#1
Preliminary
Y
Q1
ACT# 0
X
0
Q1
Q1
1
Q1
Q0
READ# 0
0
Q0
Q0
Q0
PRE#0
ACT# 1
READA# 1
36
Rev 1.0
Feb. 2001
EM639165
Write Interrupted by Write @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
DQ
Y
X
0
1
D0
D0
ACT#0 WRITE# 0
ACT#1
Preliminary
Y
Y
0
D0
D0
Y
1
D0
D1
0
D1
WRITE# 0 WRITEA# 1
interrupt
interrupt
other
same
bank
bank
37
X
D1
D0
0
D0
WRITE# 0
interrupt
other
bank
D0
1
D0
PRE#0
ACT# 1
Rev 1.0
Feb. 2001
EM639165
Read Interrupted by Read @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
Y
0
X
1
DQ
ACT#1
Y
1
Q0
ACT#0 READ#0
Preliminary
Y
Q0
READ#1
interrupt
other
bank
Y
1
Q0
Q1
0
Q1
READA# 1
interrupt
same bank
38
X
Q1
Q1
READ# 0
interrupt
other
bank
1
Q1
Q0
Q0
Q0
Q0
ACT# 1
Rev 1.0
Feb. 2001
EM639165
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
DQ
Y
Y
Y
0
1
1
D0
ACT#0
D0
WRITE# 0
Q1
READ#1
Q1
D1
1
D1
WRITE# 1
D1
D1
PRE#1
ACT#1
Preliminary
39
Rev 1.0
Feb. 2001
EM639165
Write/Read Terminated by Precharge @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
DQ
X
0
D0
ACT#0
Preliminary
Y
0
0
Y
0
D0
WRITE# 0
X
0
Q0
PRE#0 ACT#0
Te rminate
40
READ# 0
0
Q0
PRE#0
ACT#0
Te rminate
Rev 1.0
Feb. 2001
EM639165
Write/Read Terminated by Burst Terminate @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Y
Y
0
0
0
D0
ACT#0
Preliminary
Y
D0
Q0
Q0
WRITE# 0 TERM READ# 0 TERM
41
D0
0
D0
WRITE#0
D0
D0
PRE#0
Rev 1.0
Feb. 2001
EM639165
Single Write Burst Read @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Y
Y
0
0
D0
ACT#0 WRITE# 0
Preliminary
Q0
Q0
Q0
Q0
READ# 0
42
Rev 1.0
Feb. 2001
EM639165
Power-Up Sequesce and Intialize
CLK
200µs
/CS
tRP
tRFC
tRFC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-8
MA
X
A10
0
X
A9,11
0
X
BA0,1
0
0
DQ
NOP
Power On
PRE ALL REFA
REFA
REFA
MRS
ACT# 0
Minimum 8 REFA cycles
Preliminary
43
Rev 1.0
Feb. 2001
EM639165
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Y
0
D0
PRE ALL
REFA
ACT#0
D0
D0
D0
WRITE#0
All banks m ust be idle before REFA is issued.
Preliminary
44
Rev 1.0
Feb. 2001
EM639165
Self Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-8,
X
A10
X
A9,11
X
BA0,1
0
DQ
PRE ALL Self Refres h Entry
Self Refres h Exit
ACT#0
All banks m ust be idle before REFS is issued.
Preliminary
45
Rev 1.0
Feb. 2001
EM639165
CLK Suspension @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Y
Y
0
0
D0
D0
D0
D0
ACT#0 WRITE# 0 internal
CLK
suspended
Preliminary
Q0
READ# 0
46
Q0
Q0
Q0
internal
CLK
suspended
Rev 1.0
Feb. 2001
EM639165
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
PRE ALL
Preliminary
ACT# 0
47
Rev 1.0
Feb. 2001
EM639165
54 Pin TSOP II Package Outline Drawing Information
28
E
HE
0.254
54
θ°
L
L1
1
27
S
Symbol
B
e
y
Dimension in inch
Min
Normal
Max
0.047
0.002
0.00395
0.0059
0.0411
0.012
0.015
0.016
0.0047
0.0065
0.0083
0.872
0.8755
0.879
0.3960
0.400
0.4040
0.0315
0.462
0.466
0.470
0.016
0.020
0.0235
0.033
0.035
0.004
0°
5°
C
A1 A2
A
D
L
L1
Dimension in mm
Min
Normal
Max
1.194
0.05
0.1
0.150
1.044
0.3
0.35
0.40
0.120
1.165
0.210
22.149
22.238
22.327
10.058
10.16
10.262
0.80
11.735
11.8365
11.938
0.406
0.50
0.597
0.84
0.88
0.10
0°
5°
A
A1
A2
B
c
D
E
e
HE
L
L1
S
y
q
Notes:
1. Dimension D & E do not include interiead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension: mm
Preliminary
48
Rev 1.0
Feb. 2001