G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Features : Description : ∗ The GLT6400L08 is a low power CMOS Static RAM organized as 524,288 x 8 bits. Easy memory expansion is provided by an active LOW CE1 an Low-power consumption. -active: 45mA at 85ns. -stand by : 20 µA (CMOS input / output) 5 µA (CMOS input / output, SL) ∗ Single +2.7 to 3.3V power supply. active LOW OE , and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. ∗ Equal access and cycle time. Writing to the device is accomplished by taking ∗ 85 ns access time at 2.7V to 3.3V 70ns chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW. ∗ ∗ ∗ ∗ ∗ access time at 3V to 3.6V 1.0V data retention mode. TTL compatible, tri-state input/output. Automatic power-down when deselected. Industrial grade (-40°C ~ 85°C) available. Package available: sTSOP , SOP. Reading from the device is performed by taking Chip Enable 1 ( CE1 ) with Output Enable ( OE ) LOW while Write Enable ( WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected : the outputs are disabled during a write cycle. The GLT6400L08 comes with a 1V data retention feature and Lower Standby Power. The GLT6400L08 is available in a 32-pin sTSOP packages,and 32pin SOP package. Function Block Diagram : SENSE AMP ROW DECODER Row Address INPUT BUFFER Cell Array COLUMN DECODER I/O7 I/O1 CONTROL CIRCUIT OE WE CE1 CE2 Column Address G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Pin Configurations : GLT6400L08 GLT6400L08 sTSOPI A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 H X L L L X X H H L OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin Descriptions: Name A0 – A18 CE 1 OE WE I/O0 – I/O7 VCC GND NC Truth Table: CE1 WE SOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Function Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input and Data Output Power Supply Ground No Connection OE Data X X L H X High-Z High-Z Data Out High-Z Data Out Mode Standby Standby Active, Read Active, Output Disable Active, Write *Key : X = Don’t Care, L = Low, H = High G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Absolute Maximum Ratings* Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 Vcc+0.3 V PT Tstg Tbias -55 -40 1.0 +150 +85 W Power Dissipation Storage Temperature (Plastic) Temperature Under Bias °C °C *Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Parameter Symbol Supply Voltage Input Voltage * VCC Gnd VIH VIL Min Typ Max Unit 2.7 0.0 2.0 -0.5* 3 0.0 - 3.3 0.0 VCC+0.2 0.6 V V V V VIL min = -1.0V for pulse width less than tRC/2. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) DC Operating Characteristics ( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V) Parameter Input Leakage Current Sym. ILI Output Leakage Current ILO Operating Power Supply Current ICC Min VCC = Max, Vin = Gnd to VCC 85 Max 1 Min Max 1 Unit µA 1 1 µA 3 5 mA 25 45 mA 3 3 mA 0.5 0.3 mA 5 20 µA 1 5 µA 0.4 V CE1 =VIH VCC = Max, VOUT = Gnd to VCC CE1 =VIL , VIN=VIH or VIL, IOUT=0mA ICC1 Average Operating Current 70 Test Conditions CE1 =VIL , IOUT = 0mA, Min Cycle, 100% Duty ICC2 CE1 =0.2V IOUT = 0mA, Cycle Time=1µs, 100% Duty Standby Power Supply ISB Current(TTL Level) Standby Power Supply ISB1 Current (CMOS Level) CE1 =VIH CE1 ≥ VCCGLT6400L08LL 0.2V or f=0 VIN ≤ 0.2V or VIN ≥ VCC-0.2V GLT6400L08SL Output Low Voltage VOL IOL = 2 mA Output High Voltage VOH IOH = -1 mA 0.4 2.4 2.4 Data Retention Parameter Sym. VCC for Data retention VDR CE1 ≥ VCC -0.2V or Data Retention Current ICCDR Chip Deselect to Data Retention Time tCDR VIN ≥ VCC -0.2V or VIN ≤ 0.2V Operating Recovery Time(2) tR Test Conditions V Min. Max. Unit 1.0 - V - 4 µA 0 - ns tRC - ns G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Data Retention Waveform Data Retention Mode Vcc 2.7V 2.7V VDR >= 1.0V tCDR CE tR VIH VIH VDR AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Level AC Test Loads and Waveforms 0.4V to 2.4V 5 ns TTL CL* 1.4V Output Load Condition CL = 30pf + 1TTL Load *Including Scope and Jig Capacitance Read Cycle (3,9)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V ) Parameter 70 Symbol Min 85 Max 70 Min Unit Note Max Read Cycle Time tRC Address Access Time tAA 70 85 85 ns ns Chip Enable Access Time tACE 70 85 ns Output Enable Access Time tOE 40 40 ns Output Hold from address Change tOH 10 10 ns Chip Enable to Output in Low-Z tCLZ 10 10 ns 4,5 Chip Disable to Output in High-Z tCHZ ns 4,5 Output Enable to Output in Low-Z tOLZ ns 4,5 Output Disable to Output in High-Z tOHZ ns 4,5 Power-Up Time tPU ns 5 Power-Down Time tPD ns 5 25 5 35 5 25 0 30 0 70 85 G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled) tRC Address tAA tOH Data Valid DOUT Timing Waveform of Read Cycle 2 (5,6,8,9) ( CE1 Controlled) CE1 tRC OE tOE tACE tOHZ tCHZ tOLZ DOUT Data Valid tCLZ tPD ICC tPU Supply Current 50% 50% ISB Write Cycle (3,11)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V ) Parameter 70 Symbol Min 85 Max Min Unit Note Max Write Cycle Time tWC 70 85 ns Chip Enable to Write End tCW 60 70 ns Address Setup to Write End tAW 60 70 ns Address Setup Time tAS 0 0 ns Write Pulse Width tWP 50 60 ns Write Recovering Time tWR 0 0 ns Data Valid to Write End tDW 30 35 ns Data Hold Time tDH 0 0 ns Write Enable to Output in High-Z tWZ Output Active from Write End tOW 25 5 35 5 ns 4,5 ns 4,5 G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Timing Waveform of Write Cycle 1 (10,11) ( WE Controlled) tWC tAW tWR Address WE tWP tAS tDW DIN tDH Data Valid tWZ tOW DOUT Timing Waveform of Write Cycle 2 (10,11) ( CE1 Controlled) tWC tAW tWR Address tAS tCW CE1 tWP WE tDW tWZ DIN tDH Data Valid DOUT G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Notes : 1. 2. 3. 4. 5. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state voltage. This parameter is guaranteed, but is not tested. 6. WE 7. CE1 and OE is HIGH for read cycle. are LOW and for read cycle. 8. Address valid prior to or coincident with CE1 transition LOW . 9. All read cycle timings are referenced from the last valid address to the first transition address. 10. CE1 or WE must be HIGH during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Ordering Information Part Number SPEED POWER PACKAGE GLT6400L08LL-70 ST GLT6400L08SL-70 ST GLT6400L08SLI-70 ST GLT6400L08SLI-70 ST GLT6400L08LL-85 ST GLT6400L08SL-85 ST GLT6400L08SLI-85 ST GLT6400L08SLI-85 ST GLT6400L08LL-70 FC GLT6400L08SL-70 FC GLT6400L08SLI-70 FC GLT6400L08SLI-70 FC GLT6400L08LL-85 FC GLT6400L08SL-85 FC GLT6400L08SLI-85 FC GLT6400L08SLI-85 FC 70ns 70ns 70ns 70ns 85ns 85ns 85ns 85ns 70ns 70ns 70ns 70ns 85ns 85ns 85ns 85ns Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L SOP 32L SOP 32L SOP 32L SOP 32L SOP 32L SOP 32L SOP 32L SOP 32L Parts Numbers (Top Mark) Definition : GLT 6 400 L 08 LL I - 85 TC 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 64K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO) 11 : 1M(C/FPM) 12 : 1M(H/EDO) 13 : 1M(H/FPM) 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 SPEED -SRAM 10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns VOLTAGE Blank : 5V L : 3.3V M : 2.5V N : 2.1V LL : Low Low power L : Low power SL : Super Low power PACKAGE T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP (Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP FG : 48-fpBGA I : Industrial Temperature (-40°C~85°C) E : Extended Temperature (-25°C~85°C. Blank : 0°C~70°C. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) Package Information 32 pin 8x13.4mm Small Outline J-form Package (sTSOP) 32 pin 445mil Small Outline J-form Package SOP G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 -