APW7062B Synchronous Buck PWM Controller Features General Description • The APW7062B is a voltage mode and synchronous PWM controller which drives dual N-Channel MOSFETs. It inte- Simple Single-Loop Control Design - Voltage-Mode PWM Control • grates the control, monitoring, and protection functions into a single package, provides one controlled power Fast Transient Response - Full 0–100% Duty Ratio • • Excellent Output Voltage Regulation outputs with under-voltage and over-current protection. APW7062B provides excellent regulation for output load - 0.8V Internal Reference - ± 1% Over Line Voltage and Temperature variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the requirement of Over Current Fault Monitor low output voltage applications. It includes a 200kHz freerunning triangle-wave oscillator that is adjustable from - Uses Upper MOSFETs RDS (ON) • • 70kHz to 800kHz. The power-on-reset (POR) circuit monitors the VCC, EN, Converter Can Source and Sink Current Small Converter Size and OCSET input voltage to start-up or shutdown the IC. The over-current protection (OCP) monitors the output - 200kHz Free-Running Oscillator - Programmable from 70kHz to 800kHz • • current by using the voltage drop across the upper MOSFET’s RDS(ON), eliminating the need for a current sens- 14-Lead SOIC Package Lead Free and Green Devices Available ing resistor. The under-voltage protection (UVP) monitors the voltage of the FB pin for short-circuit protection. (RoHS Compliant) The over-current protection trip cycle the soft-start function until the fault events be removed. Under-voltage protection will shutdown the IC directly. Applications • • • • Pin Configuration Graphic Cards DDR Memory Power Supply DDR Memory Termination Voltage Low-Voltage Distributed Power Supplies RT 1 14 VCC OCSET 2 13 PVCC SS 3 12 LGATE COMP 4 11 PGND FB 5 10 BOOT EN 6 9 UGATE GND 7 8 PHASE ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 1 www.anpec.com.tw APW7062B Ordering and Marking Information Package Code K : SOP-14 Operating Ambient Temperature Range C : 0 to 70 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7062B Assembly Material Handling Code Temperature Range Package Code APW7062B XXXXX APW7062B K : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Parameter Rating Unit VCC to GND 30 V VBOOT BOOT to GND 30 V VPHASE PHASE to GND 30 VCC Operating Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds V 0~150 o -65 ~ 150 o 260 o C C C Note 1 : Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. Electrical Characteristics APW7062B Symbol Parameter Test Conditions Min. Typ. Unit Max. VCC SUPPLY CURRENT ICC Nominal Supply EN=VCC; UGATE and LGATE Open - 2 - mA Shutdown Supply EN=0V - 250 350 µA VOCSET=4.5VDC - - 10.4 V POWER-ON-RESET Rising VCC Threshold Falling VCC Threshold VOCSET=4.5VDC 8.8 - - V Enable-Input Threshold Voltage VOCSET=4.5VDC 0.8 - 2.0 V - 1.27 - V RT=OPEN, VCC=12 170 200 230 kHz Total Variation 6kΩ < RT to GND < 200kΩ -15 - +15 % Ramp Amplitude RT=OPEN - 1.9 - VP-P Reference Voltage Tolerance -1 - +1 % PWM Error Amplifier - 0.80 - V Rising VOCSET Threshold OSCILLATOR Free Running Frequency ∆VOSC REFERENCE VOLTAGE ACCURACY ∆VREF VREF Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 2 www.anpec.com.tw APW7062B Electrical Characteristics (Cont.) APW7062B Symbol Parameter Test Conditions Unit Min. Typ. Max. 650 800 - mA - 4 7 Ω mA GATE DRIVERS IUGATE Upper Gate Source VBOOT=12V, VUGATE=6V RUGATE Upper Gate Sink ILGATE=0.3A ILGATE Lower Gate Source PVCC=12V, VLGATE=6V 550 700 - RLGATE Lower Gate Sink ILGATE=0.3A - 4 7 Ω Dead Time VOUT=2.5V, IOUT=1A, RT=OPEN - 50 - ns - 50 - % 170 200 230 µA 8 10 12 µA TD PROTECTION FB Under Voltage IOCSET ISS OCSET Current Source VOCSET=4.5VDC Soft-Start Current Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 3 www.anpec.com.tw APW7062B Typical Operating Characteristics Power Up V CC(5V/div) Power Down VCC=12V, VIN=12V VOUT=2.5V, L=2.2uH V CC(5V/div) VCC=12V, VIN=12V VOUT=2.5V, L=2.2uH SS(2V/div) SS(2V/div) VOUT(1V/div) VOUT(1V/div) Time(10µs/div) Time(10µs/div) Enable (EN = VCC) Shutdown (EN=GND) EN(10V/div) EN(10V/div) VCC=12V, VIN=12V VOUT=2.5V, L=2.2uH SS(2V/div) SS(2V/div) VOUT(1V/div) VOUT(1V/div) Time(10µs/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 VCC=12V, VIN=12V VOUT=2.5V, L=2.2uH Time(2µs/div) 4 www.anpec.com.tw APW7062B Typical Operating Characteristics (Cont.) Load Transient Response VOUT(100mV/div) Under Voltage Protection VCC=12V, VIN=12V VOUT=2.5V, RT=Open L=2.2uH VCC=12V, VIN=12V VOUT=2.5V, L=2.2uH VOUT(2V/div) SS(5V/div) IOUT(2A/div) IL(10A/div) UGATE(20V/div) Time(20µs/div) Time(20µs/div) UGATE Rising UGATE Falling VCC=12V, VIN=12V VOUT=2.5V, RT=Open VCC=12V, VIN=12V VOUT=2.5V, RT=Open UGATE(10V/div) UGATE(10V/div) LGATE(10V/div) LGATE(10V/div) Phase(10V/div) Phase(10V/div) Time(50µs/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 Time(50µs/div) 5 www.anpec.com.tw APW7062B Typical Operating Characteristics (Cont.) UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 1.2 1.4 1 UGATE Sink Current (A) UGATE Source Current (A) V BOOT=12V V BOOT=12V 1.2 1 0.8 0.6 0.4 0.8 0.6 0.4 0.2 0.2 0 0 0 2 4 6 8 10 12 0 2 UGATE Voltage (V) 6 8 10 12 UGATE Voltage (V) LGATE Source Current vs. LGATE Voltage LGATE Sink Current vs. LGATE Voltage 1.2 1.4 PVCC=12V PVCC=12V 1.2 1 LGATE Sink Current (A) LGATE Source Current (A) 4 1 0.8 0.6 0.4 0.8 0.6 0.4 0.2 0.2 0 0 0 2 4 6 8 10 0 12 LGATE Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 2 4 6 8 10 12 LGATE Voltage (V) 6 www.anpec.com.tw APW7062B Typical Operating Characteristics (Cont.) RT Resistance vs. Switching Frequency Over Current Protection 10000 VOUT(1V/div) RT pull up to 12V RT Resistance (kΩ) 1000 SS(5V/div) IL(10A/div) 100 RT pull down to GND 10 UGATE(20V/div) 1 10 100 Time(20µs/div) 1000 Switching Frequency (kHz) VCC=12V, VIN=12V, VOUT=2.5V, ROCEST=1KΩ, RT=Open, RDS(ON)=14mΩ, IOUT=16.3A, L=2.2uH, LOUT=16.3A Reference Voltage vs. Junction Temperature Switching Frequency vs. Junction Temperature 0.8 220 210 Switching Frequency 0.798 Reference Voltage (V) VCC=12V RT=Open 0.796 0.794 0.792 200 190 180 170 160 0.79 -40 -20 0 20 40 60 80 -40 100 120 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 -20 0 20 40 60 80 100 120 Junction Temperature (°C) 7 www.anpec.com.tw APW7062B Block Diagram VCC GND OCSET Power-On Reset EN IOCSET 200µA VCC UGATE ISS 10µA O.C.P Comparator Soft Start SS BOOT PHASE 5.8V U.V.P Comparator :2 50%VREF PVCC PWM Comparator Gate Control LGATE Error Amp PGND VREF Oscillator COMP FB Triangle Wave RT Typical Application Circuit 12V C1 R1 10R 1uF D1 12V R2 10K 1 2 3 4 5 6 7 NC RT VCC OCSET PVCC SS LGA TE COMP PGND FB BOOT EN UGATE GND PHASE C7 0.1uF 1uH 1K U1 A PW7062B R4 L1 R3 1N4148 14 13 12 11 10 9 8 C2 R5 1nF C13 47pF C12 8200pF VOUT = VREF × 1 + 1 2 3 2R2 C8 0.1uF R6 + C4 100uF 16V 1.2V L2 8 7 6 5 2.2uH R7 NC Q2 A PM4220 4 1 2 3 0R D2 SR24 2A/40V C12 NC R8 1KF 1% + C9 1000uF 6.3V 30mR + C10 1000uF 6.3V 30mR C11 4.7uF R9 2KF 1% R8 R9 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 C5 4.7uF + C6 470uF 16V 30mR Q1 A PM4220 4 R10 15K SHDN 8 7 6 5 + C3 470uF 16V 30mR 8 www.anpec.com.tw APW7062B Function Pin Description RT (Pin1) output is rising rapidly. Until the output is in regulation at t2, the clamp on the COMP is released. This method pro- This pin can adjust the switching frequency. Connect a resistor from the RT to the GND for increasing the switch- vides a rapid and controlled output voltage rise. W hen over-current protection occurs, the VOUT is ing frequency: FS = 200kHz + shutdown, and re-soft-start again, if the over current condition still exists in soft-start, the VOUT is shutdowned 4.15 × 10 6 RT again. After the SS reaches 4.5V, the SS is discharged to zero. The soft-start is recurring until the over current con- (RT to GND, FS = 200kHz to 400kHz) Conversely, connect a resistor from the RT to the VCC for decreasing the switching frequency: dition is eliminated. VOLTAGE 3.51 × 10 7 FS = 200kHz RT VSOFT-START (RT to V CC , FS = 200kHz to 75kHz) OCSET (Pin2) VOUT This pin serves two functions: a shutdown control and the setting of over current-limit threshold. Pulling this pin below 1.27V will shutdown the controller, forcing the UGATE and LGATE signals to be at 0V. Error Amp Output VOSC(MIN) VSS=1.2V A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine the over current t0 limit. An internal 200µA current source will flow through this resistor, creating a voltage drop, which will be com- IPEAK = TIME t3 Figure 1. Soft-Start Interval pared with the voltage across the high side MOSFET. The threshold of the over current limit is therefore given by: t2 t1 t2 = IOCSET (200uA ) × ROCSET CSS ISS × (VOSC(MIN)+ t1) tSoftStart = t3 − t2 = RDS(ON) To avoid the noise interference from switching transient, a delay time is designed in the OCP comparator. CSS × ISS V OUT SteadyState VIN × ∆VOSC Where : t1=1.2V The over-current protection is active only when the high side MOSFET is turned on longer than 300ns. CSS = Soft-Start Capacitor ISS = Soft-Start Current = 10µA SS (Pin3) Connect a capacitor from the pin to the GND to set the VOSC(MIN) = Bottom of Oscillator = 1.35V VIN = Input Voltage soft-start interval of the converter. An internal 10µA current source charges this capacitor to 5.8V. The SS voltage ∆Vosc = Peak to Peak Oscillator Voltage = 1.9V ∆VOUTSteadyState = Steady State Output Voltage clamps the error amplifier output, and Figure1 shows the soft-start interval. At t1, the SS voltage reaches the valley of the oscillator’s triangle wave. The PWM comparator starts to generate a PWM signal to control logic, and the Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 9 www.anpec.com.tw APW7062B Function Pin Description (Cont.) COMP (Pin4) BOOT (Pin 10) This pin is the output of the error amplifier. Add an external resistor and capacitor network to provide the loop com- This pin provides the supply voltage to the high side MOSFET driver. For driving logic level N-channel MOSEFT, pensation for the PW M converter (see Application Information). a bootstrap circuit can be used to create a suitable driver’s supply. FB (Pin5) PGND (Pin11) FB pin is the inverter input of the error amplifier and it receives the feedback voltage from an external resis-tive Power ground for the gate diver. Connect the lower MOSFET source to this pin. divider across the output (V OUT). The output voltage is determined by: LGATE (Pin 12) VOUT = 0.8V × 1 + ROUT RGND Connect the pin to the external MOSFET, and provides the gate drive signal for the lower MOSFET. Where ROUT is the resistor connected from the VOUT to the FB and RGND is the resistor connected from the FB to the PVCC (Pin13) GND. If the FB voltage is under 50% VREF because of the short circuit or other influence , it will cause the under-voltage This pin provides a supply voltage for the lower gate drive, connect it to the VCC pin in common use. protection, and the device is shutdowned. Remove the error condition and restart the VCC voltage or pull the EN VCC (Pin14) from low to high once, the device can be enabled again. the VCC is above the rising threshold 10.4V, the device is turned on; conversely, when the VCC is below the falling This pin provides a supply voltage for the device. When EN (Pin6) threshold, the device is turned off. Pull the pin higher than 2V to enable the device, and pull the pin lower than 0.8V to shutdown the device. In shutdown, the SS is discharged and the UGATE and LGATE pins are held low. The EN pin is the open-collector, and it will not be floating. GND (Pin7) Signal ground for the IC. PHASE (Pin8) This pin is connected to the source of the high-side MOSFET and is used to monitor the voltage drop across the high-side MOSFET for over-current protection. UGATE (Pin9) Connect the pin to external MOSFET, and provides the gate drive for the upper MOSFET. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 10 www.anpec.com.tw APW7062B Application Information Component Selection Guidelines Output Capacitor Selection The selection of COUT is determined by the required effec- and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose tive series resistance (ESR) and voltage rating rather than the actual capacitance requirement. Therefore, select high the ripple current to be approximately 30% of the maximum output current. performance low ESR capacitors that are intended for switching regulator applications. In some applications, Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak cur- multiple capacitors have to be paralled to achieve the desired ESR value. If tantalum capacitors are used, make rent without going into saturation. In some types of inductors, especially core that is make of ferrite, the ripple sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Input Capacitor Selection Compensation The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select The output LC filter introduces a double pole, which contributes with –40dB/decade gain slope and 180 degrees the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS phase shift in the control loop. A compensation network between the COMP pin and the ground should be added. current rating requirement is approximately IOUT/2 , where IOUT is the load current. During power up, the input capaci- The simplest loop compensation network is shown in Figure 5. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is tors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors given by: manufacturer. For high frequency decoupling, a ceramic capacitor be- GAINLC = tween 0.1µF to 1µF can be connected between the VCC and the ground pin. The poles and zero of this transfer function are: Inductor Selection The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the lower the inductor’s current ripple. This will translate into lower output ripple voltage. The ripple current and ripple VIN - VOUT FS x L x FLC = 1 2 × π × L × COUT FESR = 1 2 × π × ESR × COUT The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. voltage can be approximated by: IRIPPLE = 1 + s × ESR × COUT s2 × L × COUT + s × ESR + 1 VOUT PHASE L Output VIN COUT ∆VOUT = IRIPPLE x ESR where Fs is the switching frequency of the regulator. There is a tradeoff exists between the inductor’s ripple ESR current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 Figure 2. The Output LC Filter 11 www.anpec.com.tw APW7062B Application Information (Cont.) The compensation circuit is shown in Figure 5. R3 and C1 introduce a zero and C2 introduces a pole to reduce Compensation (Cont.) the switching noise. The transfer function of error amplifier is given by: FLC -40dB/dec 1 1 GAINAMP = gm× Zo = gm × R3 + sC1 // sC2 FESR Gain -20dB/dec = gm × (R3sC1 + 1) s × s + C1 + C2 R3 × C1× C2 The poles and zero of the compensation network are: Frequency Figure 3. The Output LC Filter Gain & Frequency FP = The PWM modulator is shown in Figure 4. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given FZ by: VIN GAINPWM = ∆VOSC = 1 2 × π × R3 × C1× C2 C1 + C2 1 2 × π × R3 × C1 VOUT VIN Error Amplifier R1 Driver FB - PWM Comparator R2 VOSC + VREF COMP R3 C2 C1 Output of Error Amplifier PHASE Figure 5. Compensation Network Driver Figure 4. The PWM Modulator Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 12 www.anpec.com.tw APW7062B Application Information (Cont.) Compensation (Cont.) MOSFET Selection The closed loop gain of the converter can be written as: The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement.The losses in R2 x GAINAMP GAINLC x GAINPWM x R1 + R2 the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the Figure 6 shows the converter gain and the following guidelines will help to design the compensation network. losses are approximately given by the following : 1.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS >FO>FZ PUPPER = Iout2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS Use the following equation to calculate R3: PLOWER = Iout2(1+ TC)(RDS(ON))(1-D) R3 = ∆VOSC FESR R1 + R2 FO × × × VIN R2 gm FLC 2 where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval Where: gm=900µA/V 2.Place the zero FZ before the LC filter double poles FLC: D is the duty cycle Note that both MOSFETs have conduction losses while FZ = 0.75 x FLC Calculate the C1 by the equation: the upper MOSFET include an additional transition loss. The switching internal, tsw, is the function of the reverse transfer capacitance CRSS. Figure 7 illustrates the switching waveform internal of the MOSFET. 1 2 × π × R1× FLC × 0.75 C1 = The (1+TC) term is to factor in the temperature depen3. Set the pole at the half the switching frequency: FP = 0.5xFS Calculate the C2 by the equation: C2 = dency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Layout Consideration In high power switching regulator, a correct layout is im- C1 π × R3 × C1× FS − 1 portant to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short and wide printed circuit traces. Signal and power grounds are to be kept separate and finally FZ=0.75FLC FP=0.5FS 20⋅ log(gm⋅ R3) combined using ground plane construction or single point grounding. Figure 8 illustrates the layout, with bold lines Compensation Gain FLC 20 ⋅ log indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: • Keep the switching nodes (UGATE, LGATE, and FO VIN ? VOSC FESR PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. There fore keep Converter Gain PWM & Filter Gain Frequency Figure 6. Converter Gain & Frequency • traces to these nodes as short as possible. The ground return of CIN must return to the combine • COUT (-) terminal. Capacitor CBOOT should be connected as close to the BOOT and PHASE pins as possible. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 13 www.anpec.com.tw APW7062B Application Information (Cont.) Layout Consideration (Cont.) drain and source of MOSFET Voltage across VDS tsw Time Figure 7. Switching waveform across MOSFET VIN CIN APW7062B PGND LGATE 11 + 12 U 9 1 UGATE COUT Q1 Q2 PHASE 8 + L1 L O A D VOUT Figure 8. Recommended Layout Diagram Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 14 www.anpec.com.tw APW7062B Package Information SOP-14 D E E1 SEE VIEW A h X 45 ° e c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 b L VIEW A S Y M B O L SOP-14 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 5.80 6.20 0.228 0.244 3.80 4.00 0.150 0.157 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° E1 e 0.049 1.27 BSC 0.050 BSC 8° Note: 1. Follow JEDEC MS-012 AB. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 15 www.anpec.com.tw APW7062B Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-14 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 9.00±0.20 2.10±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOP-14 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 16 www.anpec.com.tw APW7062B Taping Direction Information SOP-14 USER DIRECTION OF FEED t Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 17 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APW7062B Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm <350 Volume mm ≥350 <2.5 mm ≥2.5 mm 240 +0/-5°C 225 +0/-5°C 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 Package Thickness 3 Volume mm <350 Volume mm 350-2000 3 Volume mm >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2008 18 www.anpec.com.tw