Cypress CY8C21223-24LGXI Psoc programmable system-on-chip Datasheet

CY8C21123, CY8C21223, CY8C21323
PSoC® Programmable System-on-Chip™
Features
■
■
Powerful Harvard Architecture Processor:
❐ M8C Processor Speeds to 24 MHz
❐ Low Power at High Speed
❐ 2.4V to 5.25V Operating Voltage
❐ Operating Voltages down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC® Blocks):
❐ Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC Refs
• Single or Dual 8-Bit 8:1 ADC
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
❐ Full Duplex UART, SPI™ Master or Slave: Connectable to All
GPIO Pins
❐ Complex Peripherals by Combining Blocks
■
Logic Block Diagram
Port 1
Complete Development Tools:
™
❐ Free Development Software (PSoC Designer )
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 Bytes Trace Memory
■
Precision, Programmable Clocking:
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations:
❐ 25 mA Sink, 10 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Eight Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
Cypress Semiconductor Corporation
Document Number: 38-12022 Rev. *K
•
198 Champion Court
Port 0
PSoC
CORE
SystemBus
Global Digital Interconnect
Global Analog Interconnect
SROM
SRAM
Flexible On-Chip Memory:
❐ 4K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
■
Additional System Resources:
2
❐ I C™ Master, Slave and MultiMaster to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
Flash
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC Block
Array
Digital
Clocks
ANALOG SYSTEM
Analog
PSoC Block
Array
POR and LVD
I2C
System Resets
Sw itch
Mode
Pump
Analog
Ref.
Internal
Voltage
Ref.
SYSTEM RESOURCES
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 29, 2009
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CY8C21123, CY8C21223, CY8C21323
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chip controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, as shown in Figure 1, consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 General Purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
Digital System
The Digital System consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral
configurations include:
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to four)
■
SPI master and slave
■
I2C slave, master, MultiMaster (one available as a System
Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to four)
PSoC Core
■
Pseudo Random Sequence Generators (8 to 32 bit)
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC Programmable
System-on-Chips, I2C functionality for implementing an I2C
master, slave, MultiMaster, an internal voltage reference that
provides an absolute value of 1.3V to a number of PSoC
subsystems, a switch mode pump (SMP) that generates normal
operating voltages off a single battery cell, and various system
resets supported by the M8C.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 3.
Figure 1. Digital System Block Diagram
Port 1
Port 0
To System Bus
DigitalClocks
FromCore
The Digital System consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
8
8
GIE[7:0]
GIO[7:0]
Document Number: 38-12022 Rev. *K
Row Output
Configuration
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
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Analog System
Additional System Resources
The Analog System consists of four configurable blocks to allow
creation of complex analog signal flows. Analog peripherals are
very flexible and may be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
System Resources, some of which listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. The merits of each
system resource are.
■
Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
■
■
Pin-to-pin comparators (one)
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■
■
1.3V reference (as a System Resource)
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
The number of blocks on the device family is listed in Table 1.
Figure 2. CY8C21x23 Analog System Block Diagram
Array Input
Configuration
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or
4 analog blocks. Table 1 lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted.
Table 1. PSoC Device Characteristics
Flash
SRAM
Size
PSoC Part
Number
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
ACI1[1:0]
Digital
IO
ACI0[1:0]
ACOL1MUX
CY8C29x66
up to 4
64
16
12
4
4
12
2K
32
K
Array
CY8C27x43
up to 2
44
8
12
4
4
12
256
Bytes
16
K
CY8C24x94
56
1
4
48
2
2
6
1K
16
K
CY8C24x23A up to 1
24
4
12
2
2
6
256
Bytes
4K
CY8C21x34
up to 1
28
4
28
0
2
4[1] 512
Bytes
8K
CY8C21x23
16
1
4
8
0
2
4[1] 256
Bytes
4K
CY8C20x34
up to 0
28
0
28
0
0
3[2] 512
Bytes
8K
ACE00
ACE01
ASE10
ASE11
.
Notes
1. Limited analog functionality
2. Two analog blocks and one CapSense™
Document Number: 38-12022 Rev. *K
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Getting Started
Development Tools
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip™
Technical Reference Manual for CY8C28xxx PSoC devices.
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built in support for third party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication
interfaces. You define when and how an output device changes
state based upon any or all other system devices. Based upon
the design, PSoC Designer automatically selects one or more
PSoC Programmable System-on-Chip Controllers that match
your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Technical Support
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 38-12022 Rev. *K
Hybrid Designs
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Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write IO registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Online Help System
Configure Components
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 38-12022 Rev. *K
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
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Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the IO pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Document Conventions
Acronyms Used
This table lists the acronyms used in this data sheet.
Table 2. Acronyms
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose IO
ICE
in-circuit emulator
IDE
integrated development environment
IO
input/output
ISSP
in-system serial programming
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PGA
programmable gain amplifier
POR
power on reset
PPOR
®
precision power on reset
PSoC
Programmable System-on-Chip™
PWM
pulse width modulator
ROM
read only memory
SC
switched capacitor
SMP
switch mode pump
SRAM
static random access memory
Units of Measure
A units of measure table is located in the section
Electrical Specifications on page 15. Table 11 on page 15 lists all
the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Document Number: 38-12022 Rev. *K
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Pin Information
This section describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations. Every port pin (labeled with
a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout
Table 3. Pin Definitions - CY8C21123 8-Pin SOIC
Pin
No.
Type
Digital
Pin
Analog Name
Description
1
IO
I
P0[5]
Analog Column Mux Input
2
IO
I
P0[3]
Analog Column Mux Input
3
IO
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[3]
Vss
Ground Connection
P1[0]
I2C Serial Data (SDA), ISSP-SDATA[3]
4
Power
5
IO
6
IO
I
P0[2]
Analog Column Mux Input
7
IO
I
P0[4]
Analog Column Mux Input
Vdd
Supply Voltage
8
Power
Figure 3. CY8C21123 8-Pin SOIC
A, I, P0[5]
A, I, P0[3]
I2C SCL, P1[1]
Vss
1
8
2
7
SOIC6
3
5
4
Vdd
P0[4], A, I
P0[2], A, I
P1[0], I2CSDA
LEGEND: A = Analog, I = Input, and O = Output.
16-Pin Part Pinout
Table 4. Pin Definitions - CY8C21223 16-Pin SOIC
Pin
No.
Type
Digital
Pin
Analog Name
Description
1
IO
I
P0[7]
Analog Column Mux Input
2
IO
I
P0[5]
Analog Column Mux Input
3
IO
I
P0[3]
Analog Column Mux Input
4
IO
I
P0[1]
Analog Column Mux Input
5
Power
SMP
Switch Mode Pump (SMP) Connection to
required External Components
6
Power
Vss
Ground Connection
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[3]
Vss
Ground Connection
I2C Serial Data (SDA), ISSP-SDATA[3]
7
IO
8
Power
9
IO
P1[0]
10
IO
P1[2]
11
IO
P1[4]
Optional External Clock Input (EXTCLK)
12
IO
I
P0[0]
Analog Column Mux Input
13
IO
I
P0[2]
Analog Column Mux Input
14
IO
I
P0[4]
Analog Column Mux Input
15
IO
I
P0[6]
Analog Column Mux Input
Vdd
Supply Voltage
16
Power
Figure 4. CY8C21223 16-Pin SOIC
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
SMP
Vss
I2CSCL, P1[1]
Vss
1
2
3
4
5
6
7
8
SOIC
16
15
14
13
12
11
10
9
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P1[4],EXTCLK
P1[2]
P1[0], I2CSDA
LEGEND A = Analog, I = Input, and O = Output.
Document Number: 38-12022 Rev. *K
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Table 5. Pin Definitions - CY8C21223 16-Pin COL [3]
I
2
IO
I
3
IO
4
IO
P1[5]
I2C Serial Data (SDA)
5
IO
P1[3]
6
IO
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[3]
Vss
Ground Connection
I2C Serial Data (SDA), ISSP-SDATA[3]
7
Power
P0[3]
Analog Column Mux Input
P0[1]
Analog Column Mux Input
P1[7]
I2C Serial Clock (SCL)
8
IO
P1[0]
9
IO
P1[6]
10
IO
11
12
Input
IO
13
I
EXTCLK
XRES
Active High External Reset with Internal
Pull Down
P0[4]
VREF
Vdd
Supply Voltage
14
IO
I
P0[7]
Analog Column Mux Input
15
IO
I
P0[5]
Analog Column Mux Input
NC
No Connect
16
Power
P1[4]
NC
P0[5], AI
P0[7], AI
Vdd
Analog
IO
AI, P0[3]
AI, P0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
1
2
3
4
16
15
14
13
Digital
1
Figure 5. CY8C21223 16-Pin COL
12
11
(Top View) 10
9
COL
6
7
8
Description
5
Pin
Name
P1[3]
Type
I2C SCL, P1[1]
Vss
2C SDA, P1[0]
Pin
No.
P0[4], VREF
XRES
P1[4]
P1[6]
LEGEND A = Analog, I = Input, and O = Output.
Notes
3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12022 Rev. *K
Page 8 of 36
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
20-Pin Part Pinout
Table 6. Pin Definitions - CY8C21323 20-Pin SSOP
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
Digital Analog
IO
I
IO
I
IO
I
IO
I
Power
IO
IO
IO
IO
Power
IO
IO
IO
IO
Input
IO
IO
IO
IO
I
I
I
I
Power
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Ground Connection
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Figure 6. CY8C21323 20-Pin SSOP
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
SSOP
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],I2C SDA
I2C Serial Clock (SCL), ISSP-SCLK[3]
Ground connection
I2C Serial Data (SDA), ISSP-SDATA[3]
Optional External Clock Input (EXTCLK)
Active High External Reset with Internal
Pull Down
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Supply Voltage
LEGEND A = Analog, I = Input, and O = Output.
Document Number: 38-12022 Rev. *K
Page 9 of 36
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CY8C21123, CY8C21223, CY8C21323
24-Pin Part Pinout
Table 7. Pin Definitions - CY8C21323 24-Pin QFN[5]
15
16
17
18
19
20
21
22
23
24
Input
IO
IO
IO
IO
I
I
I
I
Power
Power
IO
IO
IO
I
I
I
NC
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
P0[3]
Optional External Clock Input (EXTCLK)
P0[7], A, I
Vss
Vdd
P0[6], A, I
20
19
P0[3], A, I
P0[5], A, I
18
17
QFN 16
(Top View) 15
14
13
11
12
IO
IO
IO
IO
1
2
3
4
5
6
P1[2]
EXTCLK, P1[4]
Power
I2C Serial Clock (SCL), ISSP-SCLK[3]
No Connection
Ground Connection
I2C Serial Data (SDA), ISSP-SDATA[3]
A, I, P0[1]
SMP
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
Vss
I2C SDA, P1[0]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
NC
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
23
22
21
Power
IO
IO
IO
IO
Analog Column Mux Input
Switch Mode Pump (SMP) Connection to
required External Components
Ground connection
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Figure 7. CY8C21323 24-Pin QFN
24
3
4
5
6
7
8
9
10
11
12
13
14
Description
7
8
9
10
1
2
Type
Pin
Digital Analog Name
IO
I
P0[1]
Power
SMP
I2C SCL, P1[1]
NC
Pin
No.
P0[4], A, I
P0[2], A, I
P0[0], A, I
NC
XRES
P1[6]
Active High External Reset with Internal
Pull Down
No Connection
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Supply Voltage
Ground Connection
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
LEGEND A = Analog, I = Input, and O = Output.
Note
5. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12022 Rev. *K
Page 10 of 36
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CY8C21123, CY8C21223, CY8C21323
Register Reference
Register Mapping Tables
This section lists the registers of the CY8C21x23 PSoC device.
For detailed register information, refer the PSoC Programmable
System-on-Chip Technical Reference Manual.
The PSoC device has a total register address space of
512 bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Table 8. Register Conventions
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 38-12022 Rev. *K
Page 11 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 9. Register Map Bank 0 Table: User Space
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Name
Access
00
RW
40
01
RW
41
81
C1
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
PRT1DR
04
RW
44
PRT1IE
05
RW
45
85
C5
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
08
48
88
C8
09
49
89
C9
0A
4A
8A
CA
0B
4B
8B
CB
0C
4C
8C
CC
0D
4D
8D
CD
0E
4E
8E
CE
0F
4F
8F
CF
10
50
90
D0
11
51
91
D1
12
52
92
D2
13
53
93
D3
14
54
94
D4
15
55
95
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
I2C_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
60
RW
84
RW
Addr
(0,Hex)
PRT0IE
ASE11CR0
80
Access
PRT0DR
AMX_IN
ASE10CR0
Addr
(0,Hex)
C0
C3
RW
C4
D5
DC
DF
DBB00DR0
20
#
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
DBB01DR0
24
#
DBB01DR1
25
W
DBB01DR2
26
RW
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
68
#
A8
E8
DCB02DR1
29
W
ADC1_CR
69
#
A9
E9
DCB02DR2
2A
RW
6A
AA
EA
DCB02CR0
2B
#
6B
AB
EB
DCB03DR0
2C
#
TMP_DR0
6C
RW
AC
EC
DCB03DR1
2D
W
TMP_DR1
6D
RW
AD
ED
DCB03DR2
2E
RW
TMP_DR2
6E
RW
AE
EE
DCB03CR0
2F
#
TMP_DR3
6F
RW
AF
EF
61
PWM_CR
62
RW
63
CMP_CR0
64
#
65
CMP_CR1
66
Document Number: 38-12022 Rev. *K
INT_MSK0
E0
RW
A1
INT_MSK1
E1
RW
A2
INT_VC
E2
RC
A3
RES_WDT
E3
W
A4
E4
A5
RW
67
Blank fields are Reserved and must not be accessed.
A0
E5
A6
DEC_CR0
E6
RW
A7
DEC_CR1
E7
RW
# Access is bit specific.
Page 12 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 9. Register Map Bank 0 Table: User Space (continued)
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
30
70
RDI0RI
B0
RW
F0
31
71
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
34
74
RDI0LT1
B4
RW
F4
35
75
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
Access
F6
CPU_F
F7
RL
38
78
B8
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
FD
# Access is bit specific.
Table 10. Register Map Bank 1 Table: Configuration Space
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Name
Access
00
RW
40
01
RW
41
81
C1
PRT0IC0
02
RW
42
82
C2
PRT0IC1
03
RW
43
83
PRT1DM0
04
RW
44
PRT1DM1
05
RW
45
85
C5
PRT1IC0
06
RW
46
86
C6
PRT1IC1
07
RW
47
87
C7
08
48
88
C8
09
49
89
C9
0A
4A
8A
CA
0B
4B
8B
CB
0C
4C
8C
CC
0D
4D
8D
CD
0E
4E
8E
CE
0F
4F
8F
10
50
90
GDI_O_IN
D0
RW
11
51
91
GDI_E_IN
D1
RW
12
52
92
GDI_O_OU
D2
RW
13
53
93
GDI_E_OU
D3
RW
14
54
94
D4
15
55
95
D5
16
56
96
D6
17
57
97
D7
18
58
98
D8
19
59
99
D9
1A
5A
9A
DA
1B
5B
9B
DB
Document Number: 38-12022 Rev. *K
84
RW
Addr
(1,Hex)
PRT0DM1
ASE11CR0
80
Access
PRT0DM0
Blank fields are Reserved and must not be accessed.
ASE10CR0
Addr
(1,Hex)
C0
C3
RW
C4
CF
# Access is bit specific.
Page 13 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 10. Register Map Bank 1 Table: Configuration Space (continued)
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
1C
5C
9C
1D
5D
9D
OSC_GO_EN
DC
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
CMP_GO_EN
64
RW
A4
VLT_CMP
E4
R
A5
ADC0_TR
E5
RW
ADC1_TR
E6
RW
23
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
27
65
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
E7
DCB02FN
28
RW
68
A8
IMO_TR
E8
W
DCB02IN
29
RW
69
A9
ILO_TR
E9
W
2A
RW
DCB02OU
2B
AA
BDG_TR
EA
RW
CLK_CR3
6A
6B
RW
AB
ECO_TR
EB
W
DCB03FN
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
EF
30
70
RDI0RI
B0
RW
F0
31
71
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
34
74
RDI0LT1
B4
RW
F4
35
75
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
F6
CPU_F
F7
RL
38
78
B8
39
79
B9
3A
7A
BA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
Document Number: 38-12022 Rev. *K
F8
F9
FLS_PR1
FA
RW
FD
# Access is bit specific.
Page 14 of 36
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For up to date electrical specifications,
check if you have the latest data sheet by visiting the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
Refer to Table 25 on page 25 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
5.25
SLIMO Mode = 0
Figure 11. Voltage versus IMO Frequency
Figure 10. Voltage versus CPU Frequency
5.25
SLIMO
Mode=1
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.60
3.00
3.00
2.40
2.40
93 kHz
12 MHz
3 MHz
24 MHz
SLIMO
Mode=0
SLIMO
SLIMO
Mode=1
Mode=0
SLIMO SLIMO
Mode=1 Mode=1
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol
C
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
o
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 38-12022 Rev. *K
Symbol
μW
mA
ms
mV
nA
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 15 of 36
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CY8C21123, CY8C21223, CY8C21323
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 12. Absolute Maximum Ratings
Symbol
Description
TSTG
Storage Temperature
TA
Vdd
VIO
VIOZ
IMIO
ESD
LU
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
DC Voltage Applied to Tristate
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch up Current
Min
-55
Typ
–
-40
-0.5
Vss - 0.5
Vss - 0.5
-25
2000
–
–
–
–
–
–
–
–
Min
-40
-40
Typ
–
–
Max
+100
Units
Notes
°C
Higher storage temperatures
reduce data retention time.
Recommended storage temperature is +25°C ± 25°C. Extended
duration storage temperatures
above 65°C degrade reliability.
+85
°C
+6.0
V
Vdd + 0.5
V
Vdd + 0.5
V
+50
mA
–
V
Human Body Model ESD
200
mA
Operating Temperature
Table 13. Operating Temperature
Symbol
Description
TA
Ambient Temperature
TJ
Junction Temperature
Document Number: 38-12022 Rev. *K
Max
+85
+100
Units
Notes
°C
°C
The temperature rise from
ambient to junction is package
specific. SeeTable 37 on page
34. The user must limit the power
consumption to comply with this
requirement.
Page 16 of 36
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
DC Electrical Characteristics
DC Chip-Level Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 14. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
Min
2.40
Typ
–
Max
5.25
Units
Notes
V
See DC POR and LVD specifications, Table 21 on page 21.
mA Conditions are Vdd = 5.0V, 25oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 0.366 kHz.
mA Conditions are Vdd = 3.3V, 25oC,
CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
mA Conditions are Vdd = 2.55V,
25oC, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
μA Vdd = 2.55V, 0°C to 40°C
IDD
Supply Current, IMO = 24 MHz
–
3
4
IDD3
Supply Current, IMO = 6 MHz
–
1.2
2
IDD27
Supply Current, IMO = 6 MHz
–
1.1
1.5
ISB27
–
2.6
4
–
2.8
5
μA
Vdd = 3.3V, -40°C ≤ TA ≤ 85°C
VREF
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active. Mid temperature range.
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Reference Voltage (Bandgap)
1.28
1.30
1.32
V
VREF27
Reference Voltage (Bandgap)
1.16
1.30
1.330
V
Trimmed for appropriate Vdd.
Vdd = 3.0V to 5.25V
Trimmed for appropriate Vdd.
Vdd = 2.4V to 3.0V
AGND
Analog Ground
VREF - 0.003
VREF
VREF+ 0.003
V
ISB
Document Number: 38-12022 Rev. *K
Page 17 of 36
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
DC General Purpose IO Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 15. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
RPU
Pull up Resistor
4
5.6
8
kΩ
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
150 mA maximum combined IOL
budget.
VIL
Input Low Level
–
–
0.8
V
Vdd = 3.0 to 5.25
VIH
Input High Level
2.1
–
V
Vdd = 3.0 to 5.25
VH
Input Hysteresis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C
≤ TA ≤ 85°C. Typical parameters apply to 2.7V at 25°C and are for design guidance only.
Table 16. 2.7V DC GPIO Specifications
Symbol
Description
Pull up Resistor
RPU
Pull down Resistor
RPD
High Output Level
VOH
Min
4
4
Vdd 0.4
Typ
5.6
5.6
–
Max
8
8
–
VOL
Low Output Level
–
–
0.75
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysteresis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.0
–
–
–
–
–
60
1
3.5
0.75
–
–
–
10
COUT
Capacitive Load on Pins as Output
–
3.5
10
Document Number: 38-12022 Rev. *K
Units
Notes
kΩ
kΩ
V
IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to
3.0V (16 mA maximum, 50 mA Typ
combined IOH budget).
V
IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA
maximum combined IOL budget).
V
Vdd = 2.4 to 3.0
V
Vdd = 2.4 to 3.0
mV
nA
Gross tested to 1 μA
pF
Package and pin dependent.
Temp = 25°C
pF
Package and pin dependent.
Temp = 25°C
Page 18 of 36
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CY8C21123, CY8C21223, CY8C21323
DC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 17. 5V DC Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
TCVOSOA Average Input Offset Voltage Drift
Min
Typ
Max
Units
–
2.5
15
mV
–
10
–
μV/oC
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.0
–
Vdd - 1
V
GOLOA
Open Loop Gain
80
–
–
dB
ISOA
Amplifier Supply Current
–
10
30
μA
Min
Typ
Max
Units
–
2.5
15
mV
TCVOSOA Average Input Offset Voltage Drift
–
10
–
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
Table 18. 3.3V DC Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
VCMOA
Common Mode Voltage Range
0
–
Vdd - 1
V
GOLOA
Open Loop Gain
80
–
–
dB
ISOA
Amplifier Supply Current
–
10
30
μA
Min
Typ
Max
Units
Notes
Table 19. 2.7V DC Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Notes
–
2.5
15
mV
TCVOSOA Average Input Offset Voltage Drift
–
10
–
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0
–
Vdd - 1
V
GOLOA
Open Loop Gain
80
–
–
dB
ISOA
Amplifier Supply Current
–
10
30
μA
Document Number: 38-12022 Rev. *K
Page 19 of 36
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DC Switch Mode Pump Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 20. DC Switch Mode Pump (SMP) Specifications
Min
Typ
Max
Units
Notes
VPUMP5V
Symbol
5V Output Voltage from Pump
Description
4.75
5.0
5.25
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set
to 5.0V.
VPUMP3V
3.3V Output Voltage from Pump
3.00
3.25
3.60
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set
to 3.25V.
VPUMP2V
2.6V Output Voltage from Pump
2.45
2.55
2.80
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set
to 2.55V.
IPUMP
Available Output Current
VBAT = 1.8V, VPUMP = 5.0V
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.3V, VPUMP = 2.55V
5
8
8
–
–
–
–
–
–
mA
mA
mA
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote.[6] SMP trip
voltage is set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote.[6] SMP trip
voltage is set to 3.25V.
VBAT2V
Input Voltage Range from Battery
1.0
–
2.8
V
Configuration of footnote.[6] SMP trip
voltage is set to 2.55V.
VBATSTART
Minimum Input Voltage from Battery to
Start Pump
1.2
–
–
V
Configuration of footnote.[6] 0°C ≤ TA ≤
100. 1.25V at TA = -40oC.
ΔVPUMP_Line
Line Regulation (over Vi range)
–
5
–
%VO Configuration of footnote.[6] VO is the
“Vdd Value for PUMP Trip” specified by
the VM[2:0] setting in the DC POR and
LVD Specification, Table 21 on page 21.
ΔVPUMP_Load
Load Regulation
–
5
–
%VO Configuration of footnote.[6] VO is the
“Vdd Value for PUMP Trip” specified by
the VM[2:0] setting in the DC POR and
LVD Specification, Table 21 on page 21.
ΔVPUMP_Ripple Output Voltage Ripple (depends on
cap/load)
–
100
–
mVpp Configuration of footnote.[6] Load is
5 mA.
E3
Efficiency
35
50
–
%
Configuration of footnote.[6] Load is
5 mA. SMP trip voltage is set to 3.25V.
E2
Efficiency
35
80
–
%
For I load = 1mA, VPUMP = 2.55V,
VBAT = 1.3V, 10 uH inductor, 1 uF
capacitor, and Schottky diode.
FPUMP
Switching Frequency
–
1.3
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
Configuration of footnote.[6]
SMP trip voltage is set to 5.0V.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 2.55V.
Note
6. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 12 on page 21.
Document Number: 38-12022 Rev. *K
Page 20 of 36
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Figure 12. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoCTM
V ss
DC POR and LVD Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 21. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62[9]
3.09
3.16
3.32[10]
4.74
4.83
4.92
5.12
V
V
V
V
V
V
V
V
Notes
Vdd must be greater than or equal to
2.5V during startup, reset from the
XRES pin, or reset from Watchdog.
Notes
7. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
9. Always greater than 50 mV above VLVD0.
10. Always greater than 50 mV above VLVD3.
Document Number: 38-12022 Rev. *K
Page 21 of 36
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DC Programming Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 22. DC Programming Specifications
Symbol
VddIWRITE
IDDP
VILP
FlashENPB
Description
Supply Voltage for Flash Write Operations
Supply Current During Programming or Verify
Input Low Voltage During Programming or
Verify
Input High Voltage During Programming or
Verify
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
Output Low Voltage During Programming or
Verify
Output High Voltage During Programming or
Verify
Flash Endurance (per block)
FlashENT
Flash Endurance (total)[11]
FlashDR
Flash Data Retention
VIHP
IILP
IIHP
VOLV
VOHV
Min
2.70
–
–
Typ
–
5
–
Max
–
25
0.8
Units
V
mA
V
2.2
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
Vss + 0.75
V
Vdd - 1.0
–
Vdd
V
50,000
–
–
–
1,800,000
–0
–0
–0
10
–
–
Years
0
Notes
Driving internal pull down
resistor
Driving internal pull down
resistor
Erase/write cycles per
block
Erase/write cycles
Note
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no
single block ever sees more than 50,000 cycles).For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the
result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more
information.
Document Number: 38-12022 Rev. *K
Page 22 of 36
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AC Electrical Characteristics
AC Chip-Level Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 23. 5V and 3.3V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
[12,13,14]
Notes
MHz
Trimmed for 5V or 3.3V
operation using factory trim
values. See Figure 11 on
page 15.
SLIMO mode = 0.
FIMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[12,13,14]
MHz
Trimmed for 3.3V operation
using factory trim values. See
Figure 11 on page 15. SLIMO
mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6[12,13]
MHz
24 MHz only for
SLIMO mode = 0.
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3[13,14]
MHz
FBLK5
0
Digital PSoC Block Frequency (5V Nominal)
0
48
49.2[12,13,15]
MHz
FBLK33
Digital PSoC Block Frequency (3.3V Nominal)
0
24
24.6[13,15]
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
Jitter32k
32 kHz RMS Period Jitter
–
100
200
ns
Jitter32k
32 kHz Peak-to-Peak Period Jitter
–
1400
–
ns
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
–
kHz
[12,14]
MHz
Step24M
24 MHz Trim Step Size
Fout48M
48 MHz Output Frequency
–
50
46.8
48.0
Jitter24M1
24 MHz Peak-to-Peak Period Jitter (IMO)
–
300
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
49.2
Refer to the AC Digital Block
Specifications.
Trimmed. Using factory trim
values.
ps
Notes
12. 4.75V < Vdd < 5.25V.
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. 3.0V < Vdd < 3.6V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
15. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12022 Rev. *K
Page 23 of 36
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Table 24. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
0
Max
Units
[16,17,18]
Notes
12.7
MHz Trimmed for 2.7V operation using
factory trim values. See Figure 11
on page 15. SLIMO mode = 1.
FIMO12
Internal Main Oscillator Frequency for 12 MHz
11.5
12
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.35[16,17,18]
MHz Trimmed for 2.7V operation using
factory trim values. See Figure 11
on page 15. SLIMO mode = 1.
FCPU1
CPU Frequency (2.7V Nominal)
0.093
3
3.15[16,17]
MHz 24 MHz only for SLIMO mode = 0.
12
[16,17,18]
FBLK27
Digital PSoC Block Frequency (2.7V Nominal)
0
F32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
32 kHz RMS Period Jitter
–
150
200
ns
Jitter32k
32 kHz Peak-to-Peak Period Jitter
–
1400
–
ns
TXRST
External Reset Pulse Width
10
–
–
μs
FMAX
Maximum frequency of signal on row input or
row output
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
12.5
MHz Refer to the AC Digital Block
Specifications.
Figure 13. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 14. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
Notes
16. 2.4V < Vdd < 3.0V.
17. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
18. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.
Document Number: 38-12022 Rev. *K
Page 24 of 36
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AC General Purpose IO Specifications
Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 25. 5V and 3.3V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FGPIO
GPIO Operating Frequency
0
–
12
MHz
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
Normal Strong Mode
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
Min
Typ
Max
Units
Table 26. 2.7V AC GPIO Specifications
Symbol
Description
FGPIO
GPIO Operating Frequency
0
–
3
MHz
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
6
–
50
ns
Notes
Normal Strong Mode
Vdd = 2.4 to 3.0V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
6
–
50
ns
Vdd = 2.4 to 3.0V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
18
40
120
ns
Vdd = 2.4 to 3.0V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
18
40
120
ns
Vdd = 2.4 to 3.0V, 10% - 90%
Figure 15. GPIO Timing Diagram
90%
GPIO
Pin
10%
TRiseF
TRiseS
TFallF
TFallS
AC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 27. 5V and 3.3V AC Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
TCOMP1
Comparator Mode Response Time, 50 mVpp Signal Centered on Ref
100
ns
TCOMP2
Comparator Mode Response Time, 2.5V Input, 0.5V Overdrive
300
ns
Max
Units
Table 28. 2.7V AC Amplifier Specifications
Symbol
Description
Min
Typ
TCOMP1
Comparator Mode Response Time, 50 mVpp Signal Centered on Ref
600
ns
TCOMP2
Comparator Mode Response Time, 1.5V Input, 0.5V Overdrive
300
ns
Document Number: 38-12022 Rev. *K
Page 25 of 36
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AC Digital Block Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 29. 5V and 3.3V AC Digital Block Specifications
Function
All
Functions
Description
Min
Typ
Max
Units
Notes
Maximum Block Clocking Frequency (> 4.75V)
49.2
MHz
4.75V < Vdd < 5.25V
Maximum Block Clocking Frequency (< 4.75V)
24.6
MHz
3.0V < Vdd < 4.75V
[19]
–
–
ns
–
–
49.2
MHz
Maximum Frequency, With or Without Capture
–
–
24.6
MHz
Enable Pulse Width
50
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50
–
–
ns
Disable Mode
50
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
Maximum Input Clock Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Timer
Capture Pulse Width
Maximum Frequency, No Capture
Counter
Dead Band
CRCPRS
(PRS Mode)
50
4.75V < Vdd < 5.25V
4.75V < Vdd < 5.25V
Kill Pulse Width:
Maximum data rate at 4.1 MHz due
to 2 x over clocking
Width of SS_ Negated Between Transmissions
50
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due
to 8 x over clocking
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due
to 8 x over clocking
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. *K
Page 26 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 30. 2.7V AC Digital Block Specifications
Function
Description
All
Functions
Maximum Block Clocking Frequency
Timer
Capture Pulse Width
Maximum Frequency, With or Without Capture
Counter
Dead Band
Enable Pulse Width
Min
Typ
Max
Units
12.7
MHz
100[20]
–
–
ns
–
–
12.7
MHz
100
–
–
ns
Maximum Frequency, No Enable Input
–
–
12.7
MHz
Maximum Frequency, Enable Input
–
–
12.7
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
100
–
–
ns
Disable Mode
Notes
2.4V < Vdd < 3.0V
Kill Pulse Width:
100
–
–
ns
Maximum Frequency
–
–
12.7
MHz
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
12.7
MHz
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
12.7
MHz
SPIM
Maximum Input Clock Frequency
–
–
6.35
MHz
SPIS
Maximum Input Clock Frequency
Width of SS_ Negated Between Transmissions
–
–
4.1
MHz
100
–
–
ns
Maximum data rate at 3.17 MHz
due to 2 x over clocking
Transmitter
Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz
due to 8 x over clocking
Receiver
Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz
due to 8 x over clocking
Note
20. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. *K
Page 27 of 36
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CY8C21123, CY8C21223, CY8C21323
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C
and are for design guidance only.
Table 31. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Min
Typ
Max
Units
Notes
Table 32. 3.3V AC External Clock Specifications
Symbol
Description
FOSCEXT
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz
at 3.3V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.186
–
24.6
MHz
If the frequency of the external clock
is greater than 12 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Min
Typ
Max
Units
Notes
0
MHz
Maximum CPU frequency is 3 MHz at
2.7V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
If the frequency of the external clock
is greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
Table 33. 2.7V AC External Clock Specifications
Symbol
Description
FOSCEXT
Frequency with CPU Clock divide by 1
0.093
–
6.06
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.186
–
12.12
MHz
–
High Period with CPU Clock divide by 1
83.4
–
5300
ns
–
Low Period with CPU Clock divide by 1
83.4
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 38-12022 Rev. *K
Page 28 of 36
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CY8C21123, CY8C21223, CY8C21323
AC Programming Specifications
Table 34 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 34. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK3
TDSCLK2
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
15
30
–
–
Max
20
20
–
–
8
–
–
50
70
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
Notes
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
AC I2C Specifications
Table 35 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 35. AC Characteristics of the I2C SDA and SCL Pins for Vcc ≥ 3.0V
Symbol
FSCLI2C
Description
SCL Clock Frequency
Standard Mode
Min
Max
0
100
Fast Mode
Min
Max
0
400
Units
kHz
THDSTAI2C Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C Data Hold Time
TSUDATI2C Data Setup Time0
0
–
0
–
μs
2500
–0
–0
ns0
4.0
–
100[20]
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
TSUSTOI2C Setup Time for STOP Condition
Note
20. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This automatically becomes
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12022 Rev. *K
Page 29 of 36
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Table 36. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode Not Supported)
Symbol
FSCLI2C
Standard Mode
Min
Max
0
100
Description
SCL Clock Frequency
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
Fast Mode
Min
Max
–
–
Units
kHz
4.0
–
–
–
μs
4.7
–
–
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
–
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
–
–
μs
THDDATI2C Data Hold Time
0
–
–
–
μs
TSUDATI2C Data Setup Time
250
–
–
–
ns
TSUSTOI2C Setup Time for STOP Condition
4.0
–
–
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
–
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
–
–
ns
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
Document Number: 38-12022 Rev. *K
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Page 30 of 36
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CY8C21123, CY8C21223, CY8C21323
Packaging Information
This section illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each
package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 17. 8-Pin (150-Mil) SOIC
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
Document Number: 38-12022 Rev. *K
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85066 *C
Page 31 of 36
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CY8C21123, CY8C21223, CY8C21323
Figure 18. 16-Pin (150-Mil) SOIC
51-85022 *B
Figure 19. 16-Pin COL
001-09116 *D
Document Number: 38-12022 Rev. *K
Page 32 of 36
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CY8C21123, CY8C21223, CY8C21323
Figure 20. 20-Pin (210-MIL) SSOP
51-85077 *C
Figure 21. 24-Pin (4x4) QFN
SIDE VIEW
TOP VIEW
BOTTOM VIEW
0.05
3.90
4.10
1.00 MAX.
0.23±0.05
0.05 MAX.
3.70
3.80
Ø0.50
C
0.80 MAX.
2.49
0.20 REF.
N
PIN1 ID
0.20 R.
N
1
1
2
2.45
2.55
3.90
4.10
3.70
3.80
2
2.49
SOLDERABLE
EXPOSED
PAD
0.45
0.30-0.50
0.42±0.18
(4X)
0°-12°
C
SEATING
PLANE
0.50
2.45
2.55
NOTES:
1.
HATCH IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.042g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LF24A
LY24A
STANDARD
LEAD FREE
51-85203 *A
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Document Number: 38-12022 Rev. *K
Page 33 of 36
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Thermal Impedances
Table 37. Thermal Impedances per Package
Typical θJA [21]
Package
8 SOIC
186°C/W
16 SOIC
125°C/W
16 COL
46°C/W
20 SSOP
[22]
24 QFN
117°C/W
40°C/W
Solder Reflow Peak Temperature
Table 38 lists the minimum solder reflow peak temperature to achieve good solderability.
Table 38. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[23]
Maximum Peak Temperature
8 SOIC
240°C
260°C
16 SOIC
240°C
260°C
16 COL
240°C
260°C
20 SSOP
240°C
260°C
24 QFN
240°C
260°C
Notes
21. TJ = TA + POWER x θJA
22. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5°C with Sn-Pb or 245+/-5°C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12022 Rev. *K
Page 34 of 36
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CY8C21123, CY8C21223, CY8C21323
Ordering Information
The following table lists the CY8C21x23 PSoC device’s key package features and ordering codes.
Switch
Mode
Pump
Digital
PSoC
Blocks
Analog
Blocks
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8C21123-24SXI
4K
256
No
-40°C to
+85°C
4
4
6
4
0
No
8-Pin (150-Mil) SOIC
(Tape and Reel)
CY8C21123-24SXIT
4K
256
No
-40°C to
+85°C
4
4
6
4
0
No
16-Pin (150-Mil) SOIC
CY8C21223-24SXI
4K
256
Yes
-40°C to
+85°C
4
4
12
8
0
No
16-Pin (150-Mil) SOIC
(Tape and Reel)
CY8C21223-24SXIT
4K
256
Yes
-40°C to
+85°C
4
4
12
8
0
No
16-Pin (3x3) COL
CY8C21223-24LGXI
4K
256
Yes
-40°C to
+85°C
4
4
12
8
0
No
20-Pin (210-Mil) SSOP CY8C21323-24PVXI
4K
256
No
-40°C to
+85°C
4
4
16
8
0
Yes
20-Pin (210-Mil) SSOP CY8C21323-24PVXIT
(Tape and Reel)
4K
256
No
-40°C to
+85°C
4
4
16
8
0
Yes
24-Pin (4x4) QFN
CY8C21323-24LFXI
4K
256
Yes
-40°C to
+85°C
4
4
16
8
0
Yes
24-Pin (4x4) QFN
(Tape and Reel)
CY8C21323-24LFXIT
4K
256
Yes
-40°C to
+85°C
4
4
16
8
0
Yes
Package
Temperature
Range
RAM
(Bytes)
8-Pin (150-Mil) SOIC
Ordering
Code
Flash
(Bytes)
Table 39. CY8C21x23 PSoC Device Key Features and Ordering Information
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = QFN Pb-Free
AX = TQFP Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12022 Rev. *K
Page 35 of 36
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Document History Page
Document Title: CY8C21123, CY8C21223, CY8C21323 PSoC® Programmable System-on-Chip™
Document Number:38-12022
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
**
133248
NWJ
See ECN
New silicon and document (Revision **).
*A
208900
NWJ
See ECN
Add new part, new package and update all ordering codes to Pb-free.
*B
212081
NWJ
See ECN
Expand and prepare Preliminary version.
*C
227321
CMS Team
See ECN
Update specs., data, format.
*D
235973
SFV
See ECN
Updated Overview and Electrical Spec. chapters, along with 24-pin pinout.
Added CMP_GO_EN register (1,64h) to mapping table.
*E
290991
HMT
See ECN
Update data sheet standards per SFV memo. Fix device table. Add part numbers
to pinouts and fine tune. Change 20-pin SSOP to CY8C21323. Add Reflow Temp.
table. Update diagrams and specs.
*F
301636
HMT
See ECN
DC Chip-Level Specification changes. Update links to new CY.com Portal.
*G
324073
HMT
See ECN
Obtained clearer 16 SOIC package. Update Thermal Impedances and Solder
Reflow tables. Re-add pinout ISSP notation. Fix ADC type-o. Fix TMP register
names. Update Electrical Specifications. Add CY logo. Update CY copyright.
Make data sheet Final.
*H
2588457 KET/HMI/
10/22/2008 New package information on page 9. Converted data sheet to new template.
AESA
Added 16-Pin OFN package diagram.
*I
2618175 OGNE/PYRS 12/09/08
Added Note in Ordering Information Section. Changed title from PSoC
Mixed-Signal Array to PSoC Programmable System-on-Chip. Updated ‘Development Tools’ and ‘Designing with PSoC Designer’ sections on pages 5 and 6
*J
2682782 MAXK/AESA 04/03/2009 Corrected 16 COL pinout.
*K
2699713 MAXK
04/29/09
Minor ECN to correct paragraph style of 16 COL Pinout. No change in content.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
PSoC Solutions
psoc.cypress.com
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12022 Rev. *K
Revised April 29, 2009
Page 36 of 36
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights
to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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