INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4069UB gates Hex inverter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Hex inverter HEF4069UB gates DESCRIPTION The HEF4069UB is a general purpose hex inverter. Each of the six inverters is a single stage. Fig.2 Pinning diagram. HEF4069UBP(N): 14-lead DIL; plastic (SOT27-1) HEF4069UBD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4069UBT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages Fig.3 Schematic diagram (one inverter). January 1995 2 Philips Semiconductors Product specification HEF4069UB gates Hex inverter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 5 TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 45 90 ns 18 ns + (0,55 ns/pF) CL 20 40 ns 9 ns + (0,23 ns/pF) CL 15 15 25 ns 7 ns + (0,16 ns/pF) CL 5 40 80 ns 13 ns + (0,55 ns/pF) CL 10 tPHL 20 40 ns 9 ns + (0,23 ns/pF) CL 15 15 30 ns 7 ns + (0,16 ns/pF) CL 5 60 120 ns 10 tPLH 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 10 15 VDD V Dynamic power SYMBOL 5 tTHL tTLH 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL TYPICAL FORMULA FOR P (µW) 600 fi + ∑ (foCL) × VDD2 dissipation per 10 4 000 fi + ∑ (foCL) × package (P) 15 22 000 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification HEF4069UB gates Hex inverter January 1995 Fig.4 Typical transfer characteristics; ___ VO; _ _ _ ID (drain current); IO = 0; VDD = 5 V. Fig.5 Typical transfer characteristics; ___ VO; _ _ _ ID (drain current); IO = 0; VDD = 10 V. Fig.6 Typical transfer characteristics; ___ VO; _ _ _ ID (drain current); IO = 0; VDD = 15 V. 4 Philips Semiconductors Product specification HEF4069UB gates Hex inverter APPLICATION INFORMATION Some examples of applications for the HEF4069UB are shown below. In Fig.7 an astable relaxation oscillator is given. The oscillation frequency is mainly determined by R1C1, provided R1 << R2 and R2C2 << R1C1. (a) (b) The function of R2 is to minimize the influence of the forward voltage across the protection diodes on the frequency; C2 is a stray (parasitic) capacitance. The period Tp is given by Tp = T1 + T2, in which V DD + V ST 2 V DD – V ST T 1 = R1C1 In ----------------------------- and T 2 = R1C1 In ---------------------------------- where V ST V DD – V ST VST is the signal threshold level of the inverter. The period is fairly independent of VDD, VST and temperature. The duty factor, however, is influenced by VST. Fig.7 (a) Astable relaxation oscillator using two HEF4069UB inverters; the diodes may be BAW62; C2 is a parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram. January 1995 5 Philips Semiconductors Product specification HEF4069UB gates Hex inverter (1) This inverter is added to amplify the oscillator output voltage to a level sufficient to drive other LOCMOS circuits. Fig.8 Crystal oscillator for frequencies up to 10 MHz, using two HEF4069UB inverters. Fig.9 Fig.10 Supply current as a function of supply voltage. Voltage gain (VO/VI) as a function of supply voltage. It is also an example of an analogue amplifier using one HEF4069UB. Fig.11 Test set-up for measuring graphs of Figs 9 and 10. January 1995 6 Philips Semiconductors Product specification HEF4069UB gates Hex inverter Fig.12 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.13). A : average, B : average + 2 s, C : average − 2 s, where: ‘s’ is the observed standard deviation. Fig.13 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C. January 1995 7