Data Sheet November 2001 LCK4953 Low-Voltage PLL Clock Driver Features • Fully integrated PLL • Output frequency up to 130 MHz in PLL mode • • • • Nine outputs with high-impedance disable 32-lead TQFP 50 ps cycle-to-cycle jitter Pin compatible with the Motorola® MPC953 clock driver Description The LCK4953 is a PLL-based clock driver device intended for high-performance clock tree designs. The LCK4953 is 3.3 V compatible with output frequencies of up to 130 MHz and output skews of 75 ps. The LCK4953 can meet the most demanding timing requirements and employs on-chip voltage regulators to minimize cycle-to-cycle jitter and phase jitter. The LCK4953 is ideal for use as a zero delay, low skew, fan-out buffer due to its differential LVPECL reference input along with an external feedback input. The MROEB pin of the LCK4953, when driven high, will reset the internal counters and 3-state the output buffers. The LCK4953 has been optimized for zero delay performance. The LCK4953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50 Ω transmission lines. For seriesterminated 50 Ω lines, each of the LCK4953 outputs can drive two traces giving the device an effective fan-out of 1:18. For the optimum combination of board density and performance, the device is packaged in a 7 mm × 7 mm 32-lead TQFP package. Table 1. Function Table BYPASSB Function 1 0 PLL Enabled PLL Bypass MROEB Function 1 0 Outputs Disabled Outputs Enabled VCOSEL Function 1 0 ÷8 ÷4 PLLEN Function 1 0 Select VCO Select PELCLK LCK4953 Low-Voltage PLL Clock Driver Data Sheet November 2001 VCOSEL BYPASSB PLLEN VSS QFB VDD Q0 VSS 32 31 30 29 28 27 26 25 Description (continued) VDDA 1 24 Q1 FBCLK 2 23 VDD NC1 3 22 Q2 NC2 4 21 VSS 20 Q3 LCK4953 16 PECLCKN Q5 VSS 15 17 VDD 8 14 PECLCKP Q6 Q4 13 18 VSS 7 12 VSSA Q7 VDD 11 19 VDD 6 10 NC4 MROEB 5 9 NC3 5-8653(F) Figure 1. 32-Lead Pinout (Top View) Absolute Maximum Ratings Stresses which exceed the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods of time can adversely affect device reliability. Table 2. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Input Current Storage Temperature Range 2 Symbol Min Max Unit VDD VIN IIN Tstg –0.3 –0.3 — –40 4.2 VDD + 0.3 ±20 125 V V mA °C Agere Systems Inc. LCK4953 Low-Voltage PLL Clock Driver Data Sheet November 2001 Absolute Maximum Ratings (continued) Table 3. dc Characteristics (TA = 0 °C to 70 °C, VDD = 3.3 V ± 5%) Parameter Symbol Min Typ Max Unit Condition Input High-voltage LVCMOS Inputs VIH 2.0 — 3.6 V — Input Low-voltage LVCMOS Inputs VIL — — 0.8 V — Peak-to-peak Input Voltage PECL_CLK Vp-p 300 — 1000 mV — Common-mode Range PECL_CLK VCMR VDD – 1.5 — VDD – 0.6 mV —* Output High Voltage VOH 2.4 — — V IOH = –30 mA† Output Low Voltage VOL — — 0.6 V IOL = 30 mA† IIN — — ±120 µA — Input Current Input Capacitance CIN — — 4 pF — Power Dissipation Capacitance Cpd — 12 — pF Per output Maximum Quiescent Supply Current Non-PLL IDDQ — — 1 mA All VDD pins except VDDA‡ IDDPLL — — 45 mA VDDA pin only Maximum PLL Supply Current * VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the high input is within the VCMR range and the input swing lies within the Vp-p specification. † The LCK4953 outputs can drive series- or parallel-terminated 50 Ω (or 50 Ω to VCC/2) transmission lines on the incident edge. ‡ Total Power = (IDDPLL + IDDQ + fCV) * V; where f = fref, V = VDDD, C = total load capacitance on all outputs. Table 4. PLL Input Reference Characteristics (TA = 0 °C to 70 °C) Parameter Reference Input Frequency Reference Input Duty Cycle Symbol Min Max Unit Condition fref trefdc 25 25 130 75 MHz % — — Table 5. ac Characteristics (TA = 0 °C to 70 °C, VDD = 3.3 V ± 5%) Parameter Output Rise/Fall Time Output Duty Cycle Output-to-output Skews PLL VCO Lock Range Frequency Output: Frequency PLL Bypass Mode Input to Ext_FB Delay (with PLL locked) Input to Q Delay Part to Part Delay Output Disable Time Output Enable Time Cycle-to-cycle Jitter (peak-to-peak) Agere Systems Inc. Symbol Min Typ Max Unit Condition tr, tf tpw tsk(O) fVCO fout tpd (lock) tpd(bypass) 0.10 47 — 200 25 50 — –75 3 — 50 — — — — — — — ns % ps MHz MHz MHz MHz ps ns 0.8 V to 2.0 V — — — VCOSEL = 1 VCOSEL = 0 — tref = 75 MHz PLL bypassed tPLZHZ tPZL tjitter — — — — — — 1.0 53 75 520 65 130 250 125 7 1.5 7 6 50 ns ns ps — — fout > 75 MHz 3 LCK4953 Low-Voltage PLL Clock Driver Data Sheet November 2001 Electrical Characteristics PECLCKP P PECLCKN N D0 A Z /4 A DIVBY4 Z /2 DIVBY2 D1 SD Z QFB D0 D0 D1 SD D0 FBCLK PLL CORE A Z /4 A DIVBY4 Z /2 DIVBY2 D1 SD QFB Z PAD Z Z D1 SD Z Q[0:6] Q7 Q[0:6] Z PAD Q7 Z PAD PLLEN VCOSEL BYPASSB MROEN 5-8654.a (F) Figure 2. Logic Diagram Power Supply Filtering The LCK4953 is a mixed-signal product which is susceptible to random noise, especially when this noise is on the power supply pins. To isolate the output buffer switching from the internal phase-locked loop, the LCK4953 provides separate power supplies for the phase-locked loop (VDDA) and for the output buffers (VDD). In a digital system environment, besides this isolation technique, it is highly recommended that both VDDA and VDD power supplies be filtered to reduce the random noise as much as possible. Figure 3 illustrates a typical power supply filter scheme. A filter for the LCK4953 should be designed to target noise in the 100 kHz to 10 MHz range, due to its susceptibility to noise with spectral content in this range. The RC filter in Figure 3 will provide a broadband filter with approximately –40 dB attenuation for noise with spectral content above 20 kHz. More elaborate power supply schemes may be used to achieve increased power supply noise filtering. 3.3 V RS = 5 Ω—10 Ω VDDA 0.01 µF 22 µF LCK4953 VDD 0.01 µF 5-9575(F) Figure 3. Power Supply Filter 4 Agere Systems Inc. LCK4953 Low-Voltage PLL Clock Driver Data Sheet November 2001 Electrical Characteristics (continued) Driving Transmission Lines The LCK4953 clock driver was designed to drive high-speed clock terminals in a terminated transmission line environment. Point-to-point distribution of signals is a common method in most high-performance clock networks. Either series-terminated or parallel-terminated transmission lines can be used in a point-to-point scheme. The parallel technique terminates the signal at the end of a line with a 50 Ω resistance to VDD/2. This draws a fairly high level of dc current. Due to this aspect, only a single terminated line can be driven by each output of the LCK4953 clock driver. For the series-terminated case, however, there is no dc current draw; in turn, the outputs are capable of driving multiple series-terminated lines. Figure 4 illustrates an output driving a single series-terminated line. OUTPUT BUFFER OUTPUT CLOCK 14 Ω RS = 36 Ω ZO = 50 Ω 5-9576(F) Figure 4. Single Transmission Line In Figure 4, because the output buffer has an impedance of 14 Ω, the series resistance (Rs) is set at 36 Ω. This ensures that the total impedance is matched with the 50 Ω transmission line. Figure 5 illustrates an output driving two series-terminated lines. RS = 22 Ω ZO = 50 Ω RS = 22 Ω ZO = 50 Ω OUTPUT BUFFER OUTPUT CLOCK 14 Ω 5-9577(F) Figure 5. Dual Transmission Lines In Figure 5, the two series resistors (Rs) are set at 22 Ω because the 14 Ω output buffer can be viewed as two 28 Ω resistors in parallel. Accordingly, for each transmission line, the impedance is well matched. Agere Systems Inc. 5 LCK4953 Low-Voltage PLL Clock Driver Data Sheet November 2001 Outline Diagram 32-Pin TQFP Dimensions are in millimeters. 9.00 ± 0.20 7.00 ± 0.20 1.00 REF PIN #1 IDENTIFIER ZONE 32 25 0.25 GAGE PLANE 24 1 SEATING PLANE 0.45/0.75 7.00 ± 0.20 DETAIL A 9.00 ± 0.20 8 17 9 16 0.09/0.200 DETAIL A DETAIL B 0.30/0.45 1.40 ± 0.05 0.20 1.60 MAX M DETAIL B SEATING PLANE 0.10 0.80 TYP 0.05/0.15 12-3076(F) Motorola is a registerd trademark of Motorola, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved November 2001 DS02-034HSI (Replaces DS01-159ANET)