ON NCP1605DR2G Enhanced, high voltage and efficient standby mode, power factor controller Datasheet

NCP1605, NCP1605A
Enhanced, High Voltage and
Efficient Standby Mode,
Power Factor Controller
The NCP1605 is a controller that exhibits near−unity power factor
while operating in fixed frequency, Discontinuous Conduction Mode
(DCM) or in Critical Conduction Mode (CRM).
Housed in a SOIC−16 package, the circuit incorporates all the
features necessary for building robust and compact PFC stages, with
a minimum of external components. In addition, it integrates the skip
cycle capability to lower the standby losses to a minimum.
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MARKING
DIAGRAMS
16
NCP1605G
AWLYWW
General Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Near−Unity Power Factor
Fixed Frequency, Discontinuous Conduction Mode Operation
Critical Conduction Mode Achievable in Most Stressful Conditions
Lossless High Voltage Current Source for Startup
Soft Skipt Cycle for Low Power Standby Mode
Switching Frequency up to 250 kHz
Synchronization Capability
Fast Line / Load Transient Compensation
Valley Turn On
High Drive Capability: −500 mA / +800 mA
Signal to Indicate that the PFC is Ready for Operation
(“pfcOK” Pin)
VCC range: from 10 V to 20 V
Follower Boost Operation
Two VCC Turn−On Threshold Options:
15 V for NCP1605, 10.5 V for NCP1605A
This is a Pb−Free Device
•
•
1
16
NCP1605AG
AWLYWW
1
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
STBY 1
16 HV
BO 2
15 NC
Vcontrol 3
14 OVP/UVP
FB 4
13 STDWN
CSin 5
Safety Features
•
•
•
•
•
1
SOIC−16
D SUFFIX
CASE 751B
Output Under and Overvoltage Protection
Brown−Out Detection
Soft−Start for Smooth Startup Operation
Overcurrent Limitation
Zero Current Detection Protecting the PFC stage from Inrush
Currents
Thermal Shutdown
Latched Off Capability
12 pfcOK/REF5V
CSout/ZCD 6
11 VCC
Ct 7
10 DRV
OSC/SYNC 8
9
GND
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
Typical Applications
NCP1605DR2G
2500/Tape & Reel
• PC Power Supplies
• All Off Line Appliances Requiring Power Factor Correction
SOIC−16
(Pb−Free)
NCP1605ADR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 7
1
Publication Order Number:
NCP1605/D
NCP1605, NCP1605A
Rout1
Rbo1
Rout2
Rbo2
STBY control
1 16
2 15
Cbo
3 14
FB
CVctrl
Icoil
+
L1
Vout
Rovp2
OVP
6 11
7 10
Ct
8
Cosc
Rocp
Rovp1
CVCC
5 12
Ac line
Cin
Vin
VCC
D1
4 13
Rzcd
EMI
Filter
Vout
VCC
CVref
pfcOK
LOAD
M1
Cbulk +
9
Rdrv
Icoil
Rcs
Figure 1.
MAXIMUM RATINGS
Pin
Rating
Symbol
Value
Unit
10
Power Supply Input
VCC
−0.3, +20
V
10
Maximum Transient Voltage (Note 1)
VCC
−0.3, +25
V
1, 2, 4, 6, 7, 8,
13 and 14
Input Voltage
VI
−0.3, +9
V
3
VCONTROL Pin
VCONTROL
−0.3, VCONTROL MAX
(Note 2)
V
16
High Voltage Pin
HV
−0.3, +500
V
PD
RqJA
550
145
mW
°C/W
Power Dissipation and Thermal Characteristics:
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
TJ
−40, +125
°C
Maximum Junction Temperature
TJmax
150
°C
Storage Temperature Range
TSmax
−65 to 150°
°C
Lead Temperature (Soldering, 10 s)
TLmax
300
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum transient voltage with a corresponding maximum transient current at 100 mA. The maximum transient power handling capability
must be observed as well.
2. “VCONTROLMAX” is the pin clamp voltage
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2
NCP1605, NCP1605A
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0°C to +125°C, unless otherwise specified) (Note 2)
Symbol
Rating
Min
Typ
Max
Unit
Gate Drive Section
Trise
Output Voltage Rise Time @ CL = 1 nF, from 1 V to 10 V
−
40
−
ns
Tfall
Output Voltage Fall Time @ CL = 1 nF, from 10 V to 1 V
−
20
−
ns
ROH
Source Resistance @ IPin10 = 100 mA
−
15
25
W
Source Current capability (@ VPin10 = 0 V)
−
500
−
mA
ROL
Sink Resistance @ IPin10 = 100 mA
−
7
15
W
Isink
Sink Current Capability (@ VPin10 = 10 V)
−
800
−
mA
2.425
2.500
2.575
V
−
±20
−
mA
Isource
Regulation Block
VREF
Voltage Reference
IEA
Error Amplifier Current Capability
GEA
Error Amplifier Gain
100
200
300
mS
Pin 4 Bias Current @ VPin4 = VREF
−500
−
500
nA
−
−
2.7
3.6
0.6
3.0
−
−
3.3
IBPin4
VCONTROL
− VCONTROLMAX
− VCONTROLMIN
− D VCONTROLl
Pin 2 Voltage:
V
− @ VPin4 = 2 V
− @ VPin4 = 3 V
VOUTL / VREF
Ratio (VOUT Low Detect Threshold / VREF) (Note 4)
95.0
95.5
96.0
%
HOUTL / VREF
Ratio (VOUT Low Detect Hysteresis / VREF) (Note 4)
−
−
0.5
%
Pin 2 Source Current when (VOUT Low Detect) is activated
190
240
290
mA
ILEAKAGE
Current Sourced by Pin 13 @ VPin14 = 2.3 V
−500
−
500
nA
VSTDWN
Pin 13 Threshold for Shutdown
2.375
2.500
2.625
V
Overvoltage Protection Threshold
2.425
2.500
2.575
V
VOVP / VREF
Ratio (VOVP / VREF) (Note 3)
99.5
100.0
100.5
%
VUVP / VREF
Ratio UVP threshold over VREF
8
12
16
%
@ VPin14 = VOVP
@ VPin14 = VUVP
−500
−500
−
−
500
500
@ VPin4 = 1.00 V
@ VPin4 = 1.75 V
@ VPin4 = 2.50 V
54
156
313
60
182
370
69
214
428
−
5
−
V
0.9
1
1.1
V
IBOOST
Shutdown Block
Over and Under Voltage Protections
VOVP
IBPin14
Pin 13 Bias Current:
nA
Ramp Control
Pin 7 Source Current:
mA
IRAMP − 1.00 V
IRAMP − 1.75 V
IRAMP − 2.50 V
Vcl_ff
VCLCRM
RCT
Pin 7 Clamp Voltage @ VPin4 = VPin2 = 2 V and VPin6 = 0 V
Pin 7 Clamp Voltage @ VPin4 = 0 V, VPin2 = 2 V and VPin6 = 1 V
Ratio (Pin 7 Clamp Voltage / (Pin 7 Charge Current)
(VCLCRM / IRAMP) @ VPin6 = 0 V and
kW
− VPin4 = 1.00 V
− VPin4 = 1.75 V
− VPin4 = 2.50 V
TONMIN
Delay (VPin7 > 5 V) to (DRV low)
3. Not tested; guaranteed by characterization
4. Not tested; guaranteed by design
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3
−
−
−
16.7
5.4
2.7
−
−
−
−
90
200
ns
NCP1605, NCP1605A
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0°C to +125°C, unless otherwise specified) (Note 2)
Symbol
Rating
Min
Typ
Max
Unit
CINT
Average Pin 7 Internal Capacitance (VPin7 varying from 0 and 1 V)
Guaranteed by design
−
15
25
pF
VINIT
Maximum Pin 7 Voltage Allowing the Setting of the PWM Latch
−
50
90
mV
Pin 7 Sink Current (Drive low) @ VPin7 = 1 V
−
10
−
mA
−20
0
20
mV
IRAMP_SINK
Current Sense Block
Off100
Current Sense Pin Voltage, 100 mA being drawn from Pin 5
Off10
Current Sense Pin Voltage, 10 mA being drawn from Pin 5
3.0
8.0
13
mV
IMAX
Overcurrent Protection Threshold
230
250
265
mA
TOCP
(Ipin5 > 250 mA) to (DRV low) Propagation Delay (Note 3)
−
100
200
ns
KCS10
Ratio (IPin6/IPin5) @ IPin5 = 10 mA
99
108
117
%
KCS200
Ratio (IPin6/IPin5) @ IPin5 = 200 mA
98
101
103
%
VZCD
Pin 6 Comparator Threshold
50
100
200
mV
TZCD
Delay from (VPin6 < VZCD) to (DRV high)
−
120
240
ns
VSTBY
Standby Mode Threshold (VPin1 falling)
280
310
340
mV
HSTBY
Hysteresis for Standby Mode Detection
25
30
50
mV
99
100
101
%
Standby Input
VSKIPOUT / VOUTL Ratio (Pin 4 Voltage to terminate a SKIP period) over the
(VOUT Low Detect Threshold) (Note 4)
Oscillator / Synchronization Block
Icharge
Oscillator Charge Current
90
100
110
mA
Idisch
Oscillator Discharge Current
90
100
110
mA
Vsync_H
Comparator Upper Threshold
−
3.0
−
V
Vsync_L
Comparator Lower Threshold
Swing
Tsync_min
Comparator Swing (Vsync_H − Vsync_L)
Minimum Synchronization Pulse Width for Detection
−
2.0
−
V
0.9
1.0
1.1
V
−
−
500
ns
pfcOK / REF5V
VpfcOKL
Pin 12 Voltage @ VPin13 = 5 V, 250 mA being sunk by Pin 12
−
60
120
mV
VpfcOKH
Pin 12 Voltage @ VPin13 = 0 V and VPin3 = 5 V,
with a 250 mA sourced by Pin 12
Pin 12 Voltage @ VPin13 = 0 V and VPin3 = 5 V,
with a 5 mA sourced by Pin 12
4.7
5.0
5.3
V
4.5
5.0
5.3
Current Capability
5 .0
10
−
mA
Icap_ref
Brown−Out Detection Block
VBOH
Brown−Out Comparator Threshold (VPin2 rising)
0.9
1.0
1.1
V
VBOL
Brown−Out Comparator Threshold (VPin2 falling)
0.45
0.50
0.55
V
IBBO
Pin 2 Bias Current @ VPin2 = 0.5 V and 1 V
−500
−
500
nA
Thermal Shutdown
TLIMIT
Thermal Shutdown Threshold
−
155
−
°C
HTEMP
Thermal Shutdown Hysteresis
−
15
−
°C
14
9.5
15
10.5
16
11.5
V
VCC UNDERVOLTAGE Lockout Section
VCCON
Turn on Threshold Level, VCC Raising Up
NCP1605
NCP1605A
3. Not tested; guaranteed by characterization
4. Not tested; guaranteed by design
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4
NCP1605, NCP1605A
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0°C to +125°C, unless otherwise specified) (Note 2)
Symbol
VCCOFF
HUVLO
Rating
Minimum Operating Voltage after Turn−on
Difference (VCCON − VCCOFF)
NCP1605
NCP1605A
Min
Typ
Max
Unit
8.0
9.0
10
V
5.0
1.2
6.0
1.5
−
−
V
VCCSTUP
VCC Threshold below which the Startup Current Source Turns on
5.5
7.0
8.0
V
HLATCHOFF
Difference (VCCOFF − VCCSTUP)
0.6
2.0
−
V
VCC Level at which the Logic Resets
2.0
4.0
5.0
V
High−Voltage Current Source (sunk by Pin 16), VCC = 13.5 V
5
12
20
mA
Startup Charge Current flowing out of the VCC Pin, VCC = 13.5 V
5
12
20
mA
High−Voltage Current Source, VCC = 0 V
−
0.5
1.0
mA
−
2.0
310
310
2.5
3.5
570
550
5
7
780
750
mA
mA
mA
mA
VCCRST
Internal STARTUP Current Source
IC1_hv
IC1_Vcc
IC2
Device Consumption
Icc_op1
Icc_op2
Icc_OFF
Icc_latchOFF
Power Supply Current:
Operating (@ VCC = 16 V, no load, no switching)
Operating (@ VCC = 16 V, no load, switching)
Off Mode (@ VCC = 16 V, Pin 2 grounded)
Latched−Off Mode (@ VCC = 13.5 V and VPin13 = 5 V)
3. Not tested; guaranteed by characterization
4. Not tested; guaranteed by design
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5
NCP1605, NCP1605A
PIN FUNCTION DESCRIPTION
Pin
Number
Name
Function
1
STBY
An external signal (typically, a portion of the feedback signal of the downstream converter or a filtered
portion of the SMPS drive pulses) should be applied to Pin 1. When the Pin 3 voltage goes below
300 mV, the circuit enters a burst mode operation where the bulk voltage varies between the regulation
voltage and 95.5% of this level.
2
Brown−Out /
Inhibition
Apply a portion of the averaged input voltage to detect brown−out conditions. If VPin2 is lower than
0.5 V, the circuit stops pulsing until VPin2 exceeds 1 V (0.5 V hysteresis).
Ground Pin 6 to disable the part.
3
VCONTROL /
Soft−Start
The error amplifier output is available on this Pin. The capacitor connected between this pin and ground
adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor
ratios.
Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly
(soft−start).
4
Feedback
This pin receives a portion of the pre−converter output voltage. This information is used for the
regulation and the “output low” detection (VOUTL) that drastically speed up the loop response when the
output voltage drops below 95.5% of the wished level.
5
Current Sense
Input
This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the
maximum coil current and detect the core reset (coil demagnetization).
6
Current Sense
Output
This pin sources the Pin 5 current. Place a resistor between Pin 6 and ground to build the voltage
proportional to the coil current and detect the core reset. The impedance between Pin 6 and ground
should not exceed 3 times that of the Pin 5 to ground. You can further apply the voltage from an
auxiliary winding to improve the valley detection of the MOSFET drain source voltage.
7
Ct
(Ramp)
The circuit controls the power switch on−time by comparing the Pin 7 ramp to an internal voltage
(“Vton”) derived from the regulation block and the sensed “dcycle” (relative duration of the current cycle
over the corresponding switching period).
Pin 7 sources a current proportional to the squared output voltage to allow the Follower Boost operation
(optional) where the PFC output voltage stabilizes at a level that varies linearly versus the ac line
amplitude. This technique reduces the difference between the output and input voltages, to optimize the
boost efficiency and minimize the size and cost of the PFC stage
8
Oscillator /
synchronization
Connect a capacitor or apply a synchronization signal to this pin to set the switching frequency. If the
coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the
core is reset. Hence, the PFC stage can operate in CRM in the most stressful conditions.
9
GND
Connect this pin to the pre−converter ground.
10
Drive
The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively
drive high gate charge power MOSFETs.
11
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 15 V (10.5 V
for NCP1605A) and turns off when VCC goes below 9 V (typical values). After startup, the operating
range is 10 V up to 20 V.
12
PfcOK / REF5V
The Pin 12 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low
otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and
that hence, it can start operation.
13
STDWN
14
OVP / UVP
15
NC
Creepage distance.
16
HV
Connect Pin 16 to the bulk capacitor. The internal startup current source placed between Pin 16 and the
VCC terminal, charges the VCC capacitor at startup.
Apply a voltage higher than 2.5 V on Pin 13 to permanently shutdown the circuit. This pin can be used
to monitor the voltage across a thermistor in order to protect the application from an excessive heating
and/or to detect an overvoltage condition.
To resume operation, it is necessary to decrease the circuit VCC below VCCRST (4 V typically) by for
instance, unplugging the PFC stage and replugging it after VCC is discharged.
The circuit turns off when VPin14 goes below 480 mV (UVP) and disables the drive as long as the pin
voltage exceeds 2.5 V (OVP).
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6
NCP1605, NCP1605A
2.59
265
2.57
260
2.55
255
IREF, (mA)
VREF, (V)
2.53
2.51
2.49
2.47
245
2.45
240
2.43
2.41
−40
−15
10
35
60
85
235
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Reference Voltage vs. Temperature
Figure 3. Reference Current vs. Temperature
103
2.60
102
VOVP/VREF, (%)
2.56
2.52
2.48
2.44
101
100
99
98
2.40
−40
−15
10
35
60
85
97
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Overvoltage Threshold vs. Temperature
Figure 5. Ratio Overvoltage Threshold
Overvoltage Reference vs. Temperature
2.61
2.56
VSTDWN, (V)
VOVP, (V)
250
2.51
2.46
2.41
2.36
−40
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
110
Figure 6. Shutdown Threshold vs. Temperature
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7
NCP1605, NCP1605A
0.6
0.5
15.16
VUVPVREF, (%)
VUVP, (V)
0.4
0.3
0.2
11.08
9.04
0.1
0
−40
−15
10
35
60
85
7
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Undervoltage Protection Threshold vs.
Temperature
Figure 8. Ratio (VUVP/VREF) vs. Temperature
15.4
9.7
9.4
15.1
9.1
14.8
VCCOFF, (V)
VCCON, (V)
13.12
14.5
14.2
13.9
−40
8.8
8.5
8.2
−15
10
35
60
85
7.9
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. VCC Turn on Threshold vs.
Temperature (VCC Raising Up) − NCP1605
Figure 10. VCC Minimum Operating Voltage
After Turn On
8.8
6.7
8.3
7.8
VCCSTUP, (V)
HUVLO, (V)
6.4
6.1
5.8
7.3
6.8
6.3
5.8
5.5
5.3
5.2
−40
−15
10
35
60
85
4.8
−40
110
TJ, JUNCTION TEMPERATURE (°C)
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Difference (VCCON − VCCOFF) vs.
Temperature
Figure 12. VCC Threshold Below which the Startup
Current Source Turns on vs. Temperature
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8
NCP1605, NCP1605A
4
6
3.5
5
VCCRST, (V)
HLATCHOFF, (V)
3
2.5
2
1.5
3
2
1
1
0.5
−40
−15
10
35
60
85
0
−40
110
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Difference (VCCOFF−VCCSTUP) vs.
Temperature
Figure 14. VCC Level Below Which the
Logic Resets vs. Temperature
20
20
18
18
16
16
IC1_VOFF, (mA)
IC1_HV, (mA)
4
14
12
10
14
12
10
8
8
6
6
4
110
4
−40
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. High−Voltage Current Source (Sunk
by Pin 16) vs. Temperature (@ VCC = 13.5 V)
Figure 16. Startup Charge Current Flowing Out
of the VCC Pin vs. Temperature (@ VCC = 13.5 V)
90
1.2
80
70
HV_LEAKAGE, (mA)
IC2, (mA)
0.9
0.6
0.3
60
50
40
30
20
10
0
−40
0
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. High−Voltage Current Source vs.
Temperature (@ VCC = 0 V)
Figure 18. Pin 16 Leakage Current vs.
Temperature (@ VPIN16 = 500 V and VCC = 16 V)
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9
24
−12
22
−14
20
−16
IEA_SINK, (mA)
IEA_SOURCE, (mA)
NCP1605, NCP1605A
18
16
−18
−20
−22
14
12
−40
−15
10
35
60
85
−24
−40
110
−15
TJ, JUNCTION TEMPERATURE (°C)
35
60
85
110
Figure 20. Sink Current Capability of the Error
Amplifier vs. Temperature
300
150
260
100
220
50
IBPIN4, (nA)
GEA, (mS)
Figure 19. Source Current Capability of the
Error Amplifier vs. Temperature
180
140
100
0
−50
−100
60
−40
−15
10
35
60
85
−150
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Error Amplifier Gain vs. Temperature
Figure 22. Feedback Pin Bias Current vs.
Temperature (@ VPIN4 = VREF)
3.9
3.3
3.8
3.2
3.7
3.1
D(VCONTROL), (V)
VCONTROLMAX, (V)
10
TJ, JUNCTION TEMPERATURE (°C)
3.6
3.5
3.4
2.9
2.8
2.7
3.3
3.2
−40
3
2.6
−15
10
35
60
85
110
−40
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VCONTROL Maximum Voltage vs.
Temperature
Figure 24. VCONTROL Maximum Swing
(DVCONTROL) vs. Temperature
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10
110
95.9
270
95.8
260
95.7
250
95.6
240
IBOOST, (mA)
VOUTL/VREF, (%)
NCP1605, NCP1605A
95.5
95.4
230
220
95.3
210
95.2
200
95.1
190
−40
−15
10
35
60
85
110
−40
TJ, JUNCTION TEMPERATURE (°C)
105
105
100
100
IDISCH, (mA)
ICHARGE, (mA)
110
95
90
85
85
35
60
85
80
−40
110
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. Oscillator Charge Current vs.
Temperature
Figure 28. Oscillator Discharge Current vs.
Temperature
150
125
pfcOK_L (mV)
0.99
SWING, (V)
85
TJ, JUNCTION TEMPERATURE (°C)
1.01
0.97
0.95
0.93
0.91
−40
60
95
90
10
35
Figure 26. Pin 3 Source Current when (VOUT Low
Detect Threshold) is Activated vs. Temperature
110
−15
10
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. Ratio (VOUT Low Detect Threshold) /
VREF vs. Temperature
80
−40
−15
100
75
50
25
−15
10
35
60
85
0
−40
110
TJ, JUNCTION TEMPERATURE (°C)
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Oscillator Swing vs. Temperature
Figure 30. pfcOK Pin Low Level Voltage vs.
Temperature
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5.5
5
5.3
4
ICC_OP1, (mA)
pfcOK_H, (V)
NCP1605, NCP1605A
5.1
4.9
4.7
2
1
4.5
−40
−15
10
35
60
85
0
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. pfcOK Pin High Level Voltage vs.
Temperature (250 mA Load)
Figure 32. Operating Consumption vs.
Temperature (VCC = 16 V, No Load, No Switching)
800
5
700
ICCOFF, (mA)
6
4
3
600
500
400
2
1
−40
−15
10
35
60
85
300
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. Operating Consumption vs.
Temperature (VCC = 16 V, No Load, Switching)
Figure 34. Off Mode Consumption vs.
Temperature (VCC = 16 V, Pin 2 Grounded)
800
700
ICCSTDOWN, (mA)
ICC_OP2, (mA)
3
600
500
400
300
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. Shutdown Mode Consumption vs.
Temperature (VCC = 16 V, Pin 2 GND)
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12
NCP1605, NCP1605A
1.05
0.55
VCBOL, (V)
0.6
VCBOH, (V)
1.1
1
0.95
0.5
0.45
0.9
0.4
−40
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 36. Brown−Out Upper Threshold vs.
Temperature
Figure 37. Brown−Out Lower Threshold vs.
Temperature
14
14
12
12
8
OFF10, (mV)
OFF100, (mV)
10
6
4
10
8
6
2
4
0
−2
2
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 38. Current Sense Pin Voltage vs.
Temperature (100 mA Being Drawn from Pin 5)
Figure 39. Current Sense Pin Voltage vs.
Temperature (10 mA Being Drawn from Pin 5)
68
208
66
203
198
64
IRAMP_1.75 V, (mA)
IRAMP_1.00 V, (mA)
−40
62
60
58
56
193
188
183
178
173
168
54
163
158
−40
52
−40
−15
10
35
60
85
110
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. Pin 7 Source Current
@ VPIN4 = 1.0 V vs. Temperature
Figure 41. Pin 7 Source Current
@ VPIN4 = 1.75 V vs. Temperature
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13
110
NCP1605, NCP1605A
8
415
405
7
385
RCT (kW)
IRAMP_2.50 V, (mA)
395
375
365
6
5
355
345
4
335
325
−40
−15
10
35
60
85
3
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 42. Pin 7 Source Current @
VPIN4 = 2.5 V vs. Temperature
Figure 43. Ratio Pin 7 Clamp Voltage /
(Pin 7 Charge Current) that is (VCLCRM / IRAMP)
@ VPIN6 = 0 V and VPIN4 = 1.75 V
112
200
180
160
VZCD, (mV)
Kcs10, (%)
110
108
106
140
120
100
80
60
104
−40
−15
10
35
60
85
40
−40
110
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 44. Ratio (IPIN6 / IPIN5) @ IPIN5 = 10 mA vs.
Temperature
Figure 45. Pin 6 Comparator Threshold vs.
Temperature
220
340
200
330
180
320
VSKIPH, (V)
160
TZCD, (ns)
−15
140
120
100
310
300
290
80
280
60
270
40
−40
−15
10
35
60
85
260
−40
110
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 46. Delay from (ZCD Pin Low) to
(DRV High) vs. Temperature
Figure 47. Skip Cycle Threshold
(VPIN1 Falling) vs. Temperature
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110
26
160
24
140
22
120
20
ROH, (W)
180
100
80
18
16
60
14
40
12
20
10
0
−40
−15
10
35
60
85
8
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 48. Minimum On−Time vs. Temperature
Figure 49. Gate Drive Source Resistance vs.
Temperature
16
14
12
ROL, (W)
tOMIN, (ns)
NCP1605, NCP1605A
10
8
6
4
2
−40
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
110
Figure 50. Gate Drive Sink Resistance vs. Temperature
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NCP1605, NCP1605A
Vout Low Detect
95.5% Vref
200 mA
VoutL
+
-
V/I
Iout
Vcontrol
VDD
TSD
UVP
BO_NOK
STDWN
3V
FLAG1
VSTBY
300 mV
VREGUL
R
SKIP
FAULT
Management
OVP
Vref
Vton
processing
circuitry
VDD
DT
VREGUL
pfcOK
VoutL
HVCS_ON
NC
OFF
2.R
LSTBY
S
Q
R
+
UVLO (Vcc<VccOFF)
FLAG1
SKIP
+
HV
UVLOs
Latch
Reset
Internal
Thermal
Shutdown
OFF
STBY
HVCS_ON
UVLO
pfcOK
Error Amplifier
VSTBY
+
±20 mA
Vref
FB
All the RS latches are
RESET dominant
+
Ich=K.Iout.Iout
VCC
SKIP
R R
R
Q
R PWM
S Latch
OFF
OCP
Ct
Regul
Vt(on)
PWM
Comparator
OVP
Iref
VCC
outON
Output
Buffer
Drv
outON
CLK
BO /
Stdwn
+
1 V / 0.5 V
Ics
+
100 mV
CSout
outON
Ct_OK
Oscillator /
Synchronization
Block
DT
Ics
CSin
50 mV
BO_NOK
+
ZCD
Q
R
Dead−time
Detection
Latch
S
OCP
Ics > 250 mA
ZCD
+
-
REF5V
pfcOK
OVP
12% Vref
+
Vovp = Vref
+
-
UVP
S
Lstup Q
R
FLAG1
OFF
OVP
Vref
+
S
R
Q
stdwn
Vcc<VccRST
STDWN
Fi
OSC /
SYNC
51 Bl
k Di
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16
pfcOK /
REF5V
GND
NCP1605, NCP1605A
DETAILED OPERATING DESCRIPTION
Introduction
− The NCP1605(A) disables the drive to stop
delivering power as long as the output voltage
exceeds the Overvoltage Protection (OVP) level.
− The NCP1605(A) drastically speeds up the
regulation loop when the output voltage is below
95.5% of its regulation level. This function is
allowed only after the PFC stage has started up
not to eliminate the soft−start effect.
PFC OK: the circuit detects when the circuit is in normal
situation or if on the contrary, it is in a startup or fault
condition. In the first case, Pin 12 is in high state and low
otherwise. Pin 12 serves to control the downstream
converter operation in response to the PFC state.
Safety Protections: the NCP1605(A) permanently
monitors the input and output voltages, the coil current and
the die temperature to protect the system from possible
over−stresses and make the PFC stage extremely robust and
reliable. In addition to the aforementioned OVP protection,
one can list:
− Maximum Current Limit and Zero Current
Detection: the circuit permanently senses the
coil current and immediately turns off the
power switch if it is higher than the set current
limit. It also prevents any turn on of the power
switch as long as some current flows through
the coil, to ensure operation in DCM. This
feature also protects the MOSFET from the
excessive stress that could result from the
large in−rush currents that occurs during the
startup phases.
− Undervoltage Protection: the circuit turns off
when it detects that the output voltage goes
below 12% of the OVP level (typically). This
feature protects the PFC stage from starting
operation in case of too low ac line conditions
or in case of a failure in the OVP monitoring
network (e.g., bad connection).
− Brown−Out Detection: the circuit detects too
low ac line conditions and stop operating in
this case. This protection protects the PFC
stage from the excessive stress that could
damage it in such conditions.
− Thermal Shutdown: an internal thermal
circuitry disables the circuit gate drive and then
keeps the power switch off when the junction
temperature exceeds 150°C typically. The circuit
resumes operation once the temperature drops
below about 100°C (50°C hysteresis).
Output Stage Totem Pole: the NCP1605(A)
incorporates a −0.5 A / +0.8 A gate driver to efficiently
drive most TO220 or TO247 power MOSFETs.
The NCP1605(A) is a PFC driver designed to operate in
fixed frequency, Discontinuous Conduction Mode (DCM). In
the most stressful conditions, Critical Conduction Mode
(CRM) can be achieved without power factor degradation and
the circuit could be viewed as a CRM controller with a
frequency clamp (given by the oscillator). Finally, the
NCP1605(A) tends to give the best of both modes without
their respective drawbacks. Furthermore, the circuit
incorporates protection features for a rugged operation
together with some special circuitry to lower the power
consumed by the PFC stage in no load conditions. More
generally, the NCP1605(A) functions make it the ideal
candidate in systems where cost−effectiveness, reliability,
low standby power and high power factor are the key
parameters:
• Compactness and Flexibility: the controller requires
few external components while offering a large variety
of functions. Depending on the selected coil and
oscillator frequency you select, the circuit can:
1. Mostly operate in CRM and use the oscillator as a
frequency clamp.
2. Mostly operate in fixed frequency mode and only
run in CRM at high load and low line.
3. Permanently operate in fixed frequency mode
DCM.
In all cases, the circuit provides near−unity power factor.
Skip−cycle capability for low power standby: among
other applications, the circuit targets power supply where
the PFC stage must keep alive even in standby. A
continuous flow of pulses is not compatible with no−load
standby power requirements. Instead, the controller slices
the switching pattern in bunch of pulses to drastically
reduce the overall losses. The skip cycle operation is
initiated by applying to Pin 1, a signal that goes below
300 mV in standby. Typically, this signal is drawn from the
feedback of the downstream converter.
Startup Current Source and large VCC range:
meeting low standby power specifications represents a
difficult exercise when the controller requires an external,
lossy resistor connected to the bulk capacitor. The
controller disables the high−voltage current source after
startup which no longer hampers the consumption in
no−load situations. In addition, the large VCC range (10 V
to 20 V after startup), highly eases the circuit biasing.
Fast Line / Load Transient Compensation: given the
low bandwidth of the regulation block, the output voltage
of PFC stages may exhibit excessive over and undershoots
because of abrupt load or input voltage variations (e.g. at
startup). If the output voltage is too far from the regulation
level:
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17
NCP1605, NCP1605A
NCP1605(A) Operation Modes
•
•
•
DCM. It is worth noting that jumps between the CRM
and modes cause absolutely no degradation: the input
current keeps being properly shaped and there is no
discontinuity in the power transfer.
Given the dead−time presence, DCM needs a higher peak
inductor current compared to CRM for the same delivered
power. Hence, the coil is generally designed to have CRM
at the most stressful conditions while DCM limits the
switching frequency at lower load. The circuit can also
transition within an ac line cycle so that:
• CRM reduces the current stress around the sinusoid
top.
• DCM limits the frequency around the line zero
crossing.
This capability offers the best of each mode without the
drawbacks. The way the circuit modulates the MOSFET
on−time allows this facility.
Like the NCP1601, the NCP1605(A):
Features a current sense block that prevents the PFC
stage from operating in CCM: as long as the coil
current is not null, the power switch is not allowed to
turn on. Hence the circuit can only operate in either
Fixed Frequency DCM or CRM.
Features the capability to exhibit near−unity power
factor while operating in any type of Discontinuous
Conduction Mode operation: DCM or CRM.
Auto adapts: if there is some current flowing through
the coil when the clock occurs to initiate a new current
cycle, the PFC stage enters CRM. On the other hand,
if the clock occurs during dead−times, one obtains a
fixed frequency operation DCM. Thanks to its special
oscillator/synchronization arrangement, the circuit
automatically enters the appropriate mode CRM or
Current
Inductor Current, IL
Input Current, Iin
Time
DCM
Critical Mode
DCM
Figure 52. DCM and CRM Operation Within a Sinusoid Cycle
The NCP1605(A) can jump from DCM to CRM within a sinusoid cycle (and vice versa)
without any discontinuity in the current shaping or the power transfer.
NCP1605 On−time Modulation
One can show (refer to NCP1601 data sheet) that the ac
line current is given by:
Let’s study the ac line current absorbed by the PFC boost.
The initial inductor current of each switching cycle is
always zero. The coil current ramps up when the MOSFET
is on. The slope is (VIN/L) where L is the coil inductance.
At the end of the on−time (t1), the coil demagnetization
phase starts. The coil current ramps down until this
sequence ends when it reaches zero. The duration of this
phase is (t2). The system enters then the dead−time (t3) that
lasts until the next clock is generated.
Iin + Vin
ƪt1 (t21T)L t2)ƫ
(eq. 1)
Where T = (t1 + t2 + t3) is the switching period and VIN is
the ac line rectified voltage.
To the light of this equation, we immediately note that IIN
is proportional to VIN if [t1(t1 + t2)/T] is a constant.
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NCP1605, NCP1605A
Iin
Vin
Inductor Current
L
Vout
Ipk
t1
Figure 53. PFC Boost Converter
Cpin7 @ VTON
Ipin7
(eq. 2)
Iin + k @ Vin
where : k + constant +
ƪ120Cpin7m @@LV@REGUL
ƫ
(Vpin2)
(eq. 3)
timing capacitor
saw−tooth
Ich
(eq. 4)
PWM
comparator
+
to PWM latch
−
PWM Comparator
VREGUL
Cramp
2
The input current is then proportional to the input
voltage. Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CRM
case. This condition is just a particular case of this
functioning where (t3 = 0), which leads to (t1 + t2 = T) and
(VTON = VREGUL). That is why the NCP1605 automatically
adapts to the conditions and jumps from DCM and CRM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
Remark: Like in the NCP1601, the “VTON processing
circuit” is “informed” when there is an OVP condition, not
to over−dimension VTON in that conditions. Otherwise, an
OVP sequence would be viewed as a dead−time phase by
the circuit and VTON would inappropriately increase to
compensate it.
Similarly, the “VTON processing circuit” is inhibited for
a skip sequence not to over−dimension “VTON” in this case
(refer to Figure 56).
T @ VREGUL
t ) t2
or : VTON @ 1
+ VREGUL
t1 ) t2
T
Closed When
Output Low
Time
Given the regulation low bandwidth of the PFC systems,
(VCONTROL) and then (VREGUL) are slow varying signals.
Hence, the (VTON * (t1 + t2)/T) term is substantially
constant. Provided that in addition, (t1) is proportional to
(VTON), equation (1) leads to: (Iin = k * Vin), where k is a
constant. More exactly:
The charge current that is sourced by Pin 7
[Ipin7 = 60 mA/V2 * (VPin4)2] is constant at a given input
voltage (VPin4 is proportional to the output voltage). Cpin7
that is the capacitor connected between Pin 7 and ground
is also a constant. Hence, the power factor correction is
achieved when the VTON (t1 + t2)/T term is constant.
The output of the regulation block (VCONTROL) is
linearly changed into a signal (VREGUL) varying between
0 and 1 V. (VREGUL) is the voltage that is injected into the
PWM section to modulate the MOSFET duty−cycle.
However, like the NCP1601, the NCP1605(A) inserts some
circuitry that processes (VREGUL) to form the signal
(VTON) that is used in the PWM section instead of
(VREGUL) (see Figure 56). (VTON) is modulated in response
to the dead−time sensed during the precedent current
cycles, that is, for a proper shaping of the ac line current
(refer to NCP1601 data sheet). This modulation leads to:
VTON +
t3
Figure 54. Inductor Current in DCM
The NCP1605(A) operates in voltage mode. As
portrayed by Figure 55, the MOSFET on time t1 is
controlled by the signal Vton generated by the regulation
block and the Pin 4 ramp as follows:
t1 +
t2
T
Vton
R1
+
−
Turns Off MOSFET
OFF
S1
−> Vton during (t1+t2)
−> 0 V during t3 (dead−time)
−> Vton*(t1+t2)/T in average
Ramp Voltage
SKIP
S3
C1
IN1
Vton
OA1
Vton
OVP
S2
DT
(high during
dead−time)
Figure 56. VTON Processing Circuit
PWM Outtage
The integrator OA1 amplifies the error between VREGUL and
IN1 so that in average, (VTON*(t1+t2)/T) equates VREGUL.
Figure 55. PWM Circuit and Timing Diagram
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19
Vin (V)
NCP1605, NCP1605A
350,00
3,50
300,00
3,00
250,00
2,50
200,00
2,00
150,00
1,50
100,00
1,00
50,00
0,50
0,00
0,00
0
2
4
6
8
10
time (ms)
12
14
16
18
20
Figure 57. Input Voltage and On−time vs Time (example with FSW = 100 kHz, Pin =150 W, VAC = 230 V, L = 200 mH)
Regulation Block and Low Output Voltage Detection
A transconductance error amplifier with access to the
inverting input and output is provided. It features a typical
transconductance gain of 200 mS and a maximum
capability of ±20 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and
monitored by the inverting input (feedback pin − Pin 4).
The bias current is minimized (less than 500 nA) to allow
the use of a high impedance feedback network. The output
of the error amplifier is pinned out for external loop
compensation (Pin 3). Typically a capacitor in the range of
100 nF, is applied between Pin 3 and ground, to set the
regulation bandwidth below 20 Hz, as need in PFC
applications.
Vout Low
Detect
FB
Vcontrol
0.955*Vref
+
Vref
+
pfcOK
The swing of the error amplifier output is limited within
an accurate range:
• It is forced above a voltage drop (VF) by some circuitry.
• It is clamped not to exceed 3.0 V + the same VF voltage
drop.
Hence, VPin3 features a 3 V voltage swing. VPin3 is then
offset down by (VF) and divided by three before it connects
to the “VTON processing block” and the PWM section.
Finally, the output of the regulation is a signal (“VREGUL”
of the block diagram) that varies between 0 and 1 V.
VREGUL
200 mA
1V
Error
Amplifier
±20 mA
OVLflag1
+
VF
OFF
2R
3V
+
VF
VREGUL
0V
R
VF
Figure 58. Regulation Block
3 V + VF
VCONTROL
Figure 59. Correspondence between VCONTROL
and VREGUL
200 mA current source to speed−up the charge of the
compensation capacitor (Cpin3). Finally, it is like if the
comparator multiplied the error amplifier gain by 10.
One must note that this circuitry for undershoots limitation,
is not enabled during the startup sequence of the PFC stage
but only once the converter has stabilized (that is when the
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
undershoots. Overshoots are limited by the Overvoltage
Protection (see OVP section). To contain the undershoots, an
internal comparator monitors the feedback (VPin4) and when
VPin4 is lower than 95.5% of its nominal value, it connects a
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20
NCP1605, NCP1605A
Hence, one obtains the Follower Boost characteristics. The
“Follower Boost” is an operation mode where the
pre−converter output voltage stabilizes at a level that varies
linearly versus the ac line amplitude. This technique aims at
reducing the gap between the output and input voltages to
optimize the boost efficiency and minimize the cost of the
PFC stage (refer to the MC33260 data sheet for more
information, at:
http://www.onsemi.com/pub/Collateral/MC33260−D.PDF ).
Remark: the timing capacitor applied to Pin 7 is
discharged and maintained grounded when the drive is low.
Furthermore, the circuit compares the Pin 7 voltage to an
internal reference 50 mV and prevents the PWM latch from
being set as long as VPin7 is higher than this low threshold.
This is to guarantee that the timing capacitor is properly
discharged before starting a new cycle.
“pfcOK” signal of the block diagram, is high). This is
because, at the beginning of operation, the Pin 3 capacitor
must charge slowly and gradually for a soft−startup.
Remark: As shown in block diagram, the circuitry for
undershoots limitation is disabled as long as Pin 3 detects
standby conditions (VPin3 < 300 mV). This is to suppress the
risk of audible noise in standby thanks to the soft–start that
softens the bursts.
On−Time Control for Maximum Power Adjustment
As aforementioned, the NCP1605(A) processes the error
amplifier output voltage to form a signal (VTON) that is used
by the PWM section to control the on−time. (VTON)
compensates the relative weight of the dead−time sequences
measured during the precedent current cycles. During the
conduction time of the MOSFET, Pin 7 sources a current that
is proportional to the square of the voltage applied to Pin 4
(feedback pin). Practically, as Pin 4 receives a portion of the
output voltage (VOUT), IPin7 is proportional to the square of
VOUT.
The MOSFET turns off when the Pin 7 voltage exceeds
VTON. Hence, the MOSFET on−time (t1) is given by:
t1 +
Current Sense and Zero Current Detection
The NCP1605(A) is designed to monitor a negative
voltage proportional to the coil current. Practically, a
current sense resistor (RCS) is inserted in the return path to
generate a negative voltage proportional to the coil current
(VCS). The circuit uses VCS for two functions: the
limitation of the maximum coil current and the detection
of the core reset (coil demagnetization). To do so, the
circuit incorporates an operational amplifier that sources
the current necessary to maintain the CS pin voltage null
(refer to Figure 60). By inserting a resistor ROCP between
the CS pin and RCS, we adjust the CS pin current as follows:
Cpin7 VTON
where k is a constant.
k VOUT 2
The coil current averaged over one switching period is:
t ICOIL u T + IIN(t) +
VIN t1 (t1 ) t2)
T
2L
Where IIN(t) and VIN(t) are the instantaneous input current
and voltage, respectively, t2 is the core reset time and T is the
switching period. Hence, the instantaneous input power is
given by the following equation:
* [RCS ICOIL] ) [ROCP Ipin5] + Vpin5 [ 0
Which leads to:
Cpin7 VIN2 VTON (t1 ) t2)
PIN(t) + VIN(t)IIN(t) +
@
T
2 L k VOUT 2
In other words, the Pin 5 current is proportional to the coil
current.
IPin5 is utilized as follows:
• If IPin5 exceeds 250 mA, an overcurrent is detected and
the PWM latch is reset. Hence, the maximum coil
current is:
As aforementioned, we have: VTON (t1 + t2)/T = VREGUL
where VREGUL is the signal outputted by the regulation
block. Hence, the average input power is:
t PIN u+
Cpin7 Vac 2
V
2 L k VOUT 2 REGUL
R
(ICOIL)max + OCP 250 mA
RCS
The maximum value of VREGUL being 1 V, the maximum
power that can be delivered is:
t PIN u MAX +
Cpin7 Vac 2
1V
2 L k VOUT2
•
To the light of the last equations, one can note that the PFC
power capability is inversely proportional to the square of the
output voltage. One sees that if the power demand is too high
to keep the regulation, (VREGUL=1V) and the power delivery
depends on the output voltage level that stabilizes to the
following value:
VOUT +
R
Ipin5 + CS ICOIL
ROCP
The propagation delay (Ipin5 higher than 250 mA) to
(drive output low) is in the range of 100 ns, typically.
The Pin 5 current is internally copied and sourced by
Pin 6. Place a resistor (RPin6) between Pin 6 and ground
to build a voltage proportional to the coil current. The
circuit detects the core reset when VPin6 drops below
100 mV, typically. The Pin 6 voltage equating:
Vpin6 +
Ǹ
Cpin7 1 V
V
2 L k h POUT ac
Rpin6 @ Rcs
@ ICOIL ,
Rcs
the coil current threshold for zero current detection is:
Where:
• POUT is the output power.
• And h is the efficiency.
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NCP1605, NCP1605A
100 mV
400 W
ROCP
(ICOIL)zcd +
100 mV +
@ (ICOIL)MAX +
@ (ICOIL)MAX
Rpin6 @ RCS
Rpin6
Rpin6 @ 250 mA
Rdrv
Rzcd
Vin
D1
Icoil
6
EMI
Filter
Vdd
Cin
Current Mirror
Vdd
Ics
L1
CSout
100 mV
+
-
ZCD
Ics
Rsense
output
buffer
Ics > 250 mA ≥ OCP
M1
Vcc
DRV
Cbulk
LOAD
10
outON
Vzcd
Rocp CSin
Vout
S
LdT Q
R
DT
OCP
(RESET of the PWM latch)
5
Icoil
Figure 60. Current Sense Block
The CS block performs the overcurrent protection and the zero current detection.
The propagation delay (VPin6 lower than 100 mV) to (drive
output high) is in the range of 300 ns, typically.
• It is worth highlighting that the circuit permanently
The Zero Current Detection:
• Is used to detect the dead−time sequences (“DT” high)
and hence, to process (VTON) from the error amplifier
output (VCONTROL). In other words, this is an input of
the on−time modulation block.
• Prevents the MOSFET from turning on as long as the
“DT” and “ZCD” signals are low. This is the case as
long as some current flows through the coil. This
delaying action on the output stage tends to make the
MOSFET turn on at the valley. To further optimize the
valley switching, one can apply the voltage of an
auxiliary winding to Pin 6 (CSOUT). The voltage is
compared to an internal 100 mV reference, so that
ZCD turns high only if (VPin6 < 100 mV).
•
senses the coil current and that it prevents any turn on
of the power switch as long as the core is not reset.
This feature protects the MOSFET from the possible
excessive stress it could suffer from, if it was allowed
to turn on while a huge current flows through the coil.
In particular, this scheme effectively protects the PFC
stage during the startup phase when huge in−rush
currents charge the output capacitor.
In addition this detection method does not require any
auxiliary winding. A simple coil can then be used in
the PFC stage.
It is recommended to:
1. Keep ROCP equal to or lower than 5 kW
2. Choose RZCD as high as possible but not bigger
than (3 x ROCP). This is to avoid that the Pin 6
leakage prevents a proper zero current detection.
For instance, if ROCP is 2.2 kW, RZCD should not
exceed 6.6 kW.
Remarks:
• A resistor can be placed between Pin 6 and ground to
increase the ZCD precision.
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NCP1605, NCP1605A
NCP1605(A) dedicates one specific pin for the
undervoltage
and overvoltage protections. The
NCP1605(A) configuration allows the implementation of
two separate feedback networks (see Figure 62):
− One for regulation applied to Pin 4.
− Another one for the OVP function.
3. Place a resistor RDRV between the drive pin and
Pin 6 to ease the circuit detection by creating
some over−riding at the turn on instant. RDRV
should be selected in the range of 3 times RZCD.
For instance, if RZCD is 6.2 kW, a 22 kW resistor
can be used for RDRV.
Overvoltage Protection
While PFC circuits often use one single pin for both the
Overvoltage Protection (OVP) and the feedback, the
Vout (bulk voltage)
Rout1
1 16
2 15
Rout3
FB
3 14
Vout (bulk voltage)
HV
1 16
2 15
Rout1
OVP
FB
4 13
5 12
Rout2
7 10
8
8
Figure 61. Configuration with One Feedback
Network for Both OVP and Regulation
Rovp2
9
PfcOK / REF5V Signal
The NCP1605(A) can communicate with the
downstream converter. The signal “pfcOK/REF5V is high
(5 V) when the PFC stage is in normal operation (its output
voltage is stabilized at the nominal level) and low
otherwise.
More specifically, “pfcOK/REF5V” is low:
• During the PFC stage startup, that is, as long as the
output voltage has not yet stabilized at the right level.
The startup phase is detected by the latch “LSTUP” of the
block diagram. “LSTUP” is set during each “off” phase so
that its output (“STUP”) is high when the circuit enters
an active phase. The latch is reset when the error
amplifier stops charging its output capacitor, that is,
when the output voltage of the PFC stage has reached its
desired regulation level. At that moment, “STUP” falls
down to indicate the end of the startup phase.
• In case of a condition preventing the circuit from
operating properly, i.e., during the VCC charge by the
high voltage startup current source, in a Brown−out
case or when one of the following major faults turns
off the circuit:
− Incorrect feeding of the circuit (“UVLO” high when
VCC<VCCOFF, VCCOFF equating 9 V typically).
− Excessive die temperature detected by the thermal
shutdown.
− Undervoltage Protection
Rout1 ) Rout2 ) Rout3
@ Vref
Rout2 ) Rout3
The OVP level is:
Vovp +
Rovp1
Figure 62. Configuration with Two Separate
Feedback Networks
The double feedback configuration offers some
up−graded safety level as it protects the PFC stage even if
there is a failure of one of the two feedback arrangements.
However, if wished, one single feedback arrangement is
possible as portrayed by Figure 61. The regulation and
OVP blocks having the same reference voltage, the
resistance ratio Rout2 over Rout3 adjusts the OVP
threshold. More specifically,
The bulk regulation voltage is:
Vout +
6 11
7 10
9
OVP
4 13
5 12
6 11
Rout2
3 14
HV
Rout1 ) Rout2 ) Rout3
@ Vref
Rout2
The ratio OVP level over regulation level is:
R
Vovp
+ 1 ) out3
Vout
Rout2
For instance, (VOVP = 105% * Vout) leads to the
following constraint: (Rout3 = 5% * Rout2).
As soon and as long as the circuit detects that the output
voltage exceeds the OVP level, the power switch is turned
off to stop the power delivery.
Remark: Like in the NCP1601, the “VTON processing
circuit” is “informed” when there is an OVP condition, not
to over−dimension VTON in that conditions. Otherwise, an
OVP sequence would be viewed as a dead−time phase by
the circuit and VTON would inappropriately increase to
compensate it (refer to Figure 56).
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NCP1605, NCP1605A
accomplished by monitoring the Pin 1 voltage that must
receive a voltage below 300 mV in light load conditions.
Practically, a portion of the feedback signal of the
downstream converter (or some other signal able to indicate
that the power demand is low) should be applied to Pin 1.
− Latched off of the circuit (when the “STDWN” pin,
VPin13, exceeds 2.5 V).
And “pfcOK/REF5V” is high when the PFC output
voltage is properly and safely regulated. “pfcOK/REF5V”
should be used to allow operation of the downstream
converter.
Standby Management
The NCP1605(A) automatically skips switching cycles
when the power demand drops below a given level. This is
PFC stage
downstream converter
Rectified
AC line
1 16
2 15
+
3 14
4 13
+
5 12
VCC
6 11
SMPS
controller
7 10
8
9
NCP1605
Standby Input
Voltage
C
Feed−back of the
downstream converter
Figure 63. Signal for Standby Detection
In normal operation, the circuit controls the continuous
absorption of the line current necessary for matching the load
power demand. When the voltage applied to Pin 1 goes below
300 mV:
• The output pulses are blanked and Pin 3
(“VCONTROL”) is grounded.
• The output of the PFC stage being not fed any more, it
drops. When the output voltage goes below 95.5% of
the regulation level, the circuit resumes operation until
“FLAG1” becomes low (what means that the output
voltage has exceeded the regulation level).
• At that moment, if VPin1 is still below 300 mV, a new
skipping phase starts.
In other words, instead of continuously providing the
output with a small amount of power, the circuit operates
from time to time at a higher power level. As an example
and to make it simple, instead of continuously supplying
1% of PMAX, the circuit can provide the load with 10% of
PMAX for 10% of the time. The IC enters the so−called skip
cycle mode, also named controlled burst operation. This
burst operation is much more efficient compared to a
continuous power flow as it drastically reduces the number
of pulsations and therefore the switching losses associated
to them.
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NCP1605, NCP1605A
VPin1
300 mV
VCONTROL
VOUT
95.5% of the Regulation Level
SKIP
VOUTL
Drive
Figure 64. Standby Management
Remark:
properly turn on and off the “COMP_OSC” comparator.
Also the synchronization signal must be low impedance
enough not to be distorted by the Pin 8 source and sink
currents.
• The “storing circuitry” that contains a latch and some
gates. The raising edge of the “COMP_OSC” output sets
the “CLOCK Generation” latch to turn high the “CLK”
signal. If the timing capacitor of Pin 7 is properly
discharged (VPin4 <50 mV leading to “CTOK” high), the
PWM block is ready for a new cycle and “CLK” can
force the signal “VSET” in high state. As a consequence,
the PWM latch sets. In addition, “VSET” resets the
“CLOCK Generation” latch to make it ready for the next
oscillator cycle. The two inverters of Figure 66, simply
generate some delay to ensure that “VSET” keeps high
long enough to set the PWM latch and reset the
“CLOCK Generation” latch (longer delay than that
produced by the two gates, may actually be necessary).
The oscillator / Synchronization block is designed to set the
switching frequency.
However, the coil current can possibly be non zero at the
end of a clock period and the circuit would enter Continuous
Conduction Mode (CCM) if the MOSFET turned on in that
moment. In order to prevent CCM, the “storing circuitry” of
the oscillator / synchronization block, memorizes the
“COMP_OSC” rising edge (thanks to the “CLOCK
Generation” latch) and delays the next MOSFET conduction
time until the coil current has totally vanished (that is until the
signal “DT” is high − “DT” is generated by the current sense
block so that it is high during the dead−time and low
otherwise). In other words, CRM operation is obtained (refer
to Figure 65).
• Skip cycle is not allowed during the PFC startup phase
•
•
to avoid that it interferes with the soft−start. That is why,
skip cycle is enabled only when “pfcOK” is high.
Each working phase of the burst mode starts smoothly as
Pin 3 is grounded at the beginning of it. This soft−start
capability is effective to avoid the audible noise that
could possibly result from such a burst operation.
The circuit leaves the standby mode when the output
voltage goes below 95.5% of its regulation level and
VPin1 is above 330 mV (300 mV + 30 mV hysteresis).
Oscillator / Synchronization Section
The oscillator generates the clock signal to set the PWM
latch and turn the MOSFET on. The oscillator frequency is
set by the capacitor that is applied to Pin 8. Typically,
820 pF force about 60 kHz. The maximum allowable
oscillator frequency is 250 kHz. The clock frequency can
also be driven by an external synchronization signal.
This block contains two main parts (refer to Figure 66):
• The arrangement that consists of charging/discharging
current sources, a switch and a comparator. When used
in oscillator mode, a capacitor is connected between
Pin 8 and ground. A current source (100 mA) charges the
Pin 8 capacitor until its voltage exceeds VoscH. At that
moment, the comparator (“COMP_OSC”) turns high and
activates the discharge current source (200 mA). As a
consequence, Pin 8 actually sinks 100 mA that discharge
the oscillator capacitor to VoscL. At that moment, the
comparator turns low and initiates a new charge phase. If
the circuit is to be externally triggered, the
synchronization signal must cross VoscL and VoscH to
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NCP1605, NCP1605A
delay
Clock
CLK (PWM latch
SET input)
100 mA
Clock
Edge
COMP_OSC
+
-
Osc/Sync
Set
Signal
200 mA
Inductor
Current
Ct_OK
VOSCH/VOSCL
Time
Discontinuous Mode
R
CLOCK
Generation
Latch Q
S
DT
(”DT” is high
during the
dead−time)
Critical Mode
Figure 65. Oscillator Timing Diagram
Figure 66. Oscillator / Synchronization Block
HV
16
HV
15 mA / 0
HVCS_ON
15 V / 7 V
+
VCC
10
9V
+
UVLO
GND
9
+
Cvcc
Auxiliary
Winding
(When high, ”UVLO” indicates that the circuit is not properly fed and it sets the Fault latch to turn off the circuit)
Figure 67. The Current Source brings VCC above 15 V and then Turns Off
Startup Sequence / VCC Management
the NCP1605). One can note that the startup current source
is on during the VCC charging phase and off for the rest of
the time. Hence, it spends no power during the PFC stage
operation and in particular, in light load conditions. That is
why the NCP1605(A) helps meet the most stringent
standby requirements.
At the moment when the PFC stage is plugged to the
mains outlet, the internal current source starts charging the
VCC capacitor. More generally, the startup current source
is enabled whenever VCC drops below VCCSTUP (7 V,
typically). When VCC exceeds the VCCON level (typically
15 V for the NCP1605, 10.5 V for the NCP1605A), the
current source turns off and the circuit starts pulsing.
The energy stored by the VCC capacitor serves to feed the
controller and some auxiliary supply must take over before
VCC drops below VCCOFF (9 V, typically), that is, the level
below which the circuit stops pulsing.
Hence, the circuit starts operating when the VCC voltage
exceeds VCCON and stops pulsing when VCC drops below
VCCOFF. The hysteresis (6 V for the NCP1605, 1.5 V for
the NCP1605A) prevents erratic operation as the VCC
crosses the VCCON threshold.
Figure 67 shows the internal arrangement of this
structure (the VCC turn on threshold of Figure 67 is that of
Remarks:
• Some circuitry (not represented in Figure 67) limits
•
the HV pin current below 1 mA if the VCC voltage is
nearly below 1 V. This protects the circuit when the
VCC pin is accidentally grounded. The full current
capability (around 15 mA) is obtained when VCC
exceeds about 1 V.
The circuit is also kept off when the startup current
source is on to make a clear distinction between the
VCC charge phase and the operating sequence (refer to
“HVCS_ON” signal on block diagram).
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NCP1605, NCP1605A
Brown−Out Detection
Vpin2 +
The brown−out pin receives a portion of the input voltage
(VIN). As VIN is a rectified sinusoid, a capacitor must
integrate the ac line ripple so that a voltage proportional to
the average value of (VIN) is applied to the brown−out pin.
The brown−out block detects too low input voltage
conditions. A hysteresis comparator monitors the Pin 2
voltage. Before operation, the PFC stage is off and the input
bridge acts as a peak detector. Hence, the voltage applied
to Pin 2 is:
Vpin2 + Ǹ2 Vac
i.e., about 64% of the previous value. Therefore, the same
line magnitude leads to a VPin2 voltage that is 36% lower
when the PFC is working than when it is off (refer to
Figure 69). That is why the NCP1605(A) features a 50%
hysteresis (VBOL = 50% VBOH).
When the circuit starts operation, the input voltage
equates the ac line peak.
Hence, the initial threshold of the Brown−Out
comparator, must be the upper one (VBO = VBOH = 1 V
when the NCP1605 leaves the off mode).
Rbo2
.
Rbo1 ) Rbo2
When a brown−out condition is detected, the signal
“BO_NOK” turns off the circuit (refer to block diagram).
After the PFC stage has started operation, the input
voltage becomes a rectified sinusoid and the voltage
applied to Pin 2 is:
Vin
400
Ac line
EMI
Filter
RCS
Rbo1
Cin
Cbo2
BO
1 V / 0.5 V
+
-
Rbo2
2 Ǹ2 Vac
,
p
Rbo1 ) Rbo2
Start of PFC
Operation
Ǹ2 @ Vac @ sin(Rt)
VSIN
BO_NOK
200
Rbo2
Ǹ2 @ Vac
0
Figure 68. Brown−Out Block
Figure 69. Typical Input Voltage of a PFC Stage
Thermal Shutdown (TSD)
the voltage reference used for the regulation and the
overvoltage protection. The circuit also incorporates a
precise current reference (IREF) that allows the Overcurrent
Limitation to feature a ±6% accuracy over the temperature
range.
An internal thermal circuitry disables the circuit gate
drive and then keeps the power switch off when the junction
temperature exceeds 150_C typically. The output stage is
then enabled once the temperature drops below about
100_C (50_C hysteresis).
The temperature shutdown keeps active as long as the
circuit is not reset, that is, as long as VCC keeps higher than
VCCRESET. The reset action forces the TSD threshold to
be the upper one (150°C). This ensures that any cold startup
will be done with the right TSD level.
OFF Mode
As previously mentioned, the circuit turns off in the
following cases:
• When the high voltage, startup current source charges
the VCC capacitor.
• When one of the following major faults is detected:
• Incorrect feeding of the circuit (“UVLO” high when
VCC<VCCOFF, VCCOFF equating 9 V typically).
• Excessive die temperature detected by the thermal
shutdown.
• Brown−Out condition.
• Undervoltage Protection.
• VPin13 higher than 2.5 V (“STDWN” of the block
diagram turns high).
Generally speaking, the circuit turns off when the
conditions are not proper for good operation. In this mode,
the controller stops operating. The major part of the circuit
sleeps and its consumption is minimized (< 500 mA).
Output Drive Section
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. The gate drive is kept in a sinking
mode whenever the Undervoltage Lockout is active or
more generally whenever the circuit is off (i.e., when the
“Fault Latch” of the block diagram is high or when the HV
current source is on). Its high current capability
(−500 mA/+800 mA) allows it to effectively drive high
gate charge power MOSFET.
Reference Section
The circuit features an accurate internal reference
voltage (VREF). VREF is optimized to be ±3% accurate over
the temperature range (the typical value is 2.5 V). VREF is
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NCP1605, NCP1605A
• The Pin 3 capacitor is discharged and kept grounded
More specifically, when the circuit is in OFF state:
• The drive output is kept low
• All the blocks are off except:
1. The UVLO circuitry that keeps monitoring the
VCC voltage and controlling the startup current
source accordingly.
2. The TSD (thermal shutdown)
3. The “STDWN” latch that stores its output state.
4. The Undervoltage Protection (“UVP”).
5. The brown−out circuitry. One must note that the
comparator is reset during the latched−off phase
so that its threshold is the upper one (1 V) when
the circuit enters the active phase (refer to next
“VCC sequences” section).
6. The high voltage, startup current source when the
circuit is in startup phase (that is when VCC is
lower than VCCSTUP).
VCC Conditions
•
•
along the OFF time, to initialize it for the next
operating sequence, where it must be slowly and
gradually charged to offer some soft−start.
The “pfcOK” pin is grounded.
The output of the “VTON processing block” is
grounded
VCC Sequences
The following table summarizes the state of the circuit
in accordance to the VCC level.
“OFF” is Low
“OFF” is High
(no condition forces the circuit off)
(due to some protection like the thermal shutdown)
VCC exceeds VCCON
⇒ the circuit enters the
working phase
The startup current source is disabled
The circuit is fully active
The startup current source is disabled
The circuit is in OFF state
VCC drops below VCCOFF
⇒ the circuit enters the
latched−off phase
The circuit is in OFF state
The brown−out block resets during the
latched−off phase so that its comparator
threshold is forced to be the upper one (1 V)
The circuit is in OFF state
The brown−out block resets during the latched−off
phase so that its comparator threshold is forced to be
the upper one (1 V)
VCC goes below VCCSTUP
⇒ the circuit enters the
startup phase
The high voltage, startup current source turns
on to charge VCC.
The drive output and the “pfcOK” are in low
state (the circuit is off)
All the circuit blocks are reset except:
The thermal shutdown (TSD) and the
brown−out block that keep operating
The “STDWN” latch.
The high voltage, startup current source turns on to
charge VCC.
The drive output and the “pfcOK” are in low state (the
circuit is off)
All the circuit blocks are reset except:
The thermal shutdown (TSD) and the brown−out
block that keep operating
The “STDWN” latch.
VCC goes below VCCRESET
⇒ the circuit resets
The high voltage, startup current source is on.
The whole circuitry is reset including the
“TSD” and the “STDWN” latch. After reset,
the TSD threshold is 150°C and the output of
the “STDWN latch” is low.
The high voltage, startup current source is on.
The whole circuitry is reset including the “TSD” and the
“STDWN” latch. After reset, the TSD threshold is 150°C
and the output of the “STDWN latch” is low.
The figures on the following pages portray the circuit behavior during a startup phase:
• In case of normal conditions (Figure 70).
• As a function of the brown−out pin voltage (Figure 71).
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NCP1605, NCP1605A
Remarks:
The VCONTROL signal does not necessarily reach its
clamp level (3.7 V) depending of the load and of the system
time constants. In particular, if the circuit starts operation
in light load and if the bulk capacitor is not too large, the
output voltage VOUT generally exceeds the regulation level
while VCONTROL keeps below its upper limit.
The output voltage exhibits a 100 or 120 Hz ripple (at
twice the line frequency). This ripple is also present in the
VCONTROL voltage even if it is attenuated due to the
regulation low bandwidth. Like that of VOUT, this ripple is
not represented in Figure 70, for the sake of the clarity.
VCCON
VCC
VCCOFF
VCCSTUP
1V
VOUT
VOUT Regulation Level
VCONTROL MAX = 3.7 V
VCONTROL
These re−activations of “Flag1” result from VOUT
100 or 120 Hz ripple (not represented here for the
sake of clarity)
Flag1
Circuit State
OFF
pfcOK
Drive Output
Figure 70. Startup Phase in Normal Conditions
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NCP1605, NCP1605A
The Circuit is Off ≥ Low Consumption
VCCON
VCCOFF
VCC
VCCSTUP
1V
Vout Regulation Level
VOUT
1V
0.5 V
Brown−Out
Pin Voltage
Drive Output
Circuit State
OFF
pfcOK
Figure 71. Startup and Brown Out Conditions
When the high voltage, startup current source is on, the brown−out is active and its threshold is the upper one (VBO = VBOH = 1 V).
Fault Management Block
When any of the following faults is detected: brown−out
(“BO_NOK”),
Undervoltage (“UVP”), shutdown
(“STDWN”), Die Overtemperature (“TSD”), the circuit
immediately turns off and recovers operation as soon as the
fault disappears.
In case of UVLO (VCC too low to allow operation), the
circuit keeps off until the end of the next VCC charge phase
by the HV startup current source.
The following block diagram details the function.
Internal
Thermal
Shutdown
UVP
TSD
UVLO
(Vcc<VccOFF)
BO_NOK
Stdwn
S
Q
UVLO
Latch
R
HVCS_ON
Figure 72. Fault Management Block
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OFF
NCP1605, NCP1605A
Bulk
BOon
BOoff
Single Hiccup
VCC
VCCon
Internal
BOok
VCCoff
Drive
Figure 73.
The above figure shows how the circuit recovers after a brown−out event.
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NCP1605, NCP1605A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B− P
1
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
The products described herein, may be covered by the following U.S. patents: 5,502,370 6,271,735, 6,362,067, 6,970,365.
There may be other patents pending
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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