Digital Step Attenuator
75Ω DC-2000 MHz
15.5 dB, 0.5 dB Step
5 Bit, Parallel Control Interface, Dual Supply Voltage
Product Features
• Dual supply voltage: VDD=+3V, VSS=-3V
• Immune to latch up
• Excellent accuracy, 0.1 dB Typ
• Parallel control interface
• Fast switching control frequency, 1MHz Typ
• Low Insertion Loss
• High IP3, +52 dBm typ
• Very low DC power consumption
• Excellent return loss, 20 dB Typ
• Small size 4.0 x 4.0 mm
DAT-15575-PN+
DAT-15575-PN
+ RoHS compliant in accordance
with EU Directive (2002/95/EC)
The +Suffix identifies RoHS Compliance. See our web site
for RoHS Compliance methodologies and qualifications.
Typical Applications
• Base Station Infrastructure
• Portable Wireless
• CATV & DBS
• MMDS & Wireless LAN
• Wireless Local Loop
• UNII & Hiper LAN
• Power amplifier distortion canceling loops
General Description
The DAT-15575-PN is a 75Ω RF digital step attenuator that offers an attenuation range up to 15.5 dB in
0.5 dB steps. The control is a 5-bit parallel interface, operating on dual supply voltage: VDD=+3V, VSS=-3V.
The DAT-15575-PN is produced using a unique CMOS process on silicon, offering the performance of
GaAs, with the advantages of conventional CMOS devices.
Simplified Schematic
RF Input
8dB
4dB
2dB
1dB
0.5dB
RF Out
Parallel Control
Control Logic Interface
Latch Enable
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071025
Page 1 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
RF Electrical Specifications, DC-2000 MHz, TAMB=25°C, VDD=+3V, VSS=-3V
Parameter
Freq. Range
(GHz)
Min.
Typ.
Max.
Units
DC-1.2
—
0.03
0.17
dB
1.2-2.0
—
0.05
0.18
dB
DC-1.2
—
0.03
0.19
dB
1.2-2.0
—
0.1
0.2
dB
DC-1.2
—
0.07
0.23
dB
Accuracy @ 0.5 dB Attenuation Setting
Accuracy @ 1 dB Attenuation Setting
Accuracy @ 2 dB Attenuation Setting
Accuracy @ 4 dB Attenuation Setting
Accuracy @ 8 dB Attenuation Setting
1.2-2.0
—
0.15
0.25
dB
DC-1.2
—
0.05
0.25
dB
1.2-2.0
—
0.15
0.35
dB
DC-1.2
—
0.1
0.25
dB
1.2-2.0
—
0.24
0.55
dB
DC-1.2
—
1.2
1.8
dB
1.2-2.0
—
1.6
2.1
dB
Input IP3(note 2) (at Min. and Max. Attenuation)
DC-2.0
—
+52
—
dBm
Input Power @ 0.2dB Compression*
(at Min. and Max. Attenuation)
DC-2.0
—
+24
—
dBm
DC-1.2
—
1.6
2.0
—
1.2-2.0
—
1.7
2.0
—
Insertion Loss(note1) @ all attenuator set to 0dB
VSWR
Notes:
1. I. Loss values are de-embedded from test board Loss (test board’s Insertion Loss: 0.10dB @100MHz, 0.40dB @1200MHz,
0.55dB @2000MHz, 0.75dB @4000MHz)
2. Input IP3 and 1dB compression degrades below 1 MHz
DC Electrical Specifications
Parameter
Min.
Typ.
Max.
Units
VDD, Supply Voltage
2.7
3
3.3
V
VSS, Supply Voltage
-3.3
-3
-2.7
V
IDD (ISS), Supply Current
—
—
100
μA
Control Input Low
—
—
0.3xVDD
V
Control Input High
0.7xVDD
—
—
V
—
—
1
μA
Control Current
Switching Specifications
Parameter
Min.
Typ.
Max.
Units
Switching Speed, 50% Control to 0.5dB
of Attenuation Value
—
1.0
—
μSec
Switching Control Frequency
—
1.0
—
MHz
Absolute Maximum Ratings
Parameter
Ratings
Operating Temperature
-40°C to 85°C
Storage Temperature
-55°C to 100°C
-0.3V Min., 4V Max.
VDD
VSS
-4V Min., 0.3V Max.
Voltage on any input
-0.3V Min., VDD+0.3V Max.
ESD, HBM
500V
ESD, MM
100V
Input Power
+24dBm
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Page 2 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Pin Description
N/C
7
Not connected
8
Power up selection bit
9
Positive Supply Voltage
GND
10
Ground connection
GND
11
Ground connection
VSS
12
Negative supply voltage
13
Ground connection
GND
RF out
14
RF out port (Note 1)
C8
15
Control for attenuation bit, 8 dB
C4
16
Control for attenuation bit, 4 dB
C2
17
Control for attenuation bit, 2 dB
GND
18
Ground Connection
Control for attenuation bit, 1 dB
C1
19
C0.5
20
GND
Paddle
GND
4
LE
5
2x2mm
Paddle
ground
6
VDD
N/C
3
VDD
PUP2
RFin
C4
Positive Supply Voltage
2
16
6
1
15
C8
14
RFout
13
GND
12
VSS
11
GND
10
VDD
N/C
GND
Latch Enable Input (Note 2)
C2
5
17
LE
9
Ground connection
VDD
4
GND
GND
18
Not connected (Note 3)
8
RF in port (Note 1)
3
N/C
2
N/C
PUP2
RF in
C0.5
Not connected (Note 3)
C1
1
19
N/C
Description
7
Pin
Number
20
Function
Pin Configuration (Top View)
Control for attenuation bit, 0.5 dB
Paddle ground (Note 4)
Notes:
1. Both RF ports must be held at 0VDC or DC blocked with an external series capacitor.
2. Latch Enable (LE) has an internal 100KΩ resistor to VDD.
3. Place a shunt 10KΩ resistor to GND.
4. The exposed solder pad on the bottom of the package (See Pin Configuration) must
be grounded for proper device operation.
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page 3 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Typical Performance Curves
INSERTION LOSS (Ref) @ +25°C, +85°C, -45°C
7
ATTENUATION (0.5dB) @ +25°C,+85°C,-45°C
1
-45°C
+25°C
+85°C
0.9
6
5
+85°C
0.8
+25°C
0.7
0.6
4
(dB)
(dB)
-45°C
0.5
3
0.4
2
0.3
0.2
1
0.1
0
0
0
500
1000
1500
2000
2500
0
3000
500
1000
1500
2000
1.4
3
2.8
-45°C
+25°C
1.3
-45°C
+25°C
+85°C
2.6
+85°C
1.2
2.4
1.1
2.2
(dB)
(dB)
3000
ATTENUATION (2dB) @ +25°C,+85°C,-45°C
ATTENUATION (1dB) @ +25°C,+85°C,-45°C
1.5
1
2
0.9
1.8
0.8
1.6
0.7
1.4
0.6
1.2
0.5
1
0
500
1000
1500
2000
2500
3000
0
500
1000
Frequency (MHz)
1500
2000
2500
3000
Frequency (MHz)
ATTENUATION (4dB) @ +25°C,+85°C,-45°C
5
ATTENUATION (8dB) @ +25°C,+85°C,-45°C
8.8
-45°C
+25°C
+85°C
4.8
4.6
-45°C
+25°C
+85°C
8.6
8.4
8.2
(dB)
4.4
(dB)
2500
Frequency (MHz)
Frequency (MHz)
4.2
8
7.8
4
7.6
3.8
7.4
3.6
7.2
3.4
7
3.2
6.8
6.6
3
0
500
1000
1500
2000
2500
0
3000
500
1000
Frequency (MHz)
1500
2000
2500
3000
Frequency (MHz)
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Page 4 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Typical Performance Curves
ATTENUATION (15.5dB) @ +25°C,+85°C,-45°C
18
-45°C
+25°C
+85°C
(dB)
17
16
15
14
13
12
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
RETURN LOSS IN S11 (Ref) @ +25°C,+85°C,-45°C
50
-45°C
+25°C
+85°C
40
RETURN LOSS OUT S22 (Ref) @ +25°C,+85°C,-45°C
50
-45°C
+25°C
+85°C
40
30
(dB)
(dB)
30
20
20
10
10
0
0
0
500
1000
1500
2000
2500
3000
0
500
1000
Frequency (MHz)
RETURN LOSS IN S11 (Major Attenuation Steps) @ +25°C
50
ATT=0dB
ATT=1dB
ATT=4dB
ATT=15.5dB
2000
2500
3000
RETURN LOSS OUT S22 (Major Attenuation Steps) @ +25°C
50
ATT=0.5dB
ATT=2dB
ATT=8dB
ATT=0dB
ATT=1dB
ATT=4dB
ATT=15.5dB
40
30
ATT=0.5dB
ATT=2dB
ATT=8dB
30
(dB)
(dB)
40
1500
Frequency (MHz)
20
20
10
10
0
0
0
500
1000
1500
2000
2500
0
3000
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
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Page 5 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Typical Performance Curves
IP-3 INPUT (Major Attenuation Steps) @ +85°C
70
60
60
50
50
40
(dBm)
(dBm)
IP-3 INPUT (Major Attenuation Steps) @ +25°C
70
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=15.5dB
30
20
10
40
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=15.5dB
30
20
10
0
0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0
200
400
600
800
Frequency (MHz)
1000
1200
1400
1600
1800
2000
1800
2000
1800
2000
Frequency (MHz)
IP-3 INPUT (Major Attenuation Steps) @ -45°C
COMPRESSION @INPUT POWER=+24dBm (+25°C)
0.2
70
60
0
-0.2
40
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=15.5dB
30
20
10
(dB)
(dBm)
50
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=15.5dB
-0.4
-0.6
-0.8
0
0
200
400
600
800
1000
1200
1400
1600
1800
0
2000
200
400
600
800
COMPRESSION @INPUT POWER=+24dBm (+85°C)
0.2
1000
1200
1400
1600
Frequency (MHz)
Frequency (MHz)
COMPRESSION @INPUT POWER=+24dBm (-45°C)
0.2
-0.2
-0.2
(dB)
0
(dB)
0
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=15.5dB
-0.4
-0.6
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=15.5dB
-0.4
-0.6
-0.8
-0.8
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0
200
400
600
800
Frequency (MHz)
1000
1200
1400
1600
Frequency (MHz)
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Page 6 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Outline Drawing (DG983-1)
PCB Land Pattern
Suggested Layout,
Tolerance to be within ±.002
Device Marking
15575
Outline Dimensions (inch
mm )
WT.
GRAMS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
.157
.157
.035
.008
.081
.081
.010
—
.022
.020
.166
.166
.070
.012
.026
.070
4.00
4.00
0.90
0.20
2.06
2.06
0.25
—
0.56
0.50
4.22
4.22
1.78
0.31
0.66
1.78
.04
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page 7 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Suggested Layout for PCB Design (PL-200)
The suggested Layout shows only the footprint area of the DAT, and the components located near this area
(i.e.: R1, R7). For the complete Layout, see photo and schematic diagram on page 11 of 12.
NOTES:
1. TRACE WIDTH IS SHOWN FOR FR4 WITH DIELECTRIC THICKNESS.
.025” ±.002”. COPPER: 1/2 OZ. EACH SIDE.
FOR OTHER MATERIALS TRACE WIDTH MAY NEED TO BE MODIFIED.
2. 0603, 0402 SIZE CHIP FOOT PRINTS SHOWN FOR REFERENCE,
VALUES OF RESISTORS WILL VARY BASED ON APPLICATION.
3. BOTTOM SIDE OF THE PCB IS CONTINUOUS GROUND PLANE.
DENOTES PCB COPPER LAYOUT WITH SMOBC
(SOLDER MASK OVER BARE COPPER)
DENOTES COPPER LAND PATTERN FREE OF SOLDERMASK
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Page 8 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Simplified Schematic
RF Input
8dB
4dB
2dB
1dB
0.5dB
RF Out
Parallel Control
Control Logic Interface
Latch Enable
The DAT-15575-PN parallel interface consists of 5 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation
State
C8
C4
C2
C1
C0.5
Reference
0
0
0
0
0
0.5 (dB)
0
0
0
0
1
1 (dB)
0
0
0
1
0
2 (dB)
0
0
1
0
0
4 (dB)
0
1
0
0
0
8 (dB)
1
0
0
0
0
15.5 (dB)
1
1
1
1
1
Note: Not all 32 possible combinations of C0.5 - C8 are shown
in table
The parallel interface timing requirements are defined by Figure 1 (Parallel Interface Timing Diagram) and
Table 2 (Parallel Interface AC Characteristics), and switching speed.
For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenunation
state control values, then pulse LE HIGH to LOW (per Figure 1) to latch new attenuation state into device.
For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation
state control values will change device state to new attenuation. Direct mode is ideal for manual control of
the device (using hardwire, switches, or jumpers).
Figure 1: Parallel Interface Timing Diagram
Table 2. Parallel Interface AC Characteristics
LE
Parallel Data
C8:C0.5
tPDSUP
tLEPW
Symbol
Parameter
Min.
Max.
Units
tLEPW
LE minimum pulse
width
30
ns
tPDSUP
data set-up time before
clock rising edge of LE
10
ns
tPDHLD
data hold time after
clock falling edge of LE
10
ns
tPDHLD
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page 9 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Pin 1 must always be low to prevent the attenuator from entering an unknown state.
Power-up Control Settings
The DAT-15575-PN always assumes a specifiable attenuation setting on power-up, allowing a known attenuation state to be established before an initial parallel control word is provided.
When the attenuator powers up with LE=0, the control bits are automatically set to one of two possible
values. These two values are selected by the power-up control bit, PUP2, as shown in Table 3: (Power-Up
Truth Table, Parallel Mode).
Table 3. Power-Up Truth Table, Parallel Mode
Attenuation State
PUP2
LE
Reference
0
0
8 (dB)
1
0
Defined by C0.5-C8
(See Table 1-Truth Table)
X (Note 1)
1
Note 1: PUP2 Connection may be 0, 1, GROUND, or not
connect, without effect on attenuation state.
Power-Up with LE=1 provides normal parallel operation with C0.5-C8, and PUP2 is not active.
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Page 10 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
1
2
GND
VDD
13
12
11
5
6
7
8
C2
C4
C8
GND
3
10
4
C1
2
C0.5
1
C16
DC SUPPLY
J2.2
GND
TB-341 Evaluation Board Schematic Diagram
9
8
IC1
14
1
2
3
PARALLEL
CONTROL
J1.1
13
7
4
5
12
11
1
+ C1
9
8
IC2
714
6
10
2
7
3
4
5
6
C2
C4
C6
R2
N/C
R9
19
18
16
15
2
14
17
N/C
13
4
+
GND
GND
C13
C10
1
2
3
4
GND
R11
+
5
Vss
C11
R10
LE CONTROL
J1.2
11
10
9
VDD
N/C
PUP2
8
GND
IC3
6
7
VDD
1
6
VDD
LE
GND
5
R8
C12
Vss
LE
2
RFout
GND
12
GND
2
C9
R6
C8
RFout
DAT
3
1
R5
C4
C2
1
RFin
R7
C8
R4
C1
20
RFin
C7
R3
C0.5
R1
GND
C3
C5
DC SUPPLY
J2.1
Bill of Materials
R1 - R8
Resistor 0603 10 KOhm +/- 1%
R10, R11
Resistor 0603 470 Ohm +/- 1%
R9
Resistor 0402 10 KOhm +/- 1%
C2 - C10 & C13 NPO Capacitor 0603 100pF +/- 5%
C1, C11 & C12
Tantalum Capacitor 100nF +/- 10%
IC1, IC2
Hex inverting Schmitt trigger MM74HC14
IC3
Dual non-inverting Schmitt trigger SN74LVC2G17
TB-341
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page 11 of 12
DAT-15575-PN+
DAT-15575-PN
Digital Step Attenuator
Tape and Reel Packaging Information
Table T&R
TR
No.
No. of Devices
Designation
Letter
Reel Size
3000
T
13 inch
T-005
multiples of 10,
less than full
reel of 3K
PR
13 inch
multiples of 10,
on tape only
E
not
applicable
Tape
Width
Pitch
12 mm
8 mm
Unit
Orientation
Tape
Cavity
Direction of Feed
Ordering Information
Model No.
Description
DAT-15575-PN (+)
Parallel Interface,
Dual Voltage (Negative
and Positive)
TB-341
Test Board Only
Packaging
Designation Letter
(See Table T&R)
Quantity
Min.
No. of Units
Price
$
Ea.
E
10
$3.55
Not Applicable
1
$79.95
How to Order
Example: 3000 pieces of DAT-15575-PN+
3K
DAT-15575-PN+
Quantity
T&R=T
Model No.
T&R designation letter (see Table T&R)
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Page 12 of 12