14-Bit, 1 MSPS, Differential, Programmable Input PulSAR® ADC AD7952 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND VCC VEE DVDD AGND AVDD SERIAL CONFIGURATION 14 PORT PDBUF SWITCHED CAP DAC IN– OGND SERIAL DATA PORT REF IN+ OVDD AD7952 REF AMP PDREF DGND BYTESWAP PARALLEL INTERFACE CLOCK CNVST OB/2C BUSY PD CONTROL LOGIC AND CALIBRATION CIRCUITRY RESET RD CS WARP IMPULSE BIPOLAR TEN Figure 1. Table 1. 48-Lead PulSAR Selection 100 to 250 (kSPS) 500 to 570 (kSPS) 570 to 1000 (kSPS) Input Type Res (Bits) Bipolar 14 AD7951 Differential Bipolar 14 AD7952 Process controls Medical instruments High speed data acquisition Digital signal processing Instrumentation Spectrum analysis ATE Unipolar 16 Bipolar 16 AD7610 AD7663 AD7665 AD7612 AD7671 GENERAL DESCRIPTION Differential Unipolar 16 AD7675 AD7676 AD7677 APPLICATIONS The AD7952 is a 14-bit, charge redistribution, successive approximation register (SAR) architecture analog-to-digital converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage process. The device is configured through hardware or via a dedicated write-only serial configuration port for input range and operating mode. The AD7952 contains a high speed 14-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the fully differential analog inputs on IN+ and IN−. The AD7952 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power is scaled with throughput. Operation is specified from −40°C to +85°C. D[13:0] SER/PAR 06589-001 Multiple pins/software-programmable input ranges +5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p), ±10 V (40 V p-p) Pins or serial SPI®-compatible input ranges/mode selection Throughput 1 MSPS (warp mode) 800 kSPS (normal mode) 670 kSPS (impulse mode) 14-bit resolution with no missing codes INL: ±0.3 LSB typical, ±1 LSB maximum (±61 ppm of FSR) SNR: 85 dB @ 2 kHz iCMOS® process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output No pipeline delay (SAR architecture) Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation 235 mW @ 1 MSPS 10 mW @ 1 kSPS 48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm) AD7651 >1000 kSPS AD7653 AD7660 AD7650 AD7661 AD7652 AD7667 AD7664 AD7666 AD7621 AD7622 AD7623 Simultaneous/ Multichannel Unipolar 16 AD7654 AD7655 Differential Unipolar 18 AD7678 Differential Bipolar 18 AD7631 AD7679 AD7674 AD7641 AD7643 AD7634 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD7952 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 21 Applications....................................................................................... 1 Voltage Reference Input/Output .............................................. 22 General Description ......................................................................... 1 Power Supplies............................................................................ 22 Functional Block Diagram .............................................................. 1 Conversion Control ................................................................... 23 Revision History ............................................................................... 2 Interfaces.......................................................................................... 24 Specifications..................................................................................... 3 Digital Interface.......................................................................... 24 Timing Specifications .................................................................. 5 Parallel Interface......................................................................... 24 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 25 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 25 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 27 Typical Performance Characteristics ........................................... 12 Hardware Configuration ........................................................... 29 Terminology .................................................................................... 16 Software Configuration ............................................................. 29 Theory of Operation ...................................................................... 17 Microprocessor Interfacing....................................................... 30 Overview...................................................................................... 17 Application Information................................................................ 31 Converter Operation.................................................................. 17 Layout Guidelines....................................................................... 31 Modes of Operation ................................................................... 18 Evaluating Performance ............................................................ 31 Transfer Functions...................................................................... 18 Outline Dimensions ....................................................................... 32 Typical Connection Diagram ................................................... 18 Ordering Guide .......................................................................... 32 Analog Inputs.............................................................................. 20 REVISION HISTORY 2/07—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7952 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUTS Differential Voltage Range, VIN 0 V to 5 V 0 V to 10 V ±5 V ±10 V Operating Voltage Range 0 V to 5 V 0 V to 10 V ±5 V ±10 V Common-Mode Voltage Range 5V 10 V Bipolar Ranges Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error 2 No Missing Codes2 Differential Linearity Error2 Transition Noise Zero Error (Unipolar or Bipolar) Zero-Error Temperature Drift Full-Scale Error (Unipolar or Bipolar) Full-Scale Error Temperature Drift Power Supply Sensitivity AC ACCURACY Dynamic Range Signal-to-Noise Ratio, SNR Signal-to-(Noise + Distortion), SINAD Total Harmonic Distortion Spurious-Free Dynamic Range −3 dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response Conditions/Comments (VIN+) − (VIN−) VIN = 10 V p-p VIN = 20 V p-p VIN = 20 V p-p VIN = 40 V p-p VIN+, VIN− to AGND Min 14 Typ Max Unit Bits −VREF −2 VREF −2 VREF −4 VREF +VREF +2 VREF +2 VREF +4 VREF V V V V −0.1 −0.1 −5.1 −10.1 +5.1 +10.1 +5.1 +10.1 V V V V VREF/2 + 0.1 VREF + 0.2 +0.1 V V V dB μA 1 1 1 1.25 800 1.49 670 μs MSPS ms μs kSPS μs kSPS +1 LSB 3 Bits LSB LSB LSB ppm/°C LSB ppm/°C LSB VIN+, VIN− VREF/2 − 0.1 VREF − 0.2 −0.1 fIN = 100 kHz VIN = ±5 V, ±10 V @ 670 kSPS See Analog Inputs section In warp mode In warp mode In warp mode In normal mode In normal mode In impulse mode In impulse mode VREF/2 VREF 0 75 220 1 1 0 0 −1 14 −1 ±0.3 +1 0.55 −15 +15 ±1 −20 +20 ±1 ±0.8 AVDD = 5 V ± 5% fIN = 2 kHz, −60 dB fIN = 2 kHz fIN = 20 kHz fIN = 2 kHz fIN = 2 kHz fIN = 2 kHz VIN = 0 V to 5 V 84.5 84.5 83 Full-scale step 85.5 85.5 85.5 85.4 −105 102 45 2 5 500 Rev. 0 | Page 3 of 32 dB 4 dB dB dB dB dB MHz ns ps rms ns AD7952 Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time REFERENCE BUFFER REFBUFIN Input Voltage Range EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay 5 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD VCC VEE Operating Current 7 , 8 AVDD With Internal Reference With Internal Reference Disabled DVDD OVDD VCC VEE Power Dissipation With Internal Reference With Internal Reference Disabled In Power-Down Mode 9 TEMPERATURE RANGE 10 Specified Performance Conditions/Comments PDREF = PDBUF = low REF @ 25°C –40°C to +85°C AVDD = 5 V ± 5% 1000 hours CREF = 22 μF PDREF = high PDREF = PDBUF = high REF 1 MSPS throughput Min Typ Max Unit 4.965 5.000 ±3 ±15 50 10 5.035 V ppm/°C ppm/V ppm ms 2.4 2.5 2.6 V 4.75 5 200 AVDD + 0.1 V μA @ 25°C 311 1 4.33 −0.3 2.1 −1 −1 mV mV/°C kΩ +0.6 OVDD + 0.3 +1 +1 V V μA μA 0.4 V V 5.25 5.25 5.25 15.75 0 V V V V V Parallel or serial 14-bit ISINK = 500 μA ISOURCE = −500 μA OVDD − 0.6 4.75 6 4.75 2.7 7 −15.75 5 5 15 −15 @ 1 MSPS throughput 20 18.5 7 0.5 4 3 2 VCC = 15 V, with internal reference buffer VCC = 15 V VEE = −15 V @ 1 MSPS throughput PDREF = PDBUF = low PDREF = PDBUF = high PD = high TMIN to TMAX 235 215 10 −40 1 mA mA mA mA mA mA mA 260 240 mW mW μW +85 °C With VIN = unipolar 5 V or unipolar 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or VREF − 0.1 V, whichever is larger. 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. 2 3 Rev. 0 | Page 4 of 32 AD7952 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter CONVERSION AND RESET (See Figure 34 and Figure 35) Convert Pulse Width Time Between Conversions Warp Mode/Normal Mode/Impulse Mode 1 CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) Warp Mode/Normal Mode/Impulse Mode Aperture Delay End of Conversion to BUSY Low Delay Conversion Time Warp Mode/Normal Mode/Impulse Mode Acquisition Time Warp Mode/Normal Mode/Impulse Mode RESET Pulse Width PARALLEL INTERFACE MODES (See Figure 36 and Figure 38) CNVST Low to DATA Valid Delay Warp Mode/Normal Mode/Impulse Mode DATA Valid to BUSY Low Delay Bus Access Request to DATA Valid Bus Relinquish Time MASTER SERIAL INTERFACE MODES 2 (See Figure 40 and Figure 41) CS Low to SYNC Valid Delay CS Low to Internal SDCLK Valid Delay2 CS Low to SDOUT Delay CNVST Low to SYNC Delay, Read During Convert Warp Mode/Normal Mode/Impulse Mode SYNC Asserted to SDCLK First Edge Delay Internal SDCLK Period 3 Internal SDCLK High3 Internal SDCLK Low3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SDCLK Last Edge to SYNC Delay3 CS High to SYNC High-Z CS High to Internal SDCLK High-Z CS High to SDOUT High-Z BUSY High in Master Serial Read After Convert3 CNVST Low to SYNC Delay, Read After Convert Warp Mode/Normal Mode/Impulse Mode SYNC Deasserted to BUSY Low Delay Symbol Min t1 t2 10 Typ Max ns 1/1.25/1.49 t3 t4 t5 t6 t7 Unit 35 μs ns 850/1100/1350 ns ns ns 850/1100/1350 ns 2 10 t8 t9 200 10 ns ns t10 850/1100/1350 t11 t12 t13 40 15 ns ns ns ns 10 10 10 ns ns ns 20 2 t14 t15 t16 t17 50/290/530 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 Rev. 0 | Page 5 of 32 3 30 15 10 4 5 5 45 10 10 10 ns ns ns ns ns ns ns ns ns ns ns See Table 4 710/950/1190 25 ns ns AD7952 Parameter SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2 (See Figure 43, Figure 44, and Figure 46) External SDCLK, SCCLK Setup Time External SDCLK Active Edge to SDOUT Delay SDIN/SCIN Setup Time SDIN/SCIN Hold Time External SDCLK/SCCLK Period External SDCLK/SCCLK High External SDCLK/SCCLK Low Symbol Min t31 t32 t33 t34 t35 t36 t37 5 2 5 5 25 10 10 Typ Max Unit ns ns ns ns ns ns ns 18 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. 2 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SDCLK First Edge Delay Minimum Internal SDCLK Period Minimum Internal SDCLK Period Maximum Internal SDCLK High Minimum Internal SDCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SDCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum Warp Mode Normal Mode Impulse Mode 1.6mA 0 0 3 30 45 12 10 4 5 5 0 1 20 60 90 30 25 20 8 7 1 0 20 120 180 60 55 20 35 35 1 1 20 240 360 120 115 20 90 90 Unit ns ns ns ns ns ns ns ns 1.60 1.85 2.10 2.35 2.60 2.85 3.75 4.00 4.25 6.75 7.00 7.25 μs μs μs IOL 1.4V 2V CL 60pF 0.8V tDELAY IOH NOTES 1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. tDELAY 2V 0.8V 2V 0.8V Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF Figure 3. Voltage Reference Levels for Timing Rev. 0 | Page 6 of 32 06589-003 500µA 06589-002 TO OUTPUT PIN Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 AD7952 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+1, IN−1 to AGND REF, REFBUFIN, TEMP, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD VCC to AGND, DGND VEE to GND Digital Inputs PDREF, PDBUF Internal Power Dissipation2 Internal Power Dissipation3 Junction Temperature Storage Temperature Range Rating VEE − 0.3 V to VCC + 0.3 V AVDD + 0.3 V to AGND − 0.3 V ±0.3 V −0.3 V to +7 V ±7 V ±7 V –0.3 V to +16.5 V +0.3 V to −16.5 V −0.3 V to OVDD + 0.3 V ±20 mA 700 mW 2.5 W 125°C −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 See the Analog Inputs section. Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 3 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. 2 Rev. 0 | Page 7 of 32 AD7952 48 47 46 45 44 43 42 REF IN– REFGND VCC VEE IN+ AGND AVDD TEMP REFBUFIN PDREF PDBUF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 41 40 39 38 37 AGND 1 36 BIPOLAR 35 CNVST 3 34 PD 4 33 RESET OB/2C 5 32 CS 31 RD 30 TEN 8 29 BUSY NC 9 28 D13/SCCS NC 10 27 D12/SCCLK D0/DIVSCLK[0] 11 26 D11/SCIN D1/DIVSCLK[1] 12 25 D10/HW/SW AVDD 2 AGND BYTESWAP WARP PIN 1 AD7952 6 TOP VIEW (Not to Scale) IMPULSE 7 SER/PAR D9/RDERROR 06589-004 NC = NO CONNECT D8/SYNC D7/SDCLK DGND D6/SDOUT DVDD OVDD OGND D5/RDC/SDIN D4/INVSCLK D2/EXT/INT D3/INVSYNC 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 3, 42 Mnemonic AGND Type 1 P 2, 44 4 AVDD BYTESWAP P DI 5 OB/2C DI 2 6 WARP DI2 7 IMPULSE DI2 8 SER/PAR DI 9, 10 11, 12 NC D[0:1] or DIVSCLK[0:1] DO DI/O Description Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Parallel Mode Selection (8 Bit/14 Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following. Conversion Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation section for a more detailed description. Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port, and the remaining data bits are high impedance outputs. No Connect. Do not connect. In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus. Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 32 AD7952 Mnemonic D2 or EXT/INT Type 1 DI/O 14 D3 or INVSYNC DI/O 15 D4 or INVSCLK DI/O 16 D5 or RDC or DI/O Pin No. 13 Description In parallel mode, this output is used as Bit 2 of the parallel port data output bus. Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the AD7952 output data. When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output. When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. SDIN 17 OGND P 18 OVDD P 19 DVDD P 20 DGND P 21 D6 or SDOUT DO 22 D7 or SDCLK DI/O 23 D8 or SYNC DO In parallel mode, this output is used as Bit 3 of the parallel port data output bus. Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. In parallel mode, this output is used as Bit 4 of the parallel port data output bus. In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. In parallel mode, this output is used as Bit 5 of the parallel port data output bus. Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low), RDC is used to select the read mode. Refer to the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. Serial Data In. In serial slave mode (SER/PAR = high, EXT/INT = high), SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. In parallel mode, this output is used as Bit 6 of the parallel port data output bus. Serial Data Output. In all serial modes, this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7952 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK. When EXT/INT = high (slave mode): When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. In parallel mode, this output is used as Bit 7 of the parallel port data output bus. Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. In parallel mode, this output is used as Bit 8 of the parallel port data output bus. Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. Rev. 0 | Page 9 of 32 AD7952 Pin No. 24 Mnemonic D9 or RDERROR Type 1 DO 25 D10 or HW/SW DI/O 26 D11 or SCIN DI/O 27 D12 or SCCLK DI/O 28 D13 or SCCS DI/O 29 BUSY DO 30 TEN DI2 31 32 RD CS DI DI 33 RESET DI 34 PD DI2 35 CNVST DI 36 37 BIPOLAR REF DI2 AI/O 38 REFGND AI Description In parallel mode, this output is used as Bit 9 of the parallel port data output bus. Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is completed, the current data is lost and RDERROR is pulsed high. In parallel mode, this output is used as Bit 10 of the parallel port data output bus. Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7952 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7952 is configured through software using the serial configuration register. When HW/SW = high, the AD7952 is configured through dedicated hardware input pins. In parallel mode, this output is used as Bit 11 of the parallel port data output bus. Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low), this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. In parallel mode, this output is used as Bit 12 of the parallel port data output bus. Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low), this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. In parallel mode, this output is used as Bit 13 of the parallel port data output bus. Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low), this input enables the serial configuration port. See the Software Configuration section. Busy Output. Transitions high when a conversion is started and remains high until the conversion is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low), the busy time changes according to Table 4. Input Range Select. Used in conjunction with BIPOLAR per the following. Input Range (V) BIPOLAR TEN 0 to 5 Low Low 0 to 10 Low High ±5 High Low ±10 High High Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial configurable port). Reset Input. When high, reset the AD7952. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power-down. Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Input Range Select. See description for Pin 30. Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF capacitor is required with or without the internal reference and buffer. See the Reference Decoupling section. Reference Input Analog Ground. Connected to analog ground plane. Rev. 0 | Page 10 of 32 AD7952 Pin No. 39 Mnemonic IN− Type 1 AI 40 41 43 VCC VEE IN+ P P AI 45 TEMP AO 46 REFBUFIN AI 47 PDREF DI 48 PDBUF DI 1 2 Description Analog Input. Referenced to IN+. In the 0 V to 5 V input range, IN− is between 0 V and VREF V centered about VREF/2. In the 0 V to 10 V range, IN− is between 0 V and 2 VREF V centered about VREF. In the ±5 V and ±10 V ranges, IN− is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range) and centered about 0 V. In all ranges, IN− must be driven 180° out of phase with IN+. High Voltage Positive Supply. Normally 7 V to 15 V. High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). Analog Input. Referenced to IN−. In the 0 V to 5 V input range, IN+ is between 0 V and VREF V centered about VREF/2. In the 0 V to 10 V range, IN+ is between 0 V and 2 VREF V centered about VREF. In the ±5 V and ±10 V ranges, IN+ is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range) and centered about 0 V. In all ranges, IN+ must be driven 180° out of phase with IN−. Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low), this pin outputs a voltage proportional to the temperature of the AD7952. See the Temperature Sensor section. Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Single-to-Differential Driver section. Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered down. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register, and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. Rev. 0 | Page 11 of 32 AD7952 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C. 1.0 1.0 POSITIVE INL = +0.15 NEGATIVE INL = –0.15 0.5 DNL (LSB) 0 0 –0.5 0 4096 8192 12288 16384 CODE –1.0 06589-005 –1.0 –0.5 0 12288 16384 Figure 8. Differential Nonlinearity vs. Code 200 NEGATIVE INL POSITIVE INL NEGATIVE DNL POSITIVE DNL 180 200 160 NUMBER OF UNITS NUMBER OF UNITS 8192 CODE Figure 5. Integral Nonlinearity vs. Code 250 4096 06589-008 INL (LSB) 0.5 POSITIVE DNL = +0.27 NEGATIVE DNL = –0.27 150 100 50 140 120 100 80 60 40 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 INL DISTRIBUTION (LSB) 1.0 0 –1.0 06589-006 0 –1.0 –0.8 –0.6 –0.4 –0.2 Figure 6. Integral Nonlinearity Distribution (239 Devices) 0.2 0.4 0.6 0.8 1.0 Figure 9. Differential Nonlinearity Distribution (239 Devices) 300000 140000 132052 261120 129068 120000 250000 100000 COUNTS 200000 150000 80000 60000 100000 40000 50000 0 1FFF 0 2000 2001 0 2002 0 2003 CODE IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input at the Code Center 0 0 0 8192 8193 8194 8195 0 0 8196 8197 CODE IN HEX Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Transition Rev. 0 | Page 12 of 32 06589-010 0 20000 06589-007 COUNTS 0 DNL DISTRIBUTION (LSB) 06589-009 20 AD7952 SNR, SINAD REFERRED TO FULL SCALE (dB) –40 –60 –80 –100 –120 –140 0 100 200 300 400 500 FREQUENCY (kHz) 85.5 85.0 –60 14.5 –80 THD, HARMONICS (dB) 13.9 82 ENOB (Bits) 14.1 –10 0 13.7 80 100 –100 06589-012 FREQUENCY (kHz) THIRD HARMONIC –110 80 SECOND HARMONIC –130 70 1 60 100 10 FREQUENCY (kHz) Figure 12. SNR, SINAD, and ENOB vs. Frequency 86.0 90 THD –120 13.5 100 10 110 SFDR –90 Figure 15. THD, Harmonics, and SFDR vs. Frequency 86.0 0V TO 5V 0V TO 10V ±5V ±10V 85.5 0V TO 5V 0V TO 10V ±5V ±10V SINAD (dB) 85.5 85.0 84.5 85.0 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 13. SNR vs. Temperature 84.0 –55 –35 –15 5 25 45 65 85 TEMPERATURE (°C) Figure 16. SINAD vs. Temperature Rev. 0 | Page 13 of 32 105 125 06589-016 84.5 06589-013 SNR, SINAD (dB) SINAD ENOB SNR (dB) –20 120 SNR 84.0 –55 –30 –70 14.3 86 1 –40 Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) 88 78 –50 INPUT LEVEL (dB) Figure 11. FFT 20 kHz 84 SNR SINAD 06589-011 –160 86.0 06589-014 SNR = 85.4dB THD = –107dB SFDR = 116dB SINAD = 85.4dB SFDR (dB) –20 AMPLITUDE (dB OF FULL SCALE) 86.5 fS = 1000kSPS fIN = 19.94kHz 06589-015 0 AD7952 –96 124 0V TO 5V 0V TO 10V ±5V ±10V –100 0V TO 5V 0V TO 10V ±5V ±10V 122 120 118 SFDR (dB) THD (dB) –104 –108 116 114 112 –112 110 –116 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 106 –55 06589-017 –120 –55 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 17. THD vs. Temperature Figure 20. SFDR vs. Temperature (Excludes Harmonics) 1.5 5.008 NEGATIVE FULL-SCALE ERROR 1.0 0.5 5.006 5.004 VREF (V) POSITIVE FULL-SCALE ERROR 0 –0.5 5.002 5.000 ZERO ERROR 4.998 –1.5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4.996 –55 Figure 18. Zero Error, Positive and Negative Full-Scale Error vs. Temperature 60 –35 –15 5 25 45 65 85 125 105 TEMPERATURE (°C) 06589-021 –1.0 06589-018 ZERO ERROR, FULL-SCALE ERROR (LSB) –35 06589-020 108 Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) 100000 AVDD, WARP/NORMAL 10000 DVDD, ALL MODES OPERATING CURRENTS (µA) 40 30 20 10 100 10 AVDD, IMPULSE VCC +15V VEE –15V ALL MODES 1 0.1 OVDD, ALL MODES 0.01 0 1 2 3 4 5 6 REFERENCE DRIFT (ppm/°C) 7 8 06589-019 0 1000 Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Rev. 0 | Page 14 of 32 0.001 10 PDREF = PDBUF = HIGH 100 1000 10000 100000 SAMPLING RATE (SPS) Figure 22. Operating Currents vs. Sample Rate 1000000 06589-022 NUMBER OF UNITS 50 AD7952 50 PD = PDBUF = PDREF = HIGH VEE = –15V VCC = +15V 600 DVDD OVDD AVDD 500 OVDD = 2.7V @ 85°C 45 OVDD = 2.7V @ 25°C 40 t12 DELAY (ns) 35 400 300 30 25 OVDD = 5V @ 85°C 20 OVDD = 5V @ 25°C 15 200 10 100 0 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) 0 50 100 150 CL (pF) Figure 24. Typical Delay vs. Load Capacitance CL Figure 23. Power-Down Operating Currents vs. Temperature Rev. 0 | Page 15 of 32 200 06589-024 0 –55 5 06589-023 POWER–DOWN OPERATING CURRENTS (nA) 700 AD7952 TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. LSB (V ) = VINp-p Signal-to-(Noise + Distortion) Ratio (SINAD) 2N Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs a ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Bipolar Zero Error The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Unipolar Offset Error The first transition should occur at a level ½ LSB above analog ground. The unipolar offset error is the deviation of the actual transition from that point. Full-Scale Error The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full scale. The fullscale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level and includes the effect of the offset error. Closely related is the gain error (also in LSB or % of full-scale range), which does not include the effects of the offset error. The time required for the AD7952 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of the output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as TCVREF (ppm/°C) = VREF ( Max ) – VREF ( Min) VREF (25°C) × (TMAX – TMIN ) × 106 where: Dynamic Range VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX. Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX. VREF (25°C) = VREF at 25°C. Signal-to-Noise Ratio (SNR) TMIN = –40°C. TMAX = +85°C. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. 0 | Page 16 of 32 AD7952 THEORY OF OPERATION IN+ AGND LSB MSB 8192C 4096C 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP REFGND 4096C 4C 2C MSB C OUTPUT CODE C SW– LSB CNVST AGND IN– 06589-025 8192C CONTROL LOGIC Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7952 is a very fast, low power, precise, 14-bit ADC using successive approximation, capacitive digital-to-analog (CDAC) converter architecture. The AD7952 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. The AD7952 can be configured at any time for one of four input ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write-only, SPI-compatible interface via a configuration register in serial software mode. The AD7952 uses Analog Devices’ patented iCMOS high voltage process to accommodate 0 V to +5 V, 0 V to +10 V, ±5 V, and ±10 V input ranges without the use of conventional thin films. Only one acquisition cycle, t8, is required for the inputs to latch to the correct configuration. Resetting or power cycling is not required for reconfiguring the ADC. The AD7952 features different modes to optimize performance according to the applications. It is capable of converting 1,000,000 samples per second (1 MSPS) in warp mode, 800 kSPS in normal mode, and 670 kSPS in impulse mode. The AD7952 provides the user with an on-chip, track-and-hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple, multiplexed channel applications. For unipolar input ranges, the AD7952 typically requires three supplies: VCC, AVDD (which can supply DVDD), and OVDD (which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic). For bipolar input ranges, the AD7952 requires the use of the additional VEE supply. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is completed and the CNVST input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 through VREF/16,384). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings the BUSY output low. The device is housed in Pb-free, 48-lead LQFP or tiny, 48-lead LFCSP (7 mm × 7 mm) that combines space savings with flexibility. In addition, the AD7952 can be configured as either a parallel or a serial SPI-compatible interface. Rev. 0 | Page 17 of 32 AD7952 MODES OF OPERATION TRANSFER FUNCTIONS The AD7952 features three modes of operation: warp, normal, and impulse. Each of these modes is more suitable to specific applications. The mode is configured with the input pins, WARP and IMPULSE, or via the configuration register. See Table 6 for the pin details and the Hardware Configuration section and Software Configuration section for programming the mode selection with either pins or configuration register. Note that when using the configuration register, the WARP and IMPULSE inputs are don’t cares and should be tied to either high or low. Using the OB/2C digital input or via the configuration register, the AD7952 offers two output codings: straight binary and twos complement. See Figure 26 and Table 7 for the ideal transfer characteristic and digital output codes for the different analog input ranges, VIN. Note that when using the configuration register, the OB/2C input is a don’t care and should be tied to either high or low. Setting WARP = high and IMPULSE = low allows the fastest conversion rate up to 1 MSPS. However, in this mode, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (after power-up), the first conversion result should be ignored because in warp mode, the ADC performs a background calibration during the SAR conversion process. This calibration can drift if the time between conversions exceeds 1 ms, thus causing the first conversion to appear offset. This mode makes the AD7952 ideal for applications where both high accuracy and fast sample rate are required. 111...111 111...110 111...101 000...010 000...001 000...000 –FSR –FSR + 1 LSB +FSR – 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT 06589-026 ADC CODE (Straight Binary) Warp Mode Figure 26. ADC Ideal Transfer Function Normal Mode TYPICAL CONNECTION DIAGRAM Setting WARP = IMPULSE = low or WARP = IMPULSE = high allows the fastest mode (800 kSPS) without any limitation on time between conversions. This mode makes the AD7952 ideal for asynchronous applications, such as data acquisition systems, where both high accuracy and fast sample rate are required. Figure 27 shows a typical connection diagram for the AD7952 using the internal reference, serial data, and serial configuration interfaces. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. Impulse Mode Setting WARP = low and IMPULSE = high uses the lowest power dissipation mode and allows power saving between conversions. The maximum throughput in this mode is 670 kSPS, and in this mode, the ADC powers down circuits after conversion, making the AD7952 ideal for battery-powered applications. Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB FSR − 2 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 2 VIN = 0 V to 5 V (10 V p-p) 4.999695 V 4.999390 V 2.500610 V 2.5 V 2.499390 V 610.4 μV 0V VREF = 5 V VIN = 0 V to 10 V VIN = ±5 V (20 V p-p) (20 V p-p) 9.999389 V +4.999389 V 9.998779 V +4.998779 V 5.000610 V +1.228 mV 5.000000 V 0V 4.999389 V −1.228 mV 1.228 mV −4.999389 V 0V −5 V This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND). Rev. 0 | Page 18 of 32 Digital Output Code VIN = ±10 V (40 V p-p) +9.998779 V +9.997558 V +2.442 mV 0V −2.442 mV −9.998779 V −10 V Straight Binary 0x3FFF 1 0x3FFE 0x2001 0x2000 0x1FFF 0x0001 0x0000 2 Twos Complement 0x1FFF1 0x1FFE 0x0001 0x0000 0x3FFF 0x2001 0x20002 AD7952 DIGITAL SUPPLY (5V) NOTE 5 DIGITAL INTERFACE SUPPLY (2.5V, 3.3V, OR 5V) 10Ω ANALOG SUPPLY (5V) 10µF 100nF 10µF AVDD +7V TO +15.75V SUPPLY 10µF 100nF 10µF 100nF AGND 100nF 10µF 100nF DGND DVDD OVDD VCC OGND MicroConverter ®/ MICROPROCESSOR/ DSP BUSY SDCLK –7V TO –15.75V SUPPLY SERIAL PORT 1 SDOUT SCCLK VEE SERIAL PORT 2 SCIN NOTE 6 REF NOTE 4 CREF 22µF 100nF NOTE 3 SCCS REFBUFIN REFGND 33Ω NOTE 7 CNVST AD7952 D OB/2C NOTE 2 ANALOG INPUT+ U1 15Ω SER/PAR IN+ OVDD HW/SW BIPOLAR CC 2.7nF TEN CLOCK WARP IN– NOTE 2 ANALOG INPUT– U1 CC NOTE 1 15Ω IMPULSE NOTE 3 PDREF PDBUF PD RD CS RESET 2.7nF AGND DGND NOTES 1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION. 4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION. 5. OPTIONAL, SEE POWER SUPPLIES SECTION. 6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VIN(MIN) – 2V] FOR BIPOLAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. 8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOGETHER DIRECTLY UNDER THE ADC. SEE LAYOUT GUIDELINES SECTION. Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. 0 | Page 19 of 32 06589-027 NOTE 8 AD7952 Input Range Selection In parallel mode and serial hardware mode, the input range is selected by using the BIPOLAR (bipolar) and TEN (10 V range) inputs. See Table 6 for pin details and the Hardware Configuration section and Software Configuration section for programming the mode selection with either pins or the configuration register. Note that when using the configuration register, the BIPOLAR and TEN inputs are don’t cares and should be tied high or low. For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. 100 90 80 70 CMRR (dB) ANALOG INPUTS Input Structure 60 50 40 30 Figure 28 shows an equivalent circuit for the input structure of the AD7952. 20 1 10 100 1000 FREQUENCY (kHz) D3 D2 D4 RIN VEE AGND CIN 10000 Figure 29. Analog Input CMRR vs. Frequency 06589-028 D1 IN+ OR IN– CPIN 0 AVDD VCC 06589-029 10 0V TO 5V RANGE ONLY Figure 28. Simplified Analog Input The four diodes, D1 to D4, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes the diodes to become forward-biased and to start conducting current. These diodes can handle a forwardbiased current of 120 mA maximum. For instance, these conditions could eventually occur when the input buffer’s U1 supplies are different from AVDD, VCC, and VEE. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part although most op amps’ short-circuit current is <100 mA. Note that D3 and D4 are only used in the 0 V to 5 V range to allow for additional protection in applications that are switching from the higher voltage ranges. This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential input, small signals common to both inputs are rejected as shown in Figure 29, which represents the typical CMRR over frequency. During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN−, can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 70 Ω and is a lumped component comprised of serial resistors and the on resistance of the switches. CIN is primarily the ADC sampling capacitor and depending on the input range selected is typically 48 pF in the 0 V to +5 V range, typically 24 pF in the 0 V to +10 V and ±5 V ranges, and typically 12 pF in the ±10 V range. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. Because the input impedance of the AD7952 is very high, it can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7952 analog input circuit, an external, 1-pole RC filter between the amplifier’s outputs and the ADC analog inputs can be used, as shown in Figure 27. However, large source impedances significantly affect the ac performance, especially THD. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. 0 | Page 20 of 32 AD7952 applications where high frequency performance (above 100 kHz) is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The AD8610 is an option when low bias current is needed in low frequency applications. DRIVER AMPLIFIER CHOICE Although the AD7952 is easy to drive, the driver amplifier must meet the following requirements: • For multichannel, multiplexed applications, the driver amplifier and the AD7952 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 14-bit level (0.006%). For the amplifier, settling at 0.1% to 0.01% is more commonly specified. This differs significantly from the settling time at a 14-bit level and should be verified prior to driver selection. The AD8021 op amp combines ultralow noise and high gain bandwidth and meets this settling time requirement even when used with gains of up to 13. • The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7952. The noise coming from the driver is filtered by the external 1-pole, low-pass filter, as shown in Figure 27. The SNR degradation due to the amplifier is Typical Application ±15 V supplies, very low noise, low frequency ±12 V supplies, very low noise, high frequency ±12 V supplies, very low noise, high frequency, dual ±12 V supplies, low noise, high frequency, single-ended-to-differential driver ±13 V supplies, low bias current, low frequency, single/dual ADA4922-1 ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ AD8610/ AD8620 Single-to-Differential Driver OUT+ 15Ω 2 2 RG SNR 10 20 f–3dB is the cutoff frequency of the input filter (3.9 MHz). N is the noise factor of the amplifier (1 in the buffer configuration). eN+ and eN− are the equivalent input voltage noise densities of the op amps connected to IN+ and IN−, in nV/√Hz. When the resistances used around the amplifiers are small, this approximation can be used. If larger resistances are used, their noise contributions should also be root-sum squared. • Amplifier AD829 AD8021 AD8022 For single-ended sources, a single-to-differential driver, such as the ADA4922-1, can be used because the AD7952 needs to be driven differentially. The 1-pole filter using R = 15 Ω and C = 2.7 nF provides a corner frequency of 3.9 MHz. where: VNADC is the noise of the ADC, which is: V INp-p V NADC = Table 8. Recommended Driver Amplifiers The driver needs to have a THD performance suitable to that of the AD7952. Figure 15 shows the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best SNR. OUT– 15Ω U2 2.7nF REF R2 IN+ AD7952 ANALOG IN INPUT ADA4922-1 VCC 2.7nF RF R1 VEE IN– REF 10µF 100nF 06589-047 SNRLOSS ⎛ ⎜ VNADC = 20 log ⎜ ⎜ π π 2 2 ⎜ VNADC 2 + f −3dB (Ne N + ) + f −3dB (Ne N − ) 2 2 ⎝ Because the AD7952 uses a large geometry, high voltage input switch, the best linearity performance is obtained when using the amplifier at its maximum full power bandwidth. Gaining the amplifier to make use of the more dynamic range of the ADC results in increased linearity errors. For applications requiring more resolution, the use of an additional amplifier with gain should precede a unity follower driving the AD7952. See Table 8 for a list of recommended op amps. Figure 30. Single-to-Differential Driver Using the ADA4922-1 For unipolar 5 V and 10 V input ranges, the internal (or external) reference source can be used to level shift U2 for the correct input span. If using an external reference, the values for R1/R2 can be lowered to reduce resistive Johnson noise (1.29E − 10 × √R). For the bipolar ±5 V and ±10 V input ranges, the reference connection is not required because the common-mode voltage is 0 V. See Table 9 for R1/R2 for the different input ranges. Table 9. R1/R2 Configuration Input Range (V) 5 10 ±5, ±10 The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in Rev. 0 | Page 21 of 32 R1 (Ω) 2.5 k 2.5 k R2 (Ω) 2.5 k Open 100 Common-Mode Voltage (V) 2.5 5 0 AD7952 VOLTAGE REFERENCE INPUT/OUTPUT The AD7952 allows the choice of either a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. The internal reference of the AD7952 provides excellent performance and can be used in almost all applications. However, the linearity performance is guaranteed only with an external reference. Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low) To use the internal reference, the PDREF and PDBUF inputs must be low. This enables the on-chip, band gap reference, buffer, and TEMP sensor, resulting in a 5.00 V reference on the REF pin. The internal reference is temperature-compensated to 5.000 V ± 35 mV. The reference is trimmed to provide a typical drift of 3 ppm/°C. This typical drift characteristic is shown in Figure 19. For applications that use multiple AD7952s or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external 2.5 V reference voltage. The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±60 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. Temperature Sensor When the internal reference is enabled (PDREF = PDBUF = low), the on-chip temperature sensor output (TEMP) is enabled and can be use to measure the temperature of the AD7952. To improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the analog switch (such as ADG779), and the ADC itself is used to measure its own temperature. This configuration is shown in Figure 31. TEMPERATURE SENSOR IN+ ANALOG INPUT CC External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low) To use an external reference with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN, producing 5 V on the REF pin. The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. TEMP ADG779 AD7952 Figure 31. Use of the Temperature Sensor POWER SUPPLIES The AD7952 uses five sets of power supply pins: • AVDD: analog 5 V core supply • VCC: analog high voltage, positive supply • VEE: high voltage, negative supply External 5 V Reference (PDREF = High, PDBUF = High) • DVDD: digital 5 V core supply To use an external reference directly on the REF pin, PDREF and PDBUF should both be high. PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. For improved drift performance, an external reference, such as the ADR445 or the ADR435, is recommended. • OVDD: digital input/output interface supply Reference Decoupling Whether using an internal or external reference, the AD7952 voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 22 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or the ADR445/ADR435 external reference. The placement of the reference decoupling is also important to the performance of the AD7952. The decoupling capacitor should be mounted on the same side as the ADC, right at the REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. 06589-030 This circuit can also be made discretely, and thus more flexible, using any of the recommended low noise amplifiers in Table 8. Again, to preserve the SNR of the converter, the resistors, RF and RG, should be kept low. Core Supplies The AVDD and DVDD supply the AD7952 analog and digital cores, respectively. Sufficient decoupling of these supplies is required, consisting of at least a 10 μF capacitor and a 100 nF capacitor on each supply. The 100 nF capacitors should be placed as close as possible to the AD7952. To reduce the number of supplies needed, the DVDD can be supplied through a simple RC filter from the analog supply, as shown in Figure 27. High Voltage Supplies The high voltage bipolar supplies, VCC and VEE, are required and must be at least 2 V larger than the maximum input, VIN. For example, if using the bipolar 10 V range, the supplies should be ±12 V minimum. Sufficient decoupling of these supplies is also required, consisting of at least a 10 μF capacitor and a 100 nF capacitor on each supply. For unipolar operation, the VEE supply can be grounded with some slight THD performance degradation. Digital Output Supply The OVDD supplies the digital outputs and allows direct interface with any logic working between 2.3 V and 5.25 V. Rev. 0 | Page 22 of 32 AD7952 OVDD should be set to the same level as the system interface. Sufficient decoupling is required, consisting of at least a 10 μF capacitor and a 100 nF capacitor with the 100 nF capacitors placed as close as possible to the AD7952. Power Sequencing The AD7952 is independent of power supply sequencing and is very insensitive to power supply variations on AVDD over a wide frequency range, as shown in Figure 32. 80 EXT REF 75 INT REF 70 Setting PD = high powers down the AD7952, thus reducing supply currents to their minimums, as shown in Figure 23. When the ADC is in power-down, the current conversion (if any) is completed and the digital bus remains active. To further reduce the digital supply currents, drive the inputs to OVDD or OGND. Power-down can also be programmed with the configuration register. See the Software Configuration section for details. Note that when using the configuration register, the PD input is a don’t care and should be tied to either high or low. CONVERSION CONTROL 65 PSRR (dB) Power Down The AD7952 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. A detailed timing diagram of the conversion process is shown in Figure 34. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is completed. The CNVST signal operates independently of the CS and RD signals. 60 55 50 45 40 35 t2 1 10 100 1000 10000 FREQUENCY (kHz) 06589-031 30 t1 CNVST Figure 32. AVDD PSRR vs. Frequency BUSY In impulse mode, the AD7952 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced (see Figure 33). This feature makes the AD7952 ideal for very low power, battery-operated applications. t6 t5 MODE ACQUIRE CONVERT t7 ACQUIRE t8 CONVERT Figure 34. Basic Conversion Timing Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing. 1000 The CNVST trace should be shielded with ground, and a low value (such as 50 Ω) serial resistor termination should be added close to the output of the component that drives this line. 100 For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 27. 10 1 10 WARP MODE POWER IMPULSE MODE POWER PDREF = PDBUF = HIGH 100 1000 10000 100000 1000000 06589-032 POWER DISSIPATION (mW) It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND). t4 t3 06589-033 Power Dissipation vs. Throughput Figure 33. Power Dissipation vs. Sample Rate Rev. 0 | Page 23 of 32 AD7952 INTERFACES DIGITAL INTERFACE CS = RD = 0 The AD7952 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7952 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In most applications, the OVDD supply pin is connected to the host system interface 2.5 V to 5.25 V digital supply. Finally, by using the OB/2C input pin, both twos complement or straight binary coding can be used. CNVST t1 t10 BUSY t4 t3 PREVIOUS CONVERSION DATA 06589-035 DATA BUS t11 NEW DATA Figure 36. Master Parallel Data Timing for Reading (Continuous Read) Two signals, CS and RD, control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7952 in multicircuit applications and is held low in a single AD7952 design. RD is generally used to enable the conversion result on the data bus. Slave Parallel Interface In slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 37 and Figure 38, respectively. When the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. RESET The RESET input is used to reset the AD7952. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET resets the AD7952 and clears the data bus and configuration register. See Figure 35 for the RESET timing details. CS t9 RD RESET BUSY BUSY DATA BUS 06589-034 DATA BUS CNVST CURRENT CONVERSION t12 06589-036 t8 t13 Figure 35. RESET Timing Figure 37. Slave Parallel Data Timing for Reading (Read After Convert) PARALLEL INTERFACE CS = 0 The AD7952 is configured to use the parallel interface when SER/PAR is held low. t1 CNVST, RD Master Parallel Interface BUSY t4 t3 DATA BUS PREVIOUS CONVERSION t12 t13 Figure 38. Slave Parallel Data Timing for Reading (Read During Convert) Rev. 0 | Page 24 of 32 06589-037 Data can be continuously read by tying CS and RD low, thus requiring minimal microprocessor connections. However, in this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in RESET). Figure 36 details the timing for this mode. AD7952 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 39, when BYTESWAP is low, the LSB byte is output on D[7:0] and the MSB is output on D[13:8]. When BYTESWAP is high, the LSB and MSB bytes are swapped; the LSB is output on D[13:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 14-bit data can be read in two bytes on either D[13:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. The pins multiplexed on D[8:0] and used for master serial interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC, INVSCLK, RDC, SDOUT, SDCLK, and SYNC. CS RD BYTESWAP Internal Clock (SER/PAR = High, EXT/INT = Low) The AD7952 is configured to generate and provide the serial data clock, SDCLK, when the EXT/INT pin is held low. The AD7952 also generates a SYNC signal to indicate to the host when the serial data is valid. The SDCLK and the SYNC signals can be inverted, if desired, using the INVSCLK and INVSYNC inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each conversion. Figure 40 and Figure 41 show detailed timing diagrams of these two modes. Read During Convert (RDC = High) HIGH BYTE t12 PINS D[7:0] HI-Z LOW BYTE LOW BYTE t12 HI-Z t13 HIGH BYTE HI-Z 06589-038 PINS D[13:8] HI-Z Figure 39. 8-Bit and 14-Bit Parallel Interface SERIAL INTERFACE The AD7952 has a serial interface (SPI-compatible) multiplexed on the data pins D[13:0]. The AD7952 is configured to use the serial interface when SER/PAR is held high. Data Interface The AD7952 outputs 14 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 14 clock pulses provided on the SDCLK pin. The output data is valid on both the rising and falling edge of the data clock. Serial Configuration Interface The AD7952 can be configured through the serial configuration register only in serial mode, because the serial configuration pins are also multiplexed on the data pins D[13:10]. See the Hardware Configuration section and Software Configuration section for more information. Setting RDC = high allows the master read (previous conversion result) during conversion mode. Usually, because the AD7952 is used with a fast throughput, this mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instances, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SDCLK period changes because the LSBs require more time to settle and the SDCLK is derived from the SAR conversion cycle. In this mode, the AD7952 generates a discontinuous SDCLK of two different periods and the host should use an SPI interface. Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) Setting RDC = low allows the read after conversion mode. Unlike the other serial modes, the BUSY signal returns low after the 14 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer BUSY width (refer to Table 4 for BUSY timing specifications). The DIVSCLK[1:0] inputs control the SDCLK period and SDOUT data rate. As a result, the maximum throughput cannot be achieved in this mode. In this mode, the AD7952 also generates a discontinuous SDCLK; however, a fixed period and hosts supporting both SPI and serial ports can also be used. Rev. 0 | Page 25 of 32 AD7952 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 1 2 D13 D12 SDCLK t24 t21 3 12 13 D2 D1 t26 14 t15 t27 X t16 D0 06589-039 SDOUT t23 t22 Figure 40. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t19 t20 t21 t14 SDCLK t15 1 t24 2 3 12 13 t18 t16 X t22 t27 D13 D12 D2 D1 D0 06589-040 SDOUT t26 14 t23 Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 26 of 32 AD7952 The pins multiplexed on D[19:2] used for slave serial interface are: EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK, and RDERROR. External Clock (SER/PAR = High, EXT/INT = High) Setting the EXT/INT = high allows the AD7952 to accept an externally supplied serial data clock on the SDCLK pin. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. A clock can be either normally high or normally low when inactive. For detailed timing diagrams, see Figure 43 and Figure 44. While the AD7952 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result may occur. This is particularly important during the last 450 ns of the conversion phase because the AD7952 provides error correction circuitry that can correct for an improper bit decision made during the first part of the conversion phase. For this reason, it is recommended that any external clock provided is a discontinuous clock that transitions only when BUSY is low or, more importantly, that it does not transition during the last 450 ns of BUSY high. Simultaneous sampling is possible by using a common CNVST signal. Note that the SDIN input is latched on the opposite edge of SDCLK used to shift out the data on SDOUT (SDCLK falling edge when INVSCLK = low). Therefore, the MSB of the upstream converter follows the LSB of the downstream converter on the next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot be used because the SDIN-to-SDCLK setup time, t33, is less than the minimum time specified. (SDCLKto-SDOUT delay, t32, is the same for all converters when simultaneously sampled). For proper operation, the SDCLK edge for latching SDIN (or ½ period of SDCLK) needs to be t 1 / 2 SDCLK = t 32 + t 33 or the maximum SDCLK frequency needs to be 1 f SDCLK = 2(t 32 + t 33 ) If not using the daisy-chain feature, the SDIN input should always be tied either high or low. BUSY OUT BUSY BUSY AD7952 AD7952 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN External Discontinuous Clock Data Read After Conversion CNVST Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 43 shows the detailed timing diagrams for this method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both CS and RD are low. Data is shifted out MSB first with 14 clock pulses and, depending on the SDCLK frequency, can be valid on the falling and rising edges of the clock. One advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both the slow digital host interface and the fastest serial reading. Daisy-Chain Feature Also in the read after convert mode, the AD7952 provides a daisy-chain feature for cascading multiple converters together using the serial data input pin, SDIN. This feature is useful for reducing component count and wiring connections when desired, for instance, in isolated multiconverter applications. See Figure 43 for the timing details. An example of the concatenation of two devices is shown in Figure 42. SDOUT RDC/SDIN SDOUT DATA OUT CNVST CS CS SDCLK SDCLK SDCLK IN CS IN CNVST IN 06589-041 SLAVE SERIAL INTERFACE Figure 42. Two AD7952 Devices in a Daisy-Chain Configuration External Clock Data Read During Previous Conversion Figure 44 shows the detailed timing diagrams for this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 14 clock pulses, and depending on the SDCLK frequency, can be valid on both the falling and rising edges of the clock. The 14 bits have to be read before the current conversion is completed; otherwise, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. To reduce performance degradation due to digital activity, a fast discontinuous clock of at least 40 MHz is recommended to ensure that all the bits are read during the first half of the SAR conversion phase. The daisy-chain feature should not be used in this mode because digital activity occurs during the second half of the SAR conversion phase, likely resulting in performance degradation. Rev. 0 | Page 27 of 32 AD7952 External Clock Data Read After/During Conversion It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a discontinuous SDCLK whenever possible to minimize potential incorrect bit decisions. For the different modes, the use of a slower SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode, and 13 MHz in impulse mode can be used. EXT/INT = 1 SER/PAR = 1 INVSCLK = 0 RD = 0 CS BUSY t31 SDCLK t35 t31 X* 1 2 3 t32 SDOUT t36 4 13 12 14 15 16 17 t37 D13 D12 D11 D2 D1 D0 X13 X12 X13 X12 X11 X2 X1 X0 Y13 Y12 t16 t33 t34 06589-042 SDIN *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 43. Slave Serial Data Timing for Reading (Read After Convert) SER/PAR = 1 EXT/INT = 1 RD = 0 INVSCLK = 0 CS CNVST BUSY SDCLK t35 t31 X* 1 2 3 t32 13 X* 14 X* X* X* X* t37 D13 SDOUT t36 D12 D1 D0 DATA = SDIN t27 t16 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 28 of 32 06589-043 t31 AD7952 HARDWARE CONFIGURATION The AD7952 can be configured at any time with the dedicated hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/2C, and PD for parallel mode (SER/PAR = low) or serial hardware mode (SER/ PAR = high, HW/SW = high). Programming the AD7952 for mode selection and input range configuration can be done before or during conversion. Like the RESET input, the ADC requires at least one acquisition time to settle, as shown in Figure 45. See Table 6 for pin descriptions. Note that these inputs are high impedance when using the software configuration mode. it is not recommended to write to the SCP during the last 450 ns of conversion (BUSY = high), or performance degradation can result. In addition, the SCP can be accessed in both serial master and serial slave read during and read after convert modes. Note that at power-up, the configuration register is undefined. The RESET input clears the configuration register (sets all bits to 0), thus placing the configuration to 0 V to 5 V input, normal mode, and twos complemented output. Table 10. Configuration Register Description Bit 8 Name START 7 BIPOLAR 6 5 TEN PD 4 IMPULSE 3 2 WARP OB/2C 1 0 RSV RSV SOFTWARE CONFIGURATION The pins multiplexed on D[13:10] used for software configuration are: HW/SW, SCIN, SCCLK, and SCCS. The AD7952 is programmed using the dedicated write-only serial configurable port (SCP) for conversion mode, input range selection, output coding, and power-down using the serial configuration register. See Table 10 for details of each bit in the configuration register. The SCP can only be used in serial software mode selected with SER/PAR = high and HW/SW = low because the port is multiplexed on the parallel interface. The SCP is accessed by asserting the port’s chip select, SCCS, and then writing SCIN synchronized with SCCLK, which (like SDCLK) is edge sensitive depending on the state of INVSCLK. See Figure 46 for timing details. SCIN is clocked into the configuration register MSB first. The configuration register is an internal shift register that begins with Bit 8, the START bit. The 9th SPPCLK edge updates the register and allows the new settings to be used. As indicated in the timing diagram, at least one acquisition time is required from the 9th SCCLK edge. Bits [1:0] are reserved bits and are not written to while the SCP is being updated. The SCP can be written to at any time, up to 40 MHz, and it is recommended to write to while the AD7952 is not busy converting, as detailed in Figure 46. In this mode, the full 1 MSPS is not attainable because the time required for SCP access is (t31 + 9 × 1/SCCLK + t8) minimum. If the full throughput is required, the SCP can be written to during conversion; however, HW/SW = 0 PD = 0 Description START bit. With the SCP enabled (SCCS = low), when START is high, the first rising edge of SCCLK (INVSCLK = low) begins to load the register with the new configuration. Input Range Select. Used in conjunction with Bit 6, TEN, per the following. Input Range (V) BIPOLAR TEN 0 to 5 Low Low 0 to 10 Low High ±5 High Low ±10 High High Input Range Select. See Bit 7, BIPOLAR. Power Down. PD = low, normal operation. PD = high, power down the ADC. The SCP is accessible while in power-down. To power-up the ADC, write PD = low on the next configuration setting. Mode Select. Used in conjunction with Bit 3, WARP, per the following. Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High Mode Select. See Bit 4, IMPULSE. Output Coding. OB/2C = low, use twos complement output. OB/2C = high, use straight binary output. Reserved. Reserved. SER/PAR = 0, 1 t8 t8 CNVST BUSY BIPOLAR, TEN 06589-044 WARP, IMPULSE Figure 45. Hardware Configuration Timing Rev. 0 | Page 29 of 32 AD7952 BIPOLAR = 0 OR 1 TEN = 0 OR 1 WARP = 0 OR 1 IMPULSE = 0 OR 1 SER/PAR = 1 HW/SW = 0 INVSCLK = 0 t8 PD = 0 CNVST BUSY t31 SCCS t35 t31 SCCLK 1 2 3 4 t36 5 6 7 WARP OB/2C 8 9 t37 SCIN X START BIPOLAR TEN PD IMPULSE X 06589-045 t33 t34 Figure 46. Serial Configuration Port Timing The AD7952 is ideally suited for traditional dc measurement applications supporting a microprocessor and ac signal processing applications interfacing to a digital signal processor. The AD7952 is designed to interface with a parallel 8-bit or 14-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7952 to prevent digital noise from coupling into the ADC. SPI Interface The reading process can be initiated in response to the end-ofconversion signal (BUSY going low) using an interrupt line of the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 0 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, use one of the parallel interface modes. The AD7952 is compatible with SPI and QSPI digital hosts and DSPs, such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x. Figure 47 shows an interface diagram between the AD7952 and the SPI-equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7952 acts as a slave device, and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to an internal timer interrupt. DVDD AD7952* SER/PAR EXT/INT RD BUSY CS ADSP-219x* PFx SPIxSEL (PFx) SDOUT MISOx SDCLK SCKx INVSCLK CNVST PFx OR TFSx *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 47. Interfacing the AD7952 to SPI Interface Rev. 0 | Page 30 of 32 06589-046 MICROPROCESSOR INTERFACING AD7952 APPLICATION INFORMATION LAYOUT GUIDELINES While the AD7952 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7952 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7952, or as close as possible to the AD7952. If the AD7952 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7952. The DVDD supply of the AD7952 can either be a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. See Figure 27 for an example of this configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7952 has four different ground pins: REFGND, AGND, DGND, and OGND. • REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. • AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. • DGND must be tied to the analog or digital ground plane depending on the configuration. • OGND is connected to the digital system ground. To prevent coupling noise onto the die, to avoid radiating noise, and to reduce feedthrough: • Do not run digital lines under the device. • Do run the analog ground plane under the AD7952. • Shield fast switching signals, like CNVST or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. • Avoid crossover of digital and analog signals. • Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7952 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7952, and to reduce the magnitude of the supply spikes. Decoupled ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces. EVALUATING PERFORMANCE A recommended layout for the AD7952 is outlined in the EVAL-AD7952CBZ evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. 0 | Page 31 of 32 AD7952 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH VIEW A 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 48. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX 48 5.25 5.10 SQ 4.95 25 24 13 12 0.25 MIN 5.50 REF 0.05 MAX 0.02 NOM 0.50 BSC 1 (BOTTOM VIEW) 0.80 MAX 0.65 TYP SEATING PLANE PIN 1 INDICATOR EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX 0.20 REF PADDLE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 49. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model AD7952BCPZ 1 AD7952BCPZRL1 AD7952BSTZ1 AD7952BSTZRL1 EVAL-AD7952CBZ1, 2 EVAL-CONTROL BRD3 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Controller Board Package Option CP-48-1 CP-48-1 ST-48 ST-48 1 Z = Pb-free part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the CB designators. 2 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06589-0-2/07(0) T T Rev. 0 | Page 32 of 32