CY62146CV30 MoBL™ 256K x 16 Static RAM Features reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by 99% when deselected (CE HIGH). The input/output pins (I/O0 – I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW and WE LOW). • High speed: — 55 ns and 70 ns availability • Voltage range: — CY62146CV30: 2.7V – 3.3V • Pin compatible with CY62146V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz • • • • — Typical active current: 7 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power Functional Description The CY62146CV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 – I/O7), is written into the location specified on the address pins (A0 – A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 – I/O15) is written into the location specified on the address pins (A0 – A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of Read and Write modes. The CY62146CV30 is available in 48-ball FBGA packaging. Logic Block Diagram 256K × 16 RAM Array 2048 × 2048 SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 – I/O7 I/O8 – I/O15 • A13 BHE WE CE OE BLE A14 A15 A16 A17 A11 Cypress Semiconductor Corporation Document #: 38-05203 Rev. ** A12 COLUMN DECODER 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 17, 2001 CY62146CV30 MoBL™ Pin Configuration[1,2] FBGA (Top View) 4 5 3 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 1 2 BLE OE A0 I/O8 BHE I/O9 NC H Product Portfolio Power Dissipation (Industrial) VCC Range Product VCC(min.) CY62146CV30 2.7V Speed 3.3V Standby (ISB2) f = fmax Typ.[3] Max. Typ.[3] 55 ns 1.5 mA 3 mA 12 mA 25 mA 70 ns 1.5 mA 3 mA 7 mA VCC(typ.)[3] VCC(max.) 3.0V Operating, ICC f = 1 MHz Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Max. 15 mA Max. 7 µA 15 µA DC Input Voltage[4].................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ...–0.5V to Vccmax + 0.5V DC Voltage Applied to Outputs in High-Z State[4] ....................................–0.5V to VCC + 0.5V Typ.[3] Device CY62146CV30 Range Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.3V Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or VSS to ensure proper application. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. Document #: 38-05203 Rev. ** Page 2 of 12 CY62146CV30 MoBL™ Electrical Characteristics Over the Operating Range Parameter -55 Description Test Conditions Min. Typ.[3] -70 Max. VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1mA VCC = 2.7V VIH Input HIGH Voltage 2.2 VCC + 0.3V VIL Input LOW Voltage –0.3 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current ICC VCC Operating Supply Current ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, Vcc=3.3V ISB2 2.4 f = 1 MHz Typ.[3] Max. Unit 2.4 V 0.4 GND < VO < VCC, Output Disabled f = fMAX = 1/tRC Min. 0.4 V 1.8 VCC + 0.3V V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA VCC = 3.3V IOUT = 0 mA CMOS Levels 12 25 7 15 1.5 3 1.5 3 7 15 7 15 mA µA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Still Air, soldered on a 4.25 × 1.125 inch, four-layer printed circuit board Thermal Resistance (Junction to Case)[5] Symbol BGA Units ΘJA 55 °C/W ΘJC 16 °C/W Note: 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05203 Rev. ** Page 3 of 12 CY62146CV30 MoBL™ AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT 10% 30 pF R2 90% 10% 90% GND Rise TIme: 1 V/ns Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V Unit R1 1.105 KOhms R2 1.550 KOhms RTH 0.645 KOhms VTH 1.75V Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR Description Conditions VCC for Data Retention ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time Min. Typ.[3] 1.5 VCC= 1.5V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 3 Max. Unit Vccmax V 10 µA 0 ns tRC ns Note: 6. Full device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100µs or stable at VCC(min.) >100 µs. Document #: 38-05203 Rev. ** Page 4 of 12 CY62146CV30 MoBL™ Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VCC(min) VDR > 1.5 V tR tCDR CE Switching Characteristics Over the Operating Range[7] -55 Parameter Description Min -70 Max Min Max Unit READ CYCLE tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns [8] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[8,10] tLZCE CE LOW to Low Z [8] 70 55 10 70 10 5 10 ns 25 10 20 ns ns 5 20 [8, 10] ns ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 55 70 ns tDBE BHE / BLE LOW to Data Valid 25 35 ns tLZBE[9] BHE / BLE LOW to Low Z tHZBE BHE / BLE HIGH to High Z 0 25 0 5 ns 5 20 ns ns 25 ns WRITE CYCLE[11] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tBW BHE / BLE Pulse Width 50 60 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z [8, 10] WE HIGH to Low Z [8] 20 5 25 5 ns ns Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. If both byte enables are toggled together, this value is 10 ns. 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 11. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. Document #: 38-05203 Rev. ** Page 5 of 12 CY62146CV30 MoBL™ Switching Waveforms Read Cycle 1 (Address Transition Controlled) [12, 13] tRC ADDRESS tOHA DATA OUT tAA DATAIN VALID PREVIOUS DATA VALID Read Cycle 2 (OE Controlled) [13, 14] ADDRESS tRC CE tPD tHZCE tACE OE BHE/BLE ttLZOE LZOE tHZOE tDOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes: 12. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05203 Rev. ** Page 6 of 12 CY62146CV30 MoBL™ Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [11, 15, 16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Write Cycle 2 (CE Controlled) [11, 15, 16] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05203 Rev. ** Page 7 of 12 CY62146CV30 MoBL™ Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW) [16] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tHD tSD DATAI/O NOTE 17 DATAIN VALID tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW) [16] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 17 Document #: 38-05203 Rev. ** tHD DATAIN VALID Page 8 of 12 CY62146CV30 MoBL™ Typical DC and AC Parameters (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.) Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage Access Time vs. Supply Voltage 14.0 60 10.0 10.0 50 MoBL2 MoBL2 8.0 ISB (mA) (f = fmax, 70 ns) 6.0 4.0 40 6.0 TAA (ns) 8.0 ICC (mA) MoBL2 12.0 (f = fmax, 55 ns) 12.0 4.0 2.0 0.0 2.7 3.0 0 2.7 3.3 SUPPLY VOLTAGE (V) 20 10 2.0 (f = 1 MHz) 30 0 3.0 3.3 2.7 SUPPLY VOLTAGE (V) 3.0 3.3 SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE H X X X X High Z Deselect/Power-Down Standby (ISB) L X X H H High Z Output Disabled Active (ICC) L H L L L Data Out (I/OO – I/O15) Read Active (ICC) L H L H L Data Out (I/OO – I/O7); I/O8 – I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8 – I/O15); I/O0 – I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/OO – I/O15) Write Active (ICC) L L X H L Data In (I/OO – I/O7); I/O8 – I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8 – I/O15); I/O0 – I/O7 in High Z Write Active (ICC) Document #: 38-05203 Rev. ** Inputs/Outputs Mode Power Page 9 of 12 CY62146CV30 MoBL™ Ordering Information Speed (ns) 70 55 Ordering Code Package Name Package Type Operating Range CY62146CV30LL-70BAI BA48B 48-ball Fine Pitch BGA (7 mm × 8.5 mm × 1.2 mm) Industrial CY62146CV30LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) CY62146CV30LL-55BAI BA48B 48-ball Fine Pitch BGA (7 mm × 8.5 mm × 1.2 mm) CY62146CV30LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B 51-85106-*C Document #: 38-05203 Rev. ** Page 10 of 12 CY62146CV30 MoBL™ Package Diagrams (continued) 48-ball (6.0 mm × 8.0 mm × 1.0 mm) Fine Pitch BGA BV48A 51-85150-** MoBL, MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05203 Rev. ** Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62146CV30 MoBL™ Document Title: CY62146CV30 MoBLTM 256K x 16 STATIC RAM Document Number: 38-05203 REV. ECN NO. Issue Date Orig. of Change ** 112395 01/18/02 GAV Document #: 38-05203 Rev. ** Description of Change New Data Sheet Page 12 of 12