IDT IDT71V30L High-speed 3.3v 1k x 8 dual-port static ram Datasheet

IDT71V30S/L
HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
High-speed access
– Commercial: 25/35/55ns (max.)
Low-power operation
– IDT71V30S
— Active: 375mW (typ.)
— Standby: 5mW (typ.)
– IDT71V30L
— Active: 375mW (typ.)
— Standby: 1mW (typ.)
◆
◆
◆
◆
◆
On-chip port arbitration logic
Interrupt flags for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation, 2V data retention (L Only)
TTL-compatible, single 3.3V ±0.3V power supply
Industrial temperature range (-40OC to +85OC) is available
for selected speeds
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0R-I/O7R
I/O0L- I/O7L
I/O
Control
I/O
Control
(1)
(1)
BUSYL
A9L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
10
CEL
OEL
R/WL
Address
Decoder
A9R
A0R
10
ARBITRATION
and
INTERRUPT
LOGIC
(2)
CER
OER
R/WR
(2)
INTL
INTR
3741 drw 01
NOTES:
1. IDT71V30: BUSY outputs are non-tristatable push-pulls.
2. INT outputs are non-tristable push-pull output structure.
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC 3741/7
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71V30 is a high-speed 1K x 8 Dual-Port Static RAM. The
IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port
SRAM.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 375mW of power. Low-power (L)
versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery.
The IDT71V30 devices are packaged in 64-pin STQFPs.
N/C
N/C
N/C
INTL
BUSYL
R/WL
CEL
VCC
VCC
CER
R/WR
BUSYR
INTR
N/C
N/C
N/C
Pin Configurations(1,2,3)
IDT71V30TF
PP64-1(4)
64-Pin STQFP
Top View(5)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O3L
N/C
I/O4L
I/O5L
I/O6L
I/O7L
N/C
GND
GND
I/O0R
I/O1R
I/O2R
I/O3R
N/C
I/O4R
I/O5R
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
N/C
A7L
A8L
A9L
N/C
I/O0L
I/O1L
I/O2L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
INDEX
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking.
6.42
2
OER
A 0R
A 1R
A 2R
A 3R
A 4R
A 5R
A 6R
N/C
A 7R
A 8R
A 9R
N/C
N/C
I/O 7R
I/O 6R
3741 drw 03
,
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Recommended
DC Operating Conditions
Absolute Maximum Ratings(1)
Symbol
VTERM
(2)
TBIAS
Rating
Com'l & Ind
Unit
Terminal Voltage
with Respect to GND
-0.5 to +4.60
V
Temperature
Under Bias
-55 to +125
Storage
Temperature
TSTG
o
-65 to +150
C
Supply Voltage
GND
Ground
VIH
C
50
mA
Parameter
VCC
Input High Voltage
VIL
DC Output
Current
IOUT
o
Symbol
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
V
2.0
____
VCC+0.3V
V
____
0.8
(1)
Input Low Voltage
-0.3
V
3741 tbl 02
NOTE:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
3741 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
Maximum Operating
Temperature and Supply Voltage(1,2)
Grade
Commercial
Symbol
Parameter
CIN
Input Capacitance
COUT
Output
Capacitance
f=1.0MHz)
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
GND
Vcc
0OC to +70OC
0V
3.3V + 0.3
0V
3.3V + 0.3
O
Industrial
Capacitance(1) (TA = +25OC,
Ambient
Temperature
O
-40 C to +85 C
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers,
contact your sales office.
3741 tbl 03
3741 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(VCC = 3.3V ± 0.3V)
71V30S
Symbol
Parameter
Test Conditions
Min.
71V30L
Max.
Min.
Max.
Unit
10
___
5
µA
|ILI|
Input Leakage
Current(1)
VCC = 3.6V,
VIN = 0V to V CC
___
|ILO|
Output Leakage
Current
CE = VIH,
VOUT = 0V to V CC
___
10
___
5
µA
VOL
Output Low Voltage
(I/O0-I/O7)
IOL = 4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
3741 tbl 05
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Supply CurrentVIN > VCC -0.2V or < 0.2V
3
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V)
71V30X25
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Test Condition
Version
CEL and CER = VIL,
Outputs Disabled
f = fMAX(3)
CEL and CER= VIL,
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
Full Standby Current (Both
CEL and CER > VCC - 0.2V
Ports - CMOS Level Inputs) VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled
f=fMAX(3)
71V30X35
Com'l Only
71V30X55
Com'l Only
Typ.(2)
Max.
Typ. (2)
Max.
Typ. (2)
Max.
Unit
mA
COM'L
S
L
75
75
150
120
75
75
145
115
75
75
135
105
IND
S
L
___
___
___
___
___
___
___
___
___
___
___
___
COM'L
S
L
20
20
50
35
20
20
50
35
20
20
50
35
IND
S
L
___
___
___
___
___
___
___
___
___
___
___
___
COM'L
S
L
30
30
105
75
30
30
100
70
30
30
90
60
IND
S
L
___
___
___
___
___
___
___
___
___
___
___
___
COM'L
S
L
1.0
0.2
5.0
3.0
1.0
0.2
5.0
3.0
1.0
0.2
5.0
3.0
IND
S
L
___
___
___
___
___
___
___
___
___
___
___
___
COM'L
S
L
30
30
90
75
30
30
85
70
30
30
75
60
IND
S
L
___
___
___
___
___
___
___
___
___
___
___
___
mA
mA
mA
mA
3741 tbl 06
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to chip enable Truth Table I.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics
(L Version Only)
71V30L
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
VCC = 2V, CE > VCC -0.2V
tCDR
(3)
tR
(3)
Chip Deselect to Data Retention Time
Min.
Typ. (1)
Max.
Unit
2.0
____
____
V
Ind.
____
____
____
µA
Com'l.
____
100
1500
0
____
____
ns
____
____
ns
Test Condition
VIN > VCC -0.2V or VIN < 0.2V
(2)
Operation Recovery Time
tRC
3741 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
4
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
AC Test Conditions
Industrial and Commercial Temperature Ranges
Data Retention Waveform
Input Pulse Levels
DATA RETENTION MODE
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
VCC
3.0V
VDR ≥ 2.0V
tCDR
tR
Figures 1 and 2
3741 tbl 08
VDR
CE
VIH
VIH
3.3V
3741 drw 04 ,
3.3V
590Ω
DATA OUT
BUSY
INT 435Ω
3.0V
590Ω
DATA OUT
30pF
435Ω
5pF
3741 drw 05
Figure 2. Output Test Load
(For tHZ, tLZ, tWZ and tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,4)
71V30X25
Com'l Only
Symbol
Parameter
71V30X35
Com'l Only
71V30X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
____
35
____
55
____
ns
tAA
Address Access Time
____
25
____
35
____
55
ns
tACE
Chip Enable Access Time
____
25
____
35
____
55
ns
Output Enable Access Time
____
12
____
20
____
25
ns
3
____
3
____
ns
____
ns
tAOE
tOH
Output Hold from Address Change
3
____
tLZ
Output Low-Z Time (1,2)
0
____
0
____
0
tHZ
Output High-Z Time (1,2)
____
12
____
15
____
30
ns
0
____
0
____
0
____
ns
50
____
50
____
50
ns
tPU
tPD
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
____
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and power contact your sales office.
5
6.42
3741 tbl 09
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
3741 drw 06
tBDD (2,3)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operations BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
tACE
CE
tAOE
(4)
tHZ
(2)
OE
tLZ
(1)
tHZ
VALID DATA
DATAOUT
tLZ
ICC
CURRENT
ISS
(2)
(1)
tPD
tPU
50%
(4)
50%
3741 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is desserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, and tBDD.
6.42
6
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4,5)
71V30X25
Com'l Only
Symbol
Parameter
71V30X35
Com'l Only
71V30X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
25
____
35
____
55
____
ns
tEW
Chip Enable to End-of-Write
20
____
30
____
40
____
ns
tAW
Address Valid to End-of-Write
20
____
30
____
40
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
20
____
30
____
40
____
ns
0
____
0
____
ns
____
ns
tWP
Write Pulse Width
tWR
Write Recovery Time
0
____
tDW
Data Valid to End-of-Write
12
____
20
____
20
tHZ
Output High-Z Time (1,2)
____
12
____
15
____
30
ns
0
____
0
____
0
____
ns
15
____
30
ns
____
0
____
ns
tDH
tWZ
tOW
Data Hold Time
(3)
(1,2)
____
15
____
(1,2,3)
0
____
0
Write Enable to Output in High-Z
Output Active from End-of-Write
3741 tbl 10
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperatures: for specific speeds, packages and powers contact your sales office.
7
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1,(R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
tHZ (7)
OE
tAW
CE
tWP(2)
tAS (6)
tHZ (7)
tWR (3)
R/W
tWZ (7)
DATA OUT
tOW
(4)
(4)
tDW
tDH
DATA IN
3741 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE
tAS (6)
tEW
(2)
tWR
(3)
R/W
tDW
tDH
DATA IN
3741 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
6.42
8
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
71V30X25
Com'l Only
Symbol
Parameter
71V30X35
Com'l Only
71V30X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
20
____
30
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
20
____
30
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
____
30
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
30
ns
tWH
Write Hold After BUSY(5)
20
____
30
____
40
____
ns
tWDD
Write Pulse to Data Delay(1)
____
50
____
60
____
80
ns
____
35
____
45
____
65
ns
5
____
5
____
5
____
ns
____
30
____
30
____
45
ns
tDDD
Write Data Valid to Read Data Delay
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data(3)
(1)
(2)
3741 tbl 11
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”.
5. To ensure that the Write Cycle is completed on Port “B” after contention on Port “A”.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Write with Port-to-Port Read with BUSY(1,2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
DATAIN"A"
tDH
VALID
(1)
tAPS
ADDR"B"
MATCH
tBDD
t BDA
BUSY"B"
tWDD
DATAOUT"B"
VALID
tDDD
3741 drw 10
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
9
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(3)
tWP
R/W'A'
tWB
BUSY'B'
tWH
(1)
,
R/W'B'
(2)
NOTES:
3741 drw 11
1. tWH must be met for BUSY.
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
'A' AND 'B'
ADDRESSES MATCH
CE'B'
tAPS (2)
CE'A'
tBAC
tBDC
BUSY'A'
3741 drw 12
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Timing Waveform of BUSY Arbitration Controlled Address Match Timing(1)
tRC
ADDR'A'
OR tWC
ADDRESSES MATCH
tAPS
ADDRESSES DO NOT MATCH
(2)
ADDR'B'
tBAA
tBDA
BUSY'B'
3741 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
6.42
10
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
71V30X25
Com'l Only
Symbol
Parameter
71V30X35
Com'l Only
71V30X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
25
____
25
____
45
ns
25
____
25
____
45
ns
tINS
tINR
Interrupt Set Time
____
Interrupt Reset Time
____
3741 tbl 12
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Interrupt Mode(1)
INT Sets
tWC
ADDR'A'
INTERRUPT ADDRESS (2)
tWR (4)
tAS (3)
R/W'A'
tINS (3)
INT'B'
3741 drw 14
INT Clears
tRC
ADDR'B'
INTERRUPT CLEAR ADDRESS
tAS
(3)
OE'B'
tINR (3)
INT'A'
3741 drw 15
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
11
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Table I. Non-Contention Read/Write Control(4)
Left or Right Port
(1)
R/W
CE
OE
D0-7
X
H
X
Z
Port Disab led and in Power-Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L
L
X
DATAIN
H
L
L
DATAOUT
H
L
H
Z
Function
Data on Port Written Into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
3741 tbl 13
NOTES:
1. A0L – A9L ≠ A0R – A9R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Table II. Interrupt Flag(1,4)
Left Port
Right Port
R/WL
CEL
OEL
A9L-A0L
INTL
R/WR
CER
OER
A9R-A0R
INTR
L
L
X
3FF
X
X
X
X
X
L(2)
Set Right INTR Flag
X
X
X
X
X
X
L
L
3FF
H(3)
Reset Right INTR Flag
X
X
X
X
L(3)
L
L
X
3FE
X
Set Left INTL Flag
X
L
L
3FE
H(2)
X
X
X
X
X
Reset Left INTL Flag
3741 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Table III — Address BUSY Arbitration
Inputs
Function
Outputs
CEL
CER
AOL-A9L
AOR-A9R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
3741 tbl 15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V30. BUSYX outputs on the
IDT71V30 are non-tristatable push-pull.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result.
BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
6.42
12
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Functional Description
The IDT71V30 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT71V30 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FE (HEX), where a write is defined as the CE = R/W = VIL per Truth
Table II. The left port clears the interrupt by accessing address location
3FE access with CER = OER = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
right port must access the memory location 3FF. The message (8 bits)
at 3FE or 3FF is user-defined, since it is an addressable SRAM location.
If the interrupt function is not used, address locations 3FE and 3FF are not
used as mail boxes, and are part of the random access memory. Refer
to Table II for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “Busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation.
13
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
A
Device Type Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
TF
64-pin STQFP (PP64-1)
25
35
55
Commercial
Commercial
Commercial
L
S
Low Power
Standard Power
71V30
8K (1K X 8-Bit) MASTER Dual-Port RAM
Speed in
nanoseconds
3741 drw 16
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
Datasheet Document History
12/9/98:
6/15/99:
8/3/99:
9/1/99:
11/12/99:
1/17/01:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
Page 2 Fixed typographical error
Removed Preliminary
Replaced IDT logo
Pages 1 and 2 Moved all of "Description" to page 2 and adjusted page layouts
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
14
for Tech Support:
831-754-4613
[email protected]
Similar pages