SRAM AS5C2568 Austin Semiconductor, Inc. 32K x 8 SRAM PIN ASSIGNMENT (Top View) SRAM MEMORY ARRAY 28-PIN PSOJ (DJ) FEATURES • • • • • • • • • Access Times: 12, 15, & 20ns Fast output enable (tDOE) for cache applications Low active power: 400 mW (TYP) Low power standby Fully static operation, no clock or refresh required High-performance, low-power CMOS double-metal process Single +5V (+10%) Power Supply Easy memory expansion with CE\ All inputs and outputs are TTL compatible OPTIONS A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND MARKING • Timing 12ns access* 15ns access 20ns access -12 -15 -20 • Package(s)** Plastic SOJ DJ • Operating Temperature Ranges Military -55oC to +125oC Industrial -40oC to +85oC XT IT 28 VCC 27 WE\ 26 A13 25 A8 24 A9 23 A11 22 OE\ 21 A10 20 CE\ 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 No. 906 GENERAL DESCRIPTION * -12 available in IT only. ** For ceramic version of this product, see the MT5C2568 data sheet. The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs using a four-transistor memory cell. These SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. For more products and information please visit our web site at www.austinsemiconductor.com AS5C2568 Rev. 2.0 12/00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM AS5C2568 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM A0 Vcc 256 x 1024 MEMORY ARRAY DECODER GND A14 I/O0 I/O DATA CIRCUIT COLUMN I/O I/O7 9A128-1 CE\ CONTROL CIRCUIT OE\ WE\ TRUTH TABLE MODE STANDBY READ READ WRITE AS5C2568 Rev. 2.0 12/00 OE\ X L H X CE\ H L L L WE\ X H H L DQ HIGH-Z Q HIGH-Z D POWER STANDBY ACTIVE ACTIVE ACTIVE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM AS5C2568 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Input or DQ Relative to Vss..................................................................-0.5V to Vcc +0.5V Voltage on Vcc Supply Relative to Vss.......................-1V to +7V Storage Temperature..............................................-65oC to +150oC Power Dissipation.......................................................................1W Short Circuit Output Current............................................20mA Lead Temperature (soldering 10 seconds)........................+260oC Max. Junction Temperature.................................................+175oC *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC or -40oC to +85oC; VCC = 5.0V +10%) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage CONDITIONS 0V ≤ VIN ≤ Vcc Output(s) disabled 0V < VOUT < Vcc IOH = -4.0mA IOL = 8.0mA $%&' ( ' ) * ! SYMBOL VIH VIL IL I , ) * + ) - MIN 2.2 -0.5 -5 MAX Vcc+0.5 0.8 5 UNITS V V µA -5 2.4 5 µA 0.4 V V ILO VOH VOL NOTES 1 1, 2 1 1 + . /*01 $%&' ( ' ) * + , ) * + ) - . /*01 2 $%&' "# * & ' ( 3 2 4 ' 5 ' ) * + , ) 67 $%4'89'( ' ) * + ' &'22:9' ' 4' 89'( , ) 67 CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance AS5C2568 Rev. 2.0 12/00 CONDITIONS SYM MAX UNITS NOTES TA = 25oC, f = 1MHz Vcc = 5V CIN 8 pF 4 CIO 10 pF 4 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM AS5C2568 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55oC < TC < 125oC or -40oC to +85oC; VCC = 5.0V +10%) DESCRIPTION SYM -12 MIN MAX -15 MIN MAX -20 MIN MAX UNITS NOTES READ CYCLE 12 15 20 ns READ cycle time tRC Address access time tAA 12 15 20 ns Chip enable access time tACE 12 15 20 ns Output hold from address change tOH 2 2 2 ns Chip enable to output in Low-Z tLZCE 2 2 2 ns 7 Chip disable to output in High-Z tHZCE ns 6, 7 ns 4 4 7 0 8 0 9 0 Chip enable to power-up time tPU Chip disable to power-down time tPD 12 15 20 ns Output enable to access time tAOE 6 7 8 ns Output enable to output in Low-Z tLZOE Output disable to output in High-Z tHZOE 0 0 6 0 7 ns 8 ns 6 WRITE CYCLE WRITE cycle time tWC 12 15 20 ns Chip enable to end of write tCW 9 10 12 ns Address valid to end of write tAW 9 10 12 ns Address setup time tAS 0 0 0 ns Address hold from end of write tAH 0 0 0 ns WRITE pulse width tWP 10 12 15 ns Data setup time tDS 7 8 10 ns Data hold time tDH 0 0 0 ns Write disable to output in Low-Z tLZWE 2 2 2 ns 7 Write enable to output in High-Z tHZWE 0 ns 6, 7 AS5C2568 Rev. 2.0 12/00 7 0 7 0 9 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM AS5C2568 Austin Semiconductor, Inc. AC TEST CONDITIONS +5V Input pulse levels....................................................Vss to 3V Input rise and fall times.....................................................5ns Input timing reference level.............................................1.5V Output reference level......................................................1.5V Output load.................................................See figures 1 & 2 480 4. 5. 6. 480 Q 30 pF 255 Q All voltages referenced to VSS (GND). -3V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f= 1 Hz. t RC (MIN) This parameter is guaranteed but not tested. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured ±500mV typical from steady state voltage, allowing for actual tester RC time constant. 5 pF 255 Fig. 2 OUTPUT LOAD EQUIVALENT Fig. 1 OUTPUT LOAD EQUIVALENT NOTES 1. 2. 3. +5V At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle. 7. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION VCC for Retention Data CONDITIONS CE\ > (VCC - 0.2V) VIN > (VCC - 0.2V) or < 0.2V Data Retention Current SYMBOL VDR ICCDR VCC = 2V MIN 2 VCC = 3V t Chip Deselect to Data Retention Time Operation Recovery Time MAX -1.0 UNITS V mA 2.0 mA 0 CDR NOTES ns 4 ns 4, 11 -t R t RC LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE VCC 4.5V VDR > 2V t t CDR CE\ VIH VIL 123 12345678 12 12345678 12 123 12345678 12 123 12345678 12 123 12345678 12 4.5V R V DR 12345678 1234 123 12345678 1234 123 12345678 1234 123 12345678 1234 123 12345678 123 123 123 123 123 DON’T CARE 1234 1234 1234 1234UNDEFINED AS5C2568 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SRAM AS5C2568 Austin Semiconductor, Inc. READ CYCLE NO. 1 8, 9 tRC ADDRESS VALID tAA tOH DQ PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2 7, 8, 10, 12 tRC CE\ tAOE tHZOE tLZOE OE\ tLZCE tACE tHZCE DQ DATA VALID tPU tPD Icc 123 123 123 DON’T CARE 1234 1234 1234 1234 UNDEFINED AS5C2568 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SRAM AS5C2568 Austin Semiconductor, Inc. WRITE CYCLE NO. 1 12 (Chip Enabled Controlled) tWC ADDRESS tAW tAH tAS tCW CE\ tWP1 WE\ tDS D tDH DATA VAILD Q HIGH Z WRITE CYCLE NO. 2 7, 12 (Write Enabled Controlled) tWC ADDRESS tAW tAH tCW CE\ tAS tWP1 WE\ tDH D DATA VALID Q HIGH-Z 123 123 123DON’T CARE 1234 1234 1234 1234 UNDEFINED NOTE: Output enable (OE\) is inactive (HIGH). AS5C2568 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SRAM AS5C2568 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #906 (Package Designator DJ) E1 E1 A A1 R E2 D L e b ASI SPECIFICATIONS SYMBOL A b D E E1 E2 e L MIN --- MAX 0.140 0.018 TYP --0.327 0.295 0.245 0.73 0.347 0.305 0.285 0.050 BSC 0.025 --- * All measurements are in inches. AS5C2568 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM AS5C2568 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS5C2568DJ-15/IT Device Number AS5C2568 AS5C2568 AS5C2568 Package Speed ns Process Type DJ -12 /* DJ -15 /* DJ -20 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing 12ns offered in IT only AS5C2568 Rev. 2.0 12/00 -40oC to +85oC -55oC to +125oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9