DAC7632 DAC 763 2 SBAS234A – FEBRUARY 2002 – REVISED APRIL 2008 www.ti.com 16-Bit, Dual Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● ● ● ● The DAC7632 is a 16-bit, dual channel, voltage output, Digital-to-Analog Converter (DAC) which provides 15-bit monotonic performance over the specified temperature range. The device accepts 24-bit serial input data, has doublebuffered DAC input logic (allowing simultaneous update of both DACs), and provides a serial data output for daisychaining multiple devices. A programmable asynchronous reset clears all registers to a mid-scale code of 8000H or to a zero-scale code of 0000H. The DAC7632 can operate from a single +5V supply or from +5V and –5V supplies, providing an output range of 0V to +2.5V or –2.5V to +2.5V, respectively. LOW POWER: 4mW UNIPOLAR OR BIPOLAR OPERATION SETTLING TIME: 10µs to ±0.003% FSR 15-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● PROGRAMMABLE RESET TO MID-SCALE OR ZERO-SCALE ● DOUBLE-BUFFERED DATA INPUTS APPLICATIONS Low power and small size per DAC make the DAC7632 ideal for industrial process control, data acquisition systems, and closed-loop servo-control. The DAC7632 is available in an LQFP-32 package and specified over a –40°C to +85°C temperature range. ● PROCESS CONTROL ● CLOSED-LOOP SERVO-CONTROL ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS ● DAC-PER-PIN PROGRAMMERS VDD VSS VREFL Sense VCC VREFL VREFH VREFH Sense DAC7632 SDI Shift Register Input Register A DAC Register A DAC A SDO VOUTA VOUTA Sense CS CLK RST RSTSEL Input Register B DAC Register B Control Logic DAC B VOUTB VOUTB Sense LDAC LOAD AGND DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) VCC and VDD to VSS .............................................................. –0.3V to 11V VCC and VDD to GND ........................................................... –0.3V to 5.5V VREFL to VSS ............................................................. –0.3V to (VCC – VSS) VCC to VREFH ............................................................ –0.3V to (VCC – VSS) VREFH to VREFL ......................................................... –0.3V to (VCC – VSS) Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC7632VFT DAC7632VFR Tape and Reel, 250 Tape and Reel, 1000 DAC7632VFB T DAC7632VFB R Tape and Reel, 250 Tape and Reel, 1000 MONOTONICITY PACKAGE-LEAD PACKAGE DESIGNATOR DAC7632VF 14 Bits LQFP-32 VF –40°C to +85°C DAC7632 " " " " " " DAC7632VFB 15 Bits LQFP-32 VF –40°C to +85°C DAC7632B " " " " " " PRODUCT NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 DAC7632 www.ti.com SBAS234A ELECTRICAL CHARACTERISTICS: Dual Supply At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted. DAC7632VF PARAMETER ACCURACY Linearity Error Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Full-Scale Error Drift Bipolar Zero Matching Full-Scale Matching Power-Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS MIN POWER SUPPLY VDD VCC VSS ICC IDD ISS Power TEMPERATURE RANGE Specified Performance MAX ±3 ±4 ±2 ±4 RL = 10kΩ VREFL –1.25 No Oscillation MIN ±3 ±3 10 ±3 10 ±3 ±3 100 VREFH +1.25 VREFL + 1.25 –2.5 +2.5 VREFH – 1.25 8 0.5 2 60 40 f = 10kHz 7FFFH to 8000H or 8000H to 7FFFH UNITS ±2 ±2 ±1 ±3 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ LSB LSB LSB Bits mV ppm/°C mV ppm/°C mV mV ppm/V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10 +4.75 +4.75 –5.25 –1.2 –40 V mA pF mA ✻ ✻ V V µA µA ✻ µs LSB nV-s nV/√Hz nV-s ✻ 0.3 • VDD ±10 ±10 3.6 ✻ ✻ ✻ ✻ 0.7 • VDD IOH = –0.8mA IOL = 1.6mA ±2 ✻ ✻ ✻ 500 –500 To ±0.003%, 5V Output Step MAX ✻ ✻ 500 –10, +30 Indefinite GND or VCC or VSS TYP 15 ±1 5 ±1 5 ±1 ±1 10 Channel-to-Channel Matching Channel-to-Channel Matching At Full Scale DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL TYP 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage DAC Glitch DAC7632VFB 4.5 0.3 +5.0 +5.0 –5.0 0.7 50 –0.8 7.5 ✻ 0.4 +5.25 +5.25 –4.75 1.1 ✻ ✻ ✻ ✻ 11.5 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ ✻ V V V mA µA mA mW ✻ °C ✻ Specifications same as DAC7632VF. DAC7632 SBAS234A www.ti.com 3 ELECTRICAL CHARACTERISTICS: Single Supply At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted. DAC7632VF PARAMETER ACCURACY Linearity Error(1) Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Zero Scale Error Zero Scale Error Drift Full-Scale Error Full-Scale Error Drift Zero Scale Matching Full-Scale Matching Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS MIN POWER SUPPLY VDD VCC VSS ICC IDD Power TEMPERATURE RANGE Specified Performance MAX ±3 ±4 ±2 ±4 RL = 10kΩ 0 –1.25 No Oscillation MIN ±3 ±3 10 ±3 10 ±3 ±3 100 VREFH +1.25 VREFL + 1.25 –2.5 +2.5 VREFH – 1.25 8 0.5 2 60 40 7FFFH to 8000H or 8000H to 7FFFH UNITS ±2 ±2 ±1 ±3 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ LSB LSB LSB Bits mV ppm/°C mV ppm/°C mV mV ppm/V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10 +4.75 +4.75 0 –40 V mA pF mA ✻ ✻ V V µA µA ✻ µs LSB nV-s nV/√Hz nV-s ✻ 0.3 • VDD ±10 ±10 3.6 ✻ ✻ ✻ ✻ 0.7 • VDD IOH = –0.8mA IOL = 1.6mA ±2 ✻ ✻ ✻ 250 –250 To ±0.003%, 5V Output Step MAX ✻ ✻ 500 –10, +30 Indefinite GND or VCC TYP 15 ±1 5 ±1 5 ±1 ±1 10 Channel-to-Channel Matching Channel-to-Channel Matching At Full Scale DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL TYP 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage, f = 10kHz DAC Glitch DAC7632VFB 4.5 0.3 +5.0 +5.0 0 0.5 50 2.5 ✻ 0.4 +5.25 +5.25 0 0.9 ✻ ✻ ✻ 4.5 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ ✻ V V V mA µA mW ✻ °C ✻ Specifications same as DAC7632VF. NOTE: (1) If VSS = 0V, the specification applies to Code 0040H and above due to possible negative zero-scale error. 4 DAC7632 www.ti.com SBAS234A PIN CONFIGURATION 25 VOUTB 26 VOUTB Sense 27 VREFH Sense 28 VREFH 29 VREFL 30 VREFL Sense 31 VOUTA Sense SSOP 32 VOUTA Top View VCC 1 24 VSS AGND 2 23 LOAD AGND 3 22 LDAC NC 4 21 RST DAC7632 CLK NC 16 17 15 8 NC SDO 14 SDI NC 18 13 7 NC VDD 12 CS NC 19 11 6 NC DGND 10 RSTSEL NC 20 9 5 NC DGND NC = No Connection PIN DESCRIPTIONS PIN NAME DESCRIPTION PIN NAME DESCRIPTION Analog +5V Power Supply 22 LDAC DAC Register Load Control, Rising Edge Triggered LOAD DAC Input Register Load Control, Active LOW 1 VCC 2, 3 AGND Analog Ground 4 NC No Connection 23 5, 6 DGND Digital Ground 24 VSS 7 VDD Digital +5V Power Supply 25 VOUTB 8 SDO Serial Data Output 26 VOUTB Sense 9-16 NC No Connection DAC B Output Amplifier Inverting Input. Used to close the feedback loop at the load. 17 CLK Data Clock Input 27 VREFH Sense DAC A and B Reference High Sense Input 18 SDI Serial Data Input 28 VREFH DAC A and B Reference High Input 19 CS Chip Select, Active LOW 29 RSTSEL VREFL DAC A and B Reference Low Input 20 30 VREFL Sense DAC A and B Reference Low Sense Input 31 VREFA Sense DAC A Output Amplifier Inverting Input. Used to close the feedback loop at the load. 32 VOUTA 21 RST Reset Select. Determines the action of RST. If HIGH, a RST common will set the DAC registers to mid-scale code (8000H). If LOW, a RST command will set the DAC registers to zero-scale code (0000H). Reset, Rising Edge Triggered. Depending on the state of RSTSEL, the DAC registers are set to either mid-scale code or zero-scale code. DAC7632 SBAS234A www.ti.com Analog –5V Power Supply (or 0V for Single Supply) DAC B Output Voltage DAC A Output Voltage 5 TYPICAL CHARACTERISTICS: VSS = 0V At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH LE (LSB) Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 6 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Digital Input Code LE (LSB) LE (LSB) DLE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –40°C LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 +85°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) DLE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7632 www.ti.com SBAS234A TYPICAL CHARACTERISTICS: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 3 3 Code (0040H) Code (FFFFH) 2 Full-Scale Error (mV) Zero-Scale Error (mV) 2 1 DAC B 0 –1 DAC A DAC B 0 –1 DAC A –2 –2 –3 –3 –40 –15 10 35 60 –40 85 –15 35 Temperature (°C) VREFH CURRENT vs CODE (all DACs sent to indicated code) VREFL CURRENT vs CODE (all DACs sent to indicated code) 0.30 0.00 0.25 –0.05 0.20 0.15 0.10 60 85 –0.10 –0.15 –0.20 0.05 –0.25 0.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –0.30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code ANALOG SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE 1 1.0 Data = FFFFH (all DACs) No Load No Load 0.8 0.8 0.6 0.6 ICC (mA) ICC (mA) 10 Temperature (°C) VREF Current (mA) VREF Current (mA) 1 0.4 0.2 All DACs 0.4 0.2 0 –40 –15 10 35 60 0.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 85 Temperature (°C) Digital Input Code DAC7632 SBAS234A www.ti.com 7 TYPICAL CHARACTERISTICS: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to 2mV) OUTPUT VOLTAGE vs SETTLING TIME (0V to +2.5V) +5V LDAC 0 Small-Signal Settling Time: 500µV/div Output Voltage Output Voltage Large-Signal Settling Time: 1V/div Small-Signal Settling Time: 500µV/div Large-Signal Settling Time: 1V/div +5V LDAC 0 Time (2µs/div) Time (2µs/div) OUTPUT VOLTAGE vs MID-SCALE GLITCH PERFORMANCE OUTPUT VOLTAGE vs MID-SCALE GLITCH PERFORMANCE +5V LDAC 0 Output Voltage (20mV/div) Output Voltage (20mV/div) +5V LDAC 0 7FFFH to 8000H 8000H to 7FFFH Time (1µs/div) Time (1µs/div) BROADBAND NOISE OUTPUT NOISE VOLTAGE vs FREQUENCY Noise (nV/√Hz) Noise Voltage (50µV/div) 1000 100 BW = 10kHz Code = 8000H 10 Time (10µs/div) 10 100 1000 10000 100000 1000000 Frequency (Hz) 8 DAC7632 www.ti.com SBAS234A TYPICAL CHARACTERISTICS: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LOGIC SUPPLY CURRENT vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS VOUT vs RLOAD 5 Typical of One Digital Input 0.40 4 0.30 3 VOUT (V) Logic Supply Current (mA) 0.50 0.20 Source 2 0.10 1 0.00 0 0.01 0 1 2 3 4 5 Logic Input Level for Digital Inputs (V) Sink 0.1 1 10 100 RLOAD (kΩ) VSS = –5V At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) +85°C Digital Input Code 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7632 SBAS234A 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 www.ti.com 9 TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 LE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code VREFH CURRENT vs CODE (all DACs sent to indicated code) VREFL CURRENT vs CODE (all DACs sent to indicated code) +0.6 0.0 +0.5 –0.1 VREF Current (mA) VREF Current (mA) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) DLE (LSB) –40°C +0.4 +0.3 +0.2 +0.1 –0.2 –0.3 –0.4 –0.5 0.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –0.6 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code BIPOLAR ZERO ERROR vs TEMPERATURE POSITIVE FULL-SCALE ERROR vs TEMPERATURE 3 3 Code (FFFFH) Positive Full-Scale Error (mV) Code (8000H) Bipolar Zero Error (mV) 2 1 DAC B 0 –1 DAC A –2 1 DAC B 0 –1 DAC A –2 –3 –3 –40 –15 10 35 60 –40 85 –15 10 35 60 85 Temperature (°C) Temperature (°C) 10 2 DAC7632 www.ti.com SBAS234A TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. NEGATIVE FULL-SCALE ERROR vs TEMPERATURE ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE 3 1.00 Analog Supply Current (mA) Negative Full-Scale Error (mV) Code (0000H) 2 1 DAC B 0 –1 DAC A –2 No Load ICC 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 ISS –1.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –3 –40 –15 10 35 60 85 Temperature (°C) Digital Input Code VOUT vs RLOAD ANALOG SUPPLY CURRENT vs TEMPERATURE 1 5 ICC Analog Supply Current (mA) 4 Source 3 VOUT (V) 2 1 0 –1 Sink –2 –3 0.5 0 –0.5 ISS –1 Data = FFFFH (all DACs) No Load –4 –5 0.01 –1.5 0.1 1 10 –40 100 –15 10 35 60 RLOAD (kΩ) Temperature (°C) OUTPUT VOLTAGE vs SETTLING TIME (–2.5V to +2.5V) OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to –2.5V) 85 +5V LDAC 0 Output Voltage Output Voltage Large-Signal Settling Time: 2V/div Small-Signal Settling Time: 500µV/div Small-Signal Settling Time: 500µV/div Large-Signal Settling Time: 2V/div +5V LDAC 0 Time (2µs/div) Time (2µs/div) DAC7632 SBAS234A www.ti.com 11 TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs MID-SCALE GLITCH PERFORMANCE Output Voltage (50mV/div) Output Voltage (50mV/div) OUTPUT VOLTAGE vs MID-SCALE GLITCH PERFORMANCE 7FFFH to 8000H 8000H to 7FFFH +5V LDAC 0 +5V LDAC 0 Time (1µs/div) Time (1µs/div) THEORY OF OPERATION The digital input is a 24-bit serial word that contains an address bit for selecting one of two DACs, a quick load bit, six unused bits, and the 16-bit DAC code (MSB first). The converters can be powered from either a single +5V supply or a dual ±5V supply. The device offers a reset function which immediately sets all DAC output voltages, DAC registers and input registers to mid-scale (code 8000H) or to zeroscale (code 0000H), depending on the state of RSTSEL. See Figures 2 and 3 for the basic configurations of the DAC7632. The DAC7632 is a dual channel, voltage output, 16-bit DAC. The architecture is an R-2R ladder configuration with the three MSB’s segmented, followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network, segmented MSBs, and output op amp, as shown in Figure 1. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references VREFL and VREFH, respectively. RF VOUT Sense VOUT R 2R 2R 2R 2R 2R 2R 2R 2R 2R VREFH VREFH Sense VREFL VREFL Sense FIGURE 1. DAC7632 Architecture. 12 DAC7632 www.ti.com SBAS234A 0V to +2.5V 32 +2.5V 31 1 +5V 1µF 0.1µF 2 3 4 5 1µF 0.1µF 6 7 +5V 8 30 29 VREFL Sense VOUTA 28 0V to +2.5V 27 VOUTA Sense 26 VREFH Sense VREFL 25 VOUTB Sense VREFH VOUTB VCC VSS AGND LOAD AGND LDAC DAC7632 NC RST DGND RSTSEL DGND CS VDD SDI CLK SDO 24 23 LOAD INPUT REGISTER(S) 22 LOAD DAC REGISTERS 21 RESET INPUT AND DAC REGISTERS 20 19 CHIP SELECT 18 SERIAL DATA IN 17 CLOCK NC NC NC NC NC NC NC NC 9 10 11 12 13 14 15 16 NC = No Connection FIGURE 2. Basic Single-Supply Operation of the DAC7632. –2.5V to +2.5V 32 –2.5V 31 1 +5V 2 1µF 0.1µF 3 4 5 6 1µF 0.1µF 7 +5V 8 NC = No Connection. 30 29 VOUTA Sense 28 27 VREFH VREFL Sense VOUTA –2.5V to +2.5V +2.5V VREFH Sense VREFL 26 25 VOUTB Sense VOUTB 1µF VSS VCC AGND LOAD AGND LDAC DAC7632 NC DGND RST RSTSEL DGND CS VDD SDI CLK SDO 0.1µF 24 –5V 23 22 21 LOAD INPUT REGISTER(S) LOAD DAC REGISTERS RESET INPUT AND DAC REGISTERS 20 +5V 19 18 17 CHIP SELECT SERIAL DATA IN CLOCK NC NC NC NC NC NC NC NC 9 10 11 12 13 14 15 16 FIGURE 3. Basic Dual-Supply Operation of the DAC7632. DAC7632 SBAS234A www.ti.com 13 ANALOG OUTPUTS When VSS = –5V (dual-supply operation), the output amplifier can swing to within 2.25V of the supply rails over the –40°C to +85°C temperature range. When VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error when VSS = 0V. Since the output cannot swing below ground, the output voltage may not change for the first few digital input codes (0000H, 0001H, 0002H, etc.) if the output amplifier has a negative offset. At the negative limit of –2mV, the first specified output starts at code 0040H. Due to the high accuracy of these DACs, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 2.5V full-scale range has a 1LSB value of 38µV. With a load current of 1mA, series wiring and connector resistance of only 40mΩ (RW2) will cause a voltage drop of 40µV, as shown in Figure 4. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2mΩ per square. For a 1mA load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30µV. The DAC7632 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load, as shown in Figure 4, thus ensuring an accurate output voltage. REFERENCE INPUTS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.5V and VCC – 2.5V, provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note RW2 DAC7632 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 RW1 VOUT +V +2.5V RW1 VOUT RW2 FIGURE 4. Analog Output Closed-Loop Configuration RW represents wiring resistances. that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device may be affected. The current into the VREFH input and out of VREFL depends on the DAC output voltages, and can vary from a few microamps to approximately 0.5mA. The reference input appears as a varying load to the reference supply. If the reference applied can sink or source the required current, a reference buffer is not required. The DAC7632 features reference drive and sense connections such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 13 show different reference configurations and the effect on the integral linearity and differential linearity, for each case. +V DAC7632 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 OPA2234 VOUT 100Ω –2.5V 2200pF 1000pF –V +V 1000pF 100Ω +2.5V 2200pF VOUT –V FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual-Supply Performance. 14 DAC7632 www.ti.com SBAS234A +V DAC7632 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 OPA2350 VOUT 100Ω 27 VOUTB Sense 26 VOUTB 25 2kΩ 1000pF +0.050V 98kΩ +V 100Ω 1000pF VREFH Sense 2200pF +2.5V 2200pF VOUT FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 7. Integral Linearity and Differential Linearity Error Characteristic Curves for Figure 6. FIGURE 8. Integral Linearity and Differential Linearity Error Characteristic Curves for Figure 9. +V +V DAC7632 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 OPA2350 VOUT 100Ω 1000pF +V 1000pF VREFH Sense 27 VOUTB Sense 26 VOUTB 25 +1.25V 2200pF 100Ω 2200pF +2.5V VOUT FIGURE 9. Single-Supply Buffered Reference with VREFL = +1.25V and VREFH = +2.5V. DAC7632 SBAS234A www.ti.com 15 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 DAC7632 VOUT +V OPA2350 +V 100Ω 1000pF VREFH Sense 27 VOUTB Sense 26 VOUTB 25 +2.5V 2200pF VOUT FIGURE 10. Single-Supply Buffered VREFH. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 11. Linearity and Differential Linearity Error Characteristic Curves for Figure 10. FIGURE 13. Linearity and Differential Linearity Error Characteristic Curves for Figure 12. DIGITAL INTERFACE DAC7632 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 VOUT +V +2.5V VOUT FIGURE 12. Low-Cost Single-Supply Configuration. 16 See Table I for the basic control logic for the DAC7632. The interface consists of a Serial Data Clock (CLK) input, Serial Data Input (SDI), Input Register Load Control Signal (LOAD), and DAC Register Load Control Signal (LDAC). In addition, a Chip Select (CS ) input is available to enable serial communication when there are multiple serial devices attached to a single serial bus. An asynchronous Reset (RST) input (rising edge triggered) is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the Reset Select (RSTSEL) signal. The DAC code, quick load control, and address are provided via a 24-bit serial interface (see Figure 15). The first bit (DACSEL) selects the input register that will be updated when LOAD goes LOW. The third bit is a “Quick Load” bit such that if HIGH, the code in the shift register is loaded into both input registers when the LOAD signal goes LOW. If the “Quick Load” bit is LOW when an active LOAD signal is issued, the content of the shift register is loaded only to the input register that is addressed by DACSEL. The “Quick Load” bit is followed by five unused bits. The last 16 bits (MSB first) make up the DAC code. DAC7632 www.ti.com SBAS234A SERIAL DATA INPUT B23 DACSEL B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X QUICK LOAD X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DACSEL CS RST RSTSEL LDAC LOAD INPUT REGISTER DAC REGISTER MODE DAC 0 1 X X X X L L H H X X H H H H ↑ ↑ X X X X L H X X ↑ H X X L L H H X X Write Write Hold Hold Reset to 0000H Reset to 8000H Hold Hold Write Hold Reset to 0000H Reset to 8000H Write Input Write Input Update Hold Reset to Zero-Scale Reset to Mid-scale A B All All All All TABLE I. DAC7632 Logic Truth Table. Data presented to SDI is clocked into the shift register on each rising CLK edge. This data is latched into the input register(s) via a logic-low level on LOAD. The data is directed from the shift register to the desired input register(s) specified by data bits 21 and 23. The internal DAC registers are edge triggered and not level triggered. When the LDAC signal is transitioned from LOW to HIGH, the digital word currently in the input registers are latched. This double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. When the new data has been entered into the device, both DAC outputs can be updated simultaneously by the rising edge of LDAC. Additionally, it allows the input registers to be written to at any point, then the DAC output voltages can be synchronously changed via a trigger signal (LDAC). Note that CS and CLK are combined with an OR gate, which controls the serial-to-parallel shift register. These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong input register(s). If both CS and CLK are used, CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register (the remaining pin should be tied to DGND). Please refer to Table II for more information. DAC7632 SCK CLK DIN SDI CS CS CS(1) CLK(1) H(2) X(3) H H No Change L(4) L H H No Change SERIAL SHIFT REGISTER L ↑(5) H H Advanced One Bit L H H Advanced One Bit H(6) X L(7) H No Change H(6) X H ↑(8) No Change NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW. (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOAD is LOW, the input registers will change as data flows through the shift register. This will corrupt the data in each DAC register that has been erroneously selected. (8) Rising edge of RST causes no change in the contents of the serial shift register. TABLE II. Serial Shift Register Truth Table. SERIAL-DATA OUTPUT The Serial-Data Output pin (SDO) is the internal shift register’s output. For the DAC7632, SDO is a driven output and does not require an external pull-up. Any number of DAC7632s can be daisy-chained by connecting the SDO pin of one device to the SDI pin of the following device in the chain, as shown in Figure 14. DAC7632 SDI RST ↑ CLK SDO LOAD DAC7632 CLK SDO CS SDI CS SDO To Other Serial Devices FIGURE 14. Daisy-Chaining Multiple DAC7632s. DAC7632 SBAS234A www.ti.com 17 DIGITAL TIMING DIGITALLY-PROGRAMMABLE CURRENT SOURCE Figure 15 and Table III provide detailed timing for the digital interface of the DAC7632. The DAC7632 offers a unique set of features that allows a wide range of flexibility in designing application circuits such as programmable current sources. The DAC7632 offers both a differential reference input, as well as an open-loop configuration around the output amplifier. The open-loop configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitally-programmable, unidirectional current source. The availability of a differential reference allows programmability for both the fullscale and zero-scale currents. The output current is calculated as: DIGITAL INPUT CODING The DAC7632 input data is in Straight Binary format. The output voltage is given by Equation 1. VOUT = VREFL + (VREFH – VREFL) • N 65, 536 where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. V H – VREFL N IOUT = REF • 65, 536 R SENSE + (VREFL / R SENSE ) (LSB) (MSB) SDI X DACSEL QUICK LOAD X X X X X D15 D1 D0 CLK tcss tCSH tLD1 tLD2 CS tLDDD LOAD tLDRW LDAC tDS tDH SDI tSDO tCL tCH CLK SDO tLDDL tLDDH LDAC tS VOUT tS ±0.003% FSR ERROR BAND tRSTL ±0.003% FSR ERROR BAND tRSTH RST tRSSH tRSSS RSTSEL FIGURE 15. Digital Input and Output Timing. 18 DAC7632 www.ti.com SBAS234A SYMBOL DESCRIPTION MIN tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 Data Valid to CLK Rising Data Held Valid after CLK Rises CLK HIGH CLK LOW CS LOW to CLK Rising CLK HIGH to CS Rising LOAD HIGH to CLK Rising CLK Rising to LOAD LOW LOAD LOW Time LDAC LOW Time LDAC HIGH Time LOAD LOW to LDAC Rising RESETSEL Valid to RESET HIGH RESET HIGH to RESETSEL Not Valid RESET LOW Time RESET HIGH Time SDO Propagation Delay Settling Time 10 20 25 25 15 0 10 30 30 100 100 40 0 100 10 10 10 tLDRW tLDDL tLDDH tLDDD tRSSS tRSSH tRSTL tRSTH tSDO tS MAX UNITS 30 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs TABLE III. Timing Specifications (TA = –40°C to +85°C). Figure 16 shows a DAC7632 in a 4-20mA current output configuration. The output current can be determined by Equation 3: At full-scale, the output current is 16mA, plus the 4mA, for the zero current. At zero scale the output current is the offset current of 4mA (0.5V/125Ω). 2.5V – 0.5V N 0.5V IOUT = + • 65, 536 125Ω 125Ω IOUT VPROGRAMMED 125Ω DAC7632 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 OPA2350 100Ω 27 VOUTB Sense 26 VOUTB 25 2200pF 20kΩ 1000pF 80kΩ 100Ω 1000pF VREFH Sense +V 2200pF +V +2.5V IOUT VPROGRAMMED 125Ω FIGURE 16. 4-20mA Digitally-Controlled Current Source. DAC7632 SBAS234A www.ti.com 19 Revision History DATE 4/08 REVISION A PAGE SECTION — Entire Data Sheet 4 Electrical Characteristics 13 Figures 2, 3 DESCRIPTION Updated document format. Changed section title from "Dual Supply" to "Single Supply" (typo). Updated text in figures to correct names (typo). NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 20 DAC7632 www.ti.com SBAS234A PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DAC7632VFBT ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC7632 B DAC7632VFBTG4 ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC7632 B DAC7632VFR ACTIVE LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC7632 DAC7632VFRG4 ACTIVE LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC7632 DAC7632VFT ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC7632 DAC7632VFTG4 ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC7632 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7632VFBT LQFP VF 32 250 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 DAC7632VFR LQFP VF 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 DAC7632VFT LQFP VF 32 250 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7632VFBT LQFP VF DAC7632VFR LQFP VF 32 250 367.0 367.0 38.0 32 1000 367.0 367.0 38.0 DAC7632VFT LQFP VF 32 250 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MTQF002B – JANUARY 1995 – REVISED MAY 2000 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,05 MIN 0,25 0°– 7° 1,45 1,35 Seating Plane 0,75 0,45 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated