INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4522B MSI Programmable 4-bit BCD down counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Programmable 4-bit BCD down counter Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except MR, which must be LOW. When PL and CP1 are LOW, the counter advances on a LOW to HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in the zero state (O0 = O1 = O2 = O3 = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of other input conditions. DESCRIPTION The HEF4522B is a synchronous programmable 4-bit BCD down counter with an active HIGH and an active LOW clock input (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (P0 to P3), a cascade feedback input (CF), four buffered parallel outputs (O0 to O3), a terminal count output (TC) and an overriding asynchronous master reset input (MR). This device is a programmable, cascadable down counter with a decoded TC output for divide-by-n applications. In single stage applications the TC output is connected to PL. CF allows cascade divide-by-n operation with no additional gates required. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 HEF4522B MSI 2 Philips Semiconductors Product specification HEF4522B MSI Programmable 4-bit BCD down counter HEF4522BP(N): 16-lead DIL; plastic HEF4522BD(F): 16-lead DIL; ceramic (cerdip) (SOT38-1) (SOT74) HEF4522BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. PINNING PL parallel load input P0 to P3 parallel inputs CF cascade feedback input CP0 clock input (LOW to HIGH, triggered) CP1 clock input (HIGH to LOW, triggered) MR asynchronous master reset input TC terminal count output O0 to O3 buffered parallel outputs FUNCTION TABLE COUNTING MODE CF = HIGH; PL = LOW; MR = LOW OUTPUTS COUNT MR PL CP0 CP1 MODE O3 O2 O1 O0 H X X X reset (asynchronous) 9 H L L H L H X X preset (asynchronous) 8 H L L L L L H no change 7 L H H H L L 6 L H H L L L 5 L H L H L L 4 L H L L L L 3 L L H H L L 2 L L H L 1 L L L H Notes 0 L L L L 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition January 1995 3 L no change X X no change L H no change counter advances counter advances Philips Semiconductors Product specification HEF4522B MSI Programmable 4-bit BCD down counter SINGLE STAGE OPERATION Divide-by-n; MR = LOW; CF = HIGH; CP1 = LOW PL P3 P2 P1 P0 DIVIDE BY TC OUTPUT PULSE WIDTH L X X X X 10 one clock period TC H H H H 15 TC H H H L 14 TC H H L H 13 TC H H L L 12 TC H L H H 11 TC H L H L 10 TC H L L H 9 TC H L L L 8 TC L H H H 7 TC L H H L 6 TC L H L H 5 TC L H L L 4 TC L L H H 3 TC L L H L 2 TC L L L H 1 TC L L L L clock pulse HIGH no operation Fig.3 State diagram. January 1995 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 5 Programmable 4-bit BCD down counter January 1995 Product specification HEF4522B MSI Fig.4 Logic diagram. Philips Semiconductors Product specification HEF4522B MSI Programmable 4-bit BCD down counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power TYPICAL FORMULA FOR P (µW) 5 1000 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 4000 fi + ∑ (foCL) × package (P) 15 10 000 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 150 300 ns 123 ns + (0,55 ns/pF) CL 65 130 ns 54 ns + (0,23 ns/pF) CL Propagation delays CP0, CP1 → On HIGH to LOW LOW to HIGH CP0, CP1 → TC HIGH to LOW LOW to HIGH PL → On HIGH to LOW 5 10 tPHL 15 50 100 ns 42 ns + (0,16 ns/pF) CL 5 150 300 ns 123 ns + (0,55 ns/pF) CL 65 130 ns 54 ns + (0,23 ns/pF) CL 15 50 100 ns 42 ns + (0,16 ns/pF) CL 5 210 420 ns 183 ns + (0,55 ns/pF) CL 90 180 ns 79 ns + (0,23 ns/pF) CL 10 10 tPLH tPHL 15 70 140 ns 62 ns + (0,16 ns/pF) CL 5 210 420 ns 183 ns + (0,55 ns/pF) CL 90 180 ns 79 ns + (0,23 ns/pF) CL 10 tPLH 15 70 140 ns 62 ns + (0,16 ns/pF) CL 5 200 400 ns 173 ns + (0,55 ns/pF) CL 80 160 ns 69 ns + (0,23 ns/pF) CL 60 120 ns 52 ns + (0,16 ns/pF) CL 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 MR → On HIGH to LOW 5 10 tPHL 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 January 1995 6 180 360 ns 153 ns + (0,55 ns/pF) CL 70 140 ns 59 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 140 280 ns 113 ns + (0,55 ns/pF) CL 55 110 ns 44 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 10 ns + 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL (1,0 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL Philips Semiconductors Product specification HEF4522B MSI Programmable 4-bit BCD down counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Minimum clock SYMBOL 5 TYP. MAX. 80 40 ns pulse width; CP0 10 40 20 ns LOW 15 30 15 ns 5 80 40 ns Minimum clock tWCPL MIN. pulse width; CP1 10 40 20 ns HIGH 15 30 15 ns 5 100 50 ns Minimum PL pulse width; HIGH Minimum MR pulse width; HIGH Hold time Pn → PL 10 tWCPH tWPLH 40 20 ns 15 32 16 ns 5 130 65 ns 10 tWMRH 50 25 ns 15 40 20 ns 5 30 5 ns 20 5 ns 15 15 5 ns Set-up time 5 30 0 ns Pn → PL 10 20 0 ns ns Maximum clock 10 thold tsu 15 15 0 5 6 12 MHz 12 25 MHz 16 32 MHz pulse frequency 10 PL = LOW 15 fmax see also waveforms Figs 5 and 6 see note 1 Note 1. In the divide-by-n mode (PL connected to TC), one has to observe the maximum HIGH to LOW propagation delay for CP to TC, before applying the next clock pulse. January 1995 7 Philips Semiconductors Product specification Programmable 4-bit BCD down counter Fig.5 Fig.6 HEF4522B MSI Waveforms showing minimum PL pulse width, propagation delays for PL, Pn to On and hold time for PL to Pn. Waveforms showing minimum CP0 and CP1 pulse widths, propagation delays for CP0, CP1 to On and TC. January 1995 8 Philips Semiconductors Product specification Programmable 4-bit BCD down counter HEF4522B MSI APPLICATION INFORMATION Some examples of applications for the HEF4522B are: • Divide-by-n counter • Programmable frequency divider Counting cycle: Fig.7 Typical application of two HEF4522B circuits in a 2-stage programmable down counter (one cycle). S are thumbwheel switches; when open: LOW state. January 1995 9 Philips Semiconductors Product specification Programmable 4-bit BCD down counter HEF4522B MSI Counting cycle: Fig.8 Typical application of two HEF4522B circuits in a 2-stage programmable frequency divider. S are thumbwheel switches; when open: LOW state. January 1995 10