Mitel MT88L89AE 3v integrated dtmftransceiver with adaptive micro interface Datasheet

MT88L89

3V Integrated DTMF Transceiver
Advance Information with Adaptive Micro Interface
Features
ISSUE 1
•
Central office quality DTMF transmitter/
receiver
•
Low voltage operation (2.7-3.6V)
•
Adjustable guard time
•
Automatic tone burst mode
•
Call progress tone detection to -30dBm
•
Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs
•
DTMF transmitter/receiver power down via
register control
Ordering Information
MT88L89AE
20 Pin Plastic DIP
MT88L89AC
20 Pin Ceramic DIP
MT88L89AS
20 Pin SOIC
MT88L89AN
24 Pin SSOP
MT88L89AP
28 Pin PLCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
Applications
•
Credit card systems
•
Paging systems
•
Repeater systems/mobile radio
•
Interconnect dialers
•
Personal computers
Description
The MT88L89 is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
∑
TONE
Tone Burst
Gating Cct.
IN+
+
IN-
-
Row and
Column
Counters
D/A
Converters
Dial
Tone
Filter
GS
OSC1
OSC2
Low Group
Filter
Oscillator
Circuit
Control
Logic
Bias
Circuit
VDD VRef
VSS
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features.
The transmitter and receiver may
independently be powered down via register control.
Transmit Data
Register
Status
Register
Control
Logic
High Group
Filter
May 1995
Data
Bus
Buffer
D0
D1
D2
D3
Interrupt
Logic
IRQ/CP
Digital
Algorithm
and Code
Converter
Steering
Logic
ESt
Control
Register
A
Control
Register
B
Receive Data
Register
DS/RD
I/O
Control
CS
R/W/WR
RS0
St/GT
Figure 1 - Functional Block Diagram
4-125
MT88L89
1
2
3
4
5
6
7
8
9
10
11
12
20 PIN CERDIP/PLASTIC DIP/SOIC
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
24 PIN SSOP
4
3
2
1
28
27
26
IN+
INGS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
•
12
13
14
15
16
17
18
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
TONE
R/W
CS
RS0
NC
DS/RD
IRQ/CP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
IN+
INGS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
GS
NC
ININ+
VDD
St/GT
EST
Advance Information
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20
24
28
1
1
1
IN+
Non-inverting op-amp input.
2
2
2
IN-
Inverting op-amp input.
3
3
4
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
4
6
VRef
Reference Voltage output (VDD/2).
5
5
7
VSS
Ground (0V).
6
6
8
OSC1
Oscillator input. This pin can also be driven directly by an external clock.
7
7
9
OSC2
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
8
10
12
TONE
Output from internal DTMF transmitter.
9
11
13
R/W
(WR)
(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
10
12
14
CS
Chip Select input. This signal must be qualified externally by either address strobe
(AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
11
13
15
RS0
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12
14
17
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is
only required when the device is being accessed. TTL compatible.
13
15
18
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input signal
applied at the input op-amp. The input signal must be within the bandwidth limits of the
call progress filter, see Figure 8.
14- 18- 1917 21 22
D0-D3
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
18
22
26
ESt
Early Steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.
19
23
27
St/GT
Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected
at St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage
on St.
4-126
MT88L89
Advance Information
Pin Description
Pin #
Name
Description
20
24
28
20
24
28
VDD
Positive power supply (3V typ.).
8,9
16,
17
3,5,
10-11
16
2325
NC
No Connection.
Functional Description
Receiver Section
The MT88L89 Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an
internal gain setting amplifier and a DTMF generator,
which employs a burst counter to synthesize precise
tone bursts and pauses. A call progress mode can
be selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows microcontrollers, such as the
68HC11, 80C51 and TMS370C50, to access the
MT88L89 internal registers.
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). The filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
Power Down
The MT88L89 provides enhanced power down
functionality to facilitate minimization of supply
current consumption. DTMF transmitter and receiver
circuit blocks may be independently powered down
via register control. When asserted, RxEN control
bit powers down all analog and digital circuitry
associated solely with the DTMF and Call Progress
receiver. The TOUT control bit is used to disable the
transmitter and put all circuitry associated only with
the DTMF transmitter in power down mode. With the
TOUT control bit asserted, the TONE output pin is
held in a high impedance (floating) state. When both
power down control bits are asserted, circuits utilized
by both the DTMF transmitter and receiver are also
powered down. This includes the crystal oscillators,
and the V Ref generator. In addition, the IRQ , TONE
output and DATA pins are held in a high impedance
state.
Input Configuration
The input arrangement of the MT88L89 provides a
differential-input operational amplifier as well as a
bias source (VRef), which is used to bias the inputs at
VDD/2. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for gain
adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
MT88L89
IN+
C
IN-
RIN
RF
VOLTAGE GAIN
(AV) = RF / RIN
GS
VRef
Figure 3 - Single-Ended Input Configuration
MT88L89
C1
IN+
R1
INC2
R4
R5
GS
R3
R2
VRef
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
INPUT IMPEDANCE
(AV diff) - R5/R1
(Z diff) = 2 R12 + (1/ωC)2
IN
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 4 - Differential Input Configuration
4-127
MT88L89
FLOW
FHIGH
DIGIT
D3
D2
D1
D0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes vc (see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t GTP), v c reaches the threshold
4-128
(VTSt) of the steering logic to register the tone pair,
latching 62its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives vc to VDD . GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
VDD
MT88L89
C1
VDD
Vc
St/GT
ESt
R1
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
t REC ≥ t DPmax + t GTPmax - t DAmin
t REC ≤ t DPmin + t GTPmin - t DAmax
t ID ≥ t DAmax + t GTAmax - t DPmin
t DO ≤ t DAmin + t GTAmin - t DPmax
The value of t DP is a device parameter (see AC
Electrical Characteristics) and tREC is the minimum
MT88L89
Advance Information
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
VDD
C1
St/GT
R1
Increasing tREC improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t REC with a long t DO would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
R2
ESt
a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
tGTA = (RpC1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
VDD
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (tGTP) and
tone absent (t GTA) guard times. This may be
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.
C1
St/GT
Call Progress Filter
R1
R2
A call progress mode, using the MT88L89, can be
selected allowing the detection of various tones,
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
ESt
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
EVENTS
A
B
C
tREC
tREC
D
TONE
#n + 1
TONE
#n + 1
tDA
tDP
ESt
F
tDO
tID
TONE #n
Vin
E
tGTP
tGTA
V TSt
St/GT
tPStRX
RX0-RX3
DECODED TONE # (n-1)
#n
# (n + 1)
tPStb3
b3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
4-129
MT88L89
Advance Information
EXPLANATION OF EVENTS
A)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
B)
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
C)
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E)
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
F)
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
DTMF COMPOSITE INPUT SIGNAL.
Vin
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX0 -RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
b2
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
IRQ/CP
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
tREC
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
tID
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
tDO
TIME TO DETECT VALID FREQUENCIES PRESENT.
tDP
TIME TO DETECT VALID FREQUENCIES ABSENT.
tDA
GUARD TIME, TONE PRESENT.
tGTP
GUARD TIME, TONE ABSENT.
tGTA
Figure 9 - Description of Timing Events
DTMF signals cannot be detected if CP mode has
been selected (see Table 7). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hardlimited by a high gain comparator with the IRQ/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
a microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ/CP
pin will remain low.
the transmit Data Register.
Note that this is the
same as the receiver output code. The individual
tones which are generated (fLOW and fHIGH) are
referred to as Low Group and High Group tones. As
seen from the table, the low group frequencies are
697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz.
Typically, the high group to low group amplitude ratio
(twist) is 2 dB to com-pensate for high group
attenuation on long loops.
LEVEL
(dBm)
DTMF Generator
The DTMF transmitter employed in the MT88L89 is
capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding format shown in Table 1 must be written to
4-130
AAAA
AAAAAAAA
AA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAAAAAAAAAAAA
-25
0
250
= Reject
500
750
FREQUENCY (Hz)
= May Accept
AAAA
AAAA
AA
AAAA
AAAA
AA
= Accept
AAAA
AAAAAA
AA
AAAAAAAA
Figure 8 - Call Progress Response
MT88L89
Advance Information
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length,
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
of time segments is fixed at 32, however, by varying
the segment length as described above the
frequency can also be varied. The divider output
clocks another counter, which addresses the
sinewave lookup ROM.
The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones, which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
burst accuracy. A bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 6
that the distortion products are very low in amplitude.
application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst Mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms±1 ms which is a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register
indicating that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, the burst/pause
duration is doubled to 102 ms ±2 ms. Note that when
CP mode and Burst mode have been selected,
DTMF tones may be transmitted only and not
received. In applications where a non-standard
burst/pause time is desirable, a software timing loop
or external timer can be used to provide the timing
pulses when the burst mode is disabled by enabling
and disabling the transmitter.
Single Tone Generation
A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B description for details.
Burst Mode
In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular
4-131
MT88L89
ACTIVE
INPUT
OUTPUT FREQUENCY (Hz)
DTMF Clock Circuit
%ERROR
SPECIFIED
ACTUAL
L1
697
699.1
+0.30
L2
770
766.2
-0.49
L3
852
847.4
-0.54
L4
941
948.0
+0.74
H1
1209
1215.9
+0.57
H2
1336
1331.7
-0.32
H3
1477
1471.9
-0.35
H4
1633
1645.0
+0.73
The internal clock circuit is completed with the
addition of a standard television colour burst crystal
having a resonant frequency of 3.579545 MHz. A
number of MT88L89 devices can be connected as
shown in Figure 11 such that only one crystal is
required. Alternatively, the OSC1 inputs on all
devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.
MT88L89
Table 2. Actual Frequencies Versus Standard
Requirements
OSC1
OSC2
MT88L89
OSC1
OSC2
MT88L89
OSC1
OSC2
Distortion Calculations
The MT88L89 is capable of producing precise tone
bursts with minimal error in frequency (see Table 2).
The internal summing amplifier is followed by a firstorder lowpass switched capacitor filter to minimize
harmonic components and intermodulation products.
The total harmonic distortion for a single tone can be
calculated using Equation 1, which is the ratio of the
total power of all the extraneous frequencies to the
power of the fundamental frequency expressed as a
percentage.
3.579545 MHz
Figure 11 - Common Crystal Connection
Microprocessor Interface
The MT88L89 design incorporates an adaptive
interface, which allows it to be connected to various
kinds of microprocessors. Key functions of this
interface include the following:
•
Continuous activity on DS/RD is not necessary
to update the internal status registers.
•
senses whether input timing is that of an Intel or
Motorola controller by monitoring the DS (RD),
R/W (WR) and CS inputs.
•
generates equivalent CS signal for internal
operation for all processors.
•
differentiates between multiplexed and nonmultiplexed microprocessor buses. Address
and data are latched in accordingly.
•
compatible with Motorola and Intel processors.
V22f + V23f + V24f + .... V2nf
THD (%) = 100
Vfundamental
Equation 1. THD (%) For a Single Tone
The Fourier components of the tone output
correspond to V 2f.... V nf as measured on the output
waveform. The total harmonic distortion for a dual
tone can be calculated using Equation 2. VL and V H
correspond to the low group amplitude and high
group amplitude, respectively and V 2IMD is the sum
of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.
V22L + V23L + .... V2nL + V22H +
V23H + .. V2nH + V2IMD
THD (%) = 100
V2L + V2H
Equation 2. THD (%) For a Dual Tone
4-132
Figure 16 shows the timing diagram for Motorola
microprocessors with separate address and data
buses. Members of this microprocessor family
include 2 MHz versions of the MC6800, MC6802 and
MC6809. For the MC6809, the chip select (CS) input
signal is formed by NANDing the (E+Q) clocks and
address decode output. For the MC6800 and
MC6802, CS is formed by NANDing VMA and
address decode output. On the falling edge of CS,
the internal logic senses the state of data strobe
MT88L89
Advance Information
(DS). When DS is low, Motorola processor operation
is selected.
Figure 17 shows the timing diagram for the Motorola
MC68HC11 (1 MHz) microcontroller. The chip select
(CS) input is formed by NANDing address strobe
(AS) and address decode output. Again, the
MT88L89 examines the state of DS on the falling
edge of CS to determine if the micro has a Motorola
bus (when DS is low). Additionally, the Texas
Instruments TMS370CX5X is qualified to have a
Motorola interface. Figure 12(a) summarizes
connection of these Motorola processors to the
MT88L89 DTMF transceiver.
Figures 18 and 19 are the timing diagrams for the
Intel 8031/8051 (12 MHz) and 8085 (5 MHz) microcontrollers with multiplexed address and data buses.
The MT88L89 latches in the state of RD on the
falling edge of CS. When RD is high, Intel processor
operation is selected.
By NANDing the address
latch enable (ALE) output with the high-byte address
(P2) decode output, CS can be generated. Figure
12(b) summarizes the connection of these Intel
processors to the MT88L89 transceiver.
NOTE: The adaptive micro interface relies on highto-low transition on CS to recognize the
microcontroller interface and this pin must not be tied
permanently low.
MC6800/6802
MT88L89
A0-A15
CS
RS0
VMA
D0-D3
D0-D3
RW
Φ2
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 14). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
MT88L89
MC68HC11
CS
A8-A15
D0-D3
AS
RS0
AD0-AD3
R/W/WR
DS
DS/RD
DS/RD
RW
R/W/WR
(a)
MC6809
MT88L89
A0-A15
Q
E
D0-D3
R/W
CS
8031/8051
8080/8085
MT88L89
A8-A15
CS
RS0
D0-D3
ALE
D0-D3
R/W/WR
DS/RD
P0
RS0
RD
DS/RD
R/W/WR
WR
(b)
Figure 12 a) & b) - MT88L89 Interface Connections for Various Intel and Motorola Micros
4-133
MT88L89
Advance Information
Motorola
Intel
RS0
R/W
WR
RD
FUNCTION
0
0
0
1
Write to Transmit
Data Register
0
1
1
0
Read from Receive
Data Register
1
0
0
1
Write to Control Register
1
1
1
0
Read from Status Register
Table 3. Internal Register Functions
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
Table 4. CRA Bit Positions
b3
b2
b1
b0
C/R
S/D
TEST
BURST
ENABLE
Table 5. CRB Bit Positions
BIT
NAME
DESCRIPTION
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low turns the tone output
off. This bit controls all transmit tone functions.
b1
CP/DTMF
Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a retangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3
RSEL
Register Select. A logic high selects control register B for the next write cycle to the
control register address. After writing to control register B, the following control register
write cycle will be directed to control register A.
Table 6. Control Register A Description
4-134
MT88L89
Advance Information
BIT
NAME
DESCRIPTION
b0
BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
RxEN
This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power down mode.
b2
S/D
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7 . Control Register B Description
BIT
NAME
b0
IRQ
STATUS FLAG SET
STATUS FLAG CLEARED
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
b3
DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8 . Status Register Description
4-135
MT88L89
Advance Information
VDD
MT88L89
C1
R1
DTMF/CP
INPUT
R2
IN+
IN-
St/GT
GS
ESt
RL
D3
VSS
D2
OSC1
D1
OSC2
D0
TONE
IRQ/CP
R/W/WR
CS
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 Ω 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
X-tal = 3.579545 MHz
C2
R4
VRef
X-tal
DTMF
OUTPUT
C3
VDD
R3
DS/RD
RS0
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT88L89 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
4-136
To µP
or µC
MT88L89
Advance Information
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after
power up.
Description:
1)
2)
3)
4)
5)
6)
Read Status Register
Write to Control Register
Write to Control Register
Write to Control Register
Write to Control Register
Read Status Register
RS0
1
1
1
1
1
1
Intel
Motorola
WR RD
R/W
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
b3
X
0
0
1
0
X
Data
b2
X
0
0
0
0
X
b1
X
0
0
0
0
X
b0
X
0
0
0
0
X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0
1) Write to Control Register A
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
1
(burst mode)
3) Write to Transmit Data Register
0
(send a digit 7)
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register
1
R/W
0
WR RD
0
1
b3
1
b2
1
b1
0
b0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case ...
Write to Transmit Register
0
0
0
(send a digit 5)
1
0
1
0
1
-if bit 2 is set, a DTMF tone has been received, in which case ....
Read the Receive Data Register
0
1
1
0
X
X
X
X
-if both bits are set ...
Read the Receive Data Register
Write to Transmit Data Register
0
1
X
0
X
1
X
0
X
1
0
0
1
0
1
0
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
Figure 14 - Application Notes
4-137
MT88L89
Advance Information
Absolute Maximum Ratings*
Parameter
Symbol
1
Power supply voltage VDD-VSS
2
Voltage on any pin
3
4
Current at any pin (Except VDD and VSS)
Storage temperature
TST
5
Package power dissipation
PD
Min
Max
Units
6
V
VDD+0.3
V
10
mA
+150
°C
1000
mW
VDD
VI
VSS-0.3
-65
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Sym
Min
Typ‡
Max
Units
3
3.6
V
+85
°C
3.583124
MHz
1
Positive power supply
VDD
2.7
2
Operating temperature
TO
-40
3
Crystal clock frequency
fCLK
3.575965
3.579545
Test Conditions
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† -
Sym
Min
Typ‡
Max
Units
Operating supply voltage
VDD
2.7
3
3.6
V
Operating supply current
IDD
3
mA
Power consumption
PC
9
mW
Characteristics
1
2
3
4
5
6
S
U
P
I
N
P
U
T
S
7
8
9
10
O
U
T
P
U
T
S
13
14
15
16
17
18
19
High level input voltage
(OSC1)
VIHO
Low level input voltage
(OSC1)
VILO
Steering threshold voltage
VTSt
Low level output voltage
(OSC2)
VOLO
High level output voltage
(OSC2)
VOHO
2.1
.9
1.4
0.3
2.97
V
VDD=3.0V
V
VDD=3.0V
V
No load
VSS=0V
V
No load
VDD=3.0V
VRef output voltage
VRef
1.5
V
VRef output resistance
ROR
1.3
kΩ
Low level input voltage
VIL
.9
V
High level input voltage
VIH
2.1
V
Input leakage current
IIZ
Source current
IOH
Sink current
ESt
and
St/GT
IRQ/
CP
D
i
g
i
t
a
l
Data
Bus
10
Device fully enabled
VDD=3.0V
IOZ
1
Test Conditions
V
Output leakage current
(IRQ)
11
12
VSS=0 V.
µA
VOH=2.4 V
10
No load, VDD=3V
µA
VIN=VSS to VDD
-6.6
mA
VOH=2.4V
IOL
4.0
mA
VOL=0.4V
Source current
IOH
-3.0
mA
VOH=2.4V
Sink current
IOL
4
mA
VOL=0.4V
Sink current
IOL
16
mA
VOL=0.4V
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =3V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
4-138
MT88L89
Advance Information
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=3V, TO=25°C.
Characteristics
Sym
Typ‡
Min
Max
Units
Test Conditions
VSS ≤ VIN ≤ VDD
1
Input leakage current
IIN
±100
nA
2
Input resistance
RIN
10
MΩ
3
Input offset voltage
VOS
25
mV
4
Power supply rejection
PSRR
60
dB
1 kHz
5
Common mode rejection
CMRR
60
dB
0.75 ≤ VIN ≤ 4.25V
6
DC open loop voltage gain
AVOL
65
dB
7
Unity gain bandwidth
BW
1.5
MHz
8
Output voltage swing
VO
4.5
Vpp
9
Allowable capacitive load (GS)
CL
100
pF
10
Allowable resistive load (GS)
RL
50
kΩ
11
Common mode range
VCM
3.0
Vpp
RL ≥ 100 kΩ to VSS
No Load
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
MT88L89 AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
R
X
Sym
Valid input signal levels
(each tone of composite
signal)
Min
Typ‡
Max
Units
-34
-4
dBm
15.4
489
mVRMS
Notes*
1,2,3,5,6
min @ VDD=3.6V
max @ VDD=2.7V
1,2,3,5,6
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
fC=3.579545 MHz.
Notes*
1
Positive twist accept
8
dB
2,3,6,9
2
Negative twist accept
8
dB
2,3,6,9
3
4
Freq. deviation accept
R
X
Freq. deviation reject
±1.5%± 2Hz
2,3,5
±3.5%
2,3,5
5
Third tone tolerance
-16
dB
2,3,4,5,9,10
6
Noise tolerance
-12
dB
2,3,4,5,7,9,10
7
Dial tone tolerance
22
dB
2,3,4,5,8,9
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 3V, and for design aid only: not guaranteed and not subject to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
4-139
MT88L89
Advance Information
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym
Min
310
Typ‡
Max
Units
Conditions
500
Hz
@ -25 dBm,
Note 9
1
Accept Bandwidth
fA
2
Lower freq. (REJECT)
fLR
290
Hz
@ -25 dBm
3
Upper freq. (REJECT)
fHR
540
Hz
@ -25 dBm
4
Call progress tone detect level (total
power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requirements.
Actual
values are user selectable as per Figures 5, 6 and 7.
Characteristics
Sym
Min
Typ‡
Max
Units
1
Minimum tone accept duration
tREC
40
ms
2
Maximum tone reject duration
tREC
20
ms
3
Minimum interdigit pause duration
tID
40
ms
4
Maximum tone drop-out duration
tOD
20
ms
Conditions
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics† - Voltages are with respect to ground (VSS), unless otherwise stated.
Sym
Min
Typ‡
Max
Units
Tone present detect time
tDP
5
11
14
ms
Note 11
Tone absent detect time
tDA
0.5
4
8.5
ms
Note 11
Characteristics
1
2
3
4
T
O
N
E
I
N
Conditions
Delay St to b3
tPStb3
13
µs
See Figure 7
Delay St to RX0-RX3
tPStRX
8
µs
See Figure 7
5
Tone burst duration
tBST
50
52
ms
DTMF mode
6
Tone pause duration
tPS
50
52
ms
DTMF mode
7
Tone burst duration (extended)
tBSTE
100
104
ms
Call Progress mode
Tone pause duration (extended)
tPSE
100
104
ms
Call Progress mode
High group output level
VHOUT
-15.1
-11.1
dBm
RL=10kΩ
Low group output level
VLOUT
-17.1
-13.1
dBm
RL=10kΩ
8
9
10
11
12
T
O
N
E
O
U
T
Pre-emphasis
dBP
2
dB
RL=10kΩ
Output distortion (Single Tone)
THD
-35
dB
25 kHz Bandwidth
RL=10kΩ
13
±0.7
14
Frequency deviation
15
Output load resistance
RLT
10
Crystal/clock frequency
fC
3.5759
16
17
18
19
X
T
A
L
fD
Clock input rise and fall time
tCLRF
Clock input duty cycle
DCCL
Capacitive load (OSC2)
CLO
40
3.5795
50
30
±1.5
%
50
kΩ
3.5831
MHz
110
ns
Ext. clock
60
%
Ext. clock
pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
4-140
fC=3.579545 MHz
MT88L89
Advance Information
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym
Typ‡
Min
Max
Units
Conditions
1
DS/RD/WR clock frequency
fCYC
4.0
MHz
Figure 15
2
DS/RD/WR cycle period
tCYC
250
ns
Figure 15
3
DS/RD/WR low pulse width
tCL
150
ns
Figure 15
4
DS/RD/WR high pulse width
tCH
100
ns
Figure 15
5
DS/RD/WR rise and fall time
tR,tF
20
ns
Figure 15
6
R/W setup time
tRWS
0
ns
Figures 16 & 17
7
R/W hold time
tRWH
26
ns
Figures 16 & 17
8
Address setup time (RS0)
tAS
0
ns
Figures 16 - 19
9
Address hold time (RS0)
tAH
26
ns
Figures 16 - 19
10
Data hold time (read)
tDHR
22
ns
Figures 16 - 19
11
DS/RD to valid data delay (read)
tDDR
80
ns
Figures 16 - 19
12
Data setup time (write)
tDSW
35
ns
Figures 16 - 19
13
Data hold time (write)
tDHW
10
ns
Figures 16 - 19
14
Chip select setup time
tCSS
45
ns
Figures 16 - 19
15
Chip select hold time
tCSH
40
ns
Figures 16 - 19
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ± 1.5 %±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2 %).
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
tCYC
tR
DS/RD/WR
tF
tCH
tCL
Figure 15 - DS/RD/WR Clock Pulse
4-141
MT88L89
Advance Information
tRWH
tRWS
DS
Q clk*
A0-A15
(RS0)
16 bytes of Addr
R/W(read)
tDDR
tDHR
Read Data
(D3-D0)
R/W (write)
tDSW➀
Write data
(D3-D0)
tDHW
tCSH➀
tCSS
tAH
tAS
CS = (E + Q).Addr [MC6809]
tAH
tAS
CS = VMA.Addr [MC6800, MC6802]
tCSH➀
tCSS
*microprocessor pin
Figure 16 - MC6800/MC6802/MC6809 Timing Diagram
➀ tDSW is from data to DS falling edge; t CSH is from DS rising edge to CS rising edge
tRWS
DS
tRWH
R/W
tDHR
tDDR
tAS
Read
AD3-AD0
(RS0, D0-D3)
Addr
Data
Write
AD3-AD0
(RS0-D0-D3)
Addr
Data
tDSW
tAH
Addr *
non-mux
tDHW
tCSH
High Byte of Addr
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 17 - MC68HC11 Bus Timing (with multiplexed address and data buses)
4-142
MT88L89
Advance Information
tCSS
ALE*
RD
tAS
P0*
(RS0,
D0-D3)
tDHR
tDDR
tAH
Data
A0-A7
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 18 - 8031/8051/8085 Read Timing Diagram
ALE*
tCSS
WR
tAS
P0*
(RS0,
D0-D3)
P2 *
(Addr)
tAH
A0-A7
tDSW
tDHW
Data
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 19 - 8031/8051/8085 Write Timing Diagram
4-143
MT88L89
NOTES:
4-144