Infineon IR3447MTRPBF 25a highly integrated supirbuckâ® single-input voltage, synchronous buck regulator Datasheet

DCDC Converter
25A Highly Integrated SupIRBuck®
Single-Input Voltage, Synchronous
Buck Regulator
FEATURES
SupIRBuck
IR3447
DESCRIPTION
• Single 5V to 21V application
• Wide Input Voltage Range from 1.5V to 21V with
external Vcc
• Output Voltage Range: 0.6V to 0.86*PVin
• 0.5% accurate Reference Voltage
• Enhanced line/load regulation with Feed-Forward
• Programmable Switching Frequency up to 1.5MHz
• Internal Digital Soft-Start
• Enable input with Voltage Monitoring Capability
• Remote Sense Amplifier with True Differential
Voltage Sensing
• Thermally compensated current limit and Hiccup
Mode Over Current Protection
• Smart LDO to enhance efficiency
• External synchronization with Smooth Clocking
• Dedicated output voltage sensing for power good
indication and overvoltage protection which
remains active even when Enable is low.
• Enhanced Pre-Bias Start up
• Body Braking to improve transient
• Integrated MOSFET drivers and Bootstrap diode
• Thermal Shut Down
• Post Package trimmed rising edge dead-time
• Programmable Power Good Output
• Small Size 5mm x 6mm PQFN
o
o
• Operating Junction Temp: -40 C<Tj<125 C
• Lead-free, Halogen-free and RoHS Compliant
®
The IR3447 SupIRBuck is an easy-to-use, fully
integrated and highly efficient DC/DC regulator. The
onboard PWM controller and MOSFETs make IR3447
a space-efficient solution, providing accurate power
delivery for low output voltage and high current
applications.
IR3447 is a versatile regulator which offers
programmability of switching frequency and current
limit while operating in wide input and output voltage
range.
The switching frequency is programmable from 300
kHz to 1.5MHz for an optimum solution.
It also features important protection functions,
Over Voltage Protection (OVP), Pre-Bias
hiccup current limit and thermal shutdown
required system level security in the event
conditions.
such as
startup,
to give
of fault
APPLICATIONS
•
•
•
•
Server Application
Distributed Point of Load Power Architectures
Set Top Box Application
Power Supplies
ORDERING INFORMATION
Base Part
Number
Package Type
IR3447
PQFN 5mm x 6mm
1
Rev 3.7
Standard Pack
Orderable Part
Form
Quantity
Number
Tape and Reel
4000
IR3447MTRPBF
May 17, 2016
IR3447
BASIC APPLICATION
Figure 1: IR3447 Basic Application Circuit
Figure 2: Efficiency [Vin=12V, Fsw=600kHz]
PIN DIAGRAM
5mm X 6mm POWER QFN
Top View
2
Rev 3.7
May 17, 2016
IR3447
FUNCTIONAL BLOCK DIAGRAM
Vin
Smart
LDO
VCC
THERMAL
SHUTDOWN
DCM
LGnd
TSD
UVcc
UVcc
VREF
+
+ E/A
0.6V
FAULT
CONTROL
OC
POR
OV
Comp
CByp
VCC/
LDO_out
Boot
FAULT
FB
PVin
FB
HDrv
VREF
DRIVER
OVER
VOLTAGE
UVcc
Vsns
HDin
LDin
CLK
Intl_SS
POR
FAULT
Enable
UVEN
BODY
BRAKING
CONTROL
POR
POR
+
CONTROL
LOGIC
VREF
FB
RSo
ZC
OC
SW
LDrv
PGnd
SSOK
UVEN
UVcc
RSRS+
PVin
DIGITAL
SOFT
START
+
POR
ZERO CROSSING
COMPARATOR
OVER CURRENT
OCset
DCM
Rt/Sync
PGD
Figure 3: IR3447 Simplified Block Diagram
3
Rev 3.7
May 17, 2016
IR3447
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
PVin
Input voltage for power stage. Bypass capacitors between PVin and
PGND should be connected very close to this pin and PGND; also forms
input to feedforward block
2
Boot
Supply voltage for high side driver
3
Enable
Enable pin to turning on and off the IC.
4
Rt/Sync
Use an external resistor from this pin to LGND to set the switching
frequency, very close to the pin. This pin can also be used for external
synchronization.
5
OCset
6
Vsns
Current Limit setpoint. This pin allows the trip point to be set to one of
three possible settings by either floating this pin, tying it to VCC or tying it
to PGnd.
Sense pin for OVP and PGood
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator or to the output of the remote sense amplifier, via
resistor divider to set the output voltage and provide feedback to the
error amplifier.
7
FB
8
COMP
9
RSo
10, 26, 27,
29
PGND
Power ground. This pin should be connected to the system’s power
ground plane. Bypass capacitors between PVin and PGND should be
connected very close to PVIN pin (pin 1) and this pin.
11
LGND
Signal ground for internal reference and control circuitry.
12
RS-
Remote Sense Amplifier input. Connect to ground at the load.
13
RS+
Remote Sense Amplifier input. Connect to output at the load.
14
CByp
Bypassing capacitor for internal reference voltage. A capacitor between
100pF and 180pF should be connected between this pin and LGnd.
15, 19, 28,
30, 31, 33
NC
16
PGD
17
Vin
18
VCC/LDO_out
20, 21, 22,
23, 24, 25,
32
SW
4
Rev 3.7
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to FB to provide loop compensation.
Remote Sense Amplifier Output
No connection.
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to VCC.
Input Voltage for LDO.
Bias Voltage for IC and driver section, output of LDO. Add a minimum of
4.7uF bypass cap from this pin to PGnd.
Switch node. This pin is connected to the output inductor.
May 17, 2016
IR3447
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin
Vin
VCC
SW
BOOT
BOOT to SW
Input/Output pins
RS+, RS-, RSo, PGD, Enable, OCset
PGND to LGND, RS- to LGND
Junction Temperature Range
Storage Temperature Range
Machine Model
ESD
Human Body Model
Charged Device Model
Moisture Sensitivity level
RoHS Compliant
-0.3V to 25V
-0.3V to 25V
-0.3V to 8V (Note 1)
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
-0.3V to 33V
-0.3V to VCC + 0.3V (Note 2)
-0.3V to 3.9V
-0.3V to 8V (Note 1)
-0.3V to + 0.3V
-40°C to 150°C
-55°C to 150°C
Class A
Class 1C
Class III
JEDEC Level 2 @ 260°C
Yes
Note:
1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.
2. Must not exceed 8V.
THERMAL INFORMATION
Thermal Resistance, Junction to Case Top (θJC_TOP)
31.5°C/W
Thermal Resistance, Junction to PCB (θJB)
2.41°C/W
Thermal Resistance, Junction to Ambient (θJA) (Note 3)
14.7°C/W
Note:
3. Thermal resistance (θJA) is measured with components mounted on a high effective thermal conductivity
test board.
5
Rev 3.7
May 17, 2016
IR3447
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
DEFINITION
MIN
MAX
Input Bus Voltage *
1.5
21
Supply Voltage
5.0
21
Supply Voltage **
4.5
7.5
Boot to SW
Supply Voltage
4.5
7.5
VO
Output Voltage
0.6
0.86 * PVin
IO
Output Current
Fs
Switching Frequency
PVin
Vin
VCC
*
**
UNITS
V
0
±25
A
300
1500
kHz
125
°C
TJ
Junction Temperature
-40
SW node must not exceed 25V
When VCC is connected to an externally regulated supply, also connect Vin.
ELECTRICAL CHARACTERISTICS
o
Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V< VCC < 7.5V, 0 C < TJ <
o
125 C.
o
Typical values are specified at TA = 25 C.
PARAMETER
SYMBOL
CONDITIONS
PLOSS
Vin = PVin = 12V, VO =
1.2V, IO = 25A, Fs =
600kHz, L=0.215uH,
TA = 25°C, Note 4
MIN
TYP
MAX
UNIT
Power Loss
Power Loss
3.62
W
MOSFET Rds(on)
Top Switch
Rds(on)_Top
VBoot – VSW = 6.8V,
ID = 25A, Tj = 25°C
Bottom Switch
Rds(on)_Bot
VCC =6.8V, ID = 25A,
Tj = 25°C
4
5.2
1.8
2.3
mΩ
Reference Voltage
Feedback Voltage
VFB
Accuracy
0.6
Vref=0.6V,
0°C < Tj < 105°C
-0.5
Vref=0.6V,
-40°C < Tj < 125°C
-1.0
V
+0.5
%
+1.0
Supply Current
Vin Supply Current
(Standby)
Vin Supply Current (Dyn)
6
Rev 3.7
Iin(Standby)
Vin=21V, Enable low,
No Switching
Iin(Dyn)
Vin=21V, Enable high,
Fs = 600kHz
300
425
µA
40
mA
May 17, 2016
IR3447
PARAMETER
SYMBOL
CONDITIONS
Icc(Standby)
Enable low, VCC=7V,
No Switching
Icc(Dyn)
Enable high, VCC=7V,
Fs = 600kHz
VCC–Start–Threshold
VCC_UVLO_Start
VCC Rising Trip Level
4.0
4.2
4.4
VCC–Stop–Threshold
VCC_UVLO_Stop
VCC Falling Trip Level
3.8
3.9
4.2
VCC Supply Current
(Standby)
VCC Supply Current (Dyn)
MIN
TYP
MAX
UNIT
300
425
µA
40
mA
Under Voltage Lockout
Enable–Start–Threshold
Enable_UVLO_Start
Supply ramping up
1.14
1.2
1.36
Enable–Stop–Threshold
Enable_UVLO_Stop
Supply ramping down
0.9
1.0
1.06
Enable leakage current
Ien
Enable=3.3V
1
V
V
µA
Oscillator
Rt Voltage
1
Frequency Range
FS
Ramp Amplitude
Vramp
Rt=80.6k
270
300
330
Rt=39.2k
540
600
660
Rt=15k
1350
1500
1650
PVin=6.8V, PVin(max)
slew rate=1V/us,
Note 4
1.02
PVin=12V, PVin(max)
slew rate=1V/us,
Note 4
1.8
PVin=16V, PVin(max)
slew rate=1V/us,
Note 4
2.4
0.16
Ramp Offset
Ramp (os)
Note 4
Min Pulse Width
Tmin (ctrl)
Note 4
Fixed Off Time
Note 4
Max Duty Cycle
Dmax
Sync Frequency Range
200
Fs=300kHz,
PVin=Vin=12V
86
Note 4
270
Sync Pulse Duration
100
Sync Level Threshold
V
High
kHz
Vp-p
V
50
ns
230
ns
%
1650
200
ns
3
Low
kHz
0.6
V
Error Amplifier
Input Offset Voltage
Input Bias Current
Sink Current
Source Current
7
-1.5
+1.5
IFb(E/A)
-0.5
+0.5
µA
Isink(E/A)
0.4
0.85
1.2
mA
Isource(E/A)
4
5
11
mA
Vos_CByp
Rev 3.7
VFb – VREF,
VREF = 0.6V
%
May 17, 2016
IR3447
PARAMETER
SYMBOL
Slew Rate
Gain-Bandwidth Product
DC Gain
CONDITIONS
MIN
TYP
MAX
UNIT
SR
Note 4
7
12
20
V / µs
GBWP
Note 4
20
30
40
MHz
Gain
Note 4
100
110
120
dB
1.7
2
2.3
V
100
mV
1.2
V
9
MHz
Maximum Output Voltage
Vmax(E/A)
Minimum Output Voltage
Vmin(E/A)
Common Mode Voltage
Vcm_Vp
Note 4
0
Unity Gain Bandwidth
BW_RS
Note 4
3
DC Gain
Gain_RS
Note 4
Remote Sense Differential Amplifier
Offset Voltage
Offset_RS
Source Current
VREF=0.6V,
0°C < Tj < 85°C
VREF=0.6V,
-40°C < Tj < 125°C
6.4
110
-1.5
0
-2
dB
1.5
mV
2
mV
Isource_RS
3
13
20
mA
Sink Current
Isink_RS
0.4
1
2
mA
Slew Rate
Slew_RS
2
4
8
V / µs
RS+ input impedance
Rin_RS+
45
63
85
kohm
RS- input impedance
Rin_RS-
Maximum Voltage
Vmax_RS
Minimum Voltage
Min_RS
Note 4, Cload = 100pF
Note 4
V(VCC) – V(RSo)
63
0.5
1
kohm
1.5
50
V
mV
Internal Digital Soft Start
Soft Start Clock
Clk_SS
Soft Start Ramp Rate
Ramp(SS_Start)
Note 4
Note 4
180
200
220
kHz
0.3
0.4
0.5
mV /
µs
360
520
960
mV
1
µA
Bootstrap Diode
Forward Voltage
I(Boot) = 30mA
Switch Node
SW Leakage Current
lsw
SW = 0V, Enable = 0V
Internal Regulator (VCC/LDO)
Output Voltage
VCC
VCC dropout
VCC_drop
Short Circuit Current
Ishort
Zero-crossing Comparator
8
Rev 3.7
Tdly_zc
Vin(min) = 7.2V, Io=030mA, Cload = 2.2uF,
DCM=0
6.3
Vin(min) = 7.2V, Io=030mA, Cload = 2.2uF,
DCM=1
4
6.8
V
4.4
Vin = 7V, Io=70 mA,
Cload = 2.2uF
Note 4
7.1
4.8
0.7
V
70
mA
256 /
s
May 17, 2016
IR3447
PARAMETER
Delay
SYMBOL
Zero-crossing Comparator
Offset
CONDITIONS
Vos_zc
MIN
TYP
Fs
MAX
UNIT
Note 4
0
mV
Fb > Vref, SW duty
cycle, Note 3
0
%
Body Braking
BB Threshold
BB_threshold
FAULTS
Power Good
Power Good Low Upper
Threshold
VPG_low(upper)
Power Good Low Upper
Threshold Falling delay
VPG_low(upper)_Dly
Power Good High Lower
Threshold
VPG_high(lower)
Vsns Rising
95
%
VREF
Power Good High Lower
Threshold Rising Delay
VPG_high(lower)_Dly
Vsns rising
1.28
ms
Power Good Low Lower
Threshold
VPG_low(lower)
Vsns falling
90
%
VREF
Power Good Low Lower
Threshold Falling Delay
VPG_low(lower)_Dly
PGood Voltage Low
PG (voltage)
Vsns Rising
115
120
125
%
VREF
Vsns >
VPG_low(upper)
1.5
2.5
3.5
µs
Vsns <
VPG_low(lower)
101
150
IPGood = -5mA
199
µs
0.5
V
Over Voltage Protection (OVP)
OVP Trip Threshold
OVP Fault Prop Delay
OVP (trip)
Vsns Rising
115
120
125
%
VREF
OVP (delay)
Vsns rising
1.5
2.5
3.5
µs
OCSet=VCC, VCC =
6.8V, TJ = 25°C
29.25
32.5
35.75
A
OCSet=floating, VCC
= 6.8V, TJ = 25°C
23.4
26
28.6
A
OCSet=PGnd, VCC
=6.8V, TJ = 25°C
17.55
19.5
21.85
A
Over-Current Protection
OC Trip Current
ITRIP
Hiccup blanking time
Tblk_Hiccup
Note 4
20.48
ms
Thermal Shutdown
Note 4
145
°C
Hysteresis
Note 4
20
°C
Thermal Shutdown
Notes:
4. Guaranteed by design but not tested in production.
9
Rev 3.7
May 17, 2016
IR3447
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, VCC = Internal LDO, Io=0-25A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the
losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves.
The table below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
1.2
1.8
3.3
10
LOUT (uH)
0.215
0.215
0.311
0.68
Rev 3.7
P/N
PCDC1008-R215EMO (Cyntec)
PCDC1008-R215EMO (Cyntec)
FP1109-R33-R (Coiltronics)
7443320068 (Wurth Elektronik)
DCR (mΩ)
0.29
0.29
0.42
0.72
May 17, 2016
IR3447
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vin = VCC = 5V, Io=0-25A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of
the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
1.2
1.8
3.3
11
LOUT (uH)
0.215
0.215
0.311
0.68
Rev 3.7
P/N
PCDC1008-R215EMO (Cyntec)
PCDC1008-R215EMO (Cyntec)
FP1109-R33-R (Coiltronics)
7443320068 (Wurth Elektronik)
DCR (mΩ)
0.29
0.29
0.42
0.72
May 17, 2016
IR3447
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, Io=0-25A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
1.2
1.8
12
LOUT (uH)
0.215
0.215
0.311
Rev 3.7
P/N
PCDC1008-R215EMO (Cyntec)
PCDC1008-R215EMO (Cyntec)
FP1109-R33-R (Coiltronics)
DCR (mΩ)
0.29
0.29
0.42
May 17, 2016
IR3447
THERMAL DERATING CURVES
Measurements are done on IR3447 Evaluation board. PCB is a 6 layer board with 2 oz copper and FR4 material.
Vin=PVin=12V, Vout =1.2V, VCC=internal LDO (6.8V), Fs = 600kHz
Vin=PVin=12V, Vout =5.0V, VCC=internal LDO (6.8V), Fs = 600kHz
Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The
continuous current load capability might be higher than the rating of the device if input voltage is 12V typical and
switching frequency is below 600kHz. However, the maximum current is limited by the internal current limit and
designers need to consider enough guard bands between load current and minimum current limit to guarantee
that the device does not trip at steady state condition.
13
Rev 3.7
May 17, 2016
IR3447
MOSFET RDSON VARIATION OVER TEMPERATURE
14
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
15
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
16
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
OCset=VCC
OCset=VCC
OCset=Float
OCset=Float
OCset=GND
OCset=GND
OCset=VCC
OCset=Float
OCset=GND
17
Rev 3.7
May 17, 2016
IR3447
THEORY OF OPERATION
set thresholds. Normal operation resumes once VCC
and Enable rise above their thresholds.
DESCRIPTION
The IR3447 uses a PWM voltage mode control
scheme with external compensation to provide good
noise immunity and maximum flexibility in selecting
inductor values and capacitor types.
The switching frequency is programmable from
300kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3447 provides precisely regulated output voltage
programmed via two external resistors from 0.6V to
0.86*PVin.
The IR3447 operates with an internal bias supply
(LDO) which is connected to the VCC pin. This allows
operation with single supply. The bias voltage is
variable according to load condition. If the output load
current is less than half of the peak-to-peak inductor
current, a lower bias voltage, 4.4V, is used as the
internal gate drive voltage; otherwise, a higher
voltage, 6.8V, is used.
This feature helps the converter to reduce power
losses. The device can also be operated with an
external supply from 4.5V to 7.5V, allowing an
extended operating input voltage (PVin) range from
1.5V to 21V. For using the internal LDO supply, the
Vin pin should be connected to PVin pin. If an external
supply is used, it should be connected to VCC pin and
the Vin pin should be shorted to VCC pin.
The POR (Power On Ready) signal is generated when
all these signals reach the valid logic level (see
system block diagram). When the POR is asserted the
soft start sequence starts (see soft start section).
ENABLE
The Enable features another level of flexibility for
startup. The Enable has precise threshold which is
internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3447 will turn on only
when the voltage at the Enable pin exceeds this
threshold, typically, 1.2V.
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it
can be ensured that the IR3447 does not turn on until
the bus voltage reaches the desired level Figure 4.
Only after the bus voltage reaches or exceeds this
level and voltage at the Enable pin exceeds its
threshold, IR3447 will be enabled. Therefore, in
addition to being a logic input pin to enable the
IR3447, the Enable feature, with its precise threshold,
also allows the user to implement an Under-Voltage
Lockout for the bus voltage (PVin). It can help prevent
the IR3447 from regulating at low PVin voltages that
can cause excessive input current.
The device utilizes the on-resistance of the low side
MOSFET (synchronous Mosfet) as current sense
element. This method enhances the converter’s
efficiency and reduces cost by eliminating the need for
external current sense resistor.
IR3447 includes two low Rds(on) MOSFETs using IR’s
HEXFET technology. These are specifically designed
for high efficiency applications.
UNDER-VOLTAGE LOCKOUT AND POR
The under-voltage lockout circuit monitors the voltage
of VCC pin and the Enable input. It assures that the
MOSFET driver outputs remain in the off state
whenever either of these two signals drops below the
18
Rev 3.7
Figure 4: Normal Start up, device turns on when the
bus voltage reaches 10.2V
A resistor divider is used at EN pin from PVin to turn
on the device at 10.2V.
May 17, 2016
IR3447
...
HDRv
PVin=Vin
12.5%
...
LDRv
Vcc
> 1.2V
EN
Intl_SS
16
...
...
25%
...
...
87.5%
...
...
16
...
End of
PB
...
Figure 7: Pre-Bias startup pulses
Vo
SOFT-START
Figure 5: Recommended startup for Normal operation
Figure 5 shows the recommended startup sequence
for the typical operation of IR3447 with Enable used
as logic input.
PRE-BIAS STARTUP
IR3447 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
The output starts in asynchronous fashion and keeps
the synchronous MOSFET (Sync FET) off until the
first gate signal for control MOSFET (Ctrl FET) is
generated. Figure 6 shows a typical Pre-Bias condition
at start up. The sync FET always starts with a narrow
pulse width (12.5% of a switching period) and
gradually increases its duty cycle with a step of 12.5%
until it reaches the steady state value. The number of
these startup pulses for each step is 16 and it’s
internally programmed. Figure 7 shows the series of
16x8 startup pulses.
[V]
IR3447 has an internal digital soft-start to control the
output voltage rise and to limit the current surge at the
start-up. To ensure correct start-up, the soft-start
sequence initiates when the Enable and VCC rise
above their UVLO thresholds and generate the Power
On Ready (POR) signal. The internal soft-start
(Intl_SS) signal linearly rises with the rate of 0.4mV/µs
from 0V to 1.5V. Figure 8 shows the waveforms
during soft start. The normal Vout startup time is fixed,
and is equal to:
Tstart =
(0.75V − 0.15V ) = 1.5mS
0.4mV / µS
(1)
During the soft start the over-current protection (OCP)
and over-voltage protection (OVP) is enabled to
protect the device for any short circuit or over voltage
condition.
Vo
Pre-Bias
Voltage
[Time]
Figure 6: Pre-Bias startup
Figure 8: Theoretical operation waveforms during
soft-start
OPERATING FREQUENCY
The switching frequency can be programmed between
300kHz – 1500kHz by connecting an external resistor
19
Rev 3.7
May 17, 2016
IR3447
from Rt pin to LGnd. Table 1 tabulates the oscillator
frequency versus Rt.
Table 1: Switching Frequency(Fs) vs. External
Resistor(Rt)
Rt (KΩ)
80.6
60.4
48.7
39.2
34
29.4
26.1
23.2
21
19.1
17.4
16.2
15
Freq
(KHz)
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
SHUTDOWN
is on for less than 12.5% of the switching period, the
current is sampled approximately 40nS after the start
of the downward slope of the inductor current. When
the sampled current is higher than the OC Limit, an
OC event is detected.
When an Over Current event is detected, the
converter enters hiccup mode. Hiccup mode is
performed by latching the OC signal and pulling the
Intl_SS signal to ground for 20.48 mS (typ.). OC
signal clears after the completion of hiccup mode and
the converter attempts to return to the nominal output
voltage using a soft start sequence. The converter will
repeat hiccup mode and attempt to recover until the
overload or short circuit condition is removed.
Because the IR3447 uses valley current sensing, the
actual DC output current limit will be greater than OC
limit. The DC output current is approximately half of
peak to peak inductor ripple current above selected
OC limit. OC Limit, inductor value, input voltage,
output voltage and switching frequency are used to
calculate the DC output current limit for the converter.
Equation (2) to determine the approximate DC output
current limit.
IR3447 can be shutdown by pulling the Enable pin
below its 1.0V threshold. During shutdown the high
side and the low side drivers are turned off.
OVER CURRENT PROTECTION
I OCP = I LIMIT +
IOCP
ILIMIT
Δi
∆i
2
(2)
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
The Over Current (OC) protection is performed by
sensing the inductor current through the RDS(on) of the
Synchronous MOSFET. This method enhances the
converter’s efficiency, reduces cost by eliminating a
current sense resistor and any layout related noise
issues. The Over Current (OC) limit can be set to one
of three possible settings by floating the OCset pin, by
pulling up the OCset pin to VCC, or pulling down the
OCset pin to PGnd. The current limit scheme in the
IR3447 uses an internal temperature compensated
current source to achieve an almost constant OC limit
over temperature.
Over Current Protection circuit senses the inductor
current flowing through the Synchronous MOSFET.
To help minimize false tripping due to noise and
transients, inductor current is sampled for about 30 nS
on the downward inductor current slope approximately
12.5% of the switching period before the inductor
current valley. However, if the Synchronous MOSFET
20
Rev 3.7
Figure 9: Timing Diagram for Current Limit Hiccup
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3447. The
o
trip threshold is typically 145 C. When trip threshold is
May 17, 2016
IR3447
exceeded, thermal shutdown turns off both MOSFETs
and resets the internal soft start.
11. The RSA is used as a unity gain buffer and
compensation is determined normally.
Compensation
Automatic restart is initiated when the sensed
temperature drops within the operating range. There
o
is a 20 C hysteresis in the thermal shutdown
threshold.
REMOTE VOLTAGE SENSING
Figure 10: General Remote Sense Configuration
Compensation
True differential remote sensing in the feedback loop
is critical to high current applications where the output
voltage across the load may differ from the output
voltage measured locally across an output capacitor
at the output inductor, and to applications that require
die voltage sensing.
The RS+ and RS- pins of the IR3447 form the inputs
to a remote sense differential amplifier (RSA) with
high speed, low input offset and low input bias current
which ensure accurate voltage sensing and fast
transient response in such applications.
The input range for the differential amplifier is limited
to 1.5V below the VCC rail. Note that IR3447
incorporates a smart LDO which switches the VCC rail
voltage depending on the loading. When determining
the input range assume the part is in light load and
using the lower VCC rail voltage.
There are two remote sense configurations that are
usually implemented. Figure 10 shows a general
remote sense (RS) configuration. This configuration
allows the RSA to monitor output voltages above
VCC. A resistor divider is placed in between the
output and the RSA to provide a lower input voltage to
the RSA inputs. Typically, the resistor divider is
calculated to provide VREF (0.6V) across the RSA
inputs which is then outputted to RSo. The input
impedance of the RSA is 63 KOhms typically and
should be accounted for when determining values for
the resistor divider. To account for the input
impedance, assume a 63 KOhm resistor in parallel to
the lower resistor in the divider network.
The
compensation is then designed for 0.6V to match the
RSo value.
Low voltage applications can use the second remote
sense configuration. When the output voltage range
is within the RSA input specifications, no resistor
divider is needed in between the converter output and
RSA. The second configuration is shown in Figure
21
Rev 3.7
Figure 11: Remote Sense Configuration for Vout less
than VCC-1.5V
EXTERNAL SYNCHRONIZATION
IR3447 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is
important to avoid sub-harmonic oscillations due to
beat frequency for embedded systems when multiple
point-of-load (POL) regulators are used. A multifunction pin, Rt/Sync, is used to connect the external
clock. If the external clock is present before the
converter turns on, Rt/Sync pin can be connected to
the external clock signal solely and no other resistor is
needed. If the external clock is applied after the
converter turns on, or the converter switching
frequency needs to toggle between the external clock
frequency and the internal free-running frequency, an
external resistor from Rt/Sync pin to LGnd is required
to set the free-running frequency.
When an external clock is applied to Rt/Sync pin after
the converter runs in steady state with its free-running
frequency, a transition from the free-running
frequency to the external clock frequency will happen.
This transition is to gradually make the actual
switching frequency equal to the external clock
May 17, 2016
IR3447
frequency, no matter which one is higher. When the
external clock signal is removed from Rt/Sync pin, the
switching frequency is also changed to free-running
gradually. In order to minimize the impact from these
transitions to output voltage, a diode is recommended
to add between the external clock and Rt/Sync pin.
Figure 12 shows the timing diagram of these
transitions.
An internal circuit is used to change the PWM ramp
slope according to the clock frequency applied on
Rt/Sync pin. Even though the frequency of the
external synchronization clock can vary in a wide
range, the PLL circuit keeps the ramp amplitude
constant, requiring no adjustment of the loop
compensation. PVin variation also affects the ramp
amplitude, which will be discussed separately in FeedForward section.
Synchronizetothe
external clock
FreeRunning
Frequency
Returntofreerunningfreq
...
SW
Graduallychange
Graduallychange
...
Fs1
SYNC
Fs1
Fs2
Figure 12: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
FEED-FORWARD
Feed-Forward (F.F.) is an important feature, because
it can keep the converter stable and preserve its load
transient performance when PVin varies. The PWM
ramp amplitude (Vramp) is proportionally changed
with PVin to maintain PVin/Vramp almost constant
throughout PVin variation range (as shown in Figure
13). The PWM ramp amplitude is adjusted to 0.15 of
PVin. Thus, the control loop bandwidth and phase
margin can be maintained constant. Feed-forward
function can also minimize impact on output voltage
from fast PVin change. F.F. is disabled when
PVin<6.2V and the PWM ramp is typically 0.9V. For
PVin<6.2V, PVin voltage should be accounted for
when calculating control loop parameters.
22
Rev 3.7
Figure 13: Timing Diagram for Feed-Forward (F.F.)
Function
SMART LOW DROPOUT REGULATOR (LDO)
IR3447 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the whole
load range, LDO voltage is set to 6.8V (typ.) at mid- or
heavy load condition to reduce Rds(on) and thus
MOSFET conduction loss; and it is reduced to 4.4V
(typ.) at light load condition to reduce gate drive loss.
The smart LDO selects its output voltage according to
the load condition by sensing the inductor current (IL).
At light load condition, the inductor current can fall
below zero as shown in Figure 14. A zero crossing
comparator is used to detect when the inductor
current falls below zero at the LDrv Falling Edge. If the
comparator detects zero crossing events for 256
consecutive switching cycles, the smart LDO reduces
its output to 4.4V. The LDO voltage will remain low
until a zero crossing is not detected. Once a zero
crossing is not detected, the counter is reset and LDO
voltage returns to 6.8V. Figure 14 shows the timing
diagram. Whenever the device turns on, LDO always
starts with 6.8V, then goes to 4.4V / 6.8V depending
upon the load condition. However, if only Vin is
applied with Enable low, the LDO output is 4.4V.
Figure 14: Time Diagram for Smart LDO
May 17, 2016
IR3447
Users can configure the IR3447 to use a single supply
or dual supplies. Depending on the configuration used
the PVin, Vin and VCC pins are connected differently.
Below several configurations are shown.
In an
internally biased configuration, the LDO draws from
the Vin pin and provides a gate drive voltage, as
shown in Figure 15. By connecting Vin and PVin
together as shown in the Figure 16, IR3447 is an
internally biased single supply configuration that runs
off a single supply.
IR3447 can also use an external bias to provide gate
drive voltage for the drivers instead of the internal
LDO. To use an external bias, connected Vin and
VCC to the external bias. PVin can use a separate rail
as shown in Figure 17 or run off the same rail as Vin
and VCC.
Figure 17: Externally Biased Configuration
When the Vin voltage is below 6.8V, the internal LDO
enters the dropout mode at medium and heavy load.
The dropout voltage increases with the switching
frequency. Figure 18 shows the LDO voltage for
600kHz and 1000kHz switching frequency.
Figure 15: Internally Biased Configuration
Figure 18: LDO_Out Voltage in dropout mode
CBYP
Figure 16: Internally Biased Single Supply
Configuration
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to
an external bypass capacitor and it is left floating. A
minimum 100pF ceramic capacitor is required from
stability point of view
POWER GOOD OUTPUT
IR3447 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input
to the window comparator with upper and lower
threshold of OVP(trip) and VPG_high(lower)
23
Rev 3.7
May 17, 2016
IR3447
respectively. PGood signal is high whenever Vsns
voltage is within the PGood comparator window
thresholds. Hysteresis has been applied to the lower
threshold, PGood signal goes low when Vsns drops
below VPG_low(lower) instead of VPG_high(lower).
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that output
is in regulation. Figure 19 show the timing diagram of
the PGood signal. Vsns signal is also used by OVP
comparator for detecting output over voltage
condition. PGood signal is low when Enable is low.
Cbyp
0
0.6V
1.2*VREF
0.95*VREF
Vsns
0
Figure 20: Timing Diagram for OVP in non-tracking
mode
0.9*VREF
PGD
BODY BRAKING
OVP
Latch
0
1.28mS 150uS
Figure 19: PGood Timing Diagram
OVER-VOLTAGE PROTECTION (OVP)
Over-voltage protection in IR3447 is achieved by
comparing sense pin voltage Vsns to a pre-set
threshold. When Vsns exceeds the over voltage
threshold, an over voltage trip signal asserts after 2.5
uS (typ.) delay. The high side drive signal HDrv is
latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns
voltage drops below the threshold. HDrv remains
latched off until a reset is performed by cycling VCC.
OVP is active when enable is high or low.
TM
The Body Braking feature of the IR3447 allows
improved transient response for step-down load
transients. A severe step-down load transient would
cause an overshoot in the output voltage and drive the
Comp pin voltage down until control saturation occurs
demanding 0% duty cycle and the PWM input to the
Control FET driver is kept OFF. When the first such
skipped pulse occurs, the IR3447 enters Body Braking
mode, wherein the Sync FET also turned OFF. The
inductor current then decays by freewheeling through
the body diode of the Sync FET. Thus, with Body
Braking, the forward voltage drop of the body diode
provides and additional voltage to discharge the
inductor current faster to the light load value as shown
in equation (3) and equation (4) below:
Vsns voltage is set by the voltage divider connected to
the output and it can be programmed externally.
Figure 20 shows the timing diagram for OVP.
IL
VD
Vo
L
V + VD
di L
=− o
, with body braking
dt
L
(3)
V
di L
= − o , without body braking
dt
L
(4)
= Inductor current
= Forward voltage drop of the body diode of
the Sync FET.
= output voltage
= Inductor value
The Body Braking mechanism is kept OFF during prebias operation. Also, in the event of an extremely
24
Rev 3.7
May 17, 2016
IR3447
severe load step-down transient causing OVP, the
Body Brake is overridden by the OVP latch, which
turns on the Sync FET.
∴ PVin × Fs ≤
MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time
for Ctrl FET to be reliably turned on. This is very
critical parameter for low duty cycle, high frequency
applications. Conventional approach limits the pulse
width to prevent noise, jitter and pulse skipping. This
results to lower closed loop bandwidth.
IR has developed a proprietary scheme to improve
and enhance minimum pulse width which utilizes the
benefits of voltage mode control scheme with higher
switching frequency, wider conversion ratio and higher
closed loop bandwidth, the latter results in reduction
of output capacitors. Any design or application using
IR3447 must ensure operation with a pulse width that
is higher than the minimum on-time. This is necessary
for the circuit to operate without jitter and pulseskipping, which can cause high inductor current ripple
and high output voltage ripple.
t on =
Vout
D
=
Fs PVin × Fs
0.6V
= 12V / µS
50nS
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
converter should be designed at a switching
frequency that does not exceed 571 kHz. Conversely,
for operation at the maximum recommended
operating frequency (1.5 MHz) and minimum output
voltage (0.6V). The input voltage (PVin) should not
exceed 8V, otherwise pulse skipping may happen.
MAXIMUM DUTY RATIO
A certain off-time is specified for IR3447. This
provides an upper limit on the operating duty ratio at
any given switching frequency. The off-time remains
at a relatively fixed ratio to switching period in low and
mid frequency range, while in high frequency range
this ratio increases, thus the lower the maximum duty
ratio at which IR3447 can operate. Figure 21 shows a
plot of the maximum duty ratio vs. the switching
frequency with built in input voltage feed forward
mechanism.
(5)
In any application that uses IR3447, the following
condition must be satisfied:
t on (min) ≤ t on
(6)
Vout
PVin × Fs
V
∴ PVin × Fs ≤ out
t on (min)
t on (min) ≤
(7)
(8)
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.6V.
Therefore, for Vout(min) = 0.6V,
∴ PVin × Fs ≤
25
Vout
t on (min)
Rev 3.7
(9)
Figure 21: Maximum duty cycle vs. switching
frequency
May 17, 2016
IR3447
TYPICAL OPERATING WAVEFORM
DESIGN EXAMPLE
Output Voltage Programming
The following example is a typical application for
IR3447. The application circuit is shown in Figure 28.
Output voltage is programmed by reference voltage
and external voltage divider. The FB pin is the
inverting input of the error amplifier, which is internally
referenced to VREF. The divider ratio is set to equal
VREF at the FB pin when the output is at its desired
value. When an external resistor divider is connected
to the output as shown in Figure 23, the output
voltage is defined by using the following equation:
Vin = PVin = 12V
Fs = 600kHz
Vo = 1.2V
Io = 25A
Ripple Voltage = ± 1% * Vo
ΔVo = ± 4% * Vo (for 30% load transient)
 R 
Vo = Vref × 1 + 5 
 R6 
Enabling the IR3447
As explained earlier, the precise threshold of the
Enable lends itself well to implementation of a UVLO
for the Bus Voltage as shown in Figure 22.
 Vref
R6 = R5 × 
V −V
ref
 o
(12)




(13)
For the calculated values of R5 and R6, see feedback
compensation section.
Figure 22: Using Enable pin for UVLO implementation
For a typical Enable threshold of VEN = 1.2 V
PVin (min) ×
R2
= V EN = 1.2
R1 + R2
(10)
Figure 23: Typical application of the IR3447 for
programming the output voltage
Bootstrap Capacitor Selection
R2 = R1
VEN
PVin (min) − VEN
(11)
For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a
good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.
To drive the Control FET, it is necessary to supply a
gate voltage at least 4V greater than the voltage at the
SW pin, which is connected to the source of the
Control FET. This is achieved by using a bootstrap
configuration, which comprises the internal bootstrap
diode and an external bootstrap capacitor (C1). The
operation of the circuit is as follows: When the sync
FET is turned on, the capacitor node connected to SW
is pulled down to ground. The capacitor charges
towards Vcc through the internal bootstrap diode
(Figure 24), which has a forward voltage drop VD. The
voltage Vc across the bootstrap capacitor C1 is
approximately given as:
Vc ≅ Vcc − VD
26
Rev 3.7
(14)
May 17, 2016
IR3447
When the control FET turns on in the next cycle, the
capacitor node connected to SW rises to the bus
voltage Vin. However, if the value of C1 is
appropriately chosen, the voltage Vc across C1
remains approximately unchanged and the voltage at
the Boot pin becomes:
VBoot ≅ Vin + Vcc − VD
Cvin
(15)
PVin
+ VD -
Ceramic capacitors are recommended due to their
peak current capabilities. They also feature low ESR
and ESL at higher frequency which enables better
efficiency. For this application, it is advisable to have
7x22uF,
25V
ceramic
capacitors,
GRM31CR61E226KE15L from Murata. In addition to
these, although not mandatory, a 1x330uF, 25V SMD
capacitor EEV-FK1E331P from Panasonic may also
be used as a bulk capacitor and is recommended if
the input power supply is not located close to the
converter.
Inductor Selection
Boot
Vcc
C1
SW
IR3447
+
Vc
L
PGnd
Figure 24: Bootstrap circuit to generate Vc voltage
Inductors are selected based on output power,
operating frequency and efficiency requirements. A
low inductor value causes large ripple current,
resulting in the smaller size, faster response to a load
transient but may also result in reduced efficiency and
high output noise. Generally, the selection of the
inductor value can be reduced to the desired
maximum ripple current in the inductor (Δi). The
optimum point is usually found between 20% and 50%
ripple of the output current. For the buck converter,
the inductor value for the desired operating ripple
current can be determined using the following relation:
A bootstrap capacitor of value 0.1uF is suitable for
most applications.
∆i
1
; ∆t = D ×
∆t
Fs
Vo
L = (Vin − Vo ) ×
Vin × ∆i × Fs
Vin − Vo = L ×
Input Capacitor Selection
The ripple currents generated during the on time of
the control FETs should be provided by the input
capacitor. The RMS value of this ripple for each
channel is expressed by:
I RMS = I o × D × (1 − D )
D=
Vo
Vin
(16)
(17)
Where:
D is the Duty Cycle
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
Where:
Vin
V0
Δi
Fs
Δt
D
(18)
= Maximum input voltage
= Output Voltage
= Inductor Ripple Current
= Switching Frequency
= On time for Control FET
= Duty Cycle
If Δi ≈ 30%*Io, then the inductor is calculated to be
0.24μH. Select L=0.215μH, PCDC1008-R215EMO,
from Cyntec which provides an inductor suitable for
this application.
Io=25A and D = 0.1, the IRMS = 7.5A.
27
Rev 3.7
May 17, 2016
IR3447
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values. The
criterion is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent Series
Inductance (ESL) are other contributing components.
These components can be described as:
transfer function with the highest 0 dB crossing
frequency and adequate phase margin (greater than
o
45 ).
The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant
o
frequency, and a total phase lag of 180 . The resonant
frequency of the LC filter is expressed as follows:
FLC =
∆Vo = ∆Vo ( ESR ) + ∆Vo ( ESL ) + ∆Vo (C )
1
2 × π × Lo × Co
(20)
∆V0 ( ESR ) = ∆I L × ESR
V −V 
∆V0 ( ESL ) =  in o  × ESL
 L 
∆I L
∆V0 ( C ) =
8 × Co × Fs
Figure 25 shows gain and phase of the LC filter. Since
o
we already have 180 phase shift from the output filter
alone, the system runs the risk of being unstable.
(19)
Where:
ΔV0 = Output Voltage Ripple
ΔIL = Inductor Ripple Current
Since the output capacitor has a major role in the
overall performance of the converter and determines
the result of transient response, selection of the
capacitor is critical. The IR3447 can perform well with
all types of capacitors.
Phase
Gain
0dB
00
-40dB/Decade
-900
-1800
FLC Frequency
FLC
Frequency
Figure 25: Gain and Phase of LC filter
As a rule, the capacitor must have low enough ESR to
meet output ripple and load transient requirements.
The IR3447 uses a voltage-type error amplifier with
high-gain and high-bandwidth. The output of the
amplifier is available for DC gain control and AC
phase compensation.
The goal for this design is to meet the voltage ripple
requirement in the smallest possible capacitor size.
Therefore it is advisable to select ceramic capacitors
due to their low ESR and ESL and small size. Ten of
TDK
C2012X5R0J476M
(47uF/0805/X5R/6.3V)
capacitors is a good choice.
The error amplifier can be compensated either in type
II or type III compensation. Local feedback with Type
II compensation is shown in Figure 26.
It is also recommended to use a 0.1µF ceramic
capacitor at the output for high frequency filtering.
This method requires that the output capacitor have
enough ESR to satisfy stability requirements. If the
output capacitor’s ESR generates a zero at 5kHz to
50kHz, the zero generates acceptable phase margin
and the Type II compensator can be used.
Feedback Compensation
The IR3447 is a voltage mode controller. The control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast
transient response and accurate output regulation, a
compensation circuit is necessary. The goal of the
compensation network is to provide a closed-loop
28
Rev 3.7
The ESR zero of the output capacitor is expressed as
follows:
FESR =
1
2 × π × ESR × Co
(21)
May 17, 2016
IR3447
VO U T
Z IN
R3
C3
R5
R3 =
E /A
R6
C om p
Ve
VR EF
H (s) dB
FZ
Vramp × Fo × FESR × R5
F
P O LE
(26)
2
Vin × β × FLC
Zf
Fb
G ain(dB )
Use the following equation to calculate R3:
C P O LE
Where:
Vin = Maximum Input Voltage
Vramp = Amplitude of the oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
β
= (RS+ - RS-) / Vo
R5 = Feedback Resistor
F requency
To cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency pole:
Figure 26: Type II compensation network and its
asymptotic gain plot
The transfer function (Ve/Vout) is given by:
Z
Ve
1 + sR3C3
= H (s) = − f = −
Vout
Z IN
sR5C3
(22)
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a
gain and zero, expressed by:
(27)
Use equation (24), (25) and (26) to calculate C3.
One more capacitor is sometimes added in parallel
with C3 and R3. This introduces one more pole which
is mainly used to suppress the switching noise.
The additional pole is given by:
R
H ( s) = 3
R5
Fz =
FZ = 75% × FLC
1
FZ = 0.75 ×
2 × π Lo × Co
(23)
Fp =
1
2 × π × R3 × C3
(24)
First select the desired zero-crossover frequency (Fo):
Fo > FESR and Fo ≤ (1 / 5 ~ 1 / 10) × Fs
(25)
1
C × C POLE
2×π × 3
C3 + C POLE
(28)
The pole sets to one half of the switching frequency
which results in the capacitor CPOLE:
CPOLE =
1
1
π × R3 × FS −
C3
≅
1
π × R3 × FS
(29)
For a general unconditional stable solution for any
type of output capacitors with a wide range of ESR
values, we use a local feedback with a type III
compensation
network.
The
typically
used
compensation network for voltage-mode controller is
shown in Figure 27.
29
Rev 3.7
May 17, 2016
IR3447
VOUT
ZIN
C2
C4
R4
R3
Zf
Fb
R6
(34)
FZ 2
(35)
C3
R5
E/ A
Ve
Comp
VREF
1
2π × R3 × C3
1
1
=
≅
2π × C 4 × (R4 × R5 ) 2π × C 4 × R5
FZ 1 =
Cross over frequency is expressed as:
Fo = R3 × C 4 × β ×
Vin
1
×
Vramp 2π × Lo × C o
(36)
Gain (dB)
|H(s)| dB
FZ1
FZ 2
FP2
FP3
Frequency
Figure 27: Type III Compensation network and its
asymptotic gain plot
Again, the transfer function is given by:
Z
Ve
= H ( s) = − f
Vout
Z IN
By replacing Zin and Zf, according to Figure 27, the
transfer function can be expressed as:
H (s) = −
(1 + sR3C3 )[1 + sC4 (R4 + R5 )]

 C × C3 
(1 + sR4C4 )
sR5 (C2 + C3 )1 + sR3  2
 C2 + C3 

(30)
The compensation network has three poles and two
zeros and they are expressed as follows:
FP1 = 0
(31)
1
2π × R4 × C4
1
1
FP 3 =
≅
 C × C3  2π × R3 × C2

2π × R3  2
 C2 + C3 
FP 2 =
30
Rev 3.7
(32)
(33)
Based on the frequency of the zero generated by the
output capacitor and its ESR, relative to the crossover
frequency, the compensation type can be different.
Table 2 shows the compensation types for relative
locations of the crossover frequency.
Table 2: Different types of compensators
Compensator
Type
FESR vs FO
Typical Output
Capacitor
Type II
FLC < FESR < FO <
FS/2
Electrolytic
Type III
FLC < FO < FESR
SP Cap,
Ceramic
The higher the crossover frequency is, the potentially
faster the load transient response will be. However,
the crossover frequency should be low enough to
allow attenuation of switching noise. Typically, the
control loop bandwidth or crossover frequency (Fo) is
selected such that:
Fo ≤ (1/5 ~ 1/10 )* Fs
The DC gain should be large enough to provide high
DC-regulation accuracy. The phase margin should be
o
greater than 45 for overall stability.
The specifications for designing channel 1:
Vin = 12V
Vo = 1.2V
Vramp= 1.8V (This is a function of Vin, pls. see
Feed-Forward section)
Vref = 0.6V
β
= (RS+ - RS-) / Vo (This assumes the resistor
divider placed between Vout and the RSA
scales down the output voltage to Vref. If the
RSA is not used or Vout is connected directly
May 17, 2016
IR3447
Lo
Co
to the RSA, β = 1. Please refer to the Remote
Sensing Amplifier section)
= 0.215 µH
= 10 x 47µF, ESR≈3mΩ each
It must be noted here that the value of the
capacitance used in the compensator design must be
the small signal value. For instance, the small signal
capacitance of the 47µF capacitor used in this design
is 25.7µF at 1.2 V DC bias and 600 kHz frequency. It
is this value that must be used for all computations
related to the compensation. The small signal value
may be obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they may
also be inferred from measuring the power stage
transfer function of the converter and measuring the
double pole frequency FLC and using equation (20) to
compute the small signal Co.
These result to:
FLC = 21.4 kHz
FESR = 2.06 MHz
Fs/2 = 300 kHz
Select crossover frequency F0=100 kHz
R3 =
2 × π × Fo × Lo × C o × Vramp
C 4 × Vin × β
Select: R3 = 1.91 kΩ
C3 =
1
; C3 = 7.5 nF,
2 × π × FZ 1 × R3
Select: C3 = 8.2 nF
C2 =
1
; C2 = 221 pF,
2 × π × FP 3 × R3
Select: C2 = 160 pF
Calculate R4, R5 and R6:
R4 =
1
; R4 = 127.6 Ω,
2 × π × C4 × FP 2
Since FLC<F0<Fs/2<FESR, Type III is selected to place
the pole and zeros.
Select R4 = 127 Ω
Detailed calculation of compensation Type III:
R5 =
Desired Phase Margin Θ = 70°
1 − sin Θ
FZ 2 = Fo
= 17.6 kHz
1 + sin Θ
FP 2 = Fo
1 + sin Θ
= 567.1 kHz
1 − sin Θ
1
; R5 = 4.11 kΩ,
2 × π × C4 × FZ 2
Select R5 = 4.22 kΩ
R6 =
Vref
Vo − Vref
× R5 ; R6 = 4.11 kΩ,
Select R6 = 4.22 kΩ
If (β x Vo) equals Vref, R6 is not used.
Select:
FZ 1 = 0.5 × FZ 2 = 8.8 kHz and
FP 3 = 0.5 × Fs = 300 kHz
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
31
; R3 = 2.37 kΩ,
Rev 3.7
Setting the Power Good Threshold
In this design IR3447, the PGood outer limits are set
at 95% and 120% of VREF. PGood signal is asserted
1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V
(Figure 28). As long as the Vsns voltage is between
the threshold ranges, Enable is high, and no fault
happens, the PGood remains high.
May 17, 2016
IR3447
The following formula can be used to set the PGood
threshold. Vout (PGood_TH) can be taken as 95% of Vout.
Choose Rsns1=4.22 KΩ.
 Vout ( PGood _ TH )

Rsns 2 = 
− 1 × Rsns1
 0.95 × VREF 
(37)
OVP comparator also uses Vsns signal for OverVoltage detection. With above values for Rsns2 and
Rsns1, OVP trip point (Vout_OVP) is
Rev 3.7
(Rsns1 + Rsns2)
Rsns1
(38)
Vout_OVP = 1.44 V
Rsns2 = 4.22 kΩ, Select 4.22 kΩ.
32
Vout _ OVP = VREF × 1.2 ×
Selecting Power Good Pull-Up Resistor
The PGood is an open drain output and require pull
up resistors to VCC. The value of the pull-up resistors
should limit the current flowing into the PGood pin to
less than 5mA. A typical value used is 10kΩ.
May 17, 2016
IR3447
TYPICAL APPLICATION
INTERNALLY BIASED SINGLE SUPPLY
Figure 28: Application circuit for a 12V to 1.2V, 25A Point of Load Converter Using the Internal LDO
Suggested Bill of Material for application circuit 12V to 1.2V
Part Reference
Cpvin1
Cpvin2
Cref
Cvin
Cvcc
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
Qty
1
7
1
1
1
3
1
1
1
10
Value
330uF
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
160pF
47uF
L0
1
0.215uH
Rbd
Rc1
Rc2
Ren1
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
Rpg
1
1
1
1
1
U1
33
Manufacturer
Panasonic
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
Part Number
EEV-FK1E331P
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H161JA01D
C2012X5R0J476M
Cyntec
PCDC1008-R215EMO
20
127
1.91K
7.5K
49.9K
Description
SMD, electrolytic, 25V, 20%
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
0805, 6.3V, X5R, 20%
10.1x7.8x7.3mm,
DCR=0.29mΩ
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3EKF1270V
ERJ-3EKF1911V
ERJ-3EKF7501V
ERJ-3EKF4992V
4
4.22K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4221V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
ERJ-3EKF3922V
ERJ-3EKF1002V
1
IR3447
PQFN 5x6mm
Panasonic
Panasonic
International
Rectifier
Rev 3.7
IR3447MPBF
May 17, 2016
IR3447
EXTERNALLY BIASED DUAL SUPPLIES
Figure 29: Application circuit for a 12V to 1.2V, 21A Point of Load Converter using external 5V VCC
Suggested Bill of Material for application circuit 12V to 1.2V using external 5V VCC
Part Reference
Cpvin1
Cpvin2
Cref
Cvin
Cvcc
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
Qty
1
7
1
1
1
3
1
1
1
10
Value
330uF
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
160pF
47uF
L0
1
0.215uH
Rbd
Rc1
Rc2
Ren1
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
Rpg
1
1
1
1
1
U1
34
Manufacturer
Panasonic
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
Part Number
EEV-FK1E331P
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H161JA01D
C2012X5R0J476M
Cyntec
PCDC1008-R215EMO
20
52.3
1.91K
7.5K
49.9K
Description
SMD, electrolytic, 25V, 20%
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
0805, 6.3V, X5R, 20%
10.1x7.8x7.3mm,
DCR=0.29mΩ
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3EKF52R3V
ERJ-3EKF1911V
ERJ-3EKF7501V
ERJ-3EKF4992V
4
4.22K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4221V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
ERJ-3EKF3922V
ERJ-3EKF1002V
1
IR3447
PQFN 5x6mm
Panasonic
Panasonic
International
Rectifier
Rev 3.7
IR3447MPBF
May 17, 2016
IR3447
EXTERNALLY BIASED SINGLE SUPPLY
Figure 30: Application circuit for a 5V to 1.2V, 21A Point of Load Converter
Suggested bill of material for application circuit 5V to 1.2V
Part Reference
Cpvin1
Cpvin2
Cref
Cvin
Cvcc
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
Qty
1
7
1
1
1
3
1
1
1
10
Value
330uF
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
5.6nF
120pF
47uF
L0
1
0.215uH
Rbd
Rc1
Rc2
Ren1
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
Rpg
1
1
1
1
1
U1
35
Manufacturer
Panasonic
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
TDK
Part Number
EEV-FK1E331P
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H562KA01D
GRM1885C1H121JA01D
C2012X5R0J476M
Cyntec
PCDC1008-R215EMO
20
127
2.8K
21K
41.2K
Description
SMD, electrolytic, 25V, 20%
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
0805, 6.3V, X5R, 20%
10.1x7.8x7.3mm,
DCR=0.29mΩ
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF20R0V
ERJ-3EKF1270V
ERJ-3EKF2801V
ERJ-3EKF2102V
ERJ-3EKF4122V
4
4.22K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4221V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
ERJ-3EKF3922V
ERJ-3EKF1002V
1
IR3447
PQFN 5x6mm
Panasonic
Panasonic
International
Rectifier
Rev 3.7
IR3447MPBF
May 17, 2016
IR3447
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-25A, Fs=600kHz, Room Temperature, No Air Flow
Figure 31: Startup with full load, Enable Signal
CH1:Vin, CH2:Vout, CH3:PGood, CH4:Enable
Figure 32: Startup with full load, VCC signal
CH1:Vin, CH2:Vout, CH3:PGood, CH4:VCC
Figure 33: Vout Startup with Pre-Bias, 1.08V
CH1: Enable, CH2:Vout, CH3:PGood
Figure 34: Recovery from Hiccup
CH2:Vout, CH3:PGood, CH4:Iout
Figure 35: Inductor Switch Node at full load
CH2:SW
Figure 36: Output Voltage Ripple at full load
CH1:Vout
36
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=2.5A-10A, Fs=600kHz, Room Temperature, No air flow
Figure 37: Vout Transient Response, 2.5A to 10.0A step at 2.5A/uSec
CH2:Vout, CH4:Iout (10A/V)
37
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=17.5A-25A, Fs=600kHz, Room Temperature, No air flow
Figure 38: Vout Transient Response, 17.5A to 25A step at 2.5A/uSec
CH2:Vout, CH4:Iout (10A/V)
38
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=25A, Fs=600kHz, Room Temperature, No air flow
Figure 39: Bode Plot with 25A load: Fo=108 kHz, Phase Margin=50.2 Degrees
39
Rev 3.7
May 17, 2016
IR3447
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-25A, Fs=600kHz, Room Temperature, No air flow
Figure 40: Efficiency versus load current
Figure 41: Power Loss versus load current
40
Rev 3.7
May 17, 2016
IR3447
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to perform
with less than expected results.
pins. It is important to place the feedback components
including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use at least one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at
a single point. It is recommended to place all the
compensation parts over the analog ground plane in
top layer.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper
use of power planes and polygons for power
distribution and heat dissipation.
The inductor, input capacitors, output capacitors and
the IR3447 should be as close to each other as
possible. This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at the
PVin pin of IR3447.
The Power QFN is a thermally enhanced package.
Based on thermal performance it is recommended to
use at least a 6-layers PCB. To effectively remove
heat from the device the exposed pad should be
connected to the ground plane using vias. Figure
42a-f illustrates the implementation of the layout
guidelines outlined above, on the IRDC3447 6-layer
demo board.
The feedback part of the system should be kept away
from the inductor and other noise sources.
The critical bypass components such as capacitors for
PVin, Vin and VCC should be close to their respective
- Ground path between
VIN- and VOUT- should
be minimized with
maximum copper
-
Vout
- Bypass caps should be
placed as close as
possible to their
connecting pins
PVin
- Filled vias placed
under PGND and PVin
pads to help thermal
performance.
- Compensation parts
should be placed
as close as possible
to the Comp pins
- Single point connection
between AGND &
PGND, should be placed
near the part and kept
away from noise sources
AGND
PGND
- SW node copper is
kept only at the top
layer to minimize the
switching noise
Figure 42a: IRDC3447 Demo board Layout Considerations – Top Layer
41
Rev 3.7
May 17, 2016
IR3447
Vout
PGND
Figure 42b: IRDC3447 Demo board Layout Considerations – Bottom Layer
PGND
Figure 42c: IRDC3447 Demo board Layout Considerations – Mid Layer 1
Vout
PGND
Figure 42d: IRDC3447 Demo board Layout Considerations – Mid Layer 2
42
Rev 3.7
May 17, 2016
IR3447
Vout
-Feedback and Vsns traces
routing should be kept away from
noise sources
PGND
Remote Sense Traces
- tap output where voltage value is
critical.
- Avoid noisy areas and noise coupling.
- RS+ and RS- lines near each other.
- Minimize trace resistance.
Figure 42e: IRDC3447 Demo board Layout Considerations – Mid Layer 3
PGND
Figure 42f: IRDC3447 Demo board Layout Considerations – Mid Layer 4
43
Rev 3.7
May 17, 2016
IR3447
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices
should be placed to an accuracy of 0.050mm on both
X and Y axes. Self-centering behavior is highly
dependent on solders and processes, and
PCB PAD SIZES (DETAIL 1)
44
Rev 3.7
experiments should be run to confirm the limits of selfcentering on specific processes. For further
information, please refer to “SupIRBuck™ Multi-Chip
Module (MCM) Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note.” (AN1132)
PCB PAD SIZES (DETAIL 2)
May 17, 2016
IR3447
PCB PAD SPACING (DETAIL 1)
45
Rev 3.7
PCB PAD SPACING (DETAIL 2)
May 17, 2016
IR3447
SOLDER RESIST
•
•
IR recommends that the larger Power or Land
Area pads are Solder Mask Defined (SMD).
This allows the underlying Copper traces to be
as large as possible, which helps in terms of
current carrying capability and device cooling
capability.
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on
each edge) than the Solder Mask window, in
order to accommodate any layer to layer
misalignment. (i.e. 0.1mm in X & Y).
46
•
However, for the smaller Signal type leads
around the edge of the device, IR
recommends that these are Non Solder Mask
Defined or Copper Defined.
•
When using NSMD pads, the Solder Resist
Window should be larger than the Copper Pad
by at least 0.025mm on each edge, (i.e.
0.05mm in X & Y), in order to accommodate
any layer to layer misalignment.
•
Ensure that the solder resist in-between the
smaller signal lead areas are at least 0.15mm
wide, due to the high x/y aspect ratio of the
solder mask strip.
SOLDER MASK DESIGN
SOLDER MASK DESIGN
PAD SIZES (DETAIL 1)
PAD SIZES (DETAIL 2)
Rev 3.7
May 17, 2016
IR3447
47
SOLDER MASK DESIGN
SOLDER MASK DESIGN
PAD SPACING (DETAIL 1)
PAD SPACING (DETAIL 2)
Rev 3.7
May 17, 2016
IR3447
STENCIL DESIGN
•
Stencils for PQFN can be used with
thicknesses of 0.100-0.250mm (0.004-0.010”).
Stencils thinner than 0.100mm are unsuitable
because they deposit insufficient solder paste
to make good solder joints with the ground
pad; high reductions sometimes create similar
problems. Stencils in the range of 0.125mm0.200mm
(0.005-0.008”),
with
suitable
reductions, give best results.
48
•
Evaluations have shown that the best overall
performance is achieved using the stencil
design shown in following figure. This design
for a stencil thickness of 0.127mm (0.005”).
The reduction should be adjusted for stencils
of other thicknesses.
SOLDER PASTE STENCIL
SOLDER PASTE STENCIL
PAD SIZES (DETAIL 1)
PAD SIZES (DETAIL 2)
Rev 3.7
May 17, 2016
IR3447
SOLDER PASTE STENCIL
SOLDER PASTE STENCIL
PAD SPACING (DETAIL 1)
PAD SPACING (DETAIL 2)
MARKING INFORMATION
PIN 1
LOGO
PART NUMBER
SITE/DATE/MARKING CODE
3447M
?YWW?
XXXX
LOT CODE
Figure 43: Marking Information
49
Rev 3.7
May 17, 2016
IR3447
PACKAGING INFORMATION
DIMENSION TABLE
SIDE VIEW (Back)
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
A3
A
PIN
1
B
b1
0.20
0.25
0.30
b2
0.30
0.35
0.40
D
5.00 BSC
E
1
SIDE VIEW (Left)
0.203 Ref
L
6.00 BSC
0.30
0.40
aaa
0.05
bbb
0.10
ccc
0.10
N
29
0.50
SIDE VIEW (Right)
TOP VIEW
C
SEATING
PLANE
SIDE VIEW (Front)
1
1
50
Rev 3.7
May 17, 2016
IR3447
ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
5mm x 6mm PQFN
MSL2
Class A
Machine Model
(JESD22-A115A)
<200V
Human Body Model
(JESD22-A114F)
ESD
Charged Device Model
(JESD22-C101D)
Class 1C
≥1000V to <2000V
Class III
≥500V to ≤1000V
RoHS Compliant
Yes
REVISION HISTORY
51
Rev.
Date
3.0
4/29/2013
Initial DR3 Release
3.1
7/17/2013
Update block diagram
Update OVP description
Correct typos and equation
Correct packaging information
Add marking information
3.2
10/3/2013
Correct typos
3.3
4/16/2014
Update ordering options
Correct typos
Correct equation
3.4
7/28/2015
Change MSL
Correct packaging information
3.5
10/29/2015
Correct marking information
3.6
2/5/2016
Update POD, converted to Infineon format
3.7
5/17/2016
Update POD drawings
Rev 3.7
Description
May 17, 2016
IR3447
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2016
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information
regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any
kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the
product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s
technical departments to evaluate the suitability of the product for the intended application and the completeness of the
product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question please
contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives
of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product
or any consequences of the use thereof can reasonably be expected to result in personal injury.
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Rev 3.7
May 17, 2016