AKM AKD4955-A Ak4955 evaluation board rev.3 Datasheet

[AKD4955-A]
AKD4955-A
AK4955 Evaluation Board Rev.3
GENERAL DESCRIPTION
The AKD4955-A is an evaluation board for AK4955, 24bit stereo CODEC with a microphone/ speaker/ video
amplifiers, DSP and LDO. The AKD4955-A has the Digital Audio I/F and can achieve the interface with digital audio
systems via optical connector.
„ Ordering Guide
AKD4955-A
---
AK4955 Evaluation Board
(Cable for connecting with USB Port of PC and control software are packed with this.)
FUNCTION
• DIR/DIT with optical input/output
• BNC connector for an external clock input
DVDD SVDD LVDD AVDD
+5V
3.3V←5V
LDO
(T2)
1.8V←5V
LDO
(T3)
for TVDD
LIN1
AIN
Mini
Jack
3.3V←5V LDO
(T1)
RIN1
LIN2
LIN
RIN2
PIC4550
AK4955
USB
PORT4
(10pin-CTRL)
PORT3
(DSP)
RIN
LOUT
External
Clock
ROUT
Opt In
SPP
SPN
AK4118A
(DIT/DIR)
Mini
Jack
MIN
Opt Out
VOUT VIN
Figure 1.AKD4955-A Block Diagram
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„ Operation Sequence
1)
2)
Set up the Power Supply Lines.
Setup the Audio I/F Evaluation Mode.
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Setting with External Slave Mode.
(1-2) Setting with External Master Mode.
(2) Evaluation of D/A using DIR of AK4118A.
(2-1) Setting with External Slave Mode. < Default >
(2-2) Setting with External Master Mode.
(3) Evaluation of A/D, D/A using PORT3 (DSP).
(3-1) Setting with External Slave Mode.
(3-2) Setting with External Master Mode.
(3-3) Setting with PLL Slave Mode.
(3-4) Setting with PLL Master Mode.
(4) Evaluation of external Loop-back (A/D -> D/A).
(4-1) Setting with External Slave Mode.
(4-2) Setting with External Master Mode.
(4-3) Setting with PLL Slave Mode.
(4-4) Setting with PLL Master Mode.
3)
Jumper pins and SW Setting.
(1) Setting of other jumper pins.
(2) Setting of SW.
4)
Power on.
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1)
Set up the Power Supply Lines.
(1-1) In case of using the regulator. < Default >
JP20
AVDD-SEL
REG
JP23
LVDD-SEL
AVDD
REG
JP25
SVDD-SEL
LVDD
REG
SVDD
JP26
D3V-SEL
REG
D3V
JP21
DVDD-SEL
REG
DVDD
JP24
LVC-SEL
REG
LVC
Figure 2.Setting of jumper pins, when using the regulator.
Name of
Jack
+5V
AVDD
LVDD
SVDD
D3V
DVDD
LVC
AGND
DGND
Color
Default Setting
Using
red
green
green
green
green
green
green
black
black
5V
Open
Open
Open
Open
Open
Open
0V
0V
for regulator.
for AVDD of AK4955
for LVDD of AK4955
for SVDD of AK4955
for AK4118A and digital logic.
for DVDD of AK4955
for TVDD of AK4955 and digital logic.
for analog ground
for digital ground
Table 1.Set up of power supply lines
(1-2) In case of using the power supply connectors.
JP20
AVDD-SEL
REG
JP23
LVDD-SEL
AVDD
REG
JP25
SVDD-SEL
LVDD
REG
SVDD
JP26
D3V-SEL
REG
D3V
JP21
DVDD-SEL
REG
DVDD
JP24
LVC-SEL
REG
LVC
Figure 3.Setting of jumper pins, when using the power supply connectors.
Name of
Jack
+5V
AVDD
LVDD
SVDD
D3V
DVDD
LVC
AGND
DGND
Color
Default Setting
Using
red
green
green
green
green
green
green
black
black
Open
+2.8V ~ +3.6V [typ:+3.3V]
+2.7V ~ +5.5V [typ:+3.3V]
+2.7V ~ +5.5V [typ:+3.3V]
+2.7V ~ +3.6V [typ:+3.3V]
+1.6V ~ +2.0V [typ:+1.8V]
+1.6V ~ +3.6V [typ:+1.8V]
0V
0V
for regulator.
for AVDD of AK4955
for LVDD of AK4955
for SVDD of AK4955
for AK4118A and digital logic.
for DVDD of AK4955
for TVDD of AK4955 and digital logic.
for analog ground
for digital ground
Table 2.Set up of power supply lines (Note 1)
Note 1.Each supply line should be distributed from the power supply unit.
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2)
Setup the Audio I/F Evaluation Mode.
In case of using the AK4118A when evaluating the AK4955, both the AK4955 and AK4118A’s audio interface
formats must be matched.
Refer to the datasheet for AK4955’s audio interface format, and AK4118A’s audio interface format (Table 4).
The AK4118A operates at sampling frequency of 32 kHz or more. If the sampling frequency is slower than 32
kHz, please use other mode.
In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please
use other mode.
Refer to the datasheet for register setting of the AK4955.
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Setting with External Slave Mode
X1 (X’tal) and PORT2 (TOTX) are used. Nothing should be connected to PORT1 (TORX) and PORT3
(DSP).
MCKI, BICK and LRCK are supplied from the AK4118A, and SDTO of the AK4955 is output to the
AK4118A.
In addition, registers of the AK4955 should be set to “External Slave Mode” and setting of AK4118A should
be set to “Master Mode”.
SW4 (M/S) should be set to “ON (H)”.
JP11
BICK-SEL
JP13
LRCK-SEL
JP12
BICK-PHASE
6
2
JP16
MCKI-SEL
4
8
5
DIR
GND
EXT
10pin
10pin
DIR
4040
INV
5
THR
5
4
8
10pin
DIR
4040-32fs
4040-64fs
3
2
4
XTL MCKO
JP10
XTI-SEL
Figure 4.Setting of jumper pins with External Slave Mode
(1-2) Setting with External Master Mode
X1 (X’tal) and PORT2 (TOTX) are used. Nothing should be connected to PORT1 (TORX) and PORT3
(DSP).
MCKI is supplied from the AK4118A, and BICK, LRCK and SDTO of the AK4955 is output to the
AK4118A.
In addition, registers of the AK4955 should be set to “External Master Mode” and setting of AK4118A
should be set to “Slave Mode”.
SW4 (M/S) should be set to “OFF (L)”.
JP13
LRCK-SEL
JP12
BICK-PHASE
6
2
10pin
DIR
4040
INV
5
THR
5
4
8
JP16
MCKI-SEL
4
8
5
DIR
GND
EXT
10pin
JP11
BICK-SEL
10pin
DIR
4040-32fs
4040-64fs
3
2
4
XTL MCKO
JP10
XTI-SEL
Figure 5.Setting of jumper pins with External Master Mode
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(2) Evaluation of D/A using DIR of AK4118A.
(2-1) Setting with External Slave Mode < Default >
PORT1 (TORX) is used. Nothing should be connected to PORT2 (TOTX) and PORT3 (DSP).
MCKI, BICK, LRCK and SDTI are supplied from the AK4118A.
In addition, registers of the AK4955 should be set to “External Slave Mode” and setting of AK4118A should
be set to “Master Mode”.
SW4 (M/S) should be set to “ON (H)”.
JP13
LRCK-SEL
JP12
BICK-PHASE
6
2
5
6
2
JP16
MCKI-SEL
4
8
DIR
ADC
10pin
10pin
DIR
4040
INV
5
THR
5
4
8
JP15
SDTI-SEL
5
DIR
GND
EXT
10pin
JP11
BICK-SEL
10pin
DIR
4040-32fs
4040-64fs
3
2
4
XTL MCKO
JP10
XTI-SEL
Figure 6.Setting of jumper pins with External Slave Mode
(2-2) Setting with External Master Mode
PORT1 (TORX) is used. Nothing should be connected to PORT2 (TOTX) and PORT3 (DSP).
MCKI and SDTI are supplied from the AK4118A, and BICK and LRCK of the AK4955 is output to the
AK4118A.
In addition, registers of the AK4955 should be set to “External Master Mode” and setting of AK4118A
should be set to “Slave Mode”.
SW4 (M/S) should be set to “OFF (L)”.
6
2
10pin
DIR
4040
INV
5
THR
5
4
8
JP15
SDTI-SEL
5
6
2
JP16
MCKI-SEL
4
8
5
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
10pin
DIR
4040-32fs
4040-64fs
3
2
4
XTL MCKO
JP10
XTI-SEL
Figure 7.Setting of jumper pins with External Master Mode
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(3) Evaluation of A/D, D/A using PORT3 (DSP).
(3-1) Setting with External Slave Mode
Registers of the AK4955 should be set to “External Slave Mode”.
SW4 (M/S) should be set to “ON (H)”.
AK4955
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
≥ 32fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 8.External Slave Mode
PORT3 (DSP) is used. Nothing should be connected to PORT1 (TORX) and PORT2 (TOTX).
MCLK, BICK, LRCK, and SDTI are input from PORT3 (DSP) and SDTO of the AK4955 is output to the
PORT3 (DSP).
JP1４
ＭＣＫＩＯ
ＭＣＫＯ
2
ＭＣＫＩ
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
5
6
2
JP16
MCKI-SEL
4
8
5
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 9.Setting of jumper pins with External Slave Mode (Note 2)
Note 2.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
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(3-2) Setting with External Master Mode
Registers of the AK4955 should be set to “External Master Mode”.
SW4 (M/S) should be set to “OFF (L)”.
AK4955
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
32fs or 64fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 10.External Master Mode
PORT3 (DSP) is used. Nothing should be connected to PORT1 (TORX) and PORT2 (TOTX).
MCLK and SDTI are input from PORT3 (DSP) and BICK, LRCK and SDTO of the AK4955 is output to the
PORT3 (DSP).
JP1４
ＭＣＫＩＯ
ＭＣＫＯ
2
ＭＣＫＩ
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
5
6
2
JP16
MCKI-SEL
4
8
5
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 11.Setting of jumper pins with External Master Mode
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(3-3) Setting with PLL Slave Mode
A reference clock of PLL is selected among the input clocks supplied to MCKI pin. The required clock to
the AK4955 is generated by an internal PLL circuit.
SW4 (M/S) should be set to “ON (H)”.
(a) PLL Reference Clock: MCKI pin
Registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: MCKI pin).
BICK and LRCK inputs should be synchronized with MCKO output. However the phase between
MCKO and LRCK dose not matter.
11.2896MHz, 12MHz, 13.5MHz
24MHz, 25MHz, 27MHz
AK4955
DSP or μP
MCKI
MCKO
256fs/128fs/64fs/32fs
≥ 32fs
BICK
BCLK
1fs
LRCK
MCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 12.PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
J10 (EXT) and PORT3 (DSP) are used (Note 3). Nothing should be connected to PORT1 (TORX) and
PORT2 (TOTX).
MCKI is input from J10 (EXT). BICK, LRCK and SDTI are input from PORT3 (DSP). MCKO and
SDTO of the AK4955 is output to the PORT3 (DSP).
JP1４
ＭＣＫＩＯ
ＭＣＫＯ
2
ＭＣＫＩ
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
5
6
2
JP16
MCKI-SEL
4
8
JP18
EXT
5
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 13.Setting of jumper pins with PLL Slave Mode (Note 4)
Note 3.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
Note 4.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
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(b) PLL Reference Clock: BICK pin
Registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: BICK pin).
AK4955
DSP or μP
MCKO
MCKI
32fs, 64fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14.PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
PORT3 (DSP) is used. Nothing should be connected to PORT1 (TORX) and PORT2 (TOTX).
BICK, LRCK and SDTI are input from PORT3 (DSP). SDTO of the AK4955 is output to the PORT3
(DSP).
5
2 6
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
2
JP16
MCKI-SEL
4
8
5
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 15.Setting of jumper pins with PLL Slave Mode (Note 5)
Note 5.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
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(3-4) Setting with PLL Master Mode
The master clock is input from MCKI pin of J10 (EXT). An internal PLL circuit generates MCKO, BICK,
and LRCK.
In addition, registers of the AK4955 should be set to “PLL Master Mode”.
SW4 (M/S) should be set to “ON (H)”.
11.2896MHz, 12MHz, 13.5MHz
24MHz, 25MHz, 27MHz
DSP or μP
AK4955
MCKI
MCKO
256fs/128fs/64fs/32fs
MCLK
32fs, 64fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 16.PLL Master Mode
J10 (EXT) and PORT3 (DSP) are used (Note 6). Nothing should be connected to PORT1 (TORX) and
PORT2 (TOTX).
MCKI is input from J10 (EXT) and SDTI is input from PORT3 (DSP). BICK, LRCK, MCKO and SDTO of
the AK4955 are output to the PORT3 (DSP).
JP1４
ＭＣＫＩＯ
ＭＣＫＯ
2
ＭＣＫＩ
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
5
6
2
JP16
MCKI-SEL
4
8
JP18
EXT
5
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 17.Setting of jumper pins with PLL Slave Mode
Note 6.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
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(4)
Evaluation of external Loop-back (A/D -> D/A).
(4-1) Setting with External Slave Mode.
J10 (EXT) is used (Note 7). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3
(DSP).
MCKI is input from J10 (EXT). BICK and LRCK are generated by on-board divider. SDTI is connected to
SDTO of the AK4955 as loopback.
In addition, registers of the AK4955 should be set to “External Slave Mode”.
SW4 (M/S) should be set to “ON (H)”.
2
4
8
JP17
4040-SEL
5
JP18
EXT
MCKO
6
JP16
MCKI-SEL
MCKI
5
2 6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 18.Setting of jumper pins with External Slave Mode (Note 8, Note 9)
Note 7.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
Note 8.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
Note 9.When BICK of 32fs is used, JP11 (BICK-SEL) should be set to “4040-32fs” side.
(4-2) Setting with External Master Mode.
J10 (EXT) is used (Note 10). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3
(DSP).
MCKI is input from J10 (EXT), SDTI is connected to SDTO of the AK4955 as loopback.
In addition, registers of the AK4955 should be set to “External Master Mode”.
SW4 (M/S) should be set to “OFF (L)”.
2
4
8
JP17
4040-SEL
5
JP18
EXT
MCKO
6
JP16
MCKI-SEL
MCKI
5
2 6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 19.Setting of jumper pins with External Master Mode
Note 10.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
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(4-3) Setting with PLL Slave Mode.
SW4 (M/S) should be set to “ON (H)”.
(a) PLL Reference Clock: MCKI pin
J10 (EXT) is used (Note 11). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3
(DSP).
MCKI is input from J10 (EXT). BICK and LRCK are generated by using on-board divider and MCKO of
the AK4955. SDTI is connected to SDTO of the AK4955 as loopback.
In addition, registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: MCKI pin).
4
8
JP17
4040-SEL
5
JP18
EXT
MCKO
10pin
DIR
4040
2
JP16
MCKI-SEL
MCKI
5
2 6
6
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 20.Setting of jumper pins with PLL Slave Mode (Note 12, Note 13)
Note 11.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
Note 12.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
Note 13.When BICK of 32fs is used, JP11 (BICK-SEL) should be set to “4040-32fs” side.
(b) PLL Reference Clock: BICK pin
PORT3 (DSP) is used. Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and J10 (EXT).
BICK and LRCK are generated by on-board divider which used MCLK from PORT3 (DSP). SDTI is
connected to SDTO of the AK4955 as loopback.
In addition, registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: BICKI pin).
5
6
2
JP16
MCKI-SEL
4
8
JP17
4040-SEL
5
MCKO
MCKO
2
MCKI
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
MCKI
JP14
MCKIO
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 21.Setting of jumper pins with PLL Slave Mode (Note 14, Note 15)
Note 14.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
Note 15.When BICK of 32fs is used, JP11(BICK-SEL) should be set to “4040-32fs” side.
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(4-4) Setting with PLL Master Mode.
J10 (EXT) is used (Note 16). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3
(DSP).
MCKI is input from J10 (EXT), SDTI is connected to SDTO of the AK4955 as loopback.
SW4 (M/S) should be set to “OFF (L)”.
4
8
JP17
4040-SEL
5
JP18
EXT
MCKO
2
JP16
MCKI-SEL
MCKI
5
2 6
6
10pin
DIR
4040
INV
10pin
DIR
4040-32fs
4040-64fs
5
THR
5
4
8
JP15
SDTI-SEL
DIR
GND
EXT
10pin
JP13
LRCK-SEL
JP12
BICK-PHASE
DIR
ADC
10pin
JP11
BICK-SEL
Figure 22.Setting of jumper pins with PLL Master Mode
Note 16.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
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3)
Jumper pins and SW Setting.
(1) Setting of other jumper pins.
[JP6 (LIN-SEL)]: The selection of input signal to LIN1 pin and LIN2 pin.
L1-mini
: Input signal of LIN1 pin is supplied from J1 (AIN). < Default >
L1-BNC
: Input signal of LIN1 pin is supplied from J3 (LIN).
L2-mini
: Input signal of LIN2 pin is supplied from J1 (AIN).
L2-BNC
: Input signal of LIN2 pin is supplied from J3 (LIN). < Default >
[JP7 (RIN-SEL)]: The selection of input signal to RIN1 pin and RIN2 pin.
R1-mini
: Input signal of RIN1 pin is supplied from J1 (AIN). < Default >
R1-BNC
: Input signal of RIN1 pin is supplied from J5 (RIN).
R2-mini
: Input signal of RIN2 pin is supplied from J1 (AIN).
R2-BNC
: Input signal of RIN2 pin is supplied from J5 (RIN). < Default >
[JP8 (MIN-SEL)]: The selection of input mode of MIN pin.
EXT
: “External Resistance Mode”.
INT
: “Internal Resistance Mode”. < Default >
[JP9 (SPK-GND)]: The selection of condition for GND of J9 (SPK-OUT) connector.
Short
: Connect to GND. < Default >
Open
: None connect to GND.
[JP19 (GND)]: Analog ground and Digital ground
Short
: Common. (The connector “DGND” can be open.) < Default >
Open
: Separated.
[JP28 (CTRL-SEL)]: The selection of Serial Control I/F.
USB
: Use U10 (USB) connector. < Default >
10pin
: Use PORT4 (10pin-CTRL).
[JP29 (PIC)]: Not to Use.
[JP100 (MPWR-SEL)]：The selection of MIC-power.
OPEN
: MIC-power is not supplied. < Default >
SHORT
: MIC-power is supplied.
[JP101 (RIN1-SEL)]：The selection of input signal to RIN1 pin.
RIN1
: Connect to analog signal from JP7 (RIN-SEL). < Default >
DMCLK
: Connect to digital microphone clock supply input.
[JP102 (LIN1-SEL)]：The selection of input signal to LIN1 pin.
LIN1
: Connect to analog signal from JP6 (LIN-SEL). < Default >
DMDAT
: Connect to digital microphone data input.
[JP103 (CDTIO/CAD0)]：The selection of input signal to CDTIO/CAD0 pin.
CDTIO
: When I2C pin = “L”, CDTIO is selected. < Default >
CAD0
: When I2C pin = “H”, CAD0 is selected.
[JP104 (CSN/SDA)]：The selection of input signal to CSN/SDA pin.
CSN
: When I2C pin = “L”, CSN is selected. < Default >
SDA
: When I2C pin = “H”, SDA is selected.
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(2) Setting of SW.
Upper-side is “ON(H)” and lower-side is “OFF(L)”.
[SW1] (SW DIP-4): Mode setting for AK4118A.
No.
Name
1
2
3
4
DIF2
DIF1
DIF0
OCKS1
ON (“H”)
OFF (“L”)
Default
ON
OFF
OFF
OFF
See Table 4
See Table 5
Table 3.Mode setting for AK4118A
Mode
DIF2
DIF1
DIF0
DAUX
SDTO
0
1
2
3
4
5
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
6
H
H
L
24bit, Left justified
24bit, Left justified
H/L
I
7
H
H
H
24bit, I2S
24bit, I2S
L/H
I
BICK
I/O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64
I
-128fs
64
I
-128fs
Default
Table 4.Audio I/F Format Setting for AK4118A
OCKS1
L
H
MCKO1
256fs
512fs
Default
Table 5.Master Clock setting for AK4118A
[SW4] (SW DIP-3): Mode setting for AK4955.
No.
Name
ON (“H”)
OFF (“L”)
Default
1
I2C
I2C Bus
3-Wire Serial
OFF
2
CAD0
CAD0 pin = “1”
CAD0 pin = “0”
OFF
3
M/S
When the AK4955 is in
“Slave Mode”.
When the AK4955 is in
“Master Mode”.
ON
Table 6.Mode setting for AK4955
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4)
Power on.
Upper-side is “H” and lower-side is “L”.
[SW2] (DIO-PDN)
: Resets the AK4118A. Keep “H” during normal operation.
The AK4118A should be resets once bringing “L” upon power-up.
[SW3] (PDN)
: Resets the AK4955. Keep “H” during normal operation.
The AK4955 should be resets once bringing “L” upon power-up.
„ Indication for LED
[LED1] (INT0)
: Monitor INT0 pin of the AK4118A.
LED turns on when some error has occurred to AK4118A.
„ Control Port
It is possible to control AKD4955-A via general USB port. Connect cable with the U10 (USB) on board and PC.
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
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■ Analog Input / Output Circuits
1) Input circuit
(1-1) MIC/LINE1, 2 input circuit (except for Digital-MIC circuit).
MPWR
2.2k
2.2k
2.2k
2.2k
MPWR
5
mini-Rch
2
1
mini-Lch
RIN2
LIN2
RIN1
LIN1
J1
AIN
2
3
4
5
J3
LIN
1
L1-mini
L1-BNC
L2-mini
L2-BNC
BNC-Lch
JP100
MPWR-SEL
JP6
LIN1
1u
LIN2
LIN-SEL
2
3
4
5
J5
RIN
1
R1-mini
R1-BNC
R2-mini
R2-BNC
BNC-Rch
1u
JP7
RIN1
1u
RIN2
RIN-SEL
1u
Figure 23.Circuit diagram of MIC/LIN1, 2 input
The MIC/LINE1, 2 inputs are shared with J1, J3 and J5.
Please select the input to be used with JP6 (LIN-SEL) and JP7 (RIN-SEL).
(1-2) Video input circuit.
VIN
2
3
4
5
J2
1
VIN
75
0.1u
Figure 24.Circuit diagram of Video input
(1-3) Monaural input circuit.
1
MIN
1u
33k
+
2
3
4
5
J8
MIN
33k
EXT
INT
JP8
MIN
MIN-SEL
Figure 25.Circuit diagram of Monaural input
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2) Output circuit
+
(2-1) LINE output circuit.
1
LOUT
20k
1
ROUT
1u
20k
2
3
4
5
220
+
1u
J6 LOUT
J7 ROUT
2
3
4
5
220
Figure 26.Circuit diagram of LINE output
(2-2) Video output circuit.
1
VOUT
J4 VOUT
75
2
3
4
5
Figure 27.Circuit diagram of Video output
(2-3) Speaker output circuit.
5
SPN
16
16
(open)
J9
SPK-OUT
2
1
JP9
SPK-GND
SPP
(open)
Figure 28.Circuit diagram of Speaker output
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Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect a PC and an evaluation board.
3. The USB control is recognized as HID (Human Interface Device) on the PC.
It is not necessary to install a new driver.
4. Start up the control program. (Note 17)
Note 17.The AK4955 should be reset by the PDN pin after the power supplies are applied.
After that, “Dummy Command” should be executed.
5. Proceed evaluation by following the process below.
Figure 29.Window of Control Soft
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■ Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper
tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1.
[Port Reset]: Click this button after the control soft starts up.
2.
[Write Default]: Initializes Registers
When the device is reset by a hardware reset, use this button to initialize the registers.
3.
[All Write]: Executes write commands for all registers displayed.
4.
[All Read]: Executes read commands for all registers displayed.
5.
[Save]: Saves current register settings to a file.
6.
[Load]: Executes data write from a saved file.
7.
[All Req Write]: Opens “All Req Write” dialog box.
8.
[Data R/W]: Opens “Data R/W” dialog box
9.
[Sequence]: Opens “Sequence” dialog box.
10.
[Sequence(File)]: Opens “Sequence(File)” dialog box.
11.
[Read]: Reads current register settings and displays on to the register area (on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying register
settings in hexadecimal.
12.
[READ:Disable/Enable]: The register setting of [READ].
READ: Read function enable.
0: Disable < Default >
1: Enable
13.
[Dummy Command]: The dummy command is written (Note 18).
Note 18. The AK4955 should be reset by the PDN pin after the power supplies are applied.
After that, “Dummy Command” should be executed.
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■ Tab Functions
1. [Function]: Function control
This tab is for function.
Each operation is executed by [Function] buttons on the left side of the screen (Note 19, Note 20).
Note 19. Please refer to the following setting when you use the “Function” function.
Mode= “External Slave Mode”, fs= “7.35kHz～48kHz”, Audio I/F Format= “24bit MSB justified”
Note 20. The AK4955 should be reset by the PDN pin after the power supplies are applied.
After that, “Dummy Command” should be executed.
Figure 30.Window of [Function]
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2. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray).
Gray-out registers are Read only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 31.Window of [REG]
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2-1. [Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When the checkbox is checked, the data will be “H” or “1”. When the checkbox is not checked, the data will
be “L” or “0”. Click [OK] to write setting values to the registers, or click [Cancel] to cancel this setting.
Figure 32.Window of [Register Set]
2-2. [Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute a register read.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray).
Please be aware that button statuses will be changed by a Read command.
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3. [Tool]: Testing Tools
Evaluation testing tools are available in this tab.
Click buttons for each testing tool.
Figure 33.Window of [Tool]
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3-1. [Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button in the Test tab to open a repeat test dialog shown below.
Repeat writing test can be executed by this dialog.
Figure 34.Window of [Repeat Test]
[Start] Button
: Starts the repeat test.
A dialog for saving a file of the test result will open when clicking this button.
Name the file.
Test will start after specifying a saving file.
[Close] Button
: Closes this dialog and finishes the process.
[Address] Box
: Data writing address in hexadecimal numbers.
[Start Data] Box
: Start data in hexadecimal numbers.
[End Data] Box
: End data in hexadecimal numbers.
[Step] Box
: Data write step interval.
[Repeat Count] Box : Repeat count of the test writing.
[Up and Down] Box : Data write flow is changed as below.
• Checked
[Example]
Data flow
: Writes in step interval from the start data to the end data and turn back from
the end data to the start data.
Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count.
: [00→01→02→03→04→05→05→04→03→02→01→00] x Repeat Count Number
• Not checked : Writes in step interval from the start data to the end data and finishes writing.
[Example]
Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count.
Data flow
: [00→01→02→03→04→05] x Repeat Count Number
[Sampling Frequency] Box : Selects sampling frequency 44.1 kHz/48 kHz
[Count] Box
: Indicates the count number during a repeat test.
[Lch Level] Box
: Indicates the Lch Level during a repeat test.
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3-2. [Loop Setting]: Loop Dialog
Click [Loop Setting] button in the Tool tab to open loop setting dialog as shown below.
Writing test can be executed.
Figure 35.Window of [Loop]
[OK] Button
[Cancel] Button
[Address] Box
[Start Data] Box
[End Data] Box
[Interval] Box
[Step] Box
[Mode Select] Box
• Checked
: Starts the test.
: Closes the dialog and finishes the process.
: Data writing address in hexadecimal numbers.
: Start data in hexadecimal numbers.
: End data in hexadecimal numbers.
: Data write interval time.
: Data write step interval.
: Mode select check box.
[Example]
Data flow
: Writes in step interval from the start data to the end data and turn back from
the end data to the start data.
Start Data = 00, End Data = 05, Step = 1
: 00→01→02→03→04→05→05→04→03→02→01→00
• Not Checked
[Example]
Data flow
: Writes in step interval from the start data to the end data and finishes writing.
Start Data = 00, End Data = 05, Step = 1
: 00→01→02→03→04→05
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■ Dialog Boxes
1. [All Req Write]: All Reg Write dialog box
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 36.Window of [All Reg Write]
[Open (left)] : Selects a register setting file (*.akr).
[Write]
: Executes register writing by the setting of selected file.
[Write All] : Executes all register writings.
Selected files are executed in descending order.
[Help]
: Opens a help window.
[Save]
: Saves a register setting file assignment. The file name is “*.mar”.
[Open (right)]: Opens a saved register setting file assignment “*. mar”.
[Close]
: Closes the dialog box and finish the process.
~ Operating Suggestions ~
1.
2.
Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
When register settings are changed by [Save] button in the main window, re-read the file to reflect new
register settings.
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2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 37.Window of [Data R/W]
[Address] Box : Input data address in hexadecimal numbers for data writing.
[Data] Box
: Input data in hexadecimal numbers.
[Mask] Box
: Input masks data in hexadecimal numbers.
This is “AND” processed input data.
[Write]
: Writs the data generated from Data and Mask values to the address specified by
“Address” box (Note 21).
[Read]
: Reads data from the address specified by “Address” box (Note 21).
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]
: Closes the dialog box and finishes the process.
Data writing can be cancelled by this button instead of executing a write command.
Note 21.The register map will be updated after executing [Write] or [Read] commands.
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3. [Sequence]: Sequence Dialog Box
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Figure 38.Window of [Sequence]
~ Sequence Setting ~
Set register sequence by following process bellow.
1.
Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use: Not using this address
· Register: Register writing
· Reg(Mask): Register writing (Masked)
· Interval: Taking an interval
· Stop: Pausing the sequence
· End: Finishing the sequence
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2.
Input sequence
[Address] : Data address
[Data]
: Writing data
[Mask]
: Mask
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval] : Interval time
Valid boxes for each process command are shown bellow.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
~ Control Buttons~
The function of Control Button is shown bellow.
[Start]
[Help]
[Save]
[Open]
[Close]
: Executes the sequence
: Opens a help window
: Saves sequence settings as a file. The file name is “*.aks”.
: Opens a sequence setting file “*.aks”.
: Closes the dialog box and finishes the process.
~ Stop of the sequence~
When “Stop” is selected in the sequence, the process is paused and it starts again when [Start] button is clicked
Restarting step number is shown in the “Start Step” box. When finishing the process at the end of sequence,
“Start Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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4. [Sequence(File)]: Sequence Setting File Dialog Box
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 39.Window of [Sequence(File)]
[Open (left)]
[Start]
[Start All]
[Help]
[Save]
[Open(right)]
[Close]
: Opens a sequence setting file (*.aks).
: Executes the sequence by the setting of selected file.
: Executing all sequence settings.
Selected files are executed in descending order.
: Opens a help window.
: Saves a sequence setting file assignment. The file name is “*.mas”.
: Opens a saved sequence setting file assignment “*. mas”.
: Closes the dialog box and finishes the process.
~ Operating Suggestions ~
1. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click
“OK” to continue the process.
Figure 40.Window of [Sequence Pause]
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5. [Power Management Setting]: Power Management Setting Dialog Box
When [Power Management Setting] button is clicked, the window as shown in Figure 41 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 41.Window of [Power Management Setting]
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6. [Audio Mode Setting]: Audio Mode Setting Dialog Box
When [Audio Mode Setting] button is clicked, the window as shown in Figure 42 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 42.Window of [Audio Mode Setting]
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7. [PLL Setting]: PLL Setting Dialog Box
When [PLL Setting] button is clicked, the window as shown in Figure 43 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 43.Window of [PLL Setting]
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8. [ALC Setting]: ALC Setting Dialog Box
When [ALC Setting] button is clicked, the window as shown in Figure 44 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 44.Window of [ALC Setting]
[VOL Read]: When the button is pushed, reading “VOL” register is executed.
Gain: Current volume is displayed in 1.5dB step based on the reading result
of the VOL register value.
Data: The VOL register value is displayed. (HEX)
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9. [Volume Setting]: Volume Setting Dialog Box
When [Volume Setting] button is clicked, the window as shown in Figure 45 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 45.Window of [Volume Setting]
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Volume Control by Slider Menu
The volume can also be changed by writing a value in a dialog box.
The slide bar is moved to the value that written in the dialog box.
The up and down arrow keys to mouse or keyboard to adjust the settings.
Slide bar is
moved to the
selected value
The possible values are
automatically selected.
Figure 46.Volume Slider
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10. [Video Setting]: Video Setting Dialog Box
When [Video Setting] button is clicked, the window as shown in Figure 47 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 47.Window of [Video Setting]
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11. [BEEP Setting]: BEEP Setting Dialog Box
When [BEEP Setting] button is clicked, the window as shown in Figure 48 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 48.Window of [BEEP Setting]
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12. [DSP Setting]: DSP Setting Dialog Box
When [DSP Setting] button is clicked, the window as shown in Figure 49 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 49.Window of [DSP Setting]
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13. [Digital Filter]: Filter Setting Dialog Box
When [Digital Filter] button is clicked, the window as shown in Figure 50 opens.
Refer to the datasheet for register settings of the AK4955.
Figure 50.Window of [Filter Setting]
[F Response]
[Write]
[Register Setting]
[Close]
: The filter characteristic dialog is displayed.
: The calculation of all filters and writing the coefficient are executed.
: “Register Setting for Filter” dialog box is popped up.
: Closing the dialog box and finish the process.
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13-1. Parameter Setting
(1) Please set a parameter of each Filter.
Parameter
Function
Sampling Rate
Sampling frequency (fs)
HPF
Cut Off Frequency
High pass filter cut off frequency
LPF
Cut Off Frequency
Low pass filter cut off frequency
FIL3
Cut Off Frequency
FIL3 cut off frequency
Filter type
Gain
EQ0
Pole Frequency
EQ0 Pole Frequency
Zero-point Frequency
EQ0 Zero-point Frequency
Gain
Gain2
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Band Width
EQ1-5 Gain
Gain
Gain2
Setting Range
7350Hz ≤ fs ≤ 48000Hz
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/20 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
LPF or HPF
-10 ≤ Gain < 0 dB
The selection of filter type
Gain
EQ1-5 Center Frequency
EQ1-5 Band Width
EQ1-5 Gain
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-20 ≤ Gain < +12 dB
0 / +12 / +24 dB
(Note 22)
(Note 23)
0Hz ≤ Center Frequency < (0.497 * fs)
1Hz ≤ Band Width < (0.497 * fs)
-1 ≤ Gain < 3
Table 7.Parameter setting of [Filter Setting]
Note 22.A gain difference is a bandwidth of 3dB from center frequency.
Note 23.When a gain is “-1”, EQ becomes a notch filter.
(2) “LPF Enable”, “HPF Enable”, “HPFAD Enable”, “FIL3 Enable”, “EQ0 Enable”,
“EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter with a check button.
When checked it, Filter becomes ON. When “Notch Filter Auto Correction” is checked, perform
automatic correction of the center frequency of the notch filter is executed.
Figure 51.Filter ON/OFF setting button
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13-2. [Register Setting]: Register Setting for Filter Dialog Box
A register set value is displayed when push a [Register Setting] button. When a value out of a setting
range is set, error message is displayed, and a calculation of register setting is not carried out.
Figure 52.A register setting calculation result
Followings are the cases when a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
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13-3. [F Response]: Filter Plot Dialog Box
A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also
updated.
Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate]
button.
Figure 53.Window of [F Response]
[Frequency Range]
[Update]
[Gain/Phase]
[Log View]
[Close]
: The width of the frequency display is specified.
: It draws in the graph again.
: Switch of “Gain/Phase” display.
: Switch of “Linear/Log” display.
: Closing the dialog box and finish the process.
~ Adjustment of vertical range ~
[Y-axis Ref]
: Display setting of center value.
[Vertical slider]
: Movement of vertical display.
[Horizontal slider] : Adjustment of the horizontal display.
(The left side reduces, and the right side expands. )
<KM104703>
2011/08
- 44 -
[AKD4955-A]
13-4. 5-BandEQ operation on Filter Plot screen
When EQ (1~5) is turning on, a green number is displayed on the Filter Plot dialog box.
This number shows the setting of the center frequency and the gain of each EQ.
The number under the display is operated with the mouse, and it is possible to set the filter characteristic
on this screen.
The center frequency and the gain setting are changed by moving the mouse while left-clicking.
The setting of the bandwidth is changed by moving the mouse while right-clicking.
After operating the mouse
The value of the center frequency
and the gain is updated.
The number is selected.
The movement operation is done
while left-clicking.
Figure 54.Filter Setting (Left-clicking operation)
After operating the mouse
The value of the bandwidth is updated.
Figure 55.Filter Setting (Right-clicking operation)
<KM104703>
2011/08
- 45 -
[AKD4955-A]
13-5. Simulation of Fil3 Filter
Setting of Stereo-MIC
[L-ch Level]/[R-ch Level] : The level of the MIC input is input.
[Distance]
: The distance between the sound source and the MIC is set.
[Angle]
: The angle between the sound source and the MIC is set.
Figure 56.Simulation of Fil3 Filter
<KM104703>
2011/08
- 46 -
[AKD4955-A]
13-6. about “Notch Auto Correct”
If the gain of 5-Band EQ is set to “-1”, Equalizer becomes a notch filter.
When the center frequency of two or more notch filters is adjacent, the gap is generated in the center
frequency. When “Notch Auto Correct” button is checked, the center frequency of the notch filter is
automatically corrected. The gain setting of the automatic correction function is effective and only EQ of
“-1” is effective. (Note 24)
Note 24.There is a possibility that the automatic compensation is not correctly done
when the width of the center frequency is smaller than that of the bandwidth setting.
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4)
Figure 57. “Notch Auto Correct” function is “OFF”
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4)
Figure 58. “Notch Auto Correct” function is “ON”
<KM104703>
2011/08
- 47 -
[AKD4955-A]
Measurement Result
[Measurement condition]
• Measurement Unit
• MCLK
• BICK
• fs
• Bit
• Power Supply
• Band Width
• Measurement Mode
• Temperature
: Audio Precession System Two Cascade
: 12.2880MHz
: 64fs
: 48 kHz
: 24bit
: AVDD = LVDD = SVDD = 3.3V, DVDD = TVDD = 1.8V
: 20 Hz ~ 20 kHz
: External Slave Mode
: Room Temperature
[Measurement Result]
1. ADC
a). LIN1/RIN1 pins, MGAIN bits = “+18dB”
Parameter
Lch
S/(N+D)
(-1dBFS Input)
D-Range
(-60dB Input, A-weighted)
S/N
(No Signal, A-weighted)
Result
/
Rch
Unit
81.0
/
81.5
dB
88.8
/
88.7
dB
88.7
/
88.7
dB
b). LIN2/RIN2 pins, MGAIN bits = “0dB”
Parameter
Lch
S/(N+D)
(-1dBFS Input)
D-Range
(-60dB Input, A-weighted)
S/N
(No Signal, A-weighted)
Result
/
Rch
Unit
81.7
/
82.2
dB
97.7
/
97.8
dB
98.0
/
97.8
dB
2. DAC
a). LOUT/ROUT pins, LVCM bits = “01”, RL=10kΩ
Parameter
Lch
S/(N+D)
(-3dBFS Input)
S/N
(No Signal, A-weighted)
b). SPP/SPN pins, SPKG bits = “01”, RL=8Ω
Parameter
S/(N+D)
(-0.5dBFS Input)
S/N
(No Signal, A-weighted)
<KM104703>
Result
/
Rch
Unit
87.5
/
87.6
dB
92.6
/
92.5
dB
Result
Unit
80.5
dB
96.7
dB
2011/08
- 48 -
[AKD4955-A]
PLOT DATA
1-a). ADC [LIN1/RIN1 pins, MGAIN = “+18dB”]
AKM
AK4955 S/(N+D) vs. Input Level [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
-70
-72
-74
-76
-78
-80
-82
d
B
F
S
-84
-86
-88
-90
-92
-94
-96
-98
-100
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 59.S/(N+D) vs. Input Level
AKM
AK4955 S/(N+D) vs. Input Frequency [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
-70
-72
-74
-76
-78
-80
-82
d
B
F
S
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 60.S/(N+D) vs. Input Frequency
<KM104703>
2011/08
- 49 -
[AKD4955-A]
AKM
AK4955 Linearity [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
+0
T
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 61.Linearity
AKM
AK4955 Frequency Response [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
-0.5
-0.55
-0.6
-0.65
-0.7
-0.75
-0.8
-0.85
-0.9
d
B
F
S
-0.95
-1
-1.05
-1.1
-1.15
-1.2
-1.25
-1.3
-1.35
-1.4
-1.45
-1.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 62.Frequency Response
<KM104703>
2011/08
- 50 -
[AKD4955-A]
AKM
AK4955 Crosstalk [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
-70
TTTTTTTTTT
TT
TTTTTTTTT
TT TT T TT
T
TT
T T
T
T
T TT T
T TT
TT
TT
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 63.Crosstalk
AKM
AK4955 FFT (-1dBFS Input) [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 64.FFT (-1dBFS Input)
<KM104703>
2011/08
- 51 -
[AKD4955-A]
AKM
AK4955 FFT (-60dBFS Input) [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 65.FFT (-60dBFS Input)
AKM
AK4955 FFT (No Signal Input) [ ADC, LIN1/RIN1 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+18dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 66.FFT (No Signal Input)
<KM104703>
2011/08
- 52 -
[AKD4955-A]
1-b). ADC [LIN2/RIN2 pins, MGAIN = “0dB”]
AKM
AK4955 S/(N+D) vs. Input Level [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
-70
-72
-74
-76
-78
-80
-82
d
B
F
S
-84
-86
-88
-90
-92
-94
-96
-98
-100
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 67.S/(N+D) vs. Input Level
AKM
AK4955 S/(N+D) vs. Input Frequency [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
-70
-72
-74
-76
-78
-80
-82
d
B
F
S
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 68.S/(N+D) vs. Input Frequency
<KM104703>
2011/08
- 53 -
[AKD4955-A]
AKM
AK4955 Linearity [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 69.Linearity
AKM
AK4955 Frequency Response [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
-0.5
-0.55
-0.6
-0.65
-0.7
-0.75
-0.8
-0.85
-0.9
d
B
F
S
-0.95
-1
-1.05
-1.1
-1.15
-1.2
-1.25
-1.3
-1.35
-1.4
-1.45
-1.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 70.Frequency Response
<KM104703>
2011/08
- 54 -
[AKD4955-A]
AKM
AK4955 Crosstalk [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
-70
T
T T T TT
T TT
T
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 71.Crosstalk
AKM
AK4955 FFT (-1dBFS Input) [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 72.FFT (-1dBFS Input)
<KM104703>
2011/08
- 55 -
[AKD4955-A]
AKM
AK4955 FFT (-60dBFS Input) [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 73.FFT (-60dBFS Input)
AKM
AK4955 FFT (No Signal Input) [ ADC, LIN2/RIN2 ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 74.FFT (No Signal Input)
<KM104703>
2011/08
- 56 -
[AKD4955-A]
2-a). DAC [LOUT/ROUT pins, LVCM(1-0) bits = “01”]
AKM
AK4955 THD+N vs. Input Level [ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
-70
-72
-74
-76
-78
-80
-82
d
B
r
-84
-86
A
-88
-90
-92
-94
-96
-98
-100
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Figure 75.S/(N+D) vs. Input Level
AKM
AK4955 THD+N vs. Input Frequency [ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
-70
-72
-74
-76
-78
-80
-82
d
B
r
-84
-86
A
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 76.S/(N+D) vs. Input Frequency
<KM104703>
2011/08
- 57 -
[AKD4955-A]
AKM
AK4955 Linearity [ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 77.Linearity
AKM
AK4955 Frequency Response [ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
-2.5
-2.6
-2.7
-2.8
-2.9
d
B
r
-3
A
-3.1
-3.2
-3.3
-3.4
-3.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 78.Frequency Response (Pin Direct)
<KM104703>
2011/08
- 58 -
[AKD4955-A]
AKM
AK4955 Crosstalk [ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
-70
T T T
TTT
TTT
T TTTT T T TT
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 79.Crosstalk
AKM
AK4955 FFT (-3dBFS Input)[ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 80.FFT (-3dBFS Input)
<KM104703>
2011/08
- 59 -
[AKD4955-A]
AKM
AK4955 FFT (-60dBFS Input)[ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 81.FFT (-60dBFS Input)
AKM
AK4955 FFT (No Signal Input)[ DAC, LineOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, LVCMbit="01", RL=10kohm
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 82.FFT (No Signal Input)
<KM104703>
2011/08
- 60 -
[AKD4955-A]
2-b). DAC [SPP/SPN pins, SPKG(1-0) bits = “01”]
AKM
AK4955 THD+N vs. Input Level [ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
-70
-72
-74
-76
-78
-80
-82
d
B
r
-84
-86
A
-88
-90
-92
-94
-96
-98
-100
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Figure 83.S/(N+D) vs. Input Level
AKM
AK4955 THD+N vs. Input Frequency [ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
-60
-62
-64
-66
-68
-70
-72
-74
-76
d
B
r
A
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 84.S/(N+D) vs. Input Frequency
<KM104703>
2011/08
- 61 -
[AKD4955-A]
AKM
AK4955 Linearity [ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 85.Linearity
AKM
AK4955 Frequency Response [ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
+0
-0.1
-0.2
-0.3
-0.4
d
B
r
-0.5
A
-0.6
-0.7
-0.8
-0.9
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 86.Frequency Response
<KM104703>
2011/08
- 62 -
[AKD4955-A]
AKM
AK4955 FFT (-0.5dBFS Input)[ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 87.FFT (-0.5dBFS Input)
AKM
AK4955 FFT (-60dBFS Input)[ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 88.FFT (-60dBFS Input)
<KM104703>
2011/08
- 63 -
[AKD4955-A]
AKM
AK4955 FFT (No Signal Input)[ DAC, SPKOUT ]
AVDD=LVDD=SVDD=3.3V, DVDD=TVDD=1.8V, fs=48kHz, External Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 89.FFT (No Signal Input)
<KM104703>
2011/08
- 64 -
[AKD4955-A]
3. VIDEO PLOT DATA
[Measurement condition]
• Measurement unit
• Power Supply
• Temperature
• Input Level
• VG bits
: Tektronix VM700T Video Measurement set
: AVDD = LVDD = SVDD = 3.3V, DVDD = TVDD = 1.8V
: Room Temperature
: 1.0Vpp Input
: “00” (+6dB)
・S/N
• Input signal
: 0% Flat Field
• Measurement Frequency : 100kH ∼ 6MHz
Figure 90.Noise Spectrum
<KM104703>
2011/08
- 65 -
[AKD4955-A]
・DC
• Input signal
: Field Square Wave
Figure 91.Field Time Distortion
<KM104703>
2011/08
- 66 -
[AKD4955-A]
・Vector
• Input signal
: 75% Color Bar
Figure 92.Vector
<KM104703>
2011/08
- 67 -
[AKD4955-A]
Revision History
Date
(YY/MM/DD)
11/08/24
Manual
Revision
KM104703
Board
Revision
3
Reason
Page
First edition
-
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products.
You are fully responsible for the incorporation of these external circuits, application circuits, software and other
related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by
you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of
any patent, intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
<KM104703>
2011/08
- 68 -
1
49
50
51
52
53
54
55
56
2
57
58
59
60
64
CN4
64pin
61
3
62
4
63
5
D
D
0
0
R102
R103
MCKI
51
B5
LRCK
51
A5
B4
4
5
TP114
LRCK
6
TP116
BICK
R114
R115
R117
8
TP118
DVDD
9
TP120
VSS2
10
TP122
TVDD
0
LIN1
RIN1
LIN2
RIN2
DMDAT
JP102
LIN1-SEL
R106
2.2k
2.2k
2.2k
2.2k
C109
0.1u
BICK
VSS3
F5
DVDD
LVDD
D5
VCOM
F4
C115
0.1u
VSS1
E4
REGFIL
F3
MIN
A4
VSS2
B3
TVDD
A3
U100
AK4955ECB
SDTO
39
TP123
REGFIL
38
C3
TP124
MIN
37
TP126
VSS1A
36
TP127
AVDD
35
+ C113
2.2u
C112
0.1u
C116
2.2u
C117
0.1u
C118
10u
B
PVEE
34
33
F1
VSS1
E1
C2
C120
2.2u
R122
C121
R121
C122
(open)
TP133
PVEE
TP131
VOUT
C119
(open)
75
TP130
VIN
0.1u
I2C
VIN
D1
TP132
PDN C1
D2
C110 + C111
0.1u
10u
64pin
0
TP135
CCLK/SCL
TP134
CAD0
SDA
CSN
JP104
CSN/SDA
64pin
VOUT
E2
PDN
VSS1
AVDD
TP137
I2C
TP129
CDTIO/SDA
C
42
40
CDTIO/CAD0
TP136
CSN
16
CDTIO
15
43
C106 + C107
0.1u
10u
TP121
VSS1B
MCKO
CSN/SDA
0
44
TP115
VSS3
41
B2
B1
R120
CAD0
14
TP128
MCKO
TP113
SVDD
TP119
VCOM
F2
JP103
CDTIO/CAD0
13
B
46
TP117
LVDD
A2
CCLK/SCL
51
A1
12
R119
47
TP112
SPN
F6
SPP
SPN
E5
E3
R108
R111
R109
R110
1u
D4
D6
LIN1
RIN2
D3
LIN2
C5
C6
E6
100k
+ C108
10u
48
TP102
SPP
45
SVDD
11
TP125
SDTO
CN3
100k
R116
7
MPWR
A6
RIN1
100k
ROUT
R118
51
C4
R113
LOUT
TP104
MCKI
SDTI
3
B6
2
C
JP100
MPWR-SEL
TP111
MPWR
1u
C105
51
CN6
1
TP110
LIN1
VSS1
LIN1
1u
DMCLK
TP108 JP101
LIN2
RIN1-SEL C103
TP109
RIN2
C104
RIN1
R105
(short)
C101
1u
R107
C102
TP106
SDTI
2
1
TP103
RIN1
1
1
CN5
TP100
DMCLK
TP101
DMDAT
+
CN1
CN7
(open)
0
R101
TP107
LOUT
VSS1
TP105
ROUT
C100
R104
(short)
(open)
0
R100
Digital MIC
75
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
CN2
64pin
17
TP138
VSS1C
R123
A
A
Title
5
4
- 69 3
Size
A2
Date:
2
Document Number
AKD4955-A
Rev
AKD4955-A-36CSP-SUB
Monday, November 29, 2010 Sheet
1
1
of
13
1
LIN2
LIN1
E
RIN2
D
RIN1
C
ROUT
B
LOUT
A
49
50
51
52
53
54
55
56
57
58
59
60
61
62
CN4
64pin
63
E
64
E
D
D
CN3
48
CN1
AK4955-SDTI
AK4955-MCKI
1
47
SPP
2
46
SPN
3
45
4
44
AK4955-LRCK
5
43
AK4955-BICK
6
42
7
41
DVDD
8
40
9
39
TVDD
10
38
11
37
12
36
13
35
14
34
C
AK4955-SDTO
AK4955-MCKO
15
B
SVDD
LVDD
C
MIN
AVDD
33
B
64pin
CDTIO/SDA
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
CN2
64pin
17
64pin
A
B
- 70 C
VOUT
VIN
PDN
I2C
CSN
CCLK/SCL
A
CAD0
A
Title
Size
A2
Date:
D
AKD4955-A
Document Number
Rev
Under the Sub-Board
Monday, November 29, 2010 Sheet
E
1
of
6
13
A
B
5
2
1
D
E
TP41
mini-Rch
TP40
mini-Lch
E
VIN
C24
+
J1
AIN
E
C
(short)
1
J2 VIN
2
3
4
5
R24
(open)
D
2
3
4
5
1
JP6
L1-mini
L1-BNC
L2-mini
L2-BNC
TP42
BNC-Lch
LIN1
LIN2
LIN-SEL
J5
RIN
1
R1-mini
R1-BNC
R2-mini
R2-BNC
TP43
BNC-Rch
VOUT
C25
+
J3
LIN
(short)
R25
(short)
1
C26
(open)
JP7
J4 VOUT
2
3
4
5
C27
(open)
D
RIN1
RIN2
RIN-SEL
LOUT
C28
+
2
3
4
5
1u
R26
220
1
J6 LOUT
2
3
4
5
R27
20k
C
ROUT
1
TP44
MIN C30
1u
R30
33k
R31
33k
+
2
3
4
5
J8
MIN
EXT
INT
C29
+
C
1u
R28
JP8
220
1
J7 ROUT
R29
20k
2
3
4
5
MIN
MIN-SEL
B
B
5
SPP
R63
16
R32
16
C31
(open)
J9
SPK-OUT
2
1
JP9
SPK-GND
SPN
C32
(open)
A
A
Title
Size
A3
- 71 A
B
C
Date:
D
Document Number
AKD4955-A
Rev
Input/Output
Monday, November 29, 2010
Sheet
E
13
2
of
6
A
L1
GND
OUT
2
1
C33
0.1u
47u
2
D3V
D3V
C34
10u
+
E
TORX
51
TP45
RX
C35
+
R33
C36
D
1
IPS0/RX4
2
0.1u
40
39
10k
R
VCOM
41
VSS3
42
RX0
43
NC
44
RX1
45
TEST1
46
RX2
RX3
VSS4
47
48
R34
C37
0.47u
10u
37
3
E
INT1
VCC
D
38
E
1
C
AVDD
PORT1
B
INT0
36
NC
OCKS0/CSN/CAD0
35
3
DIF0/RX5
OCKS1/CCLK/SCL
34
OCKS1
4
TEST2
CM1/CDTI/SDA
33
D3V
5
DIF1/RX6
CM0/CDTO/CAD1
32
6
VSS1
PDN
31
D
8
7
6
5
D3V
INT0
DIF2
DIF1
DIF0
OCKS1
1
2
3
4
L
U2
OCKS1
7
AK4118A
DIF2/RX7
XTI
30
C38 5p
X1
12.288MHz
C39 5p
27
11
XTL1
BICK
26
12
VIN/GP0
SDTO
25
VSS2
MCKO
C
DAUX
DIR-BICK
DIR-SDTO
LRCK
MCKO2
MCKO1
XTL0
DVDD
10
VOUT/GP7
28
UOUT/GP6
DAUX
COUT/GP5
P/SN
BOUT/GP4
9
TX1/GP3
29
TX0/GP2
XTO
NC/GP1
47k
IPS1/IIC
TVDD
RP1
8
MCKO
XTL
XTI-SEL
5
4
3
2
1
C
DIO-PDN
JP10
1
SW1
2
H
24
23
22
21
20
19
18
17
16
15
14
B
13
B
PORT2
A
IN
VCC
3
2
GND
1
+
D3V
C41
0.1u
+
DIR-LRCK
C40
0.1u
C42
10u
C43
10u
DIR-MCKI
TP46
TX
C44
0.1u
A
D3V
Title
TOTX
Size
- 72 A
B
C
A3
Date:
D
Document Number
AKD4955-A
DIR/DIT
Monday, November 29, 2010
Rev
13
Sheet
E
3
of
6
A
B
C
D
U3
10
E
Q1
Q2
RST
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
VD
Q11
DGND Q12
D3V
16
8
C45
0.1u
U4
CLK
11
E
9
7
6
5
3
2
4
13
12
14
15
1
DIR-BICK
DIR-LRCK
4040
DIR
10pin
JP11
4040-64fs
4040-32fs
DIR
10pin
THR
INV
BICK-SEL
JP13
E
JP12
4
1A1
1B1
13
5
1A2
1B2
12
2
1DIR
1OE
15
6
2A1
2B1
11
7
2A2
2B2
10
3
2DIR
2OE
14
1
VCCA
VCCB
16
AK4955-BICK
BICK-PHASE
LRCK-SEL
M/S
AK4955-LRCK
74HC4040
D3V
D3V
C49
0.1u
1A
1Y
2A
2Y
3A
3Y
GND
D3V
14
13
12
11
10
9
8
VCC
6A
6Y
5A
5Y
4A
4Y
㪧㪦㪩㪫㪊
C48
0.1u
INT0
R36
74HC14
1k 2
LE1
9
7
5
3
1
SDTO
SDTI
LRCK
BICK
MCLK
8
GND
DSP
1
GND
9
D
LVC
C47
0.1u
74AVC4T245
INT0
JP14
MCKIO
DIO-PDN
LVC
U6
C
1
D2
HSU119
3
A
K
C
10
8
6
4
2
C46
0.1u
MCKI
1
2
3
4
5
6
7
H
2
L
SW2
DIO-PDN
U5
R35
10k
MCKO
1
D1
HSU119
3
A
K
D
U7
1
2
3
4
5
6
7
H
C51
0.1u
2
L
SW3
PDN
PDN
R37
10k
1A
1Y
2A
2Y
3A
3Y
GND
MCKO
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
4
1A1
1B1
13
AK4955-MCKO
5
1A2
1B2
12
AK4955-SDTO
2
1DIR
1OE
15
6
2A1
2B1
11
7
2A2
2B2
10
3
2DIR
2OE
14
1
VCCA
VCCB
16
LVC
C50
0.1u
DAUX
74HC14
DIR-SDTO
10pin
ADC
DIR
JP15
SDTI-SEL
B
2
3
4
5
MCKO
MCKI
JP17
4040-SEL
J10
EXT
1
R38
51
DIR-MCKI
10pin
EXT
GND
DIR
JP16
D3V
MCKI-SEL
C52
0.1u
8
JP18
EXT
GND
GND
9
AK4955-SDTI
AK4955-MCKI
B
LVC
C53
0.1u
74AVC4T245
SW4
H
3
2
1
M/S
CAD0
I2C
A
3
2
1
A
M/S
CAD0
I2C
L
4
5
6
LVC
Title
RP2 47k
Size
A3
- 73 A
B
C
Date:
D
Document Number
AKD4955-A
Rev
CLOCK & SW
Monday, November 29, 2010
Sheet
E
13
4
of
6
A
B
C
D
E
E
E
R39
4.7k
10
8
6
4
2
C54 2.2u
PORT4
9
7
5
3
1
CSN
CCLK/SCL
CDTI/SDA
CDTO/SDA(ACK)
10pin-CTRL
U8
10k
10k
10k
10k
PIC
TP47
RD0
TP49
RD2
TP51
RD4
TP53
RD6
1
2
3
4
R54
R55
USB(B type)
0
0
USB
7
USB
VDD0
VSS0
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
38
39
40
41
2
3
4
5
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
18
USB-RST
R47
100k
12
13
33
34
OSC1/CLKI
OSC2/CLKO/RA6
30
31
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
25
26
27
VUSB
37
C65
470n
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
19
20
21
22
23
24
R51
R50
R52
R53
51
51
51
51
U9
32
35
36
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
42
43
44
1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
R44
470
R45
470
R46
470
CTRL-SEL
C60
0.1u
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
PIC18F4550
TQFP 44-PIN
10pin
CSN
10pin
CCLK/SCL
10pin
CDTI/SDA
10pin
CDTO/SDA(ACK)
USB
MCLR_N/Vpp/RE3
17
16
15
14
11
10
9
8
JP28
USB
C58
0.1u
6
28
VSS2
VDD1
C57
0.1u
29
1
2
3
4
5
U10
VUSB
DD+
GND
C56
10u
VSS1
JP29
TP48
RD1
TP50
RD3
TP52
RD5
TP54
RD7
B
+
C
SILK-SCREEN(P1)
1:VDD
2:MCLR
3:PGD
4:PGC
5:GND
+
VSS2
C59 1u
C55
10u
4
1A1
1B1
13
5
1A2
1B2
12
2
1DIR
1OE
15
6
2A1
2B1
11
7
2A2
2B2
10
3
2DIR
2OE
14
1
VCCA
VCCB
16
CSN
D
CCLK/SCL
R40
R41
R43
R42
5V => 3.3V
NC
NC
Vin
Vout
Vcont PCL
NC
GND
8
7
6
5
D
T1
TK73633AME
1
2
3
4
D3V
D3V
C61
0.1u
8
XTI
XTO
C63
GND
GND
22p
CDTIO/SDA
LVC
C62
0.1u
9
C
74AVC4T245
X2
20MHz
C64
22p
LVC
R48
1k
R49
100
U11
CSN
CCLK/SCL
CDTI/SDA
CDTO/SDA(ACK)
D3V
1
3
5
9
11
13
1A
2A
3A
4A
5A
6A
14
Vcc
C66
0.1u 7
PIC18F4550
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
B
GND
74LVC07
A
A
Title
Size
- 74 A
B
C
A3
Date:
D
AKD4955-A
Document Number
Rev
uP-I/F
Monday, November 29, 2010 Sheet
E
13
5
of
6
B
C
D
E
JP19
GND
E
8
7
6
5
T2
TK73633AME
NC
NC
Vin
Vout
Vcont PCL
NC
GND
5V => 3.3V
C68
1u
1
2
3
4
REG
J14
AVDD
C69
2.2u
AVDD
JP20
R57
(short)
AVDD
AVDD-SEL
C70
1u
T3
TK73618AME
NC
NC
Vin
Vout
Vcont PCL
NC
GND
5V => 1.8V
1
2
3
4
REG
J15
DVDD
C71
2.2u
DVDD
TP56
GND2
TP57
GND3
E
TP58
GND4
D
JP21
R56
(short)
R58
(short)
DVDD
DVDD-SEL
REG
J17
LVDD
C73
47u
+
C72
47u
+
LVDD
JP23
R59
(short)
TVDD
LVDD
C
LVDD-SEL
1
C
8
7
6
5
TP55
GND1
1
D
C67
47u
1
+
J13
AGND
1
J12
DGND
1
J11
+5V
1
A
C75
47u
+
REG
J18
LVC
J19
SVDD
(short)
LVC
JP25
R61
(short)
SVDD
SVDD-SEL
C76
47u
+
B
1
B
SVDD
R60
LVC-SEL
1
REG
LVC
JP24
C77
47u
+
REG
D3V
R62
(short)
D3V
D3V-SEL
1
J20
D3V
JP26
+
C78
47u
A
A
Title
Size
- 75 A
B
C
A3
Date:
D
AKD4955-A
Document Number
Rev
Power Supply
Monday, November 29, 2010 Sheet
E
1
3
6
of
6
AKD4955-A Rev.3
部品面シルク図
3
- 76 -
AKD4955-A Rev.3
半田面シルク図
- 77 -
AKD4955-A Rev.3
部品面パターン図
- 78 -
AKD4955-A Rev.3
内層L2パターン図
- 79 -
AKD4955-A Rev.3
内層L3パターン図
- 80 -
AKD4955-A Rev.3
内層L4パターン図
- 81 -
AKD4955-A Rev.3
内層L5パターン図
- 82 -
AKD4955-A Rev.3
半田面パターン図
- 83 -
AKD4955-A Rev.3 部品面シルク図
3
- 84 -
AKD4955-A Rev.3 半田面シルク図
- 85 -
AKD4955-A Rev.3 部品面パターン図
- 86 -
AKD4955-A Rev.3 内層L2パターン図
- 87 -
AKD4955-A Rev.3 内層L3パターン図
- 88 -
AKD4955-A Rev.3 半田面パターン図
- 89 -