Holt HI-8589CJTF-10 Arinc 429 transmitter with line driver and dual receiver Datasheet

HI-8581, HI-8589
ARINC 429
Transmitter with Line Driver and Dual Receivers
The HI-8581 and HI-8589 from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. Both
devices provide two receivers, an independent transmitter
and line driver capability in a single package. The receiver
input circuitry and logic are designed to meet the
ARINC 429 specifications for loading, level detection,
timing, and protocol. The transmitter section provides the
ARINC 429 communication protocol and the line driver
circuits provide the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces
with CMOS and TTL.
The HI-8581 has 37.5 ohms in series with each line driver
output. The HI-8589 provides the option to bypass most of
the internal output resistance so that external series
resistance may be added for lighting protection and still
match the 75 ohm characteristic impedance of the ARINC
bus.
Each independent receiver monitors the data stream with
a sampling rate 10 times the data rate. The sampling rate
is software selectable at either 1MHz or 125KHz. The
results of a parity check are available as the 32nd ARINC
bit. The HI-8581 and HI-8589 examine the null and data
timings and will reject erroneous patterns. For example,
with a 125 KHz clock selection, the data frequency must
be between 10.4 KHz and 15.6 KHz.
• ARINC specification 429 compliant
• Direct receiver and transmitter interface to ARINC
bus in a single device
• 16-Bit parallel data bus
• Timing control 10 times the data rate
• Selectable data clocks
• Receiver error rejection per ARINC 429 standard
• Automatic transmitter data timing
• Self test mode
• Parity functions
• Low power
• Industrial & extended temperature ranges
PIN CONFIGURATION (Top View)
429DI2(B) - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-8581PQI
HI-8589PQI
&
HI-8581PQT
HI-8589PQT
33 - ENTX
32 - N/C
31 - V+
30 - TXB(OUT)
29 - TXA(OUT)
28 - V27 - GND
26 - TX/R
25 - PL2
24 - PL1
23 - BD00
BD10 - 12
BD09 - 13
BD08 - 14
BD07 - 15
BD06 - 16
GND - 17
BD05 - 18
BD04 - 19
BD03 - 20
BD02 - 21
BD01 - 22
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of
the transmitter is software selectable by dividing the
master clock, CLK, by either 10 or 80. The master clock is
used to set the timing of the ARINC transmission within the
required resolution.
FEATURES
- 429DI2(A)
- 429DI1(B)
- 429DI1(A)
- VCC
- N/C
- MR
- TXCLK
- CLK
- N/C
- N/C
- CWSTR
GENERAL DESCRIPTION
44
43
42
41
40
39
38
37
36
35
34
August 2013
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 12 for additional pin configurations)
• Parallel to serial conversion
HOLT INTEGRATED CIRCUITS www.holtic.com
(DS8581 Rev. J)
08/13
HI-8581, HI-8589
PIN DESCRIPTION
SIGNAL
FUNCTION
DESCRIPTION
VCC
POWER
+5V ±5%
V+
POWER
+9.5V to +10.5V
V-
POWER
429DI1 (A)
INPUT
ARINC receiver 1 positive input
-9.5V to -10.5V
429DI1 (B)
INPUT
ARINC receiver 1 negative input
429DI2 (A)
INPUT
ARINC receiver 2 positive input
429DI2 (B)
INPUT
ARINC receiver 2 negative input
D/R1
OUTPUT
Receiver 1 data ready flag
D/R2
OUTPUT
Receiver 2 data ready flag
SEL
INPUT
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
INPUT
Data Bus control, enables receiver 1 data to outputs
EN2
INPUT
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
I/O
Data Bus
BD14
I/O
Data Bus
BD13
I/O
Data Bus
BD12
I/O
Data Bus
BD11
I/O
Data Bus
BD10
I/O
Data Bus
BD09
I/O
Data Bus
BD08
I/O
Data Bus
BD07
I/O
Data Bus
BD06
I/O
Data Bus
GND
POWER
BD05
I/O
Data Bus
0V
BD04
I/O
Data Bus
BD03
I/O
Data Bus
BD02
I/O
Data Bus
BD01
I/O
Data Bus
BD00
I/O
Data Bus
TX/R
OUTPUT
PL1
INPUT
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
PL2
INPUT
TXA(OUT)
OUTPUT
Line driver output - A side
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
TXB(OUT)
OUTPUT
Line driver output - B side
ENTX
INPUT
Enable Transmission
CWSTR
INPUT
Clock for control word register
CLK
INPUT
Master Clock input
TX CLK
OUTPUT
MR
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
CONTROL WORD REGISTER
Both the HI-8581and HI-8589 contain 10 data flip flops whose
D inputs are connected to the data bus and clocks connected to
CWSTR. Each flip flop provides options to the user as follows:
DATA
BUS
PIN
FUNCTION CONTROL
BDO5
SELF TEST
0 = ENABLE
DESCRIPTION
If enabled, the transmitter’s digital
outputs are internally connected
to the receiver logic inputs
BDO6
RECEIVER 1
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
-
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
-
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
BDO8
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
Control word bits
BD10
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
BD11
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
INVERT
XMTR
PARITY
1 = ENABLE
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
BD13
XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14
RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
BD12
vcc
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
13 12 11 10
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
9
31 30 32
1
2
3
4
5
6
8
BYTE 2
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8581 and HI-8589 guarantee recognition of these levels with
a common mode Voltage with respect to GND less than ±4V for the
worst case condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
DIFFERENTIAL
AMPLIFIERS
429DI1 (A)
COMPARATORS
ONES
OR
429DI2 (A)
vcc
7
NULL
GND
ZEROES
429DI1 (B)
OR
429DI2 (B)
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing each receiver’s logic.
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 enables the next reception.
RECEIVER PARITY
BIT TIMING
ARINC 429 specifies the following timing for received data:
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 - 41.7 µsec
The HI-8581 and HI-8589 accepts signals meeting these specifications and rejects signals outside these tolerances using the
method described here:
1. The timing logic requires an accurate 1.0 MHz clock
source. Less than 0.1% error is recommended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be considered valid data. To qualify data bits, One or Zero in the upper
bits of the sampling shift register must be followed by Null in
the lower bits within the data bit time. A word gap Null requires three consecutive Nulls in both the upper and lower
bits of the sampling shift register. This guarantees the minimum pulse width.
3. Each data bit must follow its predecessor by not less than
8 samples and not more than 12 samples. In this manner the
bit rate is checked. With exactly 1 MHz input clock frequency,
the acceptable data bit rates are as follows:
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
DATA BIT RATE MIN
DATA BIT RATE MAX
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will always be a “0” when valid (odd parity) ARINC 429 words are received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver remains low until after both ARINC bytes
from that receiver are retrieved. This is accomplished by first activating EN with SEL, the byte selector, low to retrieve the first byte
and then activating EN with SEL high to retrieve the second byte.
EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
TO PINS
SEL
MUX
CONTROL
EN
32 TO 16 DRIVER
CLOCK
OPTION
CONTROL
BIT BD14
D/R
DECODER
CONTROL
BITS
/
CLOCK
LATCH
ENABLE
CONTROL
32 BIT LATCH
BITS 9 & 10
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
BIT CLOCK
EOS
ONES
CLK
EOS
WORD GAP
WORD GAP
TIMER
SHIFT REGISTER
BIT CLOCK
END
START
NULL
SHIFT REGISTER
ZEROS
SHIFT REGISTER
FIGURE 2.
SEQUENCE
CONTROL
ERROR
ERROR
DETECTION
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
CLOCK
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER PARITY
TRANSMITTER
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
A block diagram of the transmitter section is shown in Figure 3.
SELF TEST
FIFO OPERATION
If the BD05 control word bit is set low, the digital outputs of the
transmitter are internally connected to the logic inputs of the
receivers, bypassing the analog bus interface circuitry. Data to
Receiver 1 is as transmitted and data to Receiver 2 is the
complement. All data transmitted during self test is also present
on the TXA(OUT) and TXB(OUT) line driver outputs.
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
SYSTEM OPERATION
DATA TRANSMISSION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either TXA(OUT) or TXB(OUT). The 31 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
BIT BD12
31 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
TXA(OUT)
TXB(OUT)
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
8 X 31 FIFO
LINE DRIVER
START
SEQUENCE
ADDRESS
WORD COUNTER
AND
FIFO CONTROL
LOAD
TX/R
ENTX
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
PL1
PL2
DATA BUS
DATA
CLOCK
FIGURE 3.
DATA CLOCK
DIVIDER
TRANSMITTER BLOCK DIAGRAM
CONTROL BIT
BD13
HOLT INTEGRATED CIRCUITS
5
CLK
TX CLK
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
HI-8581-10 and HI-8589-10
LINE DRIVER OPERATION
The “-10” versions of the HI-8581 and HI-8589 products require a
10 Kohm resistor to be placed in series with each ARINC input
without affecting the ARINC input thresholds. This option is
especially useful in applications where external lightning
protection is required.
The line driver in the HI-8581 and HI-8589 is designed to directly
drive the ARINC 429 bus. The two ARINC outputs (TXA(OUT) and
TXB(OUT)) provide a differential voltage to produce a +10 volt
One, a -10 volt Zero, and a 0 volt Null. Setting Control Register bit
13 to zero causes a slope of 1.5 ms on the ARINC outputs. A one in
Control Register bit 13 causes a slope of 10 ms. Timing is set by onchip resistor and capacitor and tested to be within ARINC requirements. No additional hardware is required to control the slope. The
HI-8581 has 37.5 ohms whereas the HI-8589 has 10 ohms in
series with each line driver output. The HI-8589 is for applications
where additional external series resistance is required, such as
lightning protection.
Each ARINC input pin must be connected to the ARINC bus
through a 10 Kohm resistor in order for the chip to properly detect
the correct ARINC levels. The typical 10 volt differential signal is
translated and input to a window comparator and latch. The
comparator levels are set so that with the external 10 Kohm
resistors, they are just below the standard 6.5 volt minimum
ARINC data threshold and just above the 2.5 volt maximum
ARINC null threshold.
REPEATER OPERATION
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
Repeater mode of operation allows a data word that has been
received by the HI-8581 or HI-8589 to be placed directly into its
FIFO for transmission. Repeater operation is similar to normal
receiver operation. In normal operation, either byte of a received
data word may be read from the receiver latches first by use of SEL
input. During repeater operation however, the lower byte of the
data word must be read first. This is necessary because, as the
data is being read, it is also being loaded into the FIFO and the
transmitter FIFO is always loaded with the lower byte of the data
word first. Signal flow for repeater operation is shown in the
Timing Diagrams section.
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large currents
during supply turn-on and turn-off. The recommended sequence
is V+ followed by Vcc, always ensuring that V+ is the most
positive supply. The V- supply is not critical and can be asserted
at any time.
MASTER RESET (MR)
On a Master Reset data transmission and reception are
immediately terminated, all three FIFOs are cleared as are the
FIFO flags at the device pins and in the Status Register. The
Control Register is not affected by a Master Reset.
TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN
TXA(OUT)
ARINC BIT
TXB(OUT)
DATA
BIT 30
NULL
DATA
NULL
DATA
NULL
WORD GAP
BIT 32
BIT 31
LOADING CONTROL WORD
VALID
DATA BUS
tCWSET
tCWHLD
CWSTR
tCWSTR
HOLT INTEGRATED CIRCUITS
6
BIT 1
NEXT WORD
HI-8581, HI-8589
TIMING DIAGRAMS (cont.)
RECEIVER OPERATON
ARINC DATA
BIT 31
DATA READY FLAG
BIT 32
D/R
tEND/R
tD/R
BYTE SELECT
DON'T CARE
SEL
DON'T CARE
tSELEN
ENABLE BYTE ON BUS
tSELEN
tENSEL
DON'T CARE
tEN
tENSEL
EN
tENEN
tDATAEN
tD/REN
tDATAEN
BYTE 2 VALID
BYTE 1 VALID
DATA BUS
tENDATA
tENDATA
TRANSMITTER OPERATION
BYTE 2 VALID
BYTE 1 VALID
DATA BUS
tDWSET
tDWSET
tDWHLD
tDWHLD
PL1
tPL12
tPL
PL2
tPL12
tPL
tTX/R
TX/R
TRANSMITTING DATA
PL2
tDTX/R
tPL2EN
TX/R
tENTX/R
ENTX
tENDAT
ARINC BIT
DATA
BIT 32
+5V
ARINC BIT
DATA
BIT 2
ARINC BIT
DATA
BIT 1
+5V
TXA(OUT)
-5V
+5V
TXB(OUT)
-5V
-5V
tfx
+10V
+10V
90%
V
DIFF
(TXA(OUT) - TXB(OUT))
tfx
10%
trx
one level
trx
10%
zero level
90%
null level
-10V
HOLT INTEGRATED CIRCUITS
7
HI-8581, HI-8589
TIMING DIAGRAMS (cont.)
REPEATER OPERATION TIMING
429DI
BIT 32
tEND/R
D/R
tD/R
tD/REN
tEN
tENEN
tEN
EN
tSELEN
SEL
tENSEL
DON'T CARE
DON'T CARE
tENPL
tSELEN
tPLEN
tENSEL
PL1
tPLEN
tENPL
PL2
tTX/R
TX/R
tTX/REN
tENTX/R
ENTX
tDTX/R
tENDAT
TXA(OUT)
TXB(OUT)
BIT 1
BIT 32
tNULL
HOLT INTEGRATED CIRCUITS
8
HI-8581, HI-8589
ABSOLUTE MAXIMUM RATINGS
-0.3V to +7V Power Dissipation at 25°C
Plastic PLCC/PQFP
+12.5V
Ceramic J-LEAD CERQUAD
-12.5V
Supply Voltages Vcc
V+
VVoltage at ARINC inputs
-120V to +120V DC Current Drain per pin
Voltage at any other pin
-0.3V to Vcc +0.3V Storage Temperature Range:
260°C Operating Temperature Range:
Soldering Temperature (Reflow)
1.5 W, derate 10mW/°C
1.0 W, derate 7mW/°C
±10mA
-65°C to +150°C
(Industrial)
-40°C to +85°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±5%, V+ = 10V , V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
CONDITIONS
VIH
VIL
VNUL
Common mode voltage
less than ±4V with
respect to GND
MIN
TYP
MAX
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
27
27
UNIT
ARINC INPUTS
Differential Input Voltage:
(429DI1(A) to 429DI1(B); 429DI2(A) to 429DI2(B))
Input Resistance:
ONE
ZERO
NULL
Differential
To GND
To Vcc
RI
RG
RH
12
12
12
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To Vcc
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
Input Current:
Input Capacitance:(Guaranteed but not tested)
(429DI1(A), 429DI1(B), 429DI2(A) & 429DI2(B))
V
V
V
K
K
K
200
µA
µA
20
20
20
pF
pF
pF
0.7
V
V
BI-DIRECTIONAL INPUTS
Input Voltage:
Input Current:
2.1
1.5
-1.5
µA
µA
OTHER INPUTS
Input Voltage:
Input Current:
HOLT INTEGRATED CIRCUITS
9
3.5
-20
0.7
V
V
10
µA
HI-8581, HI-8589
DC ELECTRICAL CHARACTERISTICS (cont.)
Vcc = 5V ±5%, V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
CONDITIONS
ARINC output voltage
One or zero
Null
VDOUT
VNOUT
no load and magnitude at pin
ARINC output current
IOUT
MIN
TYP
MAX
4.50
-0.25
5.00
5.50
0.25
UNIT
ARINC OUTPUTS
"
"
"
"
"
"
80
V
V
mA
OTHER OUTPUTS
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -1.5mA
IOL = 2.6mA
2.7
Output Current:
(Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
3.0
1.1
mA
mA
Output Current:
(All Other Outputs)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
2.6
1.1
mA
mA
Output Capacitance:
0.4
CO
15
V
V
pF
Operating Voltage Range
VCC
4.75
5.25
V
V+
9.5
10.5
V
V-
-9.5
-10.5
V
Operating Supply Current
VCC
ICC1
20
mA
V+
IDD1
16
mA
V-
IEE1
16
mA
HOLT INTEGRATED CIRCUITS
10
HI-8581, HI-8589
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, V+=10V, V- = -10V, GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
80
50
10
ns
ns
ns
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
200
ns
ns
Delay - D/R LOW to EN LOW
Delay - EN LOW to D/R HIGH
tD/REN
tEND/R
0
Setup - SEL to EN LOW
Hold - SEL to EN HIGH
tSELEN
tENSEL
10
10
Delay - EN LOW to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN LOW
tEN
tENEN
80
50
ns
ns
tPL
80
ns
tDWSET
tDWHLD
50
10
ns
ns
Spacing - PL1 or PL2
tPL12
0
ns
Delay - PL2 HIGH to TX/R LOW
tTX/R
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
ns
ns
50
100
30
ns
ns
FIFO TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
840
ns
TRANSMISSION TIMING
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
Spacing - TX/R HIGH to ENTX LOW
tENTX/R
0
µs
50
0
ns
ns
LINE DRIVER OUTPUT TIMING
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed
Line driver transition differential times:
(High Speed)
(Low Speed)
tENDAT
tENDAT
25
200
µs
µs
high to low
low to high
tfx
trx
1.0
1.0
1.5
1.5
2.0
2.0
µs
µs
high to low
low to high
tfx
trx
5.0
5.0
10
10
15
15
µs
µs
Delay - EN LOW to PL LOW
tENPL
0
ns
Hold - PL HIGH to EN HIGH
tPLEN
0
ns
tTX/REN
0
ns
tMR
400
ns
REPEATER OPERATION TIMING
Delay - TX/R LOW to ENTX HIGH
MASTER RESET PULSE WIDTH
ARINC DATA RATE AND BIT TIMING
± 1%
HOLT INTEGRATED CIRCUITS
11
HI-8581, HI-8589
ADDITIONAL HI-8581 / HI-8589 PIN CONFIGURATIONS
7
8
9
10
11
12
13
14
15
16
17
429DI2(B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
7
8
9
10
11
12
13
14
15
16
17
39 ENTX
38 N/C
37 V+
36 TXB(OUT)
35 TXA(OUT)
34 V33 GND
32 TX/R
31 PL2
30 PL1
29 BD00
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
18
19
20
21
22
23
24
25
26
27
28
39 ENTX
38 N/C
37 V+
36 TXB(OUT)
35 TXA(OUT)
34 V33 GND
32 TX/R
31 PL2
30 PL1
29 BD00
18
19
20
21
22
23
24
25
26
27
28
429DI2(B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
6 429DI2(A)
5 429DI1(B)
4 429DI1(A)
3 VCC
2 N/C
1 MR
44 TXCLK
43 CLK
42 N/C
41 N/C
40 CWSTR
6 429DI2(A)
5 429DI1(B)
4 429DI1(A)
3 VCC
2 N/C
1 MR
44 TXCLK
43 CLK
42 N/C
41 N/C
40 CWSTR
(See page 1 for the 44-Pin Plastic Quad Flat Pack (PQFP) pin configuration)
HI-8581PJI / HI-8589PJI
HI-8581PJT / HI-8589PJT
44-Pin Plastic J-Lead PLCC
HI-8581CJI / HI-8589CJI
HI-8581CJT / HI-8589CJT
44-Pin J-Lead CERQUAD
ORDERING INFORMATION
HI - 8581 xx x x - xx
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
No dash number
35 Kohm
0
-10
25 Kohm
10 Kohm
PART
NUMBER
Blank
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
F
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
PART
NUMBER
PACKAGE
DESCRIPTION
CJ
44 PIN CERQUAD J LEAD (44U) not available Pb-free
PJ
44 PIN PLASTIC J LEAD PLCC (44J)
PQ
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PQS)
PART
NUMBER
OUTPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
8581
37.5 Ohms
0
8589
10 Ohms
27.5 Ohms
HOLT INTEGRATED CIRCUITS
12
HI-8581, HI-8589
REVISION HISTORY
P/N
DS8581
Rev
J
Date
Description of Change
08/06/13 Clarified description of receiver parity. Updated solder temp to reflow 260 only. Updated
PQFP package. Update Voltage at ARINC input pins from +/-29V to +/-120V. Updated last
paragraph under Retrieving Data (not visible in previous version).
HOLT INTEGRATED CIRCUITS
13
HI-8581, HI-8589 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type: 44J
PIN NO. 1
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050
(1.27) BSC
.690 ±.005
(17.526 ±.127)
SQ.
.653 ±.004
(16.586 ±.102)
SQ.
.031±.005
(.787 ±.127)
.017 ±.004
(.432 ±.102)
See Detail A
.010 ± .001
(.254 ± .03)
.173 ±.008
(4.394 ±.203)
.020
(.508) min
.610 ±.020
(15.494±.508)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
DETAIL A
R .035±.010
(.889 ±.254)
inches (millimeters)
44-PIN J-LEAD CERQUAD
Package Type: 44U
2 1 44 43
.620 ±.012
(15.748 ±.305)
.688 ±.005 max
(17.475 ±.127) SQ.
.650 ±.010
(16.510 ±.254)
SQ.
.200
max
(5.080)
.039 ±.005
(.990 ±.127)
.019 ±.002
(.483 ± .051)
.050
BSC
(1.270)
.100 ±.007
(2.540 ±.178)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
14
HI-8581, HI-8589 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type:
44PMQS
.009 MAX.
(.23)
.0315
BSC
(.80)
.394 ± .004
(10.0 ± .10)
SQ.
.520 ± .010
(13.20 ± .25)
SQ.
.014 ± .003
(.37 ± .08)
.035 ± .006
(.88 ± .15)
.012
R MAX.
(.30)
See Detail A
.096
MAX.
(2.45)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.079 ± .008
(2.0 ± .20)
.005
R MIN. Detail A
(.13)
HOLT INTEGRATED CIRCUITS
15
0° £ Q £ 7°
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