LINER LT1976 Step-down switching regulator Datasheet

LT1766/LT1766-5
5.5V to 60V 1.5A, 200kHz
Step-Down Switching Regulator
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FEATURES
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DESCRIPTIO
The LT ®1766/LT1766-5 are 200kHz monolithic buck
switching regulators that accept input voltages up to 60V.
A high efficiency 1.5A, 0.2Ω switch is included on the die
along with all the necessary oscillator, control and logic circuitry. A current mode control architecture delivers fast
transient response and excellent loop stability.
Wide Input Range: 5.5V to 60V
1.5A Peak Switch Current
Constant 200kHz Switching Frequency
Saturating Switch Design: 0.2Ω
Peak Switch Current Rating Maintained Over
Full Duty Cycle Range
Low Effective Supply Current: 2.5mA
Low Shutdown Current: 25µA
1.2V Feedback Reference Voltage (LT1766)
5V Fixed Output (LT1766-5)
Easily Synchronizable
Cycle-by-Cycle Current Limiting
Small 16-Pin SSOP and Thermally Enhanced
TSSOP Packages
Special design techniques and a new high voltage process
achieve high efficiency over a wide input range. Efficiency
is maintained over a wide output current range by using the
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry*
maintains peak switch current over the full duty cycle range.
A shutdown pin reduces supply current to 25µA and the
device can be externally synchronized from 228kHz to
700kHz with logic level inputs.
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APPLICATIO S
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The LT1766/LT1766-5 are available in a 16-pin fused-lead
SSOP package or a TSSOP package with exposed backside
for improved thermal performance.
High Voltage, Industrial and Automotive
Portable Computers
Battery-Powered Systems
Battery Chargers
Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
*Patent # 6, 498, 466
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TYPICAL APPLICATIO
5V Buck Converter
1N4148W
6
0.33µF
BOOST
4
†
VIN
2.2µF
100V
CERAMIC
SW
2
15
14
+
SHDN
BIAS
SYNC
FB
GND
1, 8, 9, 16
10
12
15.4k
4.99k
VC
11
Efficiency vs Load Current
VOUT
5V
1A
10MQ060N
LT1766
OFF ON
47µH
100
100µF 10V
SOLID
TANTALUM
VOUT = 5V
L = 47µH
VIN = 12V
90
EFFICIENCY (%)
VIN
5.5V*
TO 60V
VIN = 42V
80
70
220pF
2.2k
60
0.022µF
50
1766 TA01
*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY
†
TDK C4532X7R2A225K
0
0.25
0.75
1.00
0.50
LOAD CURRENT (A)
1.25
1766 TA02
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LT1766/LT1766-5
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ABSOLUTE
RATI GS
(Note 1)
Input Voltage (VIN) ................................................. 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, SENSE Voltage (LT1766-5) ........................... 7V
SHDN Voltage ........................................................... 6V
BIAS Pin Voltage .................................................... 30V
FB Pin Voltage/Current (LT1766) ................... 3.5V/2mA
Operating Junction Temperature Range
LT1766EFE/LT1766EFE-5/LT1766EGN/
LT1766EGN-5 (Note 8,10) ................. – 40°C to 125°C
LT1766IFE/LT1766IFE-5/
LT1766IGN/LT1766IGN-5 (Note 8,10) – 40°C to 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
GND
1
16 GND
SW
2
15 SHDN
ORDER PART
NUMBER
LT1766EFE
LT1766IFE
LT1766EFE-5
LT1766IFE-5
GND
1
16 GND
SW
2
15 SHDN
NC
3
14 SYNC
VIN
4
13 NC
NC
5
12 FB/SENSE
BOOST
6
11 VC
NC
3
VIN
4
NC
5
12 FB/SENSE
BOOST
6
11 VC
NC
7
10 BIAS
NC
7
10 BIAS
GND
8
9
GND
GND
8
9
14 SYNC
17
13 NC
ORDER PART
NUMBER
TOP VIEW
LT1766EGN
LT1766IGN
LT1766EGN-5
LT1766IGN-5
GN PART MARKING
GND
FE PACKAGE
16-LEAD PLASTIC TSSOP
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 45°C/W, θJC (PAD) = 10°C/W
EXPOSED PAD (PIN 17) IS GND.
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 85°C/W, θJC (PIN 8) = 25°C/W
FOUR CORNER PINS SOLDERED
TO GROUND PLANE
1766
1766I
17665
1766I5
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Voltage (VREF) (LT1766)
5.5V ≤ VIN ≤ 60V
VOL + 0.2 ≤ VC ≤ VOH – 0.2
1.219
●
1.204
1.195
1.234
1.243
V
V
5.5V ≤ VIN ≤ 60V
VOL + 0.2V ≤ VC ≤ VOH – 0.2V
4.94
4.90
5
●
5.06
5.10
V
V
SENSE Voltage (LT1766-5)
SENSE Pin Resistance (LT1766-5)
9.5
FB Input Bias Current (LT1766)
●
Error Amp Voltage Gain
(Notes 2, 9)
Error Amp gm
dl (VC) = ±10µA (Note 9)
●
13.8
19
kΩ
–0.5
–1.5
µA
200
400
1500
1000
2000
VC to Switch gm
V/V
3000
4200
1.7
µMho
µMho
A/V
EA Source Current
FB = 1V or VSENSE = 4.1V
●
125
225
400
µA
EA Sink Current
FB = 1.4V or VSENSE = 5.7V
●
100
225
450
µA
VC Switching Threshold
Duty Cycle = 0
0.9
V
VC High Clamp
SHDN = 1V
2.1
V
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LT1766/LT1766-5
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
PARAMETER
CONDITIONS
Switch Current Limit
VC Open, Boost = VIN + 5V, FB = 1V or VSENSE = 4.1V
Switch On Resistance
ISW = 1.5A, Boost = VIN + 5V (Note 7)
●
MIN
TYP
MAX
1.5
2
3
A
0.2
0.3
0.4
Ω
Ω
●
Maximum Switch Duty Cycle
Switch Frequency
fSW Line Regulation
FB = 1V or VSENSE = 4.1V
93
90
96
●
●
184
172
200
200
216
228
kHz
kHz
●
0.05
0.15
%/V
VC Set to Give DC = 50%
5.5V ≤ VIN ≤ 60V
UNITS
%
%
fSW Frequency Shifting Threshold
Df = 10kHz
Minimum Input Voltage
(Note 3)
●
4.6
0.8
5.5
V
Minimum Boost Voltage
(Note 4) ISW ≤ 1.5A
●
1.8
3
V
Boost Current (Note 5)
Boost = VIN + 5V, ISW = 0.5A
Boost = VIN + 5V, ISW = 1.5A
●
●
12
45
25
70
mA
mA
Input Supply Current (IVIN)
(Note 6) VBIAS = 5V
1.4
2.2
mA
Bias Supply Current (IBIAS)
(Note 6) VBIAS = 5V
2.9
4.2
mA
Shutdown Supply Current
SHDN = 0V, VIN ≤ 60V, SW = 0V, VC Open
25
75
200
µA
µA
●
V
Lockout Threshold
VC Open
●
2.3
2.42
2.53
V
Shutdown Thresholds
VC Open, Shutting Down
VC Open, Starting Up
●
●
0.15
0.25
0.37
0.45
0.6
0.6
V
V
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Resistance
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Gain is measured with a VC swing equal to 200mV above the low
clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: Boost current is the current flowing into the BOOST pin with the
pin held 5V above input voltage. It flows only during switch on time.
Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held at
5V. Total input referred supply current is calculated by summing input
supply current (IVIN) with a fraction of bias supply current (IBIAS):
ITOTAL = IVIN + (IBIAS)(VOUT/VIN)
With VIN = 15V, VOUT = 5V, IVIN = 1.4mA, IBIAS = 2.9mA, ITOTAL = 2.4mA.
1.5
●
228
20
2.2
V
700
kHz
kΩ
Note 7: Switch on resistance is calculated by dividing VIN to SW voltage by
the forced current (1.5A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 8: The LT1766EGN, LT1766EGN-5, LT1766EFE and LT1766EFE-5 are
guaranteed to meet performance specifications from 0°C to 125°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT1766IGN,
LT1766IGN-5, LT1766IFE and LT1766IFE-5 are guaranteed over the full
–40°C to 125°C operating junction temperature range.
Note 9: Transconductance and voltage gain refer to the internal amplifier
exclusive of the voltage divider. To calculate gain and transconductance,
refer to the SENSE pin on fixed voltage parts. Divide the values shown by
the ratio VOUT/1.219.
Note 10: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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LT1766/LT1766-5
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TYPICAL PERFOR A CE CHARACTERISTICS
Switch Peak Current Limit
FB Pin Voltage and Current
SHDN Pin Bias Current
1.234
TA = 25°C
2.0
250
1.229
1.224
VOLTAGE
1.219
1.0
CURRENT
1.214
CURRENT (µA)
GUARANTEED MINIMUM
1.5
1.5
FEEDBACK VOLTAGE (V)
TYPICAL
2.0
150
100
12
0
20
40
60
DUTY CYCLE (%)
100
80
6
1.204
50
100
25
75
–50 –25
0
JUNCTION TEMPERATURE (°C)
1766 G01
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
Shutdown Supply Current
Shutdown Supply Current
300
INPUT SUPPLY CURRENT (µA)
1.6
1.2
0.8
START-UP
0.4
INPUT SUPPLY CURRENT (µA)
VSHDN = 0V
35 TA = 25°C
LOCKOUT
125
1766 G03
40
2.4
SHDN PIN VOLTAGE (V)
0
125
1766 G02
Lockout and Shutdown
Thresholds
2.0
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
0.5
1.209
1.0
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
200
CURRENT (µA)
SWITCH PEAK CURRENT (A)
2.5
30
25
20
15
10
TA = 25°C
250
VIN = 60V
200
VIN = 15V
150
100
5
50
SHUTDOWN
0
0
0
–25
25
50
75
100
0
125
10
20
30
40
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
50
0
60
Error Amplifier Transconductance
Error Amplifier Transconductance
2500
3000
2000
2500
Frequency Foldback
200
TA = 25°C
600
GAIN (µMho)
1000
GAIN
2000
100
(
1500
1000
500
150
VFB 2 • 10
–3
)
ROUT
200k
VC
COUT
12pF
50
ERROR AMPLIFIER EQUIVALENT CIRCUIT
0
PHASE (DEG)
1500
TA = 25°C
500
400
300
SWITCHING
FREQUENCY
200
100
FB PIN
CURRENT
RLOAD = 50Ω
0
–50
–25
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
1766 G07
500
100
1k
10k
100k
FREQUENCY (Hz)
1M
0.5
1766 G06
PHASE
TRANSCONDUCTANCE (µmho)
0.1
0.2
0.3
0.4
SHUTDOWN VOLTAGE (V)
1766 G05
1766 G04
SWITICHING FREQUENCY (kHz)
OR FB CURRENT (µA)
0
–50
–50
10M
0
0
0.5
1.0
1.5
VFB (V)
1766 G08
1766 G09
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LT1766/LT1766-5
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TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Input Voltage with 5V
Output
Switching Frequency
7.5
230
BOOST Pin Current
45
TA = 25°C
TA = 25°C
40
210
200
190
6.5
MINIMUM INPUT
VOLTAGE TO START
6.0
MINIMUM INPUT
VOLTAGE TO RUN
5.5
180
–25
0
25
50
75
100
5.0
125
0
JUNCTION TEMPERATURE (°C)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
LOAD CURRENT (A)
1766 G10
30
25
20
15
10
0
1
600
400
SWITCH VOLTAGE (mV)
1.9
1.3
1.1
TJ = 125°C
350
300
TJ = 25°C
250
200
150
TJ = –40°C
100
0.9
1.5
Switch Minimum ON Time
vs Temperature
450
2.1
1.5
0.5
1
SWITCH CURRENT (A)
1766 G12
Switch Voltage Drop
1.7
0
1766 G11
VC Pin Shutdown Threshold
THRESHOLD VOLTAGE (V)
35
5
SWITCH MINIMUM ON TIME (ns)
170
–50
BOOST PIN CURRENT (mA)
7.0
INPUT VOLTAGE (V)
FREQUENCY (kHz)
220
500
400
300
200
100
50
0.7
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
125
0
0
0.5
1
SWITCH CURRENT (A)
1766 G13
1.5
0
50
100
25
75
–50 –25
0
JUNCTION TEMPERATURE (°C)
1766 G14
125
1766 G15
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PI FU CTIO S
GND (Pins 1, 8, 9, 16, 17): The GND pin connections act
as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the
same voltage as the GND pins of the IC. This condition will
occur when load current or other currents flow through
metal paths between the GND pins and the load ground.
Keep the paths between the GND pins and the load ground
short and use a ground plane when possible. The GND pin
also acts as a heat sink and should be soldered to a large
copper plane to reduce thermal resistance. For the FE
package, the exposed pad should be soldered to the
copper ground plane underneath the device. (See Applications Information—Layout Considerations.)
SW (Pin 2): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum
negative switch voltage allowed is – 0.8V.
NC (Pins 3, 5, 7, 13): No Connection.
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LT1766/LT1766-5
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PI FU CTIO S
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. VIN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and voltage loss approximates that of a 0.2Ω FET structure, but with much smaller die area.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency especially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
VC (Pin 11) The VC pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.9V for light loads and 2.1V at maximum load. It
can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.
FB/SENSE (Pin 12): The feedback pin is used to set the
output voltage using an external voltage divider that generates 1.22V at the pin for the desired output voltage. The
5V fixed output voltage parts have the divider included on
the chip and the FB pin is used as a SENSE pin, connected
directly to the 5V output. Three additional functions are
performed by the FB pin. When the pin voltage drops
below 0.6V, switch current limit is reduced and the external SYNC function is disabled. Below 0.8V, switching
frequency is also reduced. See Feedback Pin Functions in
Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The synchronizing range is
equal to initial operating frequency up to 700kHz. See
Synchronizing in Applications Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input drain current to a few
microamperes. This pin has two thresholds: one at 2.38V
to disable switching and a second at 0.4V to force complete micropower shutdown. The 2.38V threshold functions as an accurate undervoltage lockout (UVLO);
sometimes used to prevent the regulator from delivering
power until the input voltage has reached a predetermined
level.
If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
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BLOCK DIAGRA
The LT1766 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
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LT1766/LT1766-5
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BLOCK DIAGRA
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external
capacitor and diode. Two comparators are connected to
the shutdown pin. One has a 2.38V threshold for undervoltage lockout and the second has a 0.4V threshold for
complete shutdown.
Most of the circuitry of the LT1766 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
power will be drawn from the external source (typically the
VIN
4
RLIMIT
BIAS 10
2.9V BIAS
REGULATOR
–
+
INTERNAL
VCC
CURRENT
COMPARATOR
Σ
SLOPE COMP
RSENSE
SYNC 14
BOOST
ANTISLOPE COMP
6
SHUTDOWN
COMPARATOR
200kHz
OSCILLATOR
S
RS
FLIP-FLOP
Q1
POWER
SWITCH
DRIVER
CIRCUITRY
–
R
+
0.4V
5.5µA
2
SW
+
FREQUENCY
FOLDBACK
–
LOCKOUT
COMPARATOR
×1
2.38V
Q2
FOLDBACK
CURRENT
LIMIT
CLAMP
Q3
11
VC
ERROR
AMPLIFIER
gm = 2000µMho
12 FB
+
VC(MAX)
CLAMP
–
SHDN 15
1.22V
GND
1, 8, 9, 16, 17
1766 F01
Figure 1. LT1766 Block Diagram
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LT1766/LT1766-5
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APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1766 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The 5V fixed output voltage part (LT1766-5) has
internal divider resistors and the FB pin is renamed SENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R1 =
R2( VOUT − 1.22)
1.22
Table 1
OUTPUT
VOLTAGE
(V)
R2
(kΩ)
R1
(NEAREST 1%)
(kΩ)
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
3
4.99
7.32
+ 0.32
3.3
4.99
8.45
– 0.43
5
4.99
15.4
– 0.30
6
4.75
18.7
+ 0.38
8
4.47
24.9
+ 0.20
10
4.32
30.9
– 0.54
12
4.12
36.5
+ 0.24
15
4.12
46.4
– 0.27
More Than Just Voltage Feedback
The feedback pin is used for more than just output
voltage sensing. It also reduces switching frequency and
current limit when output voltage is very low (see the
Frequency Foldback graph in Typical Performance Characteristics). This is done to control power dissipation in
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
switching regulator to operate at very low duty cycles,
and the average current through the diode and inductor
is equal to the short-circuit current limit of the switch
(typically 2A for the LT1766, folding back to less than
1A). Minimum switch on time limitations would prevent
the switcher from attaining a sufficiently low duty cycle
if switching frequency were maintained at 200kHz, so
frequency is reduced by about 5:1 when the feedback pin
voltage drops below 0.8V (see Frequency Foldback graph).
This does not affect operation with normal load conditions; one simply sees a gear shift in switching frequency
during start-up as the output voltage rises.
In addition to lower switching frequency, the LT1766 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and inductor during short-circuit conditions. External synchronization is also disabled to prevent interference with foldback operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
these rare situations the feedback pin can be clamped above
0.6V with an external diode to defeat foldback current limit.
Caution: clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high input voltage and dead shorted output may cause the LT1766
to lose control of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 1.4kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115µA out of the FB pin with 0.44V on the pin (RDIV
≤ 3.8k). The net result is that reductions in frequency and
current limit are affected by output voltage divider impedance. Although divider impedance is not critical, caution
1766fa
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LT1766
VSW
TO FREQUENCY
SHIFTING
1.4V
–
OUTPUT
5V
Q1
ERROR
AMPLIFIER
+
L1
R1
1.2V
R4
2k
R3
1k
FB
+
C1
BUFFER
Q2
R2
5k
TO SYNC CIRCUIT
VC
GND
1766 F02
Figure 2. Frequency and Current Limit Foldback
should be used if resistors are increased beyond the
suggested values and short-circuit conditions occur with
high input voltage. High frequency pickup will increase
and the protection accorded by frequency and current
foldback will decrease.
VOUT AT IOUT = 1A
40mV/DIV
VOUT AT IOUT = 0.1A
INDUCTOR CURRENT
AT IOUT = 1A
CHOOSING THE INDUCTOR
0.5A/DIV
For most applications, the output inductor will fall into the
range of 15µH to 100µH. Lower values are chosen to
reduce physical size of the inductor. Higher values allow
more output current because they reduce peak current
seen by the LT1766 switch, which has a 1.5A limit. Higher
values also reduce output ripple voltage.
When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak inductor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested as a
way of handling these somewhat complicated and conflicting requirements.
Output Ripple Voltage
Figure 3 shows a typical output ripple voltage waveform
for the LT1766. Ripple voltage is determined by ripple
current (ILP-P) through the inductor and the high
frequency impedance of the output capacitor. The following equations will help in choosing the required inductor
INDUCTOR CURRENT
AT IOUT = 0.1A
VIN = 40V
2.5µs/DIV
VOUT = 5V
L = 47µH
C = 100µF, 10V, 0.1Ω
1766 F03
Figure 3. LT1766 Ripple Voltage Waveform
value to achieve a desirable output ripple voltage level. If
output ripple voltage is of less importance, the subsequent suggestions in Peak Inductor and Fault Current
and EMI will additionally help in the selection of the
inductor value.
Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (ILP-P) times ESR)
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is
assumed to be small compared to ESR or ESL.
VRIPPLE = (ILP-P )(ESR) + (ESL)
dI
dt
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where:
ESR = equivalent series resistance of the output
capacitor
ESL = equivalent series inductance of the output
capacitor
dI/dt = slew rate of inductor ripple current = VIN/L
Peak-to-peak ripple current (ILP-P) through the inductor
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It is
approximated by:
ILP-P =
( VOUT )( VIN – VOUT )
( VIN )( f)(L)
(5)(40 − 5)
(40)(47 • 10−6 )(200 • 103 )
= 0.465A
40
dI
=
= 10 6 • 0.85
dt 47 • 10 − 6
VRIPPLE = (0.465A )(0.1) + 10 • 10 − 9 10 6 (0.85 )
(
If maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 2A overload condition. Dead shorts will actually be more gentle on the
inductor because the LT1766 has frequency and current
limit foldback.
Peak switch and inductor current can be significantly
higher than output current, especially with smaller inductors and lighter loads, so don’t omit this step. Powdered
iron cores are forgiving because they saturate softly,
whereas ferrite cores saturate abruptly. Other core
Table 2
Example: with VIN = 40V, VOUT = 5V, L = 47µH, ESR = 0.1Ω
and ESL = 10nH, output ripple voltage can be approximated as follows:
IP-P =
or not the inductor must withstand continuous fault
conditions.
)( )
= 0.0465 + 0.0085 = 55mVP-P
To reduce output ripple voltage further requires an increase in the inductor value or a reduction in the capacitor
ESR. The latter can effect loop stability since the ESR
forms a useful zero in the overall loop response. Typically
the inductor value is adjusted with the trade-off being a
physically larger inductor with the possibility of increased
component height and cost. Choosing a smaller inductor
with lighter loads may result in discontinuous operation
but the LT1766 is designed to work well in both continuous or discontinuous mode.
VENDOR/
PART NO.
VALUE
(µH)
IDC
(Amps)
DCR
(Ohms)
HEIGHT
(mm)
CTX15-1P
15
1.4
0.087
4.2
CTX15-1
15
1.1
0.08
4.2
CTX33-2P
33
1.3
0.126
6
CTX33-2
33
1.4
0.106
6
UP2-330
33
2.4
0.099
5.9
UP2-470
47
1.9
0.146
5.9
UP2-680
68
1.7
0.19
5.9
UP2-101
100
1.4
0.277
5.9
15
1.4
0.076
3
Coiltronics
Sumida
CDRH6D28-150M
CDRH6D38-150M
15
1.6
0.062
4
CDRH6D28-330M
33
0.97
0.122
3
CDRH104R-330M
33
2.1
0.069
3.8
CDRH125-330M
33
2.1
0.044
6
CDRH104R-470M
47
2.1
0.095
3.8
CDRH125-470M
47
1.8
0.058
6
CDRH6D38-680M
68
0.75
0.173
4
CDRH104R-680M
68
1.5
0.158
3.8
CDRH125-680M
68
1.5
0.093
6
CDRH104R-101M
100
1.35
0.225
3.8
CDRH125-101M
100
1.3
0.120
6
Peak Inductor Current and Fault Current
Coilcraft
To ensure that the inductor will not saturate, the peak
inductor current should be calculated knowing the maximum load current. An appropriate inductor should then
be chosen. In addition, a decision should be made whether
DT3316P-153
15
1.8
0.06
5
DT3316P-333
33
1.3
0.09
5
DT3316P-473
47
1
0.11
5
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materials fall somewhere in between. The following formula assumes continuous mode of operation, but errs
only slightly on the high side for discontinuous mode, so
it can be used for all conditions.
IPEAK = IOUT +
(
)(
)
( )( )( )( )
VOUT VIN – VOUT
(ILP-P )
= IOUT +
2
2 VIN f L
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current (ILP-P). The following formula assumes continuous mode operation, implying that the term on the right is less than one-half of IP.
IOUT(MAX) =
Continuous Mode
EMI
Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid to
prevent EMI problems. This is a tough decision because
the rods or barrels are temptingly cheap and small and
there are no helpful guidelines to calculate when the
magnetic field radiation will be a problem.
Additional Considerations
After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department if
you feel uncertain about the final choice. They have
experience with a wide range of inductor types and can tell
you about the latest developments in low profile, surface
mounting, etc.
Maximum Output Load Current
Maximum load current for a buck converter is limited by
the maximum switch current rating (IP). The current rating
for the LT1766 is 1.5A. Unlike most current mode converters, the LT1766 maximum switch current limit does not
fall off at high duty cycles. Most current mode converters
suffer a drop off of peak switch current for duty cycles
above 50%. This is due to the effects of slope compensation required to prevent subharmonic oscillations in current mode converters. (For detailed analysis, see Application Note 19.)
The LT1766 is able to maintain peak switch current limit over
the full duty cycle range by using patented circuitry* to cancel
the effects of slope compensation on peak switch current
without affecting the frequency compensation it provides.
*Patent # 6, 498, 466
IP –
( VOUT + VF )( VIN − VOUT – VF )
ILP-P
= IP −
2
2(L)( f)( VIN )
For VOUT = 5V, VIN = 8V, VF(D1) = 0.63V, f = 200kHz and
L = 20µH:
IOUT(MAX ) = 1.5 −
(5 + 0.63)(8 − 5 – 0.63)
2(20 • 10 − 6)(200 • 10 3 )(8)
= 1.5 − 0.21 = 1.29 A
Note that there is less load current available at the higher
input voltage because inductor ripple current increases. At
VIN = 15V, duty cycle is 33% and for the same set of
conditions:
IOUT(MAX) = 1.5 −
(5 + 0.63)(15 − 5 – 0.63)
2(20 • 10 − 6)(200 • 10 3 )(15)
= 1.5 − 0.44 = 1.06 A
To calculate actual peak switch current with a given set of
conditions, use:
ILP-P
2
(VOUT + VF )(VIN − VOUT – VF )
= IOUT +
2(L)( f)(VIN )
ISW(PEAK) = IOUT +
Reduced Inductor Value and Discontinuous Mode
If the smallest inductor value is of most importance to a
converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor solution. The maximum output load current in discontinuous
mode, however, must be calculated and is defined later in
this section.
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Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple current
(ILP-P). In this mode, inductor current falls to zero before
the next switch turn on (see Figure 8). Buck converters will
be in discontinuous mode for output load current given by:
(V
+ V )( V – V
–V )
IOUT
< OUT F IN OUT F
(2)( VIN )( f)(L)
Discontinuous Mode
The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (ILP-P) low;
this is done to minimize output ripple voltage and maximize output load current. In the case of large inductor
values, as seen in the equation above, discontinuous
mode will be associated with “light loads.”
When choosing small inductor values, however, discontinuous mode will occur at much higher output load
currents. The limit to the smallest inductor value that can
be chosen is set by the LT1766 peak switch current (IP)
and the maximum output load current required, given by:
IP2
IOUT(MAX)
=
Discontinuous Mode (2)(ILP-P )
=
(IP )2 ((f)(L)(VIN ))
2( VOUT + VF )( VIN – VOUT – VF )
Example: For VIN = 15V, VOUT = 5V, VF = 0.63V, f = 200kHz
and L = 10µH.
IOUT(MAX)
Discontinuous
Mode
=
(1.5)2 • (200 • 103 )(10–5 )(15)
2(5 + 0.63)(15 – 5 – 0.63)
IOUT(MAX)
= 0.639A
Discontinuous Mode
What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be tolerated, small inductor values can be used. If a higher output
load current is required, the inductor value must be
increased. If IOUT(MAX) no longer meets the discontinuous
mode criteria, use the IOUT(MAX) equation for continuous
mode; the LT1766 is designed to operate well in both
modes of operation, allowing a large range of inductor
values to be used.
Short-Circuit Considerations
The LT1766 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by VC. However, there is finite response
time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
tON(MIN). When combined with the large ratio of VIN to
(VF + I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
f • tON ≤
VF + I • R
VIN
where:
f = switching frequency
tON = switch minimum on time
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1766 clock frequency
of 200KHz, a VIN of 40V and a (VF + I • R) of say 0.7V, the
maximum tON to maintain control would be approximately
90ns, an unacceptably short time.
The solution to this dilemma is to slow down the oscillator
when the FB pin voltage is abnormally low thereby indicating some sort of short-circuit condition. Oscillator frequency is unaffected until FB voltage drops to about 2/3 of
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its normal value. Below this point the oscillator frequency
decreases roughly linearly down to a limit of about 40kHz.
This lower oscillator frequency during short-circuit conditions can then maintain control with the effective minimum on time.
It is recommended that for [VIN/(VOUT + VF)] ratios > 10,
a soft-start circuit should be used to control the output
capacitor charge rate during start-up or during recovery
from an output short circuit, thereby adding additional
control over peak inductor current. See Buck Converter
with Adjustable Soft-Start later in this data sheet.
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT1766 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical, and values from
22µF to greater than 500µF work well, but you cannot
cheat mother nature on ESR. If you find a tiny 22µF solid
tantalum capacitor, it will have high ESR, and output ripple
voltage will be terrible. Table 2 shows some typical solid
tantalum surface mount capacitors.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E Case Size
ESR (Max, Ω )
Ripple Current (A)
0.1 to 0.3
0.7 to 1.1
0.1 to 0.3
0.7 to 1.1
0.2 (typ)
0.5 (typ)
D Case Size
AVX TPS, Sprague 593D
C Case Size
AVX TPS
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is
triangular with a typical value of 125mARMS. The formula
to calculate this is:
Output capacitor ripple current (RMS):
IRIPPLE(RMS) =
OUTPUT CAPACITOR
AVX TPS, Sprague 593D
tantalum capacitors fail during very high turn-on surges,
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true, and type TPS capacitors are
specially tested for surge capability, but surge ruggedness
is not a critical issue with the output capacitor. Solid
0.29(VOUT )( VIN − VOUT )
(L)( f)(VIN)
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Their low ESR reduces
output ripple voltage but also removes a useful zero in the
loop frequency response, common to tantalum capacitors. To compensate for this, a resistor RC can be placed
in series with the VC compensation capacitor CC. Care
must be taken however, since this resistor sets the high
frequency gain of the error amplifier, including the gain at
the switching frequency. If the gain of the error amplifier
is high enough at the switching frequency, output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
filter capacitor CF in parallel with the RC/CC network is
suggested to control possible ripple at the VC pin. An “All
Ceramic” solution is possible for the LT1766 by choosing
the correct compensation components for the given
application.
Example: For VIN = 8V to 40V, VOUT = 3.3V at 1A, the
LT1766 can be stabilized, provide good transient response and maintain very low output ripple voltage using
the following component values: (refer to the first page of
this data sheet for component references) C3 = 2.2µF,
RC = 4.7k, CC = 15nF, CF = 220pF and C1 = 47µF. See
Application Note 19 for further detail on techniques for
proper loop compensation.
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INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1766 and force the
switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from:
IRIPPLE(RMS) = IOUT VOUT ( VIN – VOUT ) / VIN2
Ceramic capacitors are ideal for input bypassing. At 200kHz
switching frequency, the energy storage requirement of
the input capacitor suggests that values in the range of
2.2µF to 20µF are suitable for most applications. If operation is required close to the minimum input required by the
output of the LT1766, a larger value may be required. This
is to prevent excessive ripple causing dips below the
minimum operating voltage resulting in erratic operation.
Depending on how the LT1766 circuit is powered up you
may need to check for input voltage transients.
The input voltage transients may be caused by input
voltage steps or by connecting the LT1766 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
cause the input voltage to swing above the DC level of input
power source and it may exceed the maximum voltage
rating of input capacitor and LT1766.
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel with
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance will
fall in the range of 5µF to 50µF.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2:1 for high surge applications.
CATCH DIODE
Highest efficiency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a significant reverse recovery time. Schottky
diodes are generally available with reverse voltage ratings
of up to 60V and even 100V, and are price competitive with
other types.
The use of so-called “ultrafast” recovery diodes is generally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internal switch will ramp up VIN current into the diode in an
attempt to get it to recover. Then, when the diode has
finally turned off, some tens of nanoseconds later, the VSW
node voltage ramps up at an extremely high dV/dt, perhaps 5 to even 10V/ns ! With real world lead inductances,
the VSW node can easily overshoot the VIN rail. This can
result in poor RFI behavior and if the overshoot is severe
enough, damage the IC itself.
The suggested catch diode (D1) is an International Rectifier 10MQ060N Schottky. It is rated at 1.5A average
forward current and 60V reverse voltage. Typical forward
voltage is 0.63V at 1A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulator input voltage. Average forward current in normal
operation can be calculated from:
ID(AVG) =
IOUT ( VIN – VOUT )
VIN
This formula will not yield values higher than 1.5A with
maximum load current of 1.5A. The only reason to
consider a larger diode is the worst-case condition of a
high input voltage and shorted output. With a shorted
condition, diode current will increase to a typical value of
2A, determined by peak switch current limit. This is safe
for short periods of time, but it would be prudent to check
with the diode manufacturer if continuous operation
under these conditions must be tolerated.
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SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
BOOST PIN
For most applications, the boost components are a 0.33µF
capacitor and a 1N4148W diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately VOUT above VIN to drive the output
stage. However, the output stage discharges the boost
capacitor during the on time of the switch. The output
driver requires at least 3V of headroom throughout this
period to keep the switch fully saturated. If the output
voltage is less than 3.3V, it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input, although, care must be taken to
prevent the 2× VIN boost voltage from exceeding the
BOOST pin absolute maximum rating. The additional
voltage across the switch driver also increases power
loss, reducing efficiency. If available, and independent
supply can be used with a local bypass capacitor.
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1766. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
Threshold voltage for lockout is about 2.38V. A 5.5µA bias
current flows out of the pin at this threshold. The internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shutdown current is not an issue, the error due to this current
can be minimized by making RLO 10k or less. If shutdown
current is an issue, RLO can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.
A 0.33µF boost capacitor is recommended for most applications. Almost any type of film or ceramic capacitor is
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
4700ns on time, 42mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuit operation or efficiency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.
R LO = 10k to 100k (25k suggested)
R HI =
RLO ( VIN − 2.38 V )
2.38 V − R LO(5.5 µA)
VIN = Minimum input voltage
RFB
L1
LT1766
2.38V
IN
INPUT
OUTPUT
VSW
+
STANDBY
RHI
–
5.5µA
+
SHDN
C1
+
TOTAL
SHUTDOWN
C2
RLO
0.4V
–
GND
1766 F04
Figure 4. Undervoltage Lockout
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Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capacitance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calculated from:
R HI =
[
RLO VIN − 2.38 ( ∆V/ VOUT + 1) + ∆V
(
2.38 − RLO (5 .5µA )
R FB = (RHI ) VOUT /∆V
]
)
25k suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V. ∆V is therefore 1.5V and
VIN = 12V. Let RLO = 25k.
[
)
2.38 – 25k(5.5µA )
25k (10.41)
=
= 116k
R HI =
(
]
25k 12 − 2.38 1.5 / 5 + 1 + 1.5
2.24
R FB = 116k 5 / 1.5 = 387k
(
)
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to initial operating frequency up to 700kHz. This means
that minimum practical sync frequency is equal to the
worst-case high self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when VC is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in
Figure 5, must be kept as short as possible. This is implemented in the suggested layout of Figure 6. Shortening
this path will also reduce the parasitic trace inductance of
approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT1766
switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages
across the LT1766 that may exceed its absolute maximum
LT1766
L1
5V
VIN
C3
HIGH
FREQUENCY
CIRCULATING
PATH
D1 C1
LOAD
1766 F05
Figure 5. High Speed Switching Path
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CONNECT TO
GROUND PLANE
GND
L1
C1
MINIMIZE LT1766
C3-D1 LOOP
GND
D2
D1
VOUT
C2
1 GND
15
3
14
4 VIN
C3
5
LT1766
6 BOOST
VIN
GND 16
2 SW
13
SHDN
FOR THE FE PACKAGE, THE
EXPOSED PAD (PIN 17) SHOULD
BE PROPERLY SOLDERED TO
THE GROUND PLANE.
NOTE: BOOST AND BIAS
COPPER TRACES ARE ON
A SEPARATE LAYER FROM
THE GROUND PLANE
KELVIN SENSE
VOUT
SYNC
FB 12
VC 11
7
BIAS 10
8 GND
GND 9
R2
R1 CFB
CF
RC
CC
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
KEEP FB AND VC COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
1766 F06
Figure 6. Suggested Layout
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and overall noise.
package, the exposed pad (Pin 17) should be soldered to
the copper ground plane underneath the device.
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1766
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
PARASITIC RESONANCE
Board layout also has a significant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, are a continuous
copper plate that runs under the LT1766 die. This is the
best thermal path for heat out of the package. Reducing
the thermal resistance from Pins 1, 8, 9 and 16 onto the
board will reduce die temperature and increase the power
capability of the LT1766. This is achieved by providing as
much copper area as possible around these pins. Adding
multiple solder filled feedthroughs under and around
these four corner pins to the ground plane will also help.
Similar treatment to the catch diode and coil terminations
will reduce any additional heating effects. For the FE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
If total lead length for the input capacitor, diode and
switch path is 1 inch, the inductance will be approximately
25nH. At switch off, this will produce a spike across the
NPN output device in addition to the input voltage. At
higher currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the
absolute max switch voltage. The path around switch,
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
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SW RISE
SW FALL
10V/DIV
SWITCH NODE
VOLTAGE
0.2A/DIV
INDUCTOR
CURRENT
AT IOUT = 0.1A
2V/DIV
50ns/DIV
VIN = 40V
VOUT = 5V
L = 47µH
1766 F07
Figure 7. Switch Node Resonance
switch off spike will also cause the SW node to go below
ground. The LT1766 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance resonate with the inductor to form damped ringing at 1MHz to
10 MHz. This ringing is not harmful to the regulator and it
has not been shown to contribute significantly to EMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
1µs/DIV
1766 F08
Figure 8. Discontinuous Mode Ringing
Boost current loss:
PBOOST =
VOUT2 (IOUT / 36)
VIN
Quiescent current loss:
PQ = VIN (0.0015) + VOUT (0.003)
RSW = Switch resistance (≈ 0.3) hot
tEFF = Effective switch current/voltage overlap time
= (tr + tf + tIr + tIf)
tr = (VIN/1.2)ns
tf = (VIN/1.7)ns
tIr = tIf = (IOUT/0.05)ns
f = Switch frequency
Example: with VIN = 40V, VOUT = 5V and IOUT = 1A:
THERMAL CALCULATIONS
2
0.3)(1) (5)
(
=
+
(
)
PSW
Switch loss:
Total power dissipation in the IC is given by:
PSW =
( ) (VOUT) + tEFF(1/2)(IOUT)(VIN)(f)
RSW IOUT
2
VIN
(
97 •10 −9 (1/ 2)(1)(40) 200 •10 3
40
= 0.04 + 0.388 = 0.43W
Power dissipation in the LT1766 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formulas show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
PBOOST
)
2
5) (1 / 36)
(
=
= 0.02W
40
PQ = 40(0.0015) + 5(0.003) = 0.08W
PTOT = PSW + PBOOST + PQ
= 0.43W + 0.02W + 0.08W = 0.53W
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Thermal resistance for the LT1766 packages is influenced
by the presence of internal or backside planes.
SSOP (GN16) Package: With a full plane under the GN16
package, thermal resistance will be about 85°C/W.
TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance will be about 45°C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
TJ = TA + (θJA • PTOT)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
PDIODE =
( VF )( VIN – VOUT )(ILOAD )
VIN
VF = Forward voltage of diode (assume 0.63V at 1A)
PDIODE =
(0.63)(40 – 5)(1)
= 0.55W
40
PINDUCTOR = (ILOAD)2 (RL)
Die temperature can peak for certain combinations of V IN,
VOUT and load current. While higher VIN gives greater
switch AC losses, quiescent and catch diode losses, a
lower VIN may generate greater losses due to switch DC
losses. In general, the maximum and minimum VIN levels
should be checked with maximum typical load current for
calculation of the LT1766 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin current
over temperature in an oven. This should be done with
minimal device power (low V IN and no switching
(VC = 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature, by increasing the voltage
drop in the path of the boost diode D2 (see Figure 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions. BOOST pin circuitry dissipates power given
by:
RL = Inductor DC resistance (assume 0.1Ω)
PINDUCTOR (1)2 (0.1) = 0.1W
Only a portion of the temperature rise in the external
inductor and diode is coupled to the junction of the LT1766.
Based on empirical measurements the thermal effect on
LT1766 junction temperature due to power dissipation in
the external inductor and catch diode can be calculated as:
∆TJ(LT1766) ≈ (PDIODE + PINDUCTOR)(10°C/W)
Using the example calculations for LT1766 dissipation,
the LT1766 die temperature will be estimated as:
TJ = TA + (θJA • PTOT) + [10 • (PDIODE + PINDUCTOR)]
With the GN16 package (θJA = 85°C/W), at an ambient
temperature of 60°C:
TJ = 60 + (85 • 0.53) + (10 • 0.65) = 112°C
With the TSSOP package (θJA = 45°C/W), at an ambient
temperature of 60°C:
TJ = 60 + (45 • 0.53) + (10 • 0.65) = 90°C
PDISS(BOOST) =
VOUT • (ISW / 36) • VC 2
VIN
Typically VC2 (the boost voltage across the capacitor C2)
equals Vout. This is because diodes D1 and D2 can be
considered almost equal, where:
VC2 = VOUT – VFD2 – (–VFD1) = VOUT
Hence the equation used for boost circuitry power dissipation given in the previous Thermal Calculations section is
stated as:
PDISS(BOOST) =
VOUT • (ISW / 36)• VOUT
VIN
Here it can be seen that boost power dissipation increases
as the square of VOUT. It is possible, however, to reduce
VC2 below VOUT to save power dissipation by increasing
the voltage drop in the path of D2. Care should be taken
that VC2 does not fall below the minimum 3.3V boost
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voltage required for full saturation of the internal power
switch. For output voltages of 5V, VC2 is approximately 5V.
During switch turn on, VC2 will fall as the boost capacitor
C2 is dicharged by the boost pin. In the previous Boost Pin
section, the value of C2 was designed for a 0.7V droop in
VC2 = VDROOP. Hence, an output voltage as low as 4V
would still allow the minimum 3.3V for the boost function
using the C2 capacitor calculated. If a target output voltage
of 12V is required, however, an excess of 8V is placed
across the boost capacitor which is not required for the
boost function but still dissipates additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 1A is given by:
D2
D4
D2
C2
BOOST
VIN
C3
L1
VOUT
SW
VIN
D1
LT1766
SHDN
BIAS
SYNC
FB
R1
GND
+
C1
R2
VC
CF
RC
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T(ambient) savings = 0.116W • 45°C/W = 5c. For a GN Package with
thermal resistance of 85°C/W, ambient temperature savings would be T/(ambient) savings = 0.116 • 85°C/W =
10c. The 7V zener should be sized for excess of 0.116W
operation. The tolerances of the zener should be considered to ensure minimum VC2 exceeds 3.3V + VDROOP.
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1766
is specified at 60V. This is based solely on internal semiconductor junction breakdown effects. Due to internal
power dissipation, the actual maximum VIN achievable in
a particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section, Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switching loss is also proportional to the square of input voltage.
For example, while the combination of VIN = 40V, VOUT =
5V at 1A and fOSC = 200kHz may be easily achievable,
simultaneously raising VIN to 60V and fOSC to 700kHz is
not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the resulting increase in internal dissipation is of insufficient time
duration to raise die temperature significantly.
A second consideration is controllability. A potential limitation occurs with a high step-down ratio of VIN to VOUT,
as this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
CC
1766 F09
Figure 9. Boost Pin, Diode Selection
PBOOST
12 • (1 / 36)• 12
=
= 0.2W
20
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
PBOOST
12 • (1 / 36)• 5
=
= 0.084 W
20
Min tON =
VOUT + VF
VIN ( fOSC )
where:
VIN = input voltage
VOUT = output voltage
VF = Schottky diode forward drop
fOSC = switching frequency
A potential controllability problem arises if the LT1766 is
called upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower then reduce the
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1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Considerations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high VIN, low VOUT
and high fOSC can result in an unacceptably short
minimum switch on time. Cycle skipping and/or odd/
even cycle behavior will result although correct output
voltage is usually maintained.
CURRENT MODE
POWER STAGE
gm = 2mho
VSW
ERROR
AMPLIFIER
OUTPUT
CFB
R1
FB
TANTALUM CERAMIC
gm =
2000µmho
+
In summary:
LT1766
–
VC control voltage to the point where some sort of cycleskipping or odd/even cycle behavior is exhibited.
RO
200k
GND
1.22V
ESR
ESL
C1
C1
+
RLOAD
VC
R2
RC
CF
CC
1766 F10
Figure 10. Model for Loop Response
80
180
60
150
GAIN
The LT1766 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1766 can be considered as two gm blocks, the error
amplifier and the power stage.
Figure 11 shows the overall loop response. At the VC pin,
the frequency compensation components used are:
RC = 2.2k, CC = 0.022µF and CF = 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ.
The ESR of the tantalum output capacitor provides a useful
zero in the loop frequency response for maintaining stabil-
GAIN (dB)
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the VC compensation to a
ground track carrying significant switch current. In addition, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with production layout and components.
40
120
20
90
PHASE
0
60
–20
30
–40
10
100
1k
10k
100k
FREQUENCY (Hz)
VIN = 42V
RC = 2.2k
VOUT = 5V
CC = 22nF
ILOAD = 500mA
CF = 220pF
COUT = 100µF, 10V, 0.1Ω
PHASE (DEG)
FREQUENCY COMPENSATION
0
1M
1766 F11
Figure 11. Overall Loop Response
ity. This ESR, however, contributes significantly to the
ripple voltage at the output (see Output Ripple Voltage in
the Applications Section). It is possible to reduce capacitor size and output ripple voltage by replacing the tantalum
output capacitor with a ceramic output capacitor because
of its very low ESR. The zero provided by the tantalum
output capacitor must now be reinserted back into the
loop. Alternatively there may be cases where, even with
the tantalum output capacitor, an additional zero is required in the loop to increase phase margin for improved
transient response.
A zero can be added into the loop by placing a resistor, RC,
at the VC pin in series with the compensation capacitor, CC
or by placing a capacitor, CFB, between the output and the
FB pin.
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When using RC, the maximum value has two limitations.
First, the combination of output capacitor ESR and RC may
stop the loop rolling off altogether. Second, if the loop gain
is not rolled off sufficiently at the switching frequency,
output ripple will peturb the VC pin enough to cause
unstable duty cycle switching similar to subharmonic
oscillations. If needed, an additional capacitor CF can be
added across the RC/CC network from the VC pin to ground
to further suppress VC ripple voltage.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example, a battery powered device with a wall adapter input,
the output of the LT1766 can be held up by the backup
supply with the LT1766 input disconnected. In this condition, the SW pin will source current into the VIN pin. If the
SHDN pin is held at ground, only the shut down current of
25µA will be pulled via the SW pin from the second supply.
With the SHDN pin floating, the LT1766 will consume its
quiescent operating current of 1.5mA. The VIN pin will also
source current to any other components connected to the
input line. If this load is greater than 10mA or the input
could be shorted to ground, a series Schottky diode must
be added, as shown in Figure 12. With these safeguards,
the output can be held at voltages up to the VIN absolute
maximum rating.
With a tantalum output capacitor, the LT1766 already
includes a resistor, RC and filter capacitor, CF, at the VC pin
(see Figures 10 and 11) to compensate the loop over the
entire VIN range (to allow for stable pulse skipping for high
VIN-to-VOUT ratios ≥10). A ceramic output capacitor can
still be used with a simple adjustment to the resistor RC for
stable operation. (See Ceramic Capacitors section for
stabilizing LT1766). If additional phase margin is required,
a capacitor, CFB, can be inserted between the output and
FB pin but care must be taken for high output voltage
applications. Sudden shorts to the output can create
unacceptably large negative transients on the FB pin.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, CSS and Q1.
As the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through CSS defined by R4 and Q1’s VBE. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
For VIN-to-VOUT ratios <10, higher loop bandwidths are
possible by readjusting the frequency compensation components at the VC pin.
When checking loop stability, the circuit should be operated over the applications’s full voltage, current and temperature range. Proper loop compensation may be obtained by emperical methods as described in detail in
Application Notes 19 and 76.
D2
1N4148W
D3
10MQ060N
REMOVABLE
INPUT
C2
0.33µF
BOOST
VIN
LT1766
R3
54k
L1
47µH
SW
5V, 1A
BIAS
R1
15.4k
SHDN
SYNC
GND
R4
25k
C3
2.2µF
RC
2.2k
CC
0.022µF
FB
VC
D1
10MQ060N
R2
4.99k
+
ALTERNATE
SUPPLY
C1
100µF
10V
CF
220pF
1766 F12
Figure 12. Dual Source Supply with 25µA Reverse Leakage
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(R4)(CSS )(VOUT )
RiseTime =
VBE
Using the values shown in Figure 10,
47 • 103 )(15 • 10–9 )(5)
(
Rise Time =
= 5ms
0.7
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
D2
1N4148W
INPUT
40V
BOOST
C3
2.2µF
50V
CER
C2
0.33µF
BIAS
L1
47µH
SW
VIN
D1
LT1766
SHDN
SYNC GND
RC
2.2k
CC
0.022µF
OUTPUT
5V
1A
C1
100µF
+
R1
15.4k
At switch off, energy is transferred by magnetic coupling
into L1B, powering the – 5V rail. C4 pulls L1B positive
during switch on time, causing current to flow, and energy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit, including
maximum output currents, see Design Note 100.
D2
1N4148W
C2
0.33µF
VIN
7.5V
TO 60V
C3
2.2µF
100V
CER
R3
2k
CSS
15nF
1766 F13
R4
47k
LT1766
R1
15.4k
SHDN
SYNC
GND
C1
100µF
10V
TANT
+
FB
R2
4.99k
VC
CF
220pF
D1
GND
C4
100µF
10V
TANT
R2
4.99k
CF
220pF Q1
VOUT1
5V
(SEE DN100
FOR MAX IOUT)
SW
VIN
RC
2.2k
CC
0.022µF
FB
VC
L1A*
50µH
BOOST
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX50-3A
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 10MQ060N
+
L1B*
C5
100µF
10V
TANT
+
1766 F14
VOUT2
–5V†
D3
Figure 14. Dual Output SEPIC Converter
Figure 13. Buck Converter with Adjustable Soft-Start
DUAL OUTPUT SEPIC CONVERTER
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 14 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard Coiltronics inductor. The topology for the 5V
output is a standard buck converter. The – 5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates a SEPIC
(single-ended primary inductance converter) topology
which improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flyback converter, during switch on time, all the converter’s
energy is stored in L1A only, since no current flows in L1B.
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT1766 accepts only positive feedback signals. The ground pin must be tied to the regulated negative
output. A resistor divider to the FB pin then provides the
proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
IMAX

( VIN )( VOUT ) 
IP – 2( V
( VOUT )( VIN – 0.3)
OUT + VIN )( f)(L) 

=
( VOUT + VIN – 0.3)( VOUT + VF )
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Output current where continuous mode is needed:
IP = Maximum rated switch current
VIN = Minimum input voltage
VOUT = Output voltage
VF = Catch diode forward voltage
0.3 = Switch voltage drop at 1.5A
ICONT >
Example: with VIN(MIN) = 5.5V, VOUT = 12V, L = 18µH,
VF = 0.63V, IP = 1.5A: IMAX = 0.280A.
OUTPUT DIVIDER
Refer to Applications Information Feedback Pin Functions
to calculate R1 and R2 for the (negative) output voltage
(from Table 1).
†
Minimum inductor discontinuous mode:
C3
2.2µF
100V
CER
C2
0.33µF
BOOST
L1*
18µH
Minimum inductor continuous mode:
LMIN =
R1
44.2k
LT1766
GND
VC
FB
CC
CF
( VIN )( VOUT )

 (V
+ V ) 
2( f)( VIN + VOUT )IP – IOUT  1 + OUT F  


VIN

For a 40V to –12V converter using the LT1766 with peak
switch current of 1.5A and a catch diode of 0.63V:
VSW
VIN
2( VOUT )(IOUT )
( f)(IP )2
LMIN =
D2
1N4148W
INPUT†
5.5V TO
48V
RC
D1
10MQO60N
+
R2
4.99k
( VIN )2 (IP )2
4( VIN + VOUT )( VIN + VOUT + VF )
C1
100µF
25V
TANT
ICONT >
OUTPUT**
–12V, 0.25A
* INCREASE L1 TO 30µH OR 60µH FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
† FOR V > 44V AND V
IN
OUT = –12V, ADDITIONAL VOLTAGE DROP IN THE
PATH OF D2 IS REQUIRED TO ENSURE BOOST PIN MAXIMUM RATING IS
NOT EXCEEDED. SEE APPLICATIONS INFORMATION (BOOST PIN VOLTAGE)
1766 F15
Figure 15. Positive-to-Negative Converter
Inductor Value
The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be used,
but in some cases (lower output load currents) it may give
a value that creates unnecessarily high output ripple
voltage.
The difficulty in calculating the minimum inductor size
needed is that you must first decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 1.5A. The first step is
to use the following formula to calculate the load current
above which the switcher must use continuous mode. If
your load current is less than this, use the discontinuous
mode formula to calculate minimum inductor needed. If
load current is higher, use the continuous mode formula.
(40)2 (1.5)2
= 0.573A
4(40 + 12)(40 + 12 + 0.63)
For a load current of 0.25A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:
LMIN =
2(12)(0.25)
= 13.3µH
(200 • 103 )(1.5)2
In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
18µH for this application.
Ripple Current in the Input and Output Capacitors
Positive-to-negative converters have high ripple current in
the input capacitor. For long capacitor lifetime, the RMS
value of this current must be less than the high frequency
ripple current rating of the capacitor. The following formula will give an approximate value for RMS ripple current. This formula assumes continuous mode and large
inductor value. Small inductors will give somewhat higher
ripple current, especially in discontinuous mode. The
exact formulas are very complex and appear in Application
Note 44, pages 29 and 30. For our purposes here a fudge
factor (ff) is used. The value for ff is about 1.2 for higher
1766fa
24
LT1766/LT1766-5
U
W
U U
APPLICATIO S I FOR ATIO
load currents and L ≥15µH. It increases to about 2.0 for
smaller inductors at lower load currents.
Input Capacitor IRMS = ( ff)(IOUT )
VOUT
VIN
ff = 1.2 to 2.0
The output capacitor ripple current for the positive-tonegative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak
value equal to the peak-to-peak triangular waveform of the
inductor. The low output ripple design in Figure 15 places
the input capacitor between VIN and the regulated negative
output. This placement of the input capacitor significantly
reduces the size required for the output capacitor (versus
placing the input capacitor between VIN and ground).
The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:
IP-P =
DC • VIN
f •L
DC = Duty Cycle =
ICOUT (RMS) =
VOUT + VF
VOUT + VIN + VF
IP-P
12
BOOST Pin Voltage
To ensure that the BOOST pin voltage does not exceed its
absolute maximum rating of 68V with respect to device
GND pin voltage, care should be taken in the generation of
boost voltage. For the conventional method of generating
boost voltage, shown in Figure 1, the voltage at the BOOST
pin during switch on time is approximately given by:
VBOOST (GND pin) = (VIN – VGNDPIN) + VC2
where:
VC2 = (D2+) – VD2 – (D1+) + VD1
= voltage across the “boost” capacitor
For the positive-to-negative converter shown in Figure 15,
the conventional Buck output node is grounded (D2+) = 0V
and the catch diode (D1+) is connected to the negative
output = VOUT = –12V. Absolute maximum ratings should
also be observed with the GND pin now at –12V. It can be
seen that for VD1 = VD2:
VC2 = (D2+) – (D1+) = |VOUT| = 12V
The output ripple voltage for this configuration is as low as
the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the
ESR of the chosen capacitor (see Output Ripple Voltage in
Applications Information).
Diode Current
The maximum VIN voltage allowed for the device (GND pin
at –12V) is 48V.
The maximum VIN voltage allowed without exceeding the
BOOST pin voltage absolute maximum rating is given by:
VIN(MAX) = Boost (Max) + (VGNDPIN) – VC2
VIN(MAX) = 68 + (–12) – 12 = 44V
Average diode current is equal to load current. Peak diode
current will be considerably higher.
Peak diode current:
Continuous Mode =
(V + V )
( VIN )( VOUT )
IOUT IN OUT +
VIN
2(L)( f)( VIN + VOUT )
Discontinuous Mode =
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with
normal loads. Care should be used if diodes rated less than
1A are used, especially if continuous overload conditions
must be tolerated.
To increase usable VIN voltage, VC2 must be reduced. This
can be achieved by placing a zener diode VZ1 (anode at
C2+) in series with D2.
Note: A maximum limit on VZ1 must be observed to
ensure a minimum VC2 is maintained on the “boost”
capacitor; referred to as “VBOOST(MIN)” in the Electrical
Characteristics.
2(IOUT )( VOUT )
(L)( f)
1766fa
25
LT1766/LT1766-5
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation BB)
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
6.60 ±0.10
9
2.94
(.116)
4.50 ±0.10
SEE NOTE 4
2.94 6.40
(.116) BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.09 – 0.20
(.0036 – .0079)
0.45 – 0.75
(.018 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
0.05 – 0.15
(.002 – .006)
FE16 (BB) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
1766fa
26
LT1766/LT1766-5
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
1766fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT1766/LT1766-5
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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4.4A (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converters
VIN: 7.3V to 45V/64V, VOUT(MIN): 2.21V, IQ: 8.5mA,
ISD: 10µA, DD-5/7, TO220-5/7
LT1076/LT1076HV
1.6A (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converters
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ISD: 10µA, DD-5/7, TO220-5/7
LT1616
500mA (IOUT), 1.4MHz, High Efficiency
Step-Down DC/DC Converter
VIN: 3.6V to 25V, VOUT(MIN): 1.25V, IQ: 1.9mA,
ISD: <1µA, ThinSOT™
LT1676
60V, 440mA (IOUT), 100kHz, High Efficiency
Step-Down DC/DC Converter
VIN: 7.4V to 60V, VOUT(MIN): 1.24V, IQ: 3.2mA,
ISD: 2.5µA, S8
LT1765
25V, 2.75A (IOUT), 1.25MHz, High Efficiency
Step-Down DC/DC Converter
VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 1mA,
ISD: 15µA, S8, TSSOP16E
LT1766
60V, 1.2A (IOUT), 200kHz, High Efficiency
Step-Down DC/DC Converter
VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA,
ISD: 25µA, TSSOP16/E
LT1767
25V, 1.2A (IOUT), 1.25MHz, High Efficiency
Step-Down DC/DC Converter
VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 1mA,
ISD: 6µA, MS8/E
LT1776
40V, 550mA (IOUT), 200kHz, High Efficiency
Step-Down DC/DC Converter
VIN: 7.4V to 40V, VOUT(MIN): 1.24V, IQ: 3.2mA,
ISD: 30µA, N8,S8
LT1940
Dual Output 1.4A (IOUT), Constant 1.1MHz, High Efficiency
Step-Down DC/DC Converter
VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 2.5mA,
ISD: <1µA, TSSOP-16E
LT1956
60V, 1.2A (IOUT), 500kHz, High Efficiency
Step-Down DC/DC Converter
VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA,
ISD: 25µA, TSSOP16/E
LT1976
60V, 1.2A (IOUT), 200kHz, Micropower (IQ = 100µA), High Efficiency
Step-Down DC/DC Converter
VIN: 3.3V to 60V, VOUT(MIN): 1.20V, IQ: 100µA,
ISD: <1µA, TSSOP16/E
LT3010
80V, 50mA, Low Noise Linear Regulator
VIN: 1.5V to 80V, VOUT(MIN): 1.28V, IQ: 30µA,
ISD: <1µA, MS8E
LTC3412
2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60µA,
ISD: <1µA, TSSOP16E
LTC3414
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
VIN: 2.3V to 5.5V, VOUT(MIN): 0.8V, IQ: 64µA,
ISD: <1µA, TSSOP20E
LT3430/LT3431
60V, 2.75A (IOUT), 200kHz/500kHz, High Efficiency
Step-Down DC/DC Converters
VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA,
ISD: 30µA, TSSOP16E
LT3433
High Voltage, Micropower (IQ = 100µA), Buck-Boost DC/DC Converter
VIN: 4V to 60V, IQ: 100µA, 500mA Switch Current,
TSSOP16E
LTC3727/LTC3727-1
36V, 500kHz, High Efficiency Step-Down DC/DC Controllers
VIN: 4V to 36V, VOUT(MIN): 0.8V, IQ: 670µA,
ISD: 20µA, QFN-32, SSOP-28
ThinSOT is a trademark of Linear Technology Corporation.
1766fa
28
Linear Technology Corporation
LT/TP 0903 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2001