AD AD538 Real-time analog computational unit acu Datasheet

a
Real-Time Analog
Computational Unit (ACU)
AD538
FUNCTIONAL BLOCK DIAGRAM
FEATURES
 VZ 
m
V OUT = VY 
 Transfer Function
 VX 
Wide Dynamic Range (Denominator) –1000:1
Simultaneous Multiplication and Division
Resistor-Programmable Powers and Roots
No External Trims Required
Low Input Offsets <100 ␮V
Low Error ⴞ0.25% of Reading (100:1 Range)
+2 V and +10 V On-Chip References
Monolithic Construction
APPLICATIONS
One- or Two-Quadrant Mult/Div
Log Ratio Computation
Squaring/Square Rooting
Trigonometric Function Approximations
Linearization Via Curve Fitting
Precision AGC
Power Functions
PRODUCT DESCRIPTION
The AD538 is a monolithic real-time computational circuit that
provides precision analog multiplication, division and exponentiation. The combination of low input and output offset voltages
and excellent linearity results in accurate computation over an
unusually wide input dynamic range. Laser wafer trimming makes
multiplication and division with errors as low as 0.25% of reading possible, while typical output offsets of 100 µV or less add to
the overall off-the-shelf performance level. Real-time analog
signal processing is further enhanced by the device’s 400 kHz
bandwidth.
The AD538’s overall transfer function is VO = VY (VZ / VX)m.
Programming a particular function is via pin strapping. No
external components are required for one-quadrant (positive
input) multiplication and division. Two-quadrant (bipolar
numerator) division is possible with the use of external level
shifting and scaling resistors. The desired scale factor for both
multiplication and division can be set using the on-chip +2 V or
+10 V references, or controlled externally to provide simultaneous multiplication and division. Exponentiation with an m
value from 0.2 to 5 can be implemented with the addition of
one or two external resistors.
IZ 1
VZ 2
LOG
RATIO
25kV
B 3
+10V 4
100V
100V
+VS 6
–VS 7
A
17
D
16
IX
15
VX
14
SIGNAL
GND
13
PWR
GND
12
C
11
IY
10
VY
25kV
+2V 5
INTERNAL
VOLTAGE
REFERENCE
18
AD538
OUTPUT
25kV
VO 8
ANTILOG
I 9
LOG
25kV
Direct log ratio computation is possible by using only the log
ratio and output sections of the chip. Access to the multiple
summing junctions adds further to the AD538’s flexibility.
Finally, a wide power supply range of ± 4.5 V to ± 18 V allows
operation from standard ± 5 V, ± 12 V and ± 15 V supplies.
The AD538 is available in two accuracy grades (A and B) over
the industrial (–25°C to +85°C) temperature range and one
grade (S) over the military (–55°C to +125°C) temperature
range. The device is packaged in an 18-lead TO-118 hermetic
side-brazed ceramic DIP. A-grade chips are also available.
PRODUCT HIGHLIGHTS
1. Real-time analog multiplication, division and exponentiation.
2. High accuracy analog division with a wide input dynamic
range.
3. On-chip +2 V or +10 V scaling reference voltages.
4. Both voltage and current (summing) input modes.
5. Monolithic construction with lower cost and higher reliability
than hybrid and modular circuits.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD538–SPECIFICATIONS (V = ⴞ15 V, T = +25ⴗC unless otherwise noted)
S
Parameters
A
AD538AD
Typ
Conditions
Min
Max
10 V ≥ VX , VY, VZ ≥ 0
VO = VY 

 VX 
400 µA ≥ IX , IY, I Z ≥ 0
VO = 25 kΩ × I Y 
I 
Min
AD538BD
Typ
Max
Min
AD538SD
Typ
Max
Units
MULTIPLIER DIVIDER
PERFORMANCE
Nominal Transfer
Function
Total Error Terms
100:1 Input Range 1
Wide Dynamic Range 2
Exponent (m) Range
OUTPUT
CHARACTERISTICS
Offset Voltage
Output Voltage Swing
Output Current
 VZ 
POWER SUPPLY
Rated
Operating Range 3
PSRR

PACKAGE OPTIONS
Ceramic (D-18)
Chips
X
I 

ⴞ1
ⴞ500
±1
±450
ⴞ2
ⴞ750
± 0.5
± 350
10 mV ≤ VX ≤ 10 V
1 mV ≤ VY ≤ 10 V
0 mV ≤ VZ ≤ 10 V
VZ ≤ 10 VX , m = 1.0
TA = T MIN to T MAX
±1
±200
±100
ⴞ2
ⴞ500
ⴞ250
±1
±450
±450
ⴞ3
ⴞ750
ⴞ750
0.2
VY = 0, VC = –600 mV
TA = T MIN to T MAX
RL = 2 kΩ
–11
5
VREF = 10 V or 2 V
TA = T MIN or TMAX
VREF = 10 V to 2 V
1
±4.5 V < V S < ±18 V
VX = V Y = V Z = 1 V
VOUT = 1 V
ⴞ4.5
–11
5
10
ⴞ50
ⴞ30
300
200
600
500
1
0.5
ⴞ18
0.1
4.5
7
–25
–65
 IZ 
ⴞ4.5
+85
+150

X

% of Reading +
µV
ⴞ1
ⴞ500
± 1.25
± 750
ⴞ2.5
ⴞ1000
% of Reading +
µV
± 0.5
± 100
± 750
ⴞ1
ⴞ250
ⴞ150
±1
± 200
± 200
ⴞ2
ⴞ500
ⴞ250
% of Reading +
µV +
µV × (V Y + VZ )/VX
±1
± 350
± 350
ⴞ2
ⴞ500
ⴞ500
±2
± 750
± 750
ⴞ4
ⴞ1000
ⴞ1000
% of Reading +
µV +
µV × (V Y + VZ )/VX
5
ⴞ250
ⴞ500
+11
10
± 15
± 20
2.5
ⴞ25
ⴞ30
300
200
600
500
± 15
0.2
0.05
4.5
7
+85
+150
AD538BD
5
± 200
± 750
–11
5
1
ⴞ18
0.1
–25
–65
AD538AD
m
VO = 25 kΩ × I Y 
I 
1.4
400
±25
±20
2.5
±15
m
ⴞ1
ⴞ500
± 100
± 350
ⴞ500
ⴞ750
+11
m
± 0.5
± 200
0.2
1.4
400
±4.5 V ≤ VS ≤ ± 18 V
±13 V ≤ VS ≤ ±18 V
RL = 2 kΩ
5
±200
±450
 VZ 
VO = VY 

 VX 
VO = 25 kΩ × I Y  Z 
 IX 
± 0.25
ⴞ0.5
± 100
ⴞ250
±0.5
±200
TA = T MIN to T MAX
m
m
100 mV ≤ VX ≤ 10 V
100 mV ≤ VY ≤ 10 V
100 mV ≤ VZ ≤ 10 V
VZ ≤ 10 VX, m = 1.0
TA = T MIN to T MAX
Quiescent Current
TEMPERATURE RANGE
Rated
Storage
 VZ 
VO = Vy 

 VX 
 IZ 
FREQUENCY RESPONSE
Slew Rate
Small Signal Bandwidth 100 mV ≤ 10 VY, VZ,
VX ≤ 10 V
VOLTAGE REFERENCE
Accuracy
Additional Error
Output Current
Power Supply Rejection
+2 V = VREF
+10 V = VREF
m
ⴞ4.5
–55
–65
10
µV
µV
V
mA
1.4
400
V/µs
kHz
ⴞ500
ⴞ1000
+11
± 25
± 30
2.5
ⴞ50
ⴞ50
mV
mV
mA
300
200
600
500
µV/V
µV/V
0.5
ⴞ18
0.1
V
V
%/V
4.5
7
mA
+125
+150
°C
°C
± 15
AD538SD
AD538SD/883B
AD538ACHIPS
NOTES
1
Over the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset
contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error.
2
The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by
the incremental gain (V Y + VZ) V X.
3
When using supplies below ± 13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
–2–
REV. C
AD538
RE-EXAMINATION OF MULTIPLIER/DIVIDER
ACCURACY
Traditionally, the “accuracy” (actually the errors) of analog
multipliers and dividers have been specified in terms of percent
of full scale. Thus specified, a 1% multiplier error with a 10 V
full-scale output would mean a worst case error of +100 mV at
“any” level within its designated output range. While this type
of error specification is easy to test evaluate, and interpret, it can
leave the user guessing as to how useful the multiplier actually is
at low output levels, those approaching the specified error limit
(in this case) 100 mV.
The AD538’s error sources do not follow the percent of fullscale approach to specification, thus it more optimally fits the
needs of the very wide dynamic range applications for which it is
best suited. Rather than as a percent of full scale, the AD538’s
error as a multiplier or divider for a 100:1 (100 mV to 10 V)
input range is specified as the sum of two error components: a
percent of reading (ideal output) term plus a fixed output offset.
Following this format the AD538AD, operating as a multiplier
or divider with inputs down to 100 mV, has a maximum error of
± 1% of reading ± 500 µV. Some sample total error calculations
for both grades over the 100:1 input range are illustrated in the
chart below. This error specification format is a familiar one to
designers and users of digital voltmeters where error is specified
as a percent of reading ± a certain number of digits on the meter
readout.
For operation as a multiplier or divider over a wider dynamic
range (>100:1), the AD538 has a more detailed error specification that is the sum of three components: a percent of reading
term, an output offset term and an input offset term for the
VY/VX log ratio section. A sample application of this specification, taken from Table I, for the AD538AD with VY = 1 V, VZ =
100 mV and VX = 10 mV would yield a maximum error of
± 2.0% of reading ± 500 µV ± (1 V + 100 mV)/10 mV × 250 µV
or ± 2.0% of reading ±500 µV ± 27.5 mV. This example illustrates that with very low level inputs the AD538’s incremental
gain (VY + VZ)/VX has increased to make the input offset contribution to error substantial.
Table I. Sample Error Calculation Chart (Worst Case)
100:1
INPUT
RANGE
Total Error =
± % rdg
± Output VOS
WIDE
DYNAMIC
RANGE
Total Error =
± % rdg
± Output VOS
± Input VOS ×
(VY + VZ)/VX
REV. C
VY
Input
(in V)
VZ
Input
(in V)
VX
Input
(in V)
Ideal
Output
(in V)
Total Offset
Error Term
(in mV)
% of Reading
Error Term
(in mV)
Total Error
Summation
(in mV)
Total Error Summation
as a % of the Ideal
Output
10
10
10
10
0.5
0.25
(AD)
(BD)
100 (AD)
50 (BD)
100.5 (AD)
50.25 (BD)
1.0 (AD)
0.5 (BD)
10
0.1
0.1
10
0.5
0.25
(AD)
(BD)
100 (AD)
50 (BD)
100.5 (AD)
50.25 (BD)
1.0 (AD)
0.5 (BD)
1
1
1
1
0.5
0.25
(AD)
(BD)
10 (AD)
5 (BD)
10.5
5.25
(AD)
(BD)
1.05 (AD)
0.5 (BD)
0.1
0.1
0.1
0.1
0.5
0.25
(AD)
(BD)
1 (AD)
0.5 (BD)
1.5
0.75
(AD)
(BD)
1.5 (AD)
0.75 (BD)
1
0.10
0.01
10
28
(AD)
16.75 (BD)
200 (AD)
100 (BD)
228 (AD)
116.75 (BD)
2.28 (AD)
1.17 (BD)
10
0.05
2
0.25
1.76
1
(AD)
(BD)
5 (AD)
2.5 (BD)
6.76
3.5
(AD)
(BD)
2.7 (AD)
1.4 (BD)
5
0.01
0.01
5
125.75 (AD)
75.4 (BD)
100 (AD)
50 (BD)
225.75 (AD)
125.4 (BD)
4.52 (AD)
2.51 (BD)
10
0.01
0.1
1
25.53 (AD)
15.27 (BD)
20 (AD)
10 (BD)
45.53 (AD)
25.27 (BD)
4.55 (AD)
2.53 (BD)
–3–
AD538
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW
Output Short Circuit-to-Ground . . . . . . . . . . . . . . . Indefinite
Input Voltages VX , VY, V Z . . . . . . . . . . . . . (+VS – 1 V), –1 V
Input Currents IX, IY, IZ, IO . . . . . . . . . . . . . . . . . . . . . . 1 mA
Operating Temperature Range . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Storage . . . . . . . . . . . . . . 60 sec, +300°C
Thermal Resistance
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
IZ
1
18 A
VZ
2
17 D
B
3
+10V
4
+2V
5
+VS
6
16 IX
AD538
15 VX
TOP VIEW
14 SIGNAL GND
(Not to Scale)
13 PWR GND
–VS
7
12 C
VO
8
11 IY
I
9
10 VY
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD538AD
AD538BD
AD538ACHIPS
AD538SD
AD538SD/883B
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
Side-Brazed Ceramic DIP
Side-Brazed Ceramic DIP
Chips
Side-Brazed Ceramic DIP
Side-Brazed Ceramic DIP
D-18
D-18
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD538 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
D-18
D-18
WARNING!
ESD SENSITIVE DEVICE
REV. C
1000
4.0
800
3.0
600
2.0
400
OFFSET
1.0
200
1M
SMALL SIGNAL BANDWITH – Hz
5.0
OUTPUT STAGE OFFSET – mV
TOTAL % OF READING ERROR
Typical Performance Characteristics– AD538
400k
VY = 10V dc
VZ = VX +0.05 VX SIN vt
100k
40k
% OF READING
–20
0
20
40
60
TEMPERATURE – 8C
80
100
10k
0.01
0
125
1000
4.0
800
3.0
600
400
OFFSET
1.0
200
TOTAL % OF READING ERROR
5.0
2.0
10
Figure 4. Small Signal Bandwidth vs. Denominator
Voltage (One-Quadrant Mult/Div)
OUTPUT STAGE OFFSET – mV
TOTAL % OF READING ERROR
Figure 1. Multiplier Error vs. Temperature
(100 mV < VX, VY, V Z ≤ 10 V)
0.1
1
DENOMINATOR VOLTAGE, VX – V dc
6.0
1200
5.0
1000
4.0
800
3.0
600
% OF READING
2.0
400
1.0
200
OUTPUT STAGE OFFSET – mV
0
–55 –40
OFFSET
% OF READING
–20
0
20
40
60
TEMPERATURE – 8C
80
100
0
–55 –40
0
125
Figure 2. Divider Error vs. Temperature
(100 mV < VX, VY, V Z ≤ 10 V)
TOTAL % OF READING ERROR
VO IN mV PEAK-TO-PEAK
VX = 10V
VY = 0V
VZ = 5V +5V SIN vt VOLTS
100
10
20
40
60
TEMPERATURE – 8C
80
100
0
125
5.0
1000
4.0
800
3.0
600
2.0
400
% OF READING
1.0
200
OFFSET
1k
10k
100k
INPUT FREQUENCY – Hz
0
–55 –40
1M
Figure 3. V Z Feedthrough vs. Frequency
REV. C
0
Figure 5. Multiplier Error vs. Temperature
(10 mV < VX, VY, V Z ≤ 100 mV)
1000
1
100
–20
–20
0
20
40
60
TEMPERATURE – 8C
80
100
0
125
Figure 6. Divider Error vs. Temperature
(10 mV < VX, VY, V Z ≤ 100 mV)
–5–
OUTPUT STAGE OFFSET – mV
0
–55 –40
AD538
100
VOLTAGE NOISE, en – mV Hz
VO IN mV PEAK-TO-PEAK
150
100
VX = 10V
VY = 5V +5V SIN vt VOLTS
VZ = 0V
10
1.0
0.1
100
1k
100k
10k
INPUT FREQUENCY – Hz
18
A
17
D
B 3
16
IX
+10V 4
15
VX
14
SIGNAL
GND
13
PWR
GND
12
C
VZ 2
LOG
RATIO
25kV
100V
100V
25kV
+2V 5
+VS 6
–VS 7
INTERNAL
VOLTAGE
REFERENCE
AD538
OUTPUT
11
IY
10
VY
ANTILOG
I 9
LOG
25kV
1
VX = 10V
0.10
10
Under normal operation, the log-ratio output will be directly
connected to a second functional block at input C, the antilog
subsection. This section performs the antilog according to the
transfer function:

q 
 VC kT 

VO = VY e 
As with the log-ratio circuit included in the AD538, the user
may use the antilog subsection by itself. When both subsections
are combined, the output at B is tied to C, the transfer function
of the AD538 computational unit is:
  kT   q   VZ  
ln


q   kT   VX  
;V
VO = VY e 
B
= VC
which reduces to:
V 
VO = VY  Z 
VX 
Figure 9. Functional Block Diagram
Finally, by increasing the gain, or attenuating the output of the
log ratio subsection via resistor programming, it is possible to
raise the quantity VZ /VX to the mth power. Without external
programming, m is unity. Thus the overall AD538 transfer
function equals:
FUNCTIONAL DESCRIPTION
As shown in Figures 9 and 10, the VZ and VX inputs connect
directly to the AD538’s input log ratio amplifiers. This subsection provides an output voltage proportional to the natural log
of input voltage VZ , minus the natural log of input voltage VX.
The output of the log ratio subsection at B can be expressed by
the transfer function:
VB
0.1
1
DC OUTPUT VOLTAGE – Volts
Figure 8. 1 kHz Output Noise Spectral Density vs. DC Output
Voltage
25kV
VO 8
VX = 0.01V
0.01
0.01
1M
Figure 7. VY Feedthrough vs. Frequency
IZ 1
10
FOR THE FREQUENCY RANGE OF 10Hz
TO 100kHz THE TOTAL RMS OUTPUT
NOISE, eo, FOR A GIVEN BANDWIDTH
Bw, IS CALCULATED eo = en Bw
VO = VY
V 
kT
=
ln  Z 
q
VX 
 VZ 
V 
 X
m
where 0.2 < m < 5.
When the AD538 is used as an analog divider, the VY input can
be used to multiply the ratio VZ / VX by a convenient scale factor.
The actual multiplication by the VY input signal is accomplished
by adding the log of the VY input signal to the signal at C, which
is already in the log domain.
where k = 1.3806 × 10–23 J/K,
q = 1.60219 × 10–19 C,
T is in Kelvins.
The log ratio configuration may be used alone, if correctly temperature compensated and scaled to the desired output level
(see Applications section).
–6–
REV. C
AD538
STABILITY PRECAUTIONS
ONE-QUADRANT MULTIPLICATION/DIVISION
At higher frequencies, the multistaged signal path of the AD538,
as illustrated in Figure 10, can result in large phase shifts. If a
condition of high incremental gain exists along that path (e.g.,
VO = VY × VZ / VX = 10 V × 10 mV/10 mV = 10 V so that
∆VO /∆VX = 1000), then small amounts of capacitive feedback
from VO to the current inputs IZ or IX can result in instability.
Appropriate care should be exercised in board layout to prevent capacitive feedback mechanisms under these conditions.
Figure 12 shows how the AD538 may be easily configured as a
precision one-quadrant multiplier/divider. The transfer function
VOUT = VY (VZ /VX) allows “three” independent input variables,
a calculation not available with a conventional multiplier. In
addition, the 1000:1 (i.e., 10 mV to 10 V) input dynamic range
of the AD538 greatly exceeds that of analog multipliers computing one-quadrant multiplication and division.
VOUT = VY
( VVZX )
Ln Z – Ln X
IX
LOGe
Ln X
M(Ln Z – Ln X)
VX
M(Ln Z – Ln X) +Ln Y
IZ 1
–
+
S
0.2#M#5
IZ
+
S
ANTILOGe
+
B
VZ M
VO = VY
VX
IY
LOGe
VZ
LOGe
Ln Z
VY
VZ
VZ
INPUT
BUFFER
Ln Y
IZ 1
LOG
RATIO
B 3
REF OUT
4
100V
50kV
11.5kV
+2V
100V
–VS 7
INTERNAL
VOLTAGE
REFERENCE
18
A
17
D
16
IX
15
VX
14
SIGNAL
GND
13
PWR
GND
12
C
11
IY
10
VY
25kV
5
+VS 6
AD538
OUTPUT
25kV
VO 8
I 9
16 IX
15
ANTILOG
LOG
100V
25kV
+2V 5
A stable bandgap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage output of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any
voltages between +2 V and +10.2 V buffered as shown in Figure
11. The output impedance at Pin 5 is approximately 5 kΩ. Note
that any loading of this pin will produce an error in the +10 V
reference voltage. External loads on the +2 V output should be
greater than 500 kΩ to maintain errors less than 1%.
25kV
17 D
3
100V
USING THE VOLTAGE REFERENCES
VZ 2
LOG
RATIO
25kV
2
+10V 4
Figure 10. Model Circuit
+2V TO +10.2V
BUFFERED
18 A
25kV
Figure 11. +2 V to +10.2 V Adjustable Reference
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pins 4 and 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
+15V
6
–15V
7
VO
14
INTERNAL
VOLTAGE
REFERENCE
13
AD538
12
OUTPUT
25kV
8
11
VX
SIGNAL
GND
VX
INPUT
PWR
GND
C
IY
IN4148
ANTILOG
OUTPUT
I
9
LOG
10
25kV
VY
VY
INPUT
Figure 12. One-Quadrant Combination Multiplier/Divider
By simply connecting the input VX (Pin 15) to the +10 V reference (Pin 4), and tying the log-ratio output at B to the antilog
input at C, the AD538 can be configured as a one-quadrant
analog multiplier with 10-volt scaling. If 2-volt scaling is desired,
VX can be tied to the +2 V reference.
When the input VX is tied to the +10 V reference terminal, the
multiplier transfer function becomes:
 V 
VO = VY  Z 
 10 V 
As a multiplier, this circuit provides a typical bandwidth of
400 kHz with values of VX , VY or VZ varying over a 100:1 range
(i.e., 100 mV to 10 V). The maximum error with a 100 mV to
10 V range for the two input variables will typically be +0.5% of
reading. Using the optional Z offset trim scheme, as shown in
Figure 13, this error can be reduced to +0.25% of reading.
By using the +10 V reference as the VY input, the circuit of
Figure 12 is configured as a one-quadrant divider with a fixed
scale factor. As with the one-quadrant multiplier, the inputs
accept only single (positive) polarity signals. The output of the
one-quadrant divider with a +10 V scale factor is:
V 
VO = 10V  Z 
 VX 
The typical bandwidth of this circuit is 370 kHz with 1 V to
10 V denominator input levels. At lower amplitudes, the bandwidth gradually decreases to approximately 200 kHz at the
2 mV input level.
REV. C
–7–
AD538
TWO-QUADRANT DIVISION
LOG RATIO OPERATION
The two-quadrant linear divider circuit illustrated in Figure 13
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage to it.
The offsetting scheme changes the divider’s transfer function
from:
Figure 14 shows the AD538 configured for computing the log of
the ratio of two input voltages (or currents). The output signal
from B is connected to the summing junction of the output amplifier via two series resistors. The 90.9 Ω metal film resistor effectively degrades the temperature coefficient of the ± 3500 ppm/°C
resistor to produce a 1.09 kΩ +3300 ppm/°C equivalent value.
In this configuration, the VY input must be tied to some voltage
less than zero (–1.2 V in this case) removing this input from the
transfer function.
V 
VO = 10V  Z 
 VX 
The 5 kΩ potentiometer controls the circuit’s scale factor adjustment providing a +1 V per decade adjustment. The output
offset potentiometer should be set to provide a zero output with
VX = VZ = 1 V. The input VZ adjustment should be set for an
output of 3 V with VZ = l mV and VX = 1 V.
to:
(V
Z
VO = 10V
+ AVX
VX
)

VZ 
= 10 V 1 A +


VX 
–VS
 VZ 
= 10 A + 10 V 

 VX 
 35 kΩ 
where A = 

 25 kΩ 
1MV
NUMERATOR
VZ
AD589
35kV
68kV
5%
10MV
IZ
VZ
3.9MV
B
+10V
R2
R1
10kV 12.4kV I
I
D
3
16 IX
4
15
100V
100V
25kV
5
14
INTERNAL
VOLTAGE
REFERENCE
AD538
13
12
OUTPUT
25kV
8
9
11
ANTILOG
LOG
25kV
10
48.7V
VX
INPUT
VX
SIGNAL
GND
PWR
GND
C
IY
VY
IN4148
+VS
10MV
10kV
OPTIONAL
OUTPUT VOS
ADJUSTMENT
The log ratio circuit shown achieves ±0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of fullscale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction at
the INPUT of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (i.e., 1 V × log10 (1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
18 A
1
35kV
LOG
RATIO
25kV
2
17 D
16
3
4
7
VO
VO
17
A
Figure 14. Log Ratio Circuit
100V
INTERNAL
VOLTAGE
REFERENCE
6
–15V
LOG
RATIO
25kV
2
–15V 7
SCALE
FACTOR
ADJUST
X
18
OUTPUT
–VS
25kV
+2V 5
OUTPUT
+2V
5kV 2kV
1%
( VVZX) VX $ VZ
100V
+15V
B
+10V
( VVZ )
1
+15V 6
–1.2V
1MV
VOS ADJ
VZ
1kV
+3500
ppm/8C
FOR
VOUT = 10
10MV IZ
90.9V
1%
DENOMINATOR
VX
–VS
VO = 1V LOG10
OPTIONAL
INPUT VOS
ADJUSTMENT
As long as the magnitude of the denominator input is equal to
or greater than the magnitude of the numerator input, the circuit will accept bipolar numerator voltages. However, under the
conditions of a 0 V numerator input, the output would incorrectly equal +14 V. The offset can be removed by connecting
the +10 V reference through resistors R1 and R2 to the output
section’s summing node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The pot R2 adjusts
out or corrects this offset, leaving the desired transfer function
of 10 V (VZ / VX).
OPTIONAL
Z OFFSET TRIM
68kV
5%
–1.2V
AD589
AD538
OUTPUT
15 VX
SIGNAL
GND
14
PWR
GND
13
IN4148
C
12
25kV
8
9
11
ANTILOG
LOG
25kV
IX
10
IY
VY
ZERO
ADJUST
Figure 13. Two-Quadrant Division with 10 V Scaling
–8–
REV. C
AD538
ANALOG COMPUTATION OF POWERS AND ROOTS
SQUARE ROOT OPERATION
It is often necessary to raise the quotient of two input signals to
a power or take a root. This could be squaring, cubing, squarerooting or exponentiation to some noninteger power. Examples
include power series generation. With the AD538, only one or
two external resistors are required to set ANY desired power,
over the range of 0.2 to 5. Raising the basic quantity VZ /VX to a
power greater than one requires that the gain of the AD538’s log
ratio subtractor be increased, via an external resistor between
pins A and D. Similarly, a voltage divider that attenuates the log
ratio output between points B and C will program the power to
a value less than one.
The explicit square root circuit of Figure 16 illustrates a precise
method for performing a real-time square root computation. For
added flexibility and accuracy, this circuit has a scale factor
adjustment.
RA
B
VZ
3
C
12
A
18
POWERS
2
VY (
VY
D
17
10
VZ m
)
VREF
VO
8
15
VX
VREF
m
RA
2
3
4
5
196V
97.6V
64.9V
48.7V
RA = 196V
M –1
RB = RC # 200V
RB
B
VZ
C
12
3
VY (
VY
ROOTS
10
VZ m
)
VREF
VO
8
15
VX
VREF
One volt scaling is achieved by dividing-down the 2 V reference
and applying approximately 1 V to both the VY and VX inputs.
In this circuit, the VX input is intentionally set low, to about
0.95 V, so that the VY input can be adjusted high, permitting a
± 5% scale factor trim. Using this trim scheme, the output voltage will be within ± 3 mV ± 0.2% of the ideal value over a 10 V
to 1 mV input range (80 dB). For a decreased input dynamic
range of 10 mV to 10 V (60 dB) the error is even less; here the
output will be within ± 2 mV ± 0.2% of the ideal value. The
bandwidth of the AD538 square root circuit is approximately
280 kHz with a 1 V p-p sine wave with a +2 V dc offset.
This basic circuit may also be used to compute the cube, fourth
or fifth roots of an input waveform. All that is required for a
given root is that the correct ratio of resistors, RC and RB, be
selected such that their sum is between 150 Ω and 200 Ω.
RC
2
The actual square rooting operation is performed in this circuit
by raising the quantity VZ / VX to the one-half power via the
resistor divider network consisting of resistors RB and RC. For
maximum linearity, the two resistors should be 1% (or better)
ratio-matched metal film types.
m
RB
RC
1/2
1/3
1/4
1/5
100V
100V
150V
162V
100V
49.9V
49.9V
40.2V
The optional absolute value circuit shown preceding the AD538
allows the use of bipolar input voltages. Only one op amp is
required for the absolute value function because the IZ input of
the AD538 functions as a summing junction. If it is necessary to
preserve the sign of the input voltage, the polarity of the op amp
output may be sensed and used after the computation to switch
the sign bit of a D.V.M. chip.
RB
= 1 –1
RC M
Figure 15. Basic Configurations and Transfer Functions
for the AD538
VOUT = 1V
OPTIONAL
ABSOLUTE VALUE SECTION
5kV
10kV
IZ
20kV
IN4148
VZ
IN4148
VIN
1V
1
LOG
RATIO
25kV
2
18
A
17
D
16
IX
RB
*
100V
+VS
B
7
VIN
20kV 2
3
20kV
VOS
1
8
+10V
6
3
15
4
100V
AD OP-07
4 OR AD611
(VOS TAP
–VS
TO –VS)
+2V
+2V
5
14
INTERNAL
VOLTAGE
REFERENCE
+15V 6
–15V 7
VO
VOUT
100V
25kV
13
AD538
12
OUTPUT
25kV
11
8
ANTILOG
I 9
LOG
1kV
10
VX
SIGNAL
GND
PWR
GND
C
IY
D1
VY IN4148
25kV
100V
SCALE FACTOR
TRIM
1kV
* RATIO MATCH 1% METAL FILM
RESISTORS FOR BEST ACCURACY
Figure 16. Square Root Circuit
REV. C
–9–
RC
100V *
AD538
TRANSDUCER LINEARIZATION
Vu = [VuREF –Vu] 3
Many electronic transducers used in scientific, commercial or
industrial equipment monitor the physical properties of a device
and/or its environment. Sensing (and perhaps compensating for)
changes in pressure, temperature, moisture or other physical
phenomenon can be an expensive undertaking, particularly
where high accuracy and very low nonlinearity are important. In
conventional analog systems accuracy may be easily increased
by offset and scale factor trims, however, nonlinearity is usually
the absolute limitation of the sensing device.
VZ
VZ
B
+10V
LOG
RATIO
25kV
4
100V
where:
25kV
+2V 5
–15V
+VS
1mF
–VS
1mF
Vu
VO
15
14
INTERNAL
VOLTAGE
REFERENCE
6
7
A
D
RA
931V, 1%
16 IX
3
AD538
13
12
OUTPUT
25kV
8
11
ANTILOG
I 9
LOG
25kV
10
VX
SIGNAL
GND
VX
PWR
GND
C
IY
IN4148
VY
0.1mF
R1*
100kV

) (( ))

17
100V
+15V
The circuit of Figure 17 is typical of those AD538 applications
where the quantity VZ /VX is raised to powers greater than one.
In an approximate arc-tangent function, the AD538 will accurately compute the angle that is defined by X and Y displacements represented by input voltages VX and VZ. With accuracy
to within one degree (for input voltages between 100 µV and
10 volts), the AD538 arc-tangent circuit is more precise than
conventional analog circuits and is faster than most digital techniques. For a direct arc-tangent computation that requires fewer
external components, refer to the AD639 data sheet. The circuit
shown is set up for the transfer function:
(
( ZX )
18
2
ARC-TANGENT APPROXIMATION
 VZ
Vθ = Vθ REF − Vθ 
 VX
u = TAN–1
IZ 1
With the ability to easily program a complex analog function,
the AD538 can effectively compensate for the nonlinearities of
an inexpensive transducer. The AD538 can be connected between the transducer preamplifier output and the next stage of
monitoring or transmitting circuitry. The recommended procedure for linearizing a particular transducer is first to find the
closest function which best approximates the nonlinearity of the
device and then, to select the appropriate exponent resistor
value(s).
1.21
1.21
(VVZX )
10kV
FULL-SCALE
ADJUST
+15V
R2*
100kV
AD547JH
118kV
* RATIO MATCH 1% METAL
1mF
100kV
–15V
FILM RESISTORS FOR BEST
ACCURACY
Figure 17. The Arc-Tangent Function
The VB /VA quantity is calculated in the same manner as in the
one-quadrant divider circuit, except that the resulting quotient
is raised to the 1.21 power. Resistor RA (nominally 931 Ω) sets
the power or m factor.
For the highest arc-tangent accuracy the external resistors R1
and R2 should be ratio matched; however, the offset trim
scheme shown in other circuits is not required since nonlinearity
effects are the predominant source of error. Also note that instability will occur as the output approaches 90° because, by definition, the arc-tangent function is infinite and therefore, the AD538’s
gain will be extremely high.
Z

X
θ = Tan −1 
The (VθREF – Vθ) function is implemented in this circuit by
adding together the output, Vθ, and an externally applied reference voltage, VθREF, via an external AD547 op amp. The 1 µF
capacitor connected around the AD547’s 100 kΩ feedback
resistor frequency compensates the loop (formed by the amplifier between Vθ and VY).
–10–
REV. C
AD538
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18
10
0.30 (7.62)
0.28 (7.12)
1
9
PIN 1
0.91 (23.12)
0.89 (22.61)
0.306 (7.78)
0.294 (7.47)
0.175 (4.45)
0.125 (3.18)
0.17 (4.32)
MAX
SEATING
PLANE
0.012 (0.305)
0.008 (0.203)
PRINTED IN U.S.A.
0.02 (0.508) 0.105 (2.67) 0.06 (1.53)
0.015 (0.381) 0.095 (2.42) 0.04 (1.02)
0.12 (3.05)
0.06 (1.53)
C959d–0–12/99 (rev. C)
Side-Brazed Ceramic DIP
(D-18)
REV. C
–11–