Fairchild FQA24N60 600v n-channel mosfet Datasheet

FQA24N60
April 2000
QFET
TM
FQA24N60
600V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.
•
•
•
•
•
•
23.5A, 600V, RDS(on) = 0.24 Ω @ VGS = 10 V
Low gate charge ( typical 110 nC)
Low Crss ( typical 56 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
"
! "
G!
G DS
Absolute Maximum Ratings
Symbol
VDSS
"
"
TO-3P
!
FQA Series
S
TC = 25°C unless otherwise noted
Parameter
ID
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
IDM
Drain Current
FQA24N60
- Continuous (TC = 100°C)
- Pulsed
Units
600
V
23.5
A
14.9
A
(Note 1)
94
A
VGSS
Gate-Source Voltage
±30
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
1300
mJ
23.5
A
IAR
Avalanche Current
(Note 1)
EAR
Repetitive Avalanche Energy
(Note 1)
31
mJ
dv/dt
PD
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 3)
4.5
310
2.5
-55 to +150
Vns
W
W/°C
°C
300
°C
TJ, TSTG
TL
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8 from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Thermal Resistance, Junction-to-Case
Parameter
RθCS
Thermal Resistance, Case-to-Sink
RθJA
Thermal Resistance, Junction-to-Ambient
©2000 Fairchild Semiconductor International
Typ
Max
--
0.4
Units
°CW
0.24
--
°CW
--
40
°CW
Rev. A, April 2000
Symbol
C
= 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
600
--
--
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/ ∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
--
0.6
--
V/°C
VDS = 600 V, VGS = 0 V
--
--
10
µA
VDS = 480 V, TC = 125°C
IDSS
Zero Gate Voltage Drain Current
--
--
100
µA
IGSSF
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
IGSSR
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
3.0
--
5.0
V
--
0.18
0.24
Ω
--
22.5
--
S
--
4200
5500
pF
--
550
720
pF
--
56
75
pF
--
90
190
ns
ns
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 11.8 A
gFS
Forward Transconductance
VDS = 50 V, ID = 11.8 A
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 300 V, ID = 23.5 A,
RG = 25 Ω
(Note 4, 5)
VDS = 480 V, ID = 23.5 A,
VGS = 10 V
(Note 4, 5)
--
270
550
--
200
410
ns
--
170
350
ns
--
110
145
nC
--
25
--
nC
--
53
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
23.5
A
ISM
--
--
94
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 23.5 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
--
470
--
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 23.5 A,
dIF / dt = 100 A/µs
--
6.2
--
µC
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 4.3mH, IAS = 23.5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 23.5A, di/dt 200A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, April 2000
FQA24N60
Electrical CharacteristicsT
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
1
150
10
ID, Drain Current [A]
ID, Drain Current [A]
Top :
1
10
25
0
10
0
-55
Notes :
1. 250s Pulse Test
2. TC = 25
10
Notes :
1. VDS = 50V
2. 250s Pulse Test
-1
-1
0
10
10
1
10
2
10
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
1.0
VGS = 10V
IDR, Reverse Drain Current [A]
RDS(ON) [ ],
Drain-Source On-Resistance
0.8
1
10
0.6
VGS = 20V
0.4
0
10
0.2
150
25
Notes :
1. VGS = 0V
2. 250s Pulse Test
Note : TJ = 25
0.0
-1
0
10
20
30
40
50
60
70
80
90
100
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and
Temperature
12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
8000
VDS = 120V
Ciss
6000
Coss
4000
Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
2000
VGS, Gate-Source Voltage [V]
10
Capacitance [pF]
FQA24N60
Typical Characteristics
VDS = 300V
VDS = 480V
8
6
4
2
Note : ID = 23.5 A
0
0
-1
10
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
20
40
60
80
100
120
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, April 2000
FQA24N60
Typical Characteristics
(Continued)
3.0
1.2
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
RDS(ON) , (Normalized)
Drain-Source On-Resistance
1.1
1.0
Notes :
1. VGS = 0 V
2. ID = 250 A
0.9
0.8
-100
-50
0
50
100
2.0
1.5
1.0
Notes :
1. VGS = 10 V
2. ID = 11.8 A
0.5
150
0.0
-100
200
-50
0
o
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
24
Operation in This Area
is Limited by R DS(on)
20
2
10
100 µs
ID, Drain Current [A]
ID, Drain Current [A]
10 µs
1 ms
1
10 ms
10
DC
0
10
Notes :
16
12
8
o
1. TC = 25 C
4
o
2. TJ = 150 C
3. Single Pulse
-1
10
0
1
10
2
10
0
25
3
10
10
50
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
10
N o te s :
1 . Z J C ( t) = 0 .4 /W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z J C ( t)
-1
0 .2
0 .1
0 .0 5
PDM
0 .0 2
10
0 .0 1
-2
t1
t2
s i n g l e p u ls e
Z
JC
75
TC, Case Temperature []
VDS, Drain-Source Voltage [V]
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, April 2000
FQA24N60
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50K
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
10V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2000 Fairchild Semiconductor International
ID (t)
VDS (t)
VDD
tp
Time
Rev. A, April 2000
FQA24N60
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A, April 2000
TO-3P
15.60 ±0.20
18.70 ±0.20
23.40 ±0.20
19.90 ±0.20
1.00 ±0.20
16.50 ±0.30
3.00 ±0.20
+0.15
1.50 –0.05
3.50 ±0.20
2.00 ±0.20
9.60 ±0.20
4.80 ±0.20
3.80 ±0.20
ø3.20 ±0.10
12.76 ±0.20
13.60 ±0.20
13.90 ±0.20
FQA24N60
Package Dimensions
1.40 ±0.20
+0.15
5.45TYP
[5.45 ±0.30]
©2000 Fairchild Semiconductor International
5.45TYP
[5.45 ±0.30]
0.60 –0.05
Rev. A, April 2000
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FACT Quiet Series™
FAST®
FASTr™
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MICROWIRE™
POP™
PowerTrench®
QFET™
QS™
Quiet Series™
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TinyLogic™
UHC™
VCX™
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
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This datasheet contains final specifications. Fairchild
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The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. A, January 2000