Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT163500 18-Bit Registered Transceiver SCCS066 - June 1997 - Revised March 2000 Features Functional Description • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permits live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 4.6 ns • Latch-up performance exceeds JEDEC standard no. 17 • ESD > 2000V per MIL-STD-883D, Method 3015 • Typical output skew < 250ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D • VCC = 2.7V to 3.6V The CY74FCT163500 is an 18-bit universal bus transceiver that can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. The CY74FCT163500 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce.The inputs and outputs are capable of being driven by 5.0V busses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power off disable feature enabling them to be used in applications requiring live insertion. Logic Block Diagram Pin Configuration SSOP/TSSOP Top View OEAB LEAB 1 56 2 55 GND CLKAB A1 3 54 B1 GND 4 53 GND A2 5 52 B2 A3 6 51 B3 VCC 7 50 VCC A4 49 B4 OEBA 8 A5 9 48 B5 CLKAB A6 10 47 B6 GND 11 46 GND A7 12 13 45 B7 44 B8 A9 A 10 14 43 B9 15 42 B10 A 11 16 41 B11 A 12 17 40 B12 GND 18 39 38 GND B13 OEAB CLKBA LEBA LEAB A8 C C B1 A1 D D C C A 13 19 D D A 14 20 37 B14 A 15 21 36 B15 VCC 22 35 VCC A 16 A 17 23 34 B16 24 25 33 B17 32 GND 26 31 B18 27 30 CLKBA 28 29 GND TO 17 OTHER CHANNELS GND A 18 OEBA LEBA Copyright © 2000, Texas Instruments Incorporated CY74FCT163500 Maximum Ratings[5, 6] Pin Summary Name Description (Above which the useful life may be impaired. For user guidelines, not tested.) OEAB A-to-B Output Enable Input OEBA B-to-A Output Enable Input (Active LOW) Storage Temperature ................................ −55°C to +125°C LEAB A-to-B Latch Enable Input Ambient Temperature with Power Applied ................................................. −55°C to +125°C LEBA B-to-A Latch Enable Input Supply Voltage Range ..................................... 0.5V to +4.6V CLKAB A-to-B Clock Input (Active LOW) DC Input Voltage .................................................−0.5V to +7.0V CLKBA B-to-A Clock Input (Active LOW) DC Output Voltage ..............................................−0.5V to +7.0V A A-to-B Data Inputs or B-to-A Three-State Outputs B B-to-A Data Inputs or A-to-B Three-State Outputs DC Output Current (Maximum Sink Current/Pin) ...........................−60 to +120 mA Power Dissipation .......................................................... 1.0W Function Table[1, 2] Inputs Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Outputs OEAB LEAB CLKAB A B L X X X Z H H X L L H H X H H H L L L H L H H H L H X B[3] H L L X B[4] Operating Range Range Industrial Ambient Temperature VCC −40°C to +85°C 2.7V to 3.6V Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LOW Transition. 2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 5. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range. 6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 2 CY74FCT163500 Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions All Inputs Min. Typ.[7] 2.0 [8] VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA IIH Input HIGH Current IIL Input LOW Current IOZH Max. Unit 5.5 V 0.8 V 100 −1.2 V VCC=Max., VI=5.5V ±1 µA VCC=Max., VI=GND. ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IODL Output LOW Current[9] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 45 180 mA IODH Output HIGH Current[9] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V –45 –180 mA VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VOL Output LOW Voltage −0.7 mV VCC–0.2 VCC=3.0V, IOH= –8 mA 2.4 3.0 VCC=3.0V, IOH= –24 mA 2.0 3.0 VCC=Min., IOL= 0.1mA IOS Short Circuit IOFF Power-Off Disable VCC=Max., VOUT=GND V V 0.2 VCC=Min., IOL= 24 mA Current[9] V –60 V 0.3 0.5 –135 –240 mA ±100 µA Typ.[7] Max. Unit VCC=0V, VOUT≤4.5V Capacitance[8] (TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Notes: 7. Typical values are at VCC=3.3V, TA = +25˚C ambient. 8. This parameter is specified but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY74FCT163500 Power Supply Characteristics Parameter Description Test Conditions Typ.[7] Max. Unit ICC Quiescent Power Supply Current VCC=Max. VIN≤0.2V, VIN≥VCC−0.2V 0.1 10 µA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max. VIN=VCC–0.6V[10] 2.0 30 µA ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, VIN=VCC or 50%DutyCycle,OutputsOpen, VIN=GND OEAB=OEBA=VCC or GND 50 75 µA/MHz IC Total Power Supply Current[12] VCC=Max., f0=10 MHz (CLKAB), f1=5 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling, OEAB=OEBA=VCC LEAB=GND VIN=VCC or VIN=GND 0.5 0.8 mA VIN=VCC–0.6V or VIN=GND 0.5 0.8 mA VIN=VCC or VIN=GND 2.5 3.8[13] mA VIN=VCC–0.6V or VIN=GND 2.6 4.1[13] mA VCC=Max., f0=10 MHz, f1=2.5 MHz, 50% Duty Cycle, Outputs Open, Eighteen Bits Toggling, OEAB=OEBA=VCC LEAB=GND Notes: 10. Per TTL driven input; all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Number of clock inputs changing at f1 NC f1 = Input signal frequency = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY74FCT163500 Switching Characteristics Over the Operating Range VCC = 3.0V to 3.6V[,14, 15] CY74FCT163500A Parameter Description Min. Max. CY74FCT163500C Min. 150 Max. Unit 150 MHz Fig. No.[16] fMAX CLKAB or CLKBA frequency tPLH tPHL Propagation Delay A to B or B to A 1.5 5.1 1.5 4.6 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 1.5 5.6 1.5 5.3 ns 1, 5 tPLH tPHL Propagation Delay CLKBA to A, CLKAB to B 1.5 5.6 1.5 5.3 ns 1, 5 tPZH tPZL Output Enable Time OEBA to A, OEAB to B 1.5 6.0 1.5 5.4 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA to A, OEAB to B 1.5 5.6 1.5 5.2 ns 1, 7, 8 tSU Set-Up Time, HIGH or LOW A to CLKAB, B to CLKBA 3.0 3.0 ns 9 tH Hold Time, HIGH or LOW A to CLKAB, B to CLKBA 0 0 ns 9 tSU Set-Up Time, HIGH or LOW A to LEAB, B to LEBA Clock HIGH 3.0 3.0 ns 4 Clock LOW 1.5 1.5 ns 4 tH Hold Time, HIGH or LOW A to LEAB, B to LEBA 1.5 1.5 ns 4 tW LEAB or LEBA Pulse Width HIGH 3.0 2.5 ns 5 tW CLKAB or CLKBA Pulse Width HIGH or LOW 3.0 3.0 ns 5 tSK(O) Output Skew[17] 0.5 0.5 ns Ordering Information CY74FCT163500 Speed (ns) 4.6 5.1 Ordering Code Package Name Package Type CY74FCT163500CPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT163500CPVC/PVCT O56 56-Lead (300-Mil) SSOP CY74FCT163500APVC/PVCT O56 56-Lead (300-Mil) SSOP Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 16. See “Parameter Measurement Information” in the General Information section. 17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. 5 Operating Range Industrial Industrial CY74FCT163500 Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 6 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CY74FCT163500APVC OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT163500APVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT163500CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163500CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163500CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT163500CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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