CPC5622 LITELINK® III Phone Line Interface IC (DAA) INTEGRATED CIRCUITS DIVISION Features Description • Superior voice solution with low noise and excellent part-to-part gain accuracy • 3 kVRMS line isolation • Simultaneous ringing detection and CID monitoring for worldwide applications • Provides both full-wave ringing detect and half-wave ringing detect for maximum versatility • Transmit power of up to +10 dBm into 600 • Data access arrangement (DAA) solution for modem speeds up to V.92 • 3.3V or 5 V power supply operation • Easy interface with modem ICs and voice CODECs • Worldwide dial-up telephone network compatibility • CPC5622 can be used in circuits that comply with the requirements of TIA/EIA/IS-968 (FCC part 68), UL60950 (UL1950), EN/IEC 60950-1 Supplementary Isolation Compliant, IEC60950, EN55022B, CISPR22B, EN55024, and TBR-21 • Line-side circuit powered from telephone line • Compared to other silicon DAA solutions, LITELINK: - Uses fewer passive components - Takes up less printed-circuit board space - Uses less telephone line power - Is a single-IC solution LITELINK III is a single-package silicon phone line interface (PLI) DAA used in voice and data communication applications to make connections between low-voltage equipment and high-voltage telephone networks. Applications Ordering Information • • • • • • • LITELINK uses on-chip optical components and a few inexpensive external components to form the required high voltage isolation barrier. LITELINK eliminates the need for large isolation transformers or capacitors used in other phone line interface configurations. LITELINK also provides AC and DC phone line terminations, switchhook, 2-wire to 4-wire hybrid, ringing detection, and full time receive on-hook transmission capability. The CPC5622 is a member of, and builds upon, IXYS Integrated Circuits Division’s third generation of LITELINK products with improved insertion loss performance and lower minimum current draw from the phone line. The CPC5622 version of LITELINK III provides concurrent ringing detection and CID monitoring for world wide applications. Both half-wave and full-wave ringing detection are provided for maximum versatility. Computer telephony and gateways, such as VoIP PBXs Satellite and cable set-top boxes V.92 (and other standard) modems Fax machines Voicemail systems Embedded modems for POS terminals, automated banking, remote metering, vending machines, security, and surveillance Part Number CPC5622A CPC5622ATR 32-Pin SOIC Phone Line Interface, 50/tube 32-Pin SOIC Phone Line Interface, tape and reel, 1000/reel CPC5622 Block Diagram Isolation Barrier Tx+ Transmit Diff. Amplifier Tx- TIP Transmit Isolation Amplifier MODE 3kVrms Description Tx. Gain Trim OH Isolation Rx. Gain Trim Transconductance Stage 2-4 Wire Hybrid AC/DC Termination Hook Switch Receive Isolation Amplifier RING Rx+ Receive Diff. Amplifier Rx- Pb DS-CPC5622-R03 e3 Ringing Detect Outputs RING RING2 Rx Amp & Ringing Det. CSNOOP Half Wave Full Wave www.ixysic.com Snoop Amplifier CSNOOP RSNOOP RSNOOP 1 INTEGRATED CIRCUITS DIVISION CPC5622 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 5 2. Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Resistive Termination Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Resistive Termination Application Circuit Part List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Reactive Termination Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Reactive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 9 3. Using LITELINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch Hook Control (On-hook and Off-hook States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 On-hook Operation: OH=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Ringing Signal Reception via the Snoop Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Off-Hook Operation: OH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Receive Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Transmit Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Initialization Requirement Following Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Setting a Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Mode Pin Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 12 12 12 13 13 13 13 13 13 13 4. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. LITELINK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 1. Electrical Specifications 1.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit VDD -0.3 6 V Logic Inputs -0.3 VDD + 0.3 V Continuous Tip to Ring Current (RZDC = 5.2) - 150 mA Total Package Power Dissipation - 1 W Isolation Voltage - 3000 Vrms Operating temperature -40 +85 °C Storage temperature -40 +125 °C Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. Unless otherwise specified all specifications are at 25C and VDD=5.0V. R03 www.ixysic.com 3 INTEGRATED CIRCUITS DIVISION CPC5622 1.2 Performance Parameter DC Characteristics Operating Voltage VDD Operating Current IDD Operating Voltage VDDL Operating Current IDDL On-hook Characteristics Metallic DC Resistance Longitudinal DC Resistance Ringing Signal Detect Level Ringing Signal Detect Level Snoop Circuit Frequency Response Snoop Circuit CMRR1 Ringer Equivalence 1 Longitudinal Balance Off-Hook Characteristics AC Impedance Longitudinal Balance1 Return Loss Transmit and Receive Characteristics Frequency Response Transhybrid Loss Transmit and Receive Insertion Loss Average In-band Noise Harmonic Distortion Transmit Level Receive Level RX+/RX- Output Drive Current TX+/TX- Input Impedance Isolation Characteristics Isolation Voltage Surge Rise Time MODE and OH Control Logic Inputs Input Low Voltage Input High Voltage High Level Input Current Low Level Input Current RING and RING2 Output Logic Levels Output High Voltage Output Low Voltage Minimum Typical Maximum Unit Conditions 3.0 2.8 - 9 7 5.5 13 3.2 8 V mA V mA Low-voltage side Low-voltage side Line side, derived from tip and ring Line side, drawn from tip and ring while off-hook 10 10 5 28 - - M M Vrms Vrms 166 - >4000 Hz - 40 - dB Tip to ring, 100 Vdc applied 150 Vdc applied from tip and ring to Earth ground 68 Hz ringing signal applied across tip and ring 15 Hz ringing signal applied across tip and ring -3 dB corner frequency @ 166 Hz, in IXYS Integrated Circuits Division application circuit 120 VRMS 60 Hz common-mode signal across tip and ring 60 0.01B - - REN dB 60 - 600 26 - dB dB Tip to ring, using resistive termination application circuit Per FCC part 68 Into 600 at 1800 Hz 30 - 4000 Hz - 36 - dB -0.4 0 0.4 dB - -126 -80 - 60 90 2.2 2.2 0.5 120 dBm/Hz dB VP-P VP-P mA k -3 dB corner frequency 30 Hz Into 600 at 1800 Hz, with C18 in the resistive termination application circuit 30 Hz to 4 kHz, Resistive termination application circuit with MODE de-asserted. Reactive termination application circuit with MODE asserted. 4 kHz flat bandwidth 3000 2000 - - Vrms V/S 2.0 - - 0.8 -120 -120 VIL VIH A A VIN VDD VIN = GND VDD -0.4 - 0.4 V V IOUT = -400 A IOUT = 1 mA - Per FCC part 68 -3 dBm, 600 Hz, 2nd harmonic Single-tone sine wave. Or 0 dBm into 600 . Single-tone sine wave. Or 0 dBm into 600 Sink and source Line side to Low-voltage side, one minute duration No damage via tip and ring Specifications subject to change without notice. All performance characteristics based on the use of IXYS Integrated Circuits Division application circuits. Functional operation of the device at conditions beyond those specified here is not implied. NOTES: 1) This parameter is layout and component tolerance dependent. 4 www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 1.3 Pin Description Pin Name Figure 1. Pinout Function 1 VDD Low-voltage (CPE) side power supply 2 TXSM Transmit summing junction 3 TX- Negative differential transmit signal to DAA from low-voltage side 4 TX+ Positive differential transmit signal to DAA from low-voltage side 5 TX Transmit differential amplifier output 6 MODE When asserted low, changes gain of TX path (-7 dB) and RX path (+7 dB) to accommodate reactive termination networks 7 GND Low-voltage (CPE) side analog ground 8 OH Assert logic low for off-hook operation 9 RING Half wave ringing detect output signal 10 RING2 Full wave ringing detect output signal 11 RX- Negative differential analog signal received from the telephone line. Must be AC coupled with 0.1 F. 12 RX+ Positive differential analog signal received from the telephone line. Must be AC coupled with 0.1 F. 13 SNP+ Positive differential snoop input 14 SNP- Negative differential snoop input 15 RXF Receive photodiode amplifier output 16 RX Receive photodiode summing junction 17 VDDL Power supply for line side, regulated from tip and ring. 18 RXS Receive isolation amp summing junction 19 RPB Receive LED pre-bias current set 20 BR- Bridge rectifier return 21 ZDC Electronic inductor DCR/current limit 22 DCS2 DC feedback output 23 DCS1 V to I slope control 24 NTF Network amplifier feedback 25 GAT External MOSFET gate control 26 NTS Receive signal input 27 BR- Bridge rectifier return 28 TXSL Transmit photodiode summing junction 29 ZNT Receiver impedance set 30 ZTX Transmit transconductance gain set 31 TXF Transmit photodiode amplifier output 32 REFL 1.25 VDC reference R03 www.ixysic.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD TXSM TXTX+ TX MODE GND OH RING RING2 RXRX+ SNP+ SNPRXF RX REFL TXF ZTX ZNT TXSL BRNTS GAT NTF DCS1 DCS2 ZDC BRRPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 INTEGRATED CIRCUITS DIVISION CPC5622 2. Application Circuits LITELINK can be used with telephone networks worldwide. Some public telephone networks, notably in North America and Japan require a resistive line termination. Other telephone networks, such as in Europe, China and elsewhere, require a reactive line termination. The application circuits that follow address both types of line termination models. A reactive termination application circuit that describes the TBR-21 implementation is shown in Figure 3 on page 8. This circuit can be easily adapted for other reactive termination needs. 2.1 Resistive Termination Application Circuit Figure 2. Resistive Termination Application Circuit Schematic 3.3 or 5V R23 2 10 C1 1μ FB1 600 Ω 200 mA C16 10μ A U1 A R1 (RTX) 80.6K TXTX+ 1 VDD 2 TXSM C13 0.1μ 3 TX- C2 0.1μ 4 TX+ TXF OH 29 28 6 MODE BR- 27 7 GND NTS 26 8 OH GAT 25 RING2 10 RING2 RX+ NTF BR- 30 ZNT 9 RING C9 0.1μ 31 TXSL RING RX- ZTX CPC5622 5 TX A REFL 32 LITELINK R5 (RTXF) 60.4K R75 (RNTX) 261K BR- R12 (RNTF) 24 499K C14 C4 0.1μ 11 RX- DCS1 23 DCS2 C12 (CDCS) 0.027μ BR- ZDC 21 BR- 20 14 SNP- RPB 19 15 RXF RXS BR- R3 (RSNPD) 1.5M C8 (CSNP+) 4 220pF 47 5% C15 0.01μ 500V R20 (RVDDL) 2 5% BR- + DB1 TIP R18 (RZTX) 3.32K C18 15p 3 R10 (RZNT) 301 R4 (RPB) 68.1 C7 (CSNP-) 4 220pF Q1 CPC5602C BRR76 (RHTF) 200K R8 221K (RHTX) VDDL 17 R2 (RRXF) 130K R14 (RGAT) R16 (R 3 ZDC) 8.2 18 BR- SP1 1 BR- RING BR- R6 (RSNP-2) R44 (RSNP-1) 1.8M 1.8M R7 (RSNP+2) 1.8M R45 (RSNP+1) 1.8M NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this Sidactor. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 H inductor, Toko 380HB-2215 or similar. See the Power Quality section of IXYS Integrated Circuits Division application note AN-146, Guidelines for Effective LITELINK Designs for more information. 6 R21 (RDCS1B) 6.49M R15 (RDCS2) 22 13 SNP+ R22 (RDCS1A) 6.49 M C21 100p BR- (CGAT) 1.69M 0.1μ 12 RX+ 16 RX C10 0.01μ 500V R13 (RNTS) 1M ³Optional for enhanced transhybrid loss. 4 Use voltage ratings based on the isolation requirements of your application. www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 2.1.1 Resistive Termination Application Circuit Part List Quantity Reference Designator Description 1 5 C1 C2, C4, C9, C13, C14 1 F, 16 V, ±10% 0.1 F, 16 V, ±10% 2 C7, C8 1 C10, C15 C12 C16 C18 (optional) C21 R1 R2 R3 R4 R5 0.01 F, 500 V, ±10% 0.027 F, 16 V, ±10% 10 F, 16 V, ±10% 15 pF, 16 V, ±10% 100 pF, 16 V, 10% 80.6 k, 1/16 W, ±1% 130 k, 1/16 W, ±1% 1.5 M, 1/16 W, ±1% 68.1 , 1/16 W, ±1% 60.4 k, 1/16 W, ±1% 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R6, R7, R44, R45 2 R8 R10 R12 R13 R14 R15 R16 R18 R20 R21, R22 R23 R75 R76 FB1 DB1 1 SP1 1 1 Q1 U1 4 Supplier(s) 220 pF, ±5% AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1.8 M, 1/10 W, ±1% 221 k, 1/16 W, ±1% 301 , 1/16 W, ±1% 499 k, 1/16 W, ±1% Panasonic, Electro Films, FMI, Vishay, 1 M, 1/16 W, ±1% etc. 47 , 1/16 W, ±5% 1.69 M, 1/16 W, ±1% 8.2 , 1/8 W, ±1% 3.32 k 1/16 W, ±1% 2 , 1/16 W, ±5% 6.49 M, 1/16 W, ±1% 10 1/16 W, ±5%, or 220 H inductor 261 k, 1/16 W, ±1% 200 k, 1/16 W, ±1% 600 , 200 mA ferrite bead Murata BLM11A601S or similar S1ZB60 bridge rectifier Shindengen, Diodes, Inc. Bourns (TISP4350H3) or 350 V Teccor (P3100SC) CPC5602 FET IXYS Integrated Circuits Division CPC5622 LITELINK 1 Use voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. 2 Use components that allow enough space to account for the possibility of high-voltage arcing. R03 www.ixysic.com 7 INTEGRATED CIRCUITS DIVISION CPC5622 2.2 Reactive Termination Application Circuit Figure 3. Reactive Termination Application Circuit Schematic 3.3 or 5V R23 2 10 C1 1μ FB1 600 Ω 200 mA C16 10μ A U1 A R1 (RTX) 80.6K TXTX+ 1 VDD 2 TXSM TXF 3 TX- ZTX C2 0.1μ 4 TX+ ZNT 29 TXSL 28 6 MODE BR- 27 7 GND NTS 26 8 OH GAT 25 OH RING 9 RING RING2 10 RING2 RX+ NTF BR- 30 0.1μ A C9 0.1μ 31 C13 5 TX RX- LITELINK REFL 32 R5 (RTXF) 60.4K R75 (RNTX) 110K BR- R12 (RNTF) 24 C14 C4 0.1μ 11 RX- DCS2 C12 (CDCS) 0.027μ R15 (RDCS2) 22 BR- ZDC 21 13 SNP+ BR- 20 14 SNP- 19 RPB Q1 CPC5602C 47 5% RXS BR- BR- + DB1 TIP - 200K R4 (RPB) 68.1 C15 0.01μ 500V R20 (RVDDL) 2 5% BRR76 (RHTF) 200K R8 (RHTX) VDDL 17 R2 (RRXF) 130K R14 (RGAT) R16 (R 3 ZDC) 8.2 18 15 RXF 16 RX R21 (RDCS1B) 6.49M 1.69M 0.1μ 12 RX+ R22 (RDCS1A) 6.49M C21 100p BR- (CGAT) 221K DCS1 23 C10 0.01μ 500V R13 (RNTS) 1M R18 (RZTX) 10K R10 59 (RZNT1) BR- SP1 1 BR- RING C20 (CZNT) 0.68μ R11 169 (RZNT2) BR- C7 (CSNP-) 4 220p R3 (RSNPD) 1.5M C8 (CSNP+) 4 220p R6 (RSNP-2) R44 (RSNP-1) 1.8M 1.8M R7 (RSNP+2) 1.8M 1.8M NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this Sidactor. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 H inductor, Toko 380HB-2215 or similar. See the Power Quality section of IXYS Integrated Circuits Division application note AN-146, Guidelines for Effective LITELINK Designs for more information. 8 R45 (RSNP+1) 3 RZDC sets the loop-current limit, see “Setting a Current Limit” on page 13. Also see IXYS Integrated Circuits Division application note AN-146 for heat sinking recommendations for the CPC5602C FET. 4 Use voltage ratings based on the isolation requirements of your application. www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 2.2.1 Reactive Termination Application Circuit Part List Quantity Reference Designator Description 1 5 C1 C2, C4, C9, C13, C14 1 F, 16 V, ±10% 0.1 F, 16 V, ±10% 2 C7, C8 1 C10, C15 C12 C16 C20 C21 R1 R2 R3 R4 R5 0.01 F, 500 V, ±10% 0.027 F, 16 V, ±10% 10 F, 16 V, ±10% 0.68 F, 16 V, ±10% 100 pF, 16 V, 10% 80.6 k, 1/16 W, ±1% 130 k, 1/16 W, ±1% 1.5 M, 1/16 W, ±1% 68.1 , 1/16 W, ±1% 60.4 k 1/16 W, ±1% 2 1 1 1 1 1 1 1 1 1 220 pF, ±5% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R6, R7, R44, R45 2 R8 R10 R11 R12 R13 R14 R15 R16 R18 R20 R21, R22 R23 R75 R76 FB1 DB1 200 k, 1/16 W, ±1% 59 , 1/16 W, ±1% 169 , 1/16 W, ±1% 221 k, 1/16 W, ±1% 1 M, 1/16 W, ±1% 47 , 1/16 W, ±5% 1.69 M, 1/16 W, ±1% 8.2 , 1/8 W, ±1% 10 k, 1/16 W, ±1% 2 , 1/16 W, ±5% 6.49 M, 1/16 W, ±1% 10 , 1/16 W, ±5%, or 220 H inductor 110 k, 1/16 W, ±1% 200 k, 1/16 W, ±1% 600 200 mA ferrite bead S1ZB60 bridge rectifier 1 SP1 350 V 1 1 Q1 U1 CPC5602 FET CPC5622 LITELINK 4 1 Supplier AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1.8 M, 1/10 W, ±1% Panasonic, Electro Films, FMI, Vishay, etc. Murata BLM11A601S or similar Shindengen, Diodes, Inc. Bourns (TISP4350H3) or Teccor (P3100SC) IXYS Integrated Circuits Division Use voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. 2Use R03 components that allow enough space to account for the possibility of high-voltage arcing. www.ixysic.com 9 INTEGRATED CIRCUITS DIVISION CPC5622 3. Using LITELINK As a full-featured telephone line interface, LITELINK performs the following functions: LITELINK’s ringing detector and CID amplifiers are both active. • • • • • • • Asserting OH low causes LITELINK to answer or originate a call by entering the off-hook state. In the off-hook state, loop current flows through LITELINK. DC termination and V/I slope control AC impedance control 2-wire to 4-wire conversion (hybrid) Current limiting Ringing detect signalling reception Caller ID signalling reception Switch hook 3.2 On-hook Operation: OH=1 LITELINK can accommodate specific application features without sacrificing basic functionality or performance. Application features include, but are not limited to: • • • • • • • • High transmit power operation Pulse dialing Ground start Loop start Parallel telephone off-hook detection (line intrusion) Battery reversal detection Line presence detection World-wide programmable operation This section of the data sheet describes LITELINK operation in standard configuration for usual operation. IXYS Integrated Circuits Division offers additional application information on-line (see Section 5 on page 14) for the following topics: • • • • • • Circuit isolation considerations Optimizing LITELINK performance Data Access Arrangement architecture LITELINK circuit descriptions Surge protection EMI considerations Other specific application materials are also referenced in this section as appropriate. 3.1 Switch Hook Control (On-hook and Off-hook States) LITELINK operates in one of two conditions, on-hook and off-hook. In the on-hook condition the telephone line is available for calls. In the off-hook condition the telephone line is engaged. The OH control input is used to place LITELINK in one of these two states. With OH high, LITELINK is on-hook and ready to make or receive a call. Also while on-hook, 10 The LITELINK application circuit leakage current is less than 10 A with 100 V across ring and tip, equivalent to greater than 10 M on-hook resistance. 3.2.1 Ringing Signal Reception via the Snoop Circuit In the on-hook state (OH not asserted), an internal multiplexer engages the snoop circuitry. This circuit simultaneously monitors the telephone line for two conditions; incoming ringing signal and caller ID data bursts. Refer to the application schematic diagram (see Figure 2 on page 6). C7 (CSNP-) and C8 (CSNP+) provide a high-voltage isolation barrier between the telephone line and SNP- and SNP+ input pins of the LITELINK while coupling AC signals to the snoop amplifier. The snoop circuit “snoops” the telephone line continuously while drawing no dc current. In the LITELINK, the incoming ringing signals are compared to a reference level. When the ringing signal exceeds the preset threshold, the internal comparators generate the RING and RING2 signals which are output from LITELINK at pins 9 and 10, respectively. Selection of which output to use is dependent upon the support logic responsible for monitoring and filtering the ringing detect signals. To reduce or eliminate false ringing detects this signal should be digitally filtered and qualified by the system as a valid ringing signal. A logic low output on RING or RING2 indicates that the LITELINK ringing signal detect threshold has been exceeded. In the absence of any incoming ac signal the RING and RING2 outputs are held high. The CPC5622 RING output signal is generated by a half-wave ringing detector while the RING2 output is generated by a full-wave ringing detector. A half-wave ringing detector’s output frequency follows the frequency of the incoming ringing signal from the Central Office (CO) while a full-wave ringing detector’s output frequency is twice that of the incoming signal. Because RING is the output of a half-wave detector, it www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 will output one logic low pulse per cycle of the ringing frequency. Also, because the RING2 is the output of a full-wave detector it will output two logic low pulses per cycle of the ringing frequency. Hence, the nomenclature RING2 for twice the output pulses. The set-up of the ringing detector comparator causes the RING output pulses to remain low for most of one half-cycle of the ringing signal and remains high for the entire second half-cycle of the ringing signal. For the RING2 output, the pulses remain low during most of both halves of the ringing cycle and returns high for only a short period near the zero-crossing of the ringing signal. Both of the ringing outputs remain high during the silent interval between ringing bursts. Hysteresis is employed in the LITELINK ringing detector circuit to improve noise immunity. The ringing detection threshold depends on the values of R3 (RSNPD), R6 & R44 (RSNP-), R7 & R45 (RSNP+), C7 (CSNP-), and C8 (CSNP+). The value of these components shown in the application circuits are recommended for typical operation. The ringing detection threshold can be changed according to the following formula: 750mV V RINGPK = ----------------- R SNPD R SNP TOTAL 2 1 + R SNPD + -------------------------------------2 f RING C SNP Where: • RSNPD = R3 in the application circuits shown in this data sheet. • RSNPTOTAL = the total of R6, R7, R44, and R45 in the application circuits shown in this data sheet. • CSNP = C7 = C8 in the application circuits shown in this data sheet. • And ƒRING is the frequency of the ringing signal. IXYS Integrated Circuits Division Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the ringing detection threshold will also change the caller ID gain and the timing of the polarity reversal detection pulse, if used. R03 3.2.2 Polarity Reversal Detection in On-hook State The full-wave ringing detector in the CPC5622 makes it possible to detect an on-hook tip and ring battery polarity reversal using the RING2 output. When the polarity of the battery voltage applied to tip and ring reverses, a pulse on RING2 indicates the event. The system logic must be able to discriminate a single pulse of approximately 1 msec when using the recommended external snoop circuit components from a valid ringing signal. 3.2.3 On-hook Caller ID Signal Reception On-hook Caller IDentity (CID) data burst signals are coupled through the snoop components, buffered through LITELINK and output at the RX+ and RXpins. In North America, CID data signals are typically sent between the first and second ringing signal while in other countries the CID information may arrive prior to any other signalling state. In applications that transmit CID after the first ringing burst such as in North American, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: 1. Detect the first full ringing signal burst on RING or RING2. 2. Monitor and process the CID data from the RX outputs. For applications as in China and Brazil where CID may arrive prior to ringing, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: 1. Simultaneously monitor for CID data from the RX outputs and for ringing on RING or RING2. 2. Process the appropriate signalling data. Note: Taking LITELINK off-hook (via the OH pin) disconnects the snoop path from the receive outputs and disables the ringing detector outputs RING and RING2. CID gain from tip and ring to RX+ and RX- is determined by: www.ixysic.com 11 INTEGRATED CIRCUITS DIVISION CPC5622 6R SNPD GAIN CID dB = 20 log ------------------------------------------------------------------------------------------------2 1 R SNP + R SNPD + -------------------------2TOTAL fC SNP Where: • RSNPD = R3 in the application circuits in this data sheet. • RSNPTOTAL = the total of R6, R7, R44, and R45 in the application circuits in this data sheet. • CSNP = C7 = C8 in the application circuits in this data sheet. • and ƒ is the frequency of the CID signal To accommodate single-supply operation, LITELINK includes a small DC bias on the RX+ and RX- outputs of 1.0 Vdc. Most applications should AC couple the receive outputs as shown in Figure 4. LITELINK may be used for differential or single-ended output as shown in Figure 4. Single-ended use will produce 6 dB less signal output amplitude. Do not exceed 0 dBm referenced to 600 (2.2 VP-P) signal output level with the standard application circuits. See application note AN-157, Increased LITELINK III Transmit Power for more information. Figure 4. Differential and Single-ended Receive Path Connections to LITELINK Low-Voltage Side CODEC or Voice Circuit The recommended components in the application circuits yield a gain 0.26 dB at 2000 Hz. IXYS Integrated Circuits Division Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the CID gain will also change the ringing detection threshold and the timing of the polarity reversal detection pulse, if used. For single-ended receive applications where only one RX output is used, the snoop circuit gain can be adjusted back to 0 dB by changing the value of the snoop series resistors R6, R7, R44 and R45 from 1.8M to 715k This change results in negligible modification to the ringing detect threshold. 3.3 Off-Hook Operation: OH=0 3.3.1 Receive Signal Path Signals to and from the telephone network appear on the tip and ring connections of the application circuit. Receive signals are extracted from transmit signals by the LITELINK two-wire to four-wire hybrid then converted to infrared light by the receive path LED. The intensity of the light is modulated by the receive signal and coupled across the electrical isolation barrier by a reflective dome. On the low voltage side of the barrier, the receive signal is converted by a photodiode into photocurrent. The photocurrent, a linear representation of the receive signal, is amplified and converted to a differential voltage output on RX+ and RX-. Variations in gain are controlled to within ±0.4 dB by factory gain trim, which sets the output to unity gain. 12 RX+ 0.1μF LITELINK RX+ 0.1μF RX- RX RX- 0.1μF RX+ 3.3.2 Transmit Signal Path Transmit signals from the CODEC to the TX+ and TXpins of LITELINK should be coupled through capacitors as shown in Figure 5 to minimize dc offset errors. Differential transmit signals are converted to single-ended signals within LITELINK then coupled to the optical transmit amplifier in a manner similar to the receive path. The output of the optical amplifier is coupled to a voltage-to-current converter via a transconductance stage where the transmit signal modulates the telephone line loop current. As in the receive path, the transmit gain is calibrated at the factory, limiting insertion loss to 0 ±0.4 dB. Differential and single-ended transmit signals into LITELINK should not exceed a signal level of 0 dBm referenced to 600 (or 2.2 VP-P). For output power levels above 0dBm consult the application note AN-157, Increased LITELINK III Transmit Power for more information. www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 Figure 5. Differential and Single-ended Transmit Path Connections to LITELINK LITELINK Low-Voltage Side CODEC or Transmit Circuit 0.1μf TX- 0.1μf TX+ TXA1 TXA2 Whether using the recommended value above or when setting RZDC higher for a lower loop current limit refer to the guidelines for FET thermal management provided in AN-146, Guidelines for Effective LITELINK Designs. 3.6 AC Characteristics + 3.6.1 Resistive Termination Applications North American and Japanese telephone line AC termination requirements are met with a resistive 600 ac 2-wire termination. For these applications LITELINK’s 2-wire network termination impedance is set by the resistor RZNT (R10) located at the ZNT pin, pin 29, with a value of 301. LITELINK Low-Voltage Side CODEC or Transmit Circuit 0.1μf TXA1 N/C TXTX+ + 3.6.2 Reactive Termination Applications Many countries use a single-pole complex impedance to model the telephone network transmission line characteristic impedance as shown in the table below. 3.4 Initialization Requirement Following Power-up Line Impedance Model OH must be de-asserted (set logic high) once after power-up for at least 50ms to transfer internal gain trim values within LITELINK. This would be normal operation in most applications. Failure to comply with this requirement will result in transmission gain errors and possibly distortion. 3.5 DC Characteristics The CPC5622 is designed for worldwide applications. Modification of the values of the components at the ZDC, DCS1, and DCS2 pins allow for control of the VI slope characteristics of LITELINK. Selecting appropriate resistor values for RZDC (R16) and RDCS2 (R15) in the provided application circuits enable compliance with various DC requirements. 3.5.1 Setting a Current Limit LITELINK includes a telephone line current limit feature that is selectable by choosing the desired value for RZDC (R16) using the following formula: 1V I CL Amps = ------------- + 0.008A R ZDC IXYS Integrated Circuits Division recommends using 8.2 for RZDC for most applications, limiting telephone line current to 130 mA. R03 RS RP Australia China TBR 21 RS 220 200 270 RP 820 680 750 CP 120 nF 100 nF 150 nF CP Proper gain and termination impedance circuits for a complex impedance requires the use of complex network on ZNT as shown in the “Reactive Termination Application Circuit” on page 8. 3.6.3 Mode Pin Usage Asserting the MODE pin low (MODE = 0) introduces a 7 dB pad into the transmit path and adds 7 dB of gain to the receive path. These changes compensate for the gain changes made to the transmit and receive paths necessary for reactive termination implementations. Overall insertion loss with the reactive termination application circuit and MODE asserted is 0 dB. Overall insertion loss with MODE de-asserted (MODE = 1) for the resistive termination application circuit is 0 dB. www.ixysic.com 13 INTEGRATED CIRCUITS DIVISION CPC5622 4. Regulatory Information LITELINK III can be used to build products that comply with the requirements of TIA/EIA/IS-968 (formerly FCC part 68), FCC part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, and many other standards. LITELINK provides supplementary isolation. Metallic surge requirements are met through the inclusion of a crow bar protection device in the application circuit. Longitudinal surge protection is provided by LITELINK’s optical-across-the-barrier technology and the use of high-voltage components in the application circuit as needed. The information provided in this document is intended to inform the equipment designer but it is not sufficient to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to conform to all relevant regulations, designers using LITELINK are advised to carefully verify that their end-product design complies with all applicable safety, EMC, and other relevant standards and regulations. Semiconductor components are not rated to withstand electrical overstress or electrostatic discharges resulting from inadequate protection measures at the board or system level. 5. LITELINK Design Resources The IXYS Integrated Circuits Division web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. LITELINK data sheets also contains additional application and design information. See the following links: LITELINK datasheets and reference designs Application note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold Application note AN-146, Guidelines for Effective LITELINK Designs Application note AN-155 Understanding LITELINK Display Feature Signal Routing and Applications 14 www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 6. LITELINK Performance The following graphs show LITELINK performance using the North American application circuit shown in this data sheet. Figure 9. Transmit THD on Tip and Ring Figure 6. Receive Frequency Response at RX 2 0 0 -20 -2 -40 -4 -60 Gain -6 dBm THD+N dB -80 -8 -100 -10 -120 -12 -14 0 500 1000 1500 2000 2500 3000 3500 4000 -140 0 500 1000 1500 Frequency 2000 2500 3000 3500 4000 Frequency Figure 10.Transhybrid Loss Figure 7. Transmit Frequency Response at TX 0 2 -5 0 -10 -2 -15 -4 THL -20 dB Gain dBm -6 -25 -8 -30 -10 -35 -12 -40 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 Frequency 2000 2500 3000 3500 4000 Frequency Figure 8. Receive THD on RX Figure 11.Return Loss 60 0 -20 55 -40 50 -60 THD+N dB -80 Return Loss 45 (dB) -100 40 -120 35 -140 0 500 1000 1500 2000 2500 3000 3500 4000 30 0 Frequency 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) R03 www.ixysic.com 15 INTEGRATED CIRCUITS DIVISION CPC5622 Figure 12.Snoop Circuit Frequency Response 5 0 -5 Gain (dBm ) -10 -15 -20 -25 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) Figure 13.Snoop Circuit THD + N +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 500 1k 1.5k 2k Hz 2.5k 3k 3.5k 4k Figure 14.Snoop Circuit Common Mode Rejection +0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 CMRR -30 (dBm) -32.5 -35 -37.5 -40 -42.5 -45 -47.5 -50 -52.5 -55 -57.5 -60 20 50 100 200 500 1K 2K 4K Frequency (Hz) 16 www.ixysic.com R03 INTEGRATED CIRCUITS DIVISION CPC5622 7. Manufacturing Information 7.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC5622A MSL 3 7.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 7.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC5622A 260°C for 30 seconds 7.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake could be necessary if a wash is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used Pb R03 e3 www.ixysic.com 17 INTEGRATED CIRCUITS DIVISION CPC5622 7.5 Mechanical Dimensions Figure 15. CPC5622A Package Dimensions 7.239 ± 0.051 (0.285 ± 0.002) 10.287 ± .254 (0.405 ± 0.010) PCB Land Pattern 0.203 (0.008) 7.493 ± 0.127 (0.295 ± 0.005) 9.30 (0.366) 1.90 (0.0748) 10.363 ± 0.127 (0.408 ± 0.005) Pin 1 0.635 ± 0.076 (0.025 ± 0.003) 0.330 ± 0.051 (0.013 ± 0.002) 0.635 (0.025) 0.635 x 45º 1.016 Typ. (0.025 x 45º) (0.040 Typ.) 0.40 (0.0157) 1.981 ± 0.051 (0.078 ± 0.002) 2.134 Max (0.084 Max) 9.525 ± 0.076 (0.375 ± 0.003) Dimensions mm (inches) MIN 0, MAX 0.102 (MIN 0, MAX 0.004) Figure 16. CPC5622ATR Tape and Reel Dimensions 330.2 DIA. (13.00 DIA.) W=16 (0.630) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) B0=10.70 (0.421) K0=3.20 (0.126) A0=10.90 (0.429) P=12.00 (0.472) K1=2.70 (0.106) Embossed Carrier Embossment NOTES: 1. All dimensions carry tolerances of EIA Standard 481-2 2. The tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2 Dimensions mm (inches) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5622-R03 Copyright © 2012, IXYS Integrated Circuits Division LITELINK® is a registered trademark of IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/22/2012 18 www.ixysic.com R03