PHILIPS HEF40160BF 4-bit synchronous decade counter with asynchronous reset Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40160B
MSI
4-bit synchronous decade counter
with asynchronous reset
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
9 (O0 = O3 = HIGH, O1 = O2 = LOW) and when CET is
HIGH. A LOW on MR sets all outputs (O0 to O3 and TC)
LOW, independent of the state of all other inputs.
Multistage synchronous counting is possible without
additional components by using a carry look-ahead
counting technique; in this case, TC is used to enable
successive cascaded stages. CEP, CET and PE must be
stable only during the set-up time before the LOW to HIGH
transition of CP.
DESCRIPTION
The HEF40160B is a fully synchronous edge-triggered
4-bit decade counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P0 to P3), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O0 to O3) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P0 to P3 regardless of the levels
of CEP and CET inputs.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
HEF40160B
MSI
2
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Philips Semiconductors
3
4-bit synchronous decade counter with
asynchronous reset
January 1995
Product specification
HEF40160B
MSI
Fig.2 Logic diagram.
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
PINNING
PE
parallel enable input
P0 to P3
parallel data inputs
CEP
count enable parallel input
CET
count enable trickle input
CP
clock input (LOW to HIGH, edge-triggered)
MR
master reset input (active LOW)
O0 to O3
parallel outputs
TC
terminal count output
HEF40160BP(N):
Fig.3 Pinning diagram.
16-lead DIL; plastic
(SOT38-1)
HEF40160BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40160BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
SYNCHRONOUS MODE SELECTION
PE
CEP
CET
TERMINAL COUNT GENERATION
MODE
CET
(O0 ⋅ O1 ⋅ O2 ⋅ O3)
TC
L
X
X
preset
L
L
L
H
L
X
no change
L
H
L
H
X
L
no change
H
L
L
H
H
H
count
H
H
H
Notes
Note
1. MR = HIGH
1. TC = CET . O0 . O1 . O2 . O3
2. H = HIGH state (the more positive voltage)
3. L = LOW state (the less positive voltage)
4. X = state is immaterial
Fig.4 State diagram.
January 1995
4
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
Dynamic power
5
TYPICAL FORMULA FOR P (µW)
1 200 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
dissipation per
10
5 600 fi + ∑ (foCL) ×
package (P)
15
16 000 fi + ∑ (foCL) ×
VDD2
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
CP → On
HIGH to LOW
LOW to HIGH
CP → TC
HIGH to LOW
LOW to HIGH
CET → TC
HIGH to LOW
LOW to HIGH
MR → On
HIGH to LOW
MR → TC
HIGH to LOW
5
220
ns
83 ns + (0,55 ns/pF) CL
45
90
ns
34 ns + (0,23 ns/pF) CL
15
30
60
ns
22 ns + (0,16 ns/pF) CL
5
115
230
ns
88 ns + (0,55 ns/pF) CL
10
tPHL
45
95
ns
34 ns + (0,23 ns/pF) CL
15
35
65
ns
27 ns + (0,16 ns/pF) CL
5
130
260
ns
103 ns + (0,55 ns/pF) CL
10
tPLH
55
105
ns
44 ns + (0,23 ns/pF) CL
15
35
75
ns
27 ns + (0,16 ns/pF) CL
5
140
280
ns
113 ns + (0,55 ns/pF) CL
55
115
ns
44 ns + (0,23 ns/pF) CL
10
10
tPHL
tPLH
15
40
80
ns
32 ns + (0,16 ns/pF) CL
5
105
210
ns
78 ns + (0,55 ns/pF) CL
50
100
ns
39 ns + (0,23 ns/pF) CL
10
tPHL
15
35
75
ns
27 ns + (0,16 ns/pF) CL
5
90
185
ns
63 ns +
35
70
ns
24 ns + (0,23 ns/pF) CL
10
tPLH
(0,55 ns/pF) CL
15
25
50
ns
17 ns + (0,16 ns/pF) CL
5
120
245
ns
93 ns + (0,55 ns/pF) CL
50
100
ns
39 ns + (0,23 ns/pF) CL
10
tPHL
15
35
70
ns
27 ns + (0,16 ns/pF) CL
5
145
295
ns
118 ns + (0,55 ns/pF) CL
60
120
ns
49 ns + (0,23 ns/pF) CL
45
85
ns
37 ns + (0,16 ns/pF) CL
10
tPHL
15
January 1995
110
5
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
VDD
V
Output transition times
HIGH to LOW
LOW to HIGH
SYMBOL
HEF40160B
MSI
MIN.
TYP.
5
TYPICAL EXTRAPOLATION
FORMULA
MAX.
60
120
ns
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10
10
tTHL
tTLH
15
10 ns + (1,0 ns/pF) CL
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Minimum clock
pulse width; LOW
Minimum MR
pulse width; LOW
Recovery time
for MR
SYMBOL
5
MIN.
TYP.
MAX.
100
50
ns
40
20
ns
15
30
15
ns
5
100
50
ns
10
tWCPL
40
20
ns
15
30
15
ns
5
25
0
ns
10
15
0
ns
15
10
0
ns
Set-up times
5
110
55
ns
Pn → CP
10
PE → CP
CEP, CET → CP
10
tWMRL
tRMR
40
20
ns
15
30
15
ns
5
120
60
ns
40
20
ns
15
25
10
ns
5
260
130
ns
100
50
ns
10
10
tsu
tsu
tsu
15
70
35
ns
Hold times
5
20
−35
ns
Pn → CP
10
10
−10
ns
15
5
−10
ns
5
15
−45
ns
5
−15
ns
PE → CP
CEP, CET → CP
10
thold
thold
15
5
−10
ns
5
25
−105
ns
15
−35
ns
10
−25
ns
10
thold
15
January 1995
6
see also waveforms
Figs 5, 6, 7 and 8
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
VDD
V
Maximum clock
pulse frequency
SYMBOL
MIN.
5
10
2,5
fmax
15
Conditions
PE = LOW
P0 to P3 = HIGH
Fig.5
Waveforms showing
minimum CP and MR pulse
widths and MR to CP
recovery time.
Conditions: PE = MR = HIGH.
Fig.6
Waveforms
showing
set-up times
and hold times
for CEP and
CET inputs.
January 1995
HEF40160B
MSI
7
TYP.
MAX.
5
MHz
7
14
MHz
9
18
MHz
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
Conditions
PE = LOW
MR = HIGH
Fig.7 Waveforms showing set-up times and hold times for Pn inputs.
Condition
MR = HIGH
Fig.8 Waveforms showing set-up times and hold times for PE inputs.
Note
Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
8
HEF40160B
MSI
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
Fig.9 Timing diagram.
APPLICATION INFORMATION
An example of an application for the HEF40160B is:
• Programmable decade counter.
January 1995
9
HEF40160B
MSI
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
NOTE
On the TC outputs, glitches can occur
during counting. In totally synchronous
mode they will not have any adverse
affect. However the TC output in
asynchronous mode can cause
problems.
Fig.10 Synchronous multi-stage counting scheme.
January 1995
10
HEF40160B
MSI
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