ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8521I-03 is a low skew, 1-to-9 Differential-to-LVHSTL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8521I-03 has two selectable clock inputs. Redundant clock pairs, CLK0, nCLK0 and CLK1, nCLK1 can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 9 LVHSTL outputs Guaranteed output skew and part-to-part skew characteristics make the ICS8521I-03 ideal for today’s most advanced applications, such as IA64 and static RAMs. • Propagation delay: 1.6ns (maximum) ,&6 • Redundant differential CLK0, nCLK0 and CLK1, nCLK1 inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • VOH = 1V (maximum) • 3.3V core, 1.8V output operating supply voltages • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT CLK0 nCLK0 CLK1 nCLK1 CLK_SEL 0 1 VDDO nQ2 Q2 Q LE nQ1 Q1 nQ0 Q0 VDDO D CLK_EN 32 31 30 29 28 27 26 25 Q0 nQ0 VDD CLK0 nCLK0 CLK_SEL CLK1 nCLK1 GND CLK_EN Q1 nQ1 Q2 nQ2 Q3 nQ3 1 2 3 4 5 6 7 8 ICS8521I-03 24 23 22 21 20 19 18 17 VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO 9 1 0 1 1 1 2 1 3 1 4 1 5 16 VDDO Q6 nQ6 Q7 nQ7 Q5 nQ5 Q8 nQ8 VDDO Q4 nQ4 32-Lead LQFP 7mm x 7mm x 1.4mm Package Body Y Package Top View Q6 nQ6 Q7 nQ7 Q8 nQ8 8521AYI-03 www.icst.com/products/hiperclocks.html 1 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Type Description Power Core supply pin. 2 CLK0 Input Pulldown 3 nCLK0 Input Pullup 4 CLK_SEL Input Pulldown 5 CLK1 Input Pulldown Pullup 6 nCLK1 Input 7 GND Power 8 CLK_EN Input Pullup Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0, nCLK0. LVTTL / LVCMOS interface levels. Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS /LVTTL interface levels. 9, 16, 17, 24, 25, 32 10, 11 VDDO Power Output supply pins. nQ8, Q8 Output Differential output pair. LVHSTL interface level. 12, 13 nQ7, Q7 Output Differential output pair. LVHSTL interface level. 14, 15 nQ6, Q6 Output Differential output pair. LVHSTL interface level. 18, 19 nQ5, Q5 Output Differential output pair. LVHSTL interface level. 20, 21 nQ4, Q4 Output Differential output pair. LVHSTL interface level. 22, 23 nQ3, Q3 Output Differential output pair. LVHSTL interface level. 26, 27 nQ2, Q2 Output Differential output pair. LVHSTL interface level. 28, 29 nQ1, Q1 Output Differential output pair. LVHSTL interface level. 30, 31 nQ0, Q0 Output Differential output pair. LVHSTL interface level. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 8521AYI-03 www.icst.com/products/hiperclocks.html 2 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Sourced Q0:Q8 nQ0:nQ8 0 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH 0 1 CLK1, nCLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0, nCLK0 Enabled Enabled 1 1 CLK1, nCLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B. Enabled Disabled nCLK0, CLK1 CLK0, CLK1 CLK_EN nQ0:nQ8 Q0:Q8 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK0 or CLK1 nCLK0 or nCLK1 Q0:Q8 nQ0:nQ8 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels". 8521AYI-03 www.icst.com/products/hiperclocks.html 3 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions VDDO Output Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 2.0 V 95 mA Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current 5 µA IIL Input Low Current CLK_EN VIN = VDD = 3.465V CLK_SEL VIN = VDD = 3.465V CLK_EN VIN = 0V, VDD = 3.465V -150 150 µA µA CLK_SEL VIN = 0V, VDD = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLKx VIN = VDD = 3.465V Test Conditions Minimum Typical 150 µA nCLKx VIN = VDD = 3.465V 5 µA CLKx VIN = 0V, VDD = 3.465V -5 µA nCLKx VIN = 0V, VDD = 3.465V -150 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLKx and nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8521AYI-03 www.icst.com/products/hiperclocks.html 4 1.3 V VDD - 0.85 V REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 0.7 1.0 V VOL Output Low Voltage; NOTE 1 0 0.4 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V Maximum Units 500 MHz NOTE 1: Outputs terminated with 50Ω to ground. TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 1.0 ƒ≤ 266MHz www.icst.com/products/hiperclocks.html 5 ns 50 ps 250 ps 200 700 ps 48 52 % 55 % 266MHz < ƒ ≤ 500MHz 45 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8521AYI-03 1.6 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.8V ± 0.2V 3.3V ± 5% VDD VDD Qx SCOPE nCLK0, nCLK1 VDDO V LVHSTL V Cross Points PP CMR CLK0, CLK1 nQx GND GND = 0V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK0, nCLK1 80% CLK0, CLK1 80% VSW I N G Clock Outputs nQ0:nQ8 20% 20% tR tF Q0:Q8 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0:nQ8 Q0:Q8 Pulse Width t odc = PERIOD t PW t PERIOD odc & tPERIOD 8521AYI-03 www.icst.com/products/hiperclocks.html 6 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8521AYI-03 www.icst.com/products/hiperclocks.html 7 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER SCHEMATIC EXAMPLE This application note provides general design guide using ICS8521I-03 LVHSTL buffer. Figure 3A shows a schematic example of the ICS8521I-03 LVHSTL Clock buffer. In this example, the input is driven by an LVHSTL driver. CLK_EN is set at logic low to select CLK0/nCLK0 input. Zo = 50 + Zo = 50 - VDDO=1.8V VDDO=1.8V C1 0.1u C2 0.1u VDD=3.3V R2 50 R1 50 C6 0.1u 0.1u 32 31 30 29 28 27 26 25 C5 U1 Zo = 50 Ohm Zo = 50 Ohm R12 1K VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO 24 23 22 21 20 19 18 17 R10 50 R11 VDDO=1.8V ICS8521I-03 9 10 11 12 13 14 15 16 R9 50 VDD CLK0 nCLK0 CLK_SEL CL:K1 nCLK1 GND CLK_EN VDDO nQ8 Q8 nQ7 Q7 nQ6 Q6 VDDO LVHSTL Driv er 1 2 3 4 5 6 7 8 VDDO Q0 nQ0 Q1 nQ1 Q2 nQ2 VDDO 1.8V 1K VDD=3.3V VDDO=1.8V C4 0.1u C7 0.1u Zo = 50 + C3 0.1u Zo = 50 - R8 50 R7 50 FIGURE 3A. ICS8521I-03 SCHEMATIC EXAMPLE 8521AYI-03 www.icst.com/products/hiperclocks.html 8 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER, GROUND AND BYPASS CAPACITOR This section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital IC. This layout guide is a general recommendation. The actual board design will depend on the component types being used, the board density and cost constraints. This description assumes that the board has clean power and ground planes. The goal is to minimize the ESR between the clean power/ground plane and the IC power/ground pin. A low ESR bypass capacitor should be used on each power pin. The value of bypass capacitors ranges from 0.01uF to 0.1uF. The bypass capacitors should be located as close to the power pin as possible. It is preferable to locate the bypass capacitor on the same side as the IC. Figure 3B shows suggested capacitor placement. Placing the bypass capacitor on the same side as the IC allows the capacitor to have direct contact with the IC power pin. This can avoid any vias between the bypass capacitor and the IC power pins. The vias should be placed at the Power/Ground pads. There should be a minimum of one via per pin. Increasing the number of vias from the Power/Ground pads to Power/Ground planes can improve the conductivity Zo = 50 + Zo = 50 - VDDO=1.8V VDDO=1.8V C1 0.1u C2 0.1u VDD=3.3V R2 50 R1 50 C6 0.1u 0.1u 32 31 30 29 28 27 26 25 C5 U1 Zo = 50 Ohm Zo = 50 Ohm R12 1K VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO 24 23 22 21 20 19 18 17 R10 50 R11 VDDO=1.8V ICS8521I-03 9 10 11 12 13 14 15 16 R9 50 VDD CLK0 nCLK0 CLK_SEL CL:K1 nCLK1 GND CLK_EN VDDO nQ8 Q8 nQ7 Q7 nQ6 Q6 VDDO LVHSTL Driv er 1 2 3 4 5 6 7 8 VDDO Q0 nQ0 Q1 nQ1 Q2 nQ2 VDDO 1.8V 1K VDD=3.3V VDDO=1.8V C4 0.1u C7 0.1u Zo = 50 + C3 0.1u Zo = 50 - R8 50 FIGURE 3B. RECOMMENDED LAYOUT 8521AYI-03 OF BYPASS CAPACITOR PLACEMENT www.icst.com/products/hiperclocks.html 9 R7 50 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8521AYI-03 BY www.icst.com/products/hiperclocks.html 10 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8521I-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521I-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 32.8mW = 295.2mW Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 295.2mW = 624.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.624W * 42.1°C/W = 111.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE qJA FOR 32-PIN LQFP, FORCED CONVECTION qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8521AYI-03 www.icst.com/products/hiperclocks.html 11 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50Ω FIGURE 5. LVHSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V OL_MAX L /R ) * (V L -V DDO_MAX ) OH_MAX -V DDO_MAX ) OL_MAX Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8521AYI-03 www.icst.com/products/hiperclocks.html 12 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8521I-03 is: 944 8521AYI-03 www.icst.com/products/hiperclocks.html 13 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8521AYI-03 www.icst.com/products/hiperclocks.html 14 REV. A APRIL 29, 2003 ICS8521I-03 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number ICS8521AYI-03 ICS8521AYI-03T Marking ICS8521AYI-03 ICS8521AYI-03 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40°C to 85°C -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8521AYI-03 www.icst.com/products/hiperclocks.html 15 REV. A APRIL 29, 2003