IDT70121S/L IDT70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT Features ◆ ✵ ◆ ◆ High-speed access – Commercial: 25/35/45/55ns (max.) – Industrial: 35ns (max.) Low-power operation – IDT70121/70125S Active: 675mW (typ.) Standby: 5mW (typ.) – IDT70121/70125L Active: 675mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Fully asychronous operation from either port MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip On-chip port arbitration logic (IDT70121 only) BUSY output flag on Master; BUSY input on Slave INT flag for port-to-port communication Battery backup operation—2V data retention TTL-compatible, signal 5V (±10%) power supply Available in 52-pin PLCC Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram OEL OER CEL R/WL CER R/WR I/O0L- I/O8L I/O0R-I/O8R I/O Control I/O Control (1,2) (1,2) BUSYL A10L A0L BUSYR Address Decoder MEMORY ARRAY 11 CEL OEL R/WL Address Decoder A10R A0R 11 ARBITRATION INTERRUPT LOGIC (2) INTL CER OER R/WR INTR (2) 2654 drw 01 NOTES: 1. 70121 (MASTER): BUSY is non-tri-stated push-pull output. 70125 (SLAVE): BUSY is input. 2. INT is non-tri-stated push-pull output. APRIL 2006 1 ©2006 Integrated Device Technology, Inc. DSC 2654/10 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Description feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for Data/Control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 675mW of power. Low-power (L) versions offer battery backup data retention capability with each port typically consuming 200µW from a 2V battery. The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC. The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit DualPort RAM or as a “MASTER” Dual-Port RAM together with the IDT70125 “SLAVE” Dual-Port in 18-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power-down 47 48 50 49 51 52 3 2 46 1 8 9 45 10 44 11 43 IDT70121/125J J52-1(4) 12 13 14 42 41 40 52-Pin PLCC Top View(5) 15 39 32 33 31 30 29 27 34 28 20 26 35 24 36 19 25 37 18 23 17 21 38 22 16 I/O 4L I/O 5L I/O 6L I/O 7L I/O 8L GND I/O 0R I/O 1R I/O 2R I/O 3R I/O 4R I/O 5R I/O 6R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 4 7 INDEX 6 5 05/27/04 A0L OEL A10L INTL BUSYL R/WL CEL VCC CER R/WR BUSYR INTR A10R Pin Configurations(1,2,3) OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O8R I/O7R . 2654 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 o Storage Temperature TSTG IOUT Symbol o -65 to +150 DC Output Current Recommended DC Operating Conditions 50 C VCC Supply Voltage GND Ground VIH VIL C Parameter Input High Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) Input Low Voltage -0.5 (2) 6.0 ____ 0.8 V 2654 tbl 03 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. mA V 2654 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(1) Max. Unit V IN = 3dV 9 pF V OUT = 3dV 10 pF 2654 tbl 04 NOTE: 1. This parameter is determined by device characterization but is not production tested. Maximum Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature GND Vcc 0OC to +70OC 0V 5.0V + 10% 0V 5.0V + 10% O O -40 C to +85 C NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2654 tbl 02 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 70121S 70125S Symbol Parameter Test Conditions (1) 70121L 70125L Min. Max. Min. Max. Unit |ILI| Input Leakage Current V CC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA |ILO| Output Leakage Current V CC = 5.5V, CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA 0.4 ___ 0.4 V ___ 2.4 ___ V VOL Output Low Voltage IOL = +4mA ___ VOH Output High Voltage IOH = -4mA 2.4 2654 tbl 05 NOTE: 1. At Vcc < 2.0V leakages are undefined. 3 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,4) (VCC = 5V ± 10%) 70121X25 70125X25 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition Version CE = VIL, Outputs Disabled f = fMAX(2) ISB1 Standby Current (Both Ports - TTL Level Inputs) CE"A" = CE"B" = VIH f = fMAX ISB2 ISB3 ISB4 Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) 70121X35 70125X35 Com'l & Ind Typ. Max. Typ. Max. Unit mA COM'L S L 135 135 260 220 135 135 250 210 IND S L ___ ___ ___ ___ 135 135 275 250 COM'L S L 30 30 65 45 30 30 65 45 IND S L ___ ___ ___ ___ 30 30 80 65 COM'L S L 80 80 175 145 80 80 165 135 IND S L ___ ___ ___ ___ 80 80 190 165 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 IND S L ___ ___ ___ ___ 1.0 0.2 15 5 S L 70 70 170 140 70 70 160 130 S L ___ ___ ___ ___ 70 70 185 160 mA (2) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(2) CE"A" and CE"B" > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(2) COM'L IND mA mA mA 2654 tbl 06a 70121X45 70125X45 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition Version CE = VIL, Outputs Disabled 70121X55 70125X55 Com'l Only Typ. Max. Typ. Max. Unit mA COM'L S L 135 135 245 205 135 135 240 200 IND S L ___ ___ ___ ___ ___ ___ ___ ___ COM'L S L 30 30 65 45 30 30 65 45 IND S L ___ ___ ___ ___ ___ ___ ___ ___ COM'L S L 80 80 160 130 80 80 155 125 IND S L ___ ___ ___ ___ ___ ___ ___ ___ COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 IND S L ___ ___ ___ ___ ___ ___ ___ ___ COM'L S L 70 70 155 125 70 70 150 120 IND S L ___ ___ ___ ___ ___ ___ ___ ___ (2) f = fMAX ISB1 Standby Current (Both Ports - TTL Level Inputs) CE"A" = CE"B" = VIH mA (2) f = fMAX ISB2 ISB3 ISB4 Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(2) CE"A" and CE"B" > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled, f = fMAX(2) mA mA mA 2654 tbl 06b NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vcc=5V, TA=+25°C for Typ, and is not production tested. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". 4 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Data Retention Characteristics (L Version Only) Symbol Parameter Test Condition Min. Typ.(1) Max. Unit 2.0 ___ ___ V µA VDR VCC for Data Retention ICCDR Data Retention Current VCC = 2V, CE > VCC - 0.2V IND. ___ 100 4000 tCDR (3) Chip Deselect to Data Retention Time VIN > VCC - 0.2V or V IN < 0.2 COM'L. ___ 100 1500 tR(3) Operation Recovery Time tRC(2) ___ ___ V 2654 tbl 07 NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed but is not production tested. Data Retention Waveform DATA RETENTION MODE Vcc VDR ≥ 2V 4.5V 4.5V tCDR CE tR VDR VIH VIH 2654 drw 03 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2654 tbl 08 5V 5V 1250Ω 1250Ω DATAOUT BUSY INT DATAOUT 775Ω 775Ω 30pF 5pF* 2654 drw 04 Figure 1. AC Output Test Load Figure 2. Output Test Load (For tLZ , tHZ , tWZ, tOW) *Including scope and jig. 5 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) 70121X25 70125X25 Com'l Only Symbol Parameter 70121X35 70125X35 Com'l & Ind Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 25 ____ 35 ____ ns tAA Address Access Time ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 25 ____ 35 ns Output Enable Access Time ____ 12 ____ 25 ns 0 ____ 0 ____ ns 0 ____ 0 ____ ns ____ 10 ____ 15 ns 0 ____ 0 ____ ns 50 ____ 50 ns tAOE Output Hold from Address Change tOH Output Low-Z Time tLZ (1,2) Output High-Z Time tHZ (1,2) Chip Enable to Power Up Time tPU (2) Chip Disable to Power Down Time tPD (2) ____ 2654 tbl 09a 70121X45 70125X45 Com'l Only Symbol Parameter 70121X55 70125X55 Com'l Only Min. Max. Min. Max. Unit Read Cycle Time 45 ____ 55 ____ ns tAA Address Access Time ____ 45 ____ 55 ns tACE Chip Enable Access Time ____ 45 ____ 55 ns tAOE Output Enable Access Time ____ 30 ____ 35 ns 0 ____ 0 ____ ns 0 ____ 0 ____ ns ____ 20 ____ 30 ns 0 ____ 0 ____ ns 50 ____ 50 ns READ CYCLE tRC tOH Output Hold from Address Change (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enable to Power Up Time (2) tPD Chip Disable to Power Down Time (2) ____ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. 'X' in part numbers indicates power rating (S or L). 6 6.42 2654 tbl 09b APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Side(1,2,4) tRC ADDRESS tAA tOH tOH DATAOUT PREVIOUS DATA VALID DATA VALID BUSYOUT 2654 drw 05 tBDD (3,4) Timing Waveform of Read Cycle No. 2, Either Side(5) tACE CE tAOE (4) tHZ (2) OE tHZ (2) tLZ (1) VALID DATA DATAOUT tLZ (1) ICC CURRENT ISS tPD tPU 50% (4) 50% 2654 drw 06 NOTES: 1. Timing depends on which signal is aserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW. 7 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70121X25 70125X25 Com'l Only Symbol Parameter 70121X35 70125X35 Com'l & Ind Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time (4) 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width(6) 20 ____ 30 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns 12 ____ 20 ____ ns ____ 10 ____ 15 ns 0 ____ 0 ____ ns ____ 10 ____ 15 ns 0 ____ 0 ____ tDW tHZ Data Valid to End-of-Write Output High-Z Time Data Hold Time tDH (1,2,3) (5) (1,3) tWZ Write Enable to Output in High-Z tOW Output Active from End-of-Write (1,2,3,5) ns 2654 tbl 10a 70121X45 70125X45 Com'l Only Symbol Parameter 70121X55 70125X55 Com'l Only Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time (4) 45 ____ 55 ____ ns tEW Chip Enable to End-of-Write 35 ____ 40 ____ ns 35 ____ 40 ____ ns 0 ____ 0 ____ ns tAW tAS Address Valid to End-of-Write Address Set-up Time (6) tWP Write Pulse Width 35 ____ 40 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 20 ____ 20 ____ ns ____ 20 ____ 30 ns 0 ____ 0 ____ ns ____ 20 ____ 30 ns 0 ____ 0 ____ tHZ Output High-Z Time (1,2,3) (5) tDH Data Hold Time tWZ Write Enable to Output in High-Z(1,3) tOW Output Active from End-of-Write (1,2,3,5) ns 2654 tbl 10b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. For MASTER/SLAVE combination, tWC = t BAA + tWP, since R/W = VIL must occur after tBAA . 4. 'X' in part numbers indicates power rating (S or L). 5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW. 6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW . If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 8 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tWR(3) tAW CE R/W tWP (2) tAS(6) tHZ tWZ (7) DATAOUT (7) tOW (4) (4) tDW tDH DATAIN 2654 drw 07 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE tAS(6) tEW (2) tWR (3) R/W tDW tDH DATAIN 2654 drw 08 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or t WP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW . If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 70121X25 70125X25 Com'l Only Symbol Parameter 70121X35 70125X35 Com'l & Ind Min. Max. Min. Max. Unit 20 ____ 20 ns BUSY TIMING (For MASTER IDT70121) tBAA BUSY Access Time from Address ____ tBDA BUSY Disable Time from Address ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ns tWDD Write Pulse to Data Delay (1) 50 tDDD Write Data Valid to Read Data Delay tAPS Arbitration Priority Set-up Time (2) tBDD BUSY Disable to Valid Data tWH Write Hold After BUSY (1) 60 35 (3) (5) 45 ____ 5 ____ ____ ns ____ 30 ns 15 ____ 30 20 ____ ns 5 BUSY INPUT TIMING (For SLAVE IDT70125) tWB Write to BUSY Input(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 15 ____ 20 ____ ns ____ 50 ____ 60 ns 35 ____ 45 tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ____ ns 2654 tbl 11a 70121X45 70125X45 Com'l Only Symbol Parameter 70121X55 70125X55 Com'l Only Min. Max. Min. Max. Unit 20 ____ 30 ns BUSY TIMING (For MASTER IDT 70121) tBAA BUSY Access Time from Address ____ tBDA BUSY Disable Time from Address ____ 20 ____ 30 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 30 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 30 ns tWDD tDDD Write Pulse to Data Delay (1) 70 Write Data Valid to Read Data Delay (1) (2) 80 55 65 5 ____ 5 ____ ns 35 ____ 45 ns tAPS Arbitration Priority Set-up Time tBDD BUSY Disable to Valid Data ____ tWH Write Hold After BUSY(5) 20 ____ 20 ____ ns (3) BUSY INPUT TIMING (For SLAVE IDT 70125) tWB Write to BUSY Input(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 20 ____ 20 ____ ns ____ 70 ____ 80 ns 55 ____ 65 tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ____ NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.. 5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 6. 'X' in part numbers indicates power rating (S or L). 10 6.42 ns 2654 tbl 11b APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3) tWC ADDR 'A' MATCH tWP R/W'A' tDW DATAIN'A' tDH VALID tAPS (1) ADDR'B' MATCH tBDA tBDD BUSY'B' tWDD DATAOUT 'B' VALID (4) tDDD 2654 drw 09 NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT70125). 2. CE L = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is oppsite from port "A". Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH R/W"B" (1) (2) 2654 drw 10 NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A". Timing Waveform of BUSY Arbritration Controlled by CE Timing(1) ADDR"A and B" (1) ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC tBDC BUSY"B" 2654 drw 11 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). 11 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of BUSY Arbritration Controlled by Address(1) tRC OR tWC ADDR'A' ADDRESSES MATCH ADDRESSES DO NOT MATCH tAPS(2) ADDR'B' tBAA tBDA BUSY'B' 2654 drw 12 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 70121X35 70125X35 Com'l & Ind 70121X25 70125X25 Com'l Only Symbol Parameter Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 35 ns tINR Interrupt Reset Time ____ 25 ____ 35 ns 2654 tbl 12a 70121X45 70125X45 Com'l Only Symbol Parameter 70121X55 70125X55 Com'l Only Min. Max. Min. Max. Unit 0 ____ 0 ____ ns 0 ____ 0 ____ ns 40 ____ 45 ns 40 ____ 45 ns INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time ____ Interrupt Reset Time ____ 2654 tbl 12b NOTES: 1. 'X' in part numbers indicates power rating (S or L). 12 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Interrupt Mode(1) tWC INTERRUPT SET ADDRESS (2) ADDR'A' tWR(4) tAS(3) R/W'A' tINS (3) INT'B' NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 2654 drw 13 Truth Tables Truth Table I. Non-Contention Read/Write Control(4) Left or Right Port(1) R/W CE OE D0-8 X H X Z Port Disab le and in Power-Down Mode, ISB2 or ISB4 X H X Z CER = CEL = H, Power-DownMode, ISB1 or ISB3 L L X DATAIN H L L DATAOUT H L H Z Function Data on Port Written Into Memory (2) Data in Memory Output on Port(3) High-Impedance Outputs 2654 tbl 13 NOTES: 1. A0L – A10L ≠ A0R – A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE Truth Table II. Interrupt Flag(1,4) Left Port Right Port R/WL CEL OEL A10L-A0L INTL R/WR CER OER A10R-A0R INTR L L X 7FF X X X X X L(2) Set Right INTR Flag X X X X X X L L 7FF H(3) Reset Right INTR Flag X X X X L(3) L L X 7FE X Set Left INTL Flag X L L 7FE H(2) X X X X X Reset Left INTL Flag Function 2654 tbl 14 NOTES: 1. Assumes BUSYL = BUSYR = V IH 2. If BUSY L = VIL, then No Change. 3. If BUSY R = VIL, then No Change. 4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE 13 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges The IDT70121/125 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70121/125 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CE = R/W = VIL per Truth Table II. The left port clears the interrupt by access address location 7FE access when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (9 bits) at 7FE or 7FF is userdefined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Table II for the interrupt operation. The BUSY outputs on the IDT70121/125 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70121/125 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70121 RAM the BUSY pin is an output of the part, and the BUSY pin is an input of the IDT70125 as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and CE MASTER Dual Port RAM BUSYL BUSYR CE SLAVE Dual Port RAM BUSYL BUSYR DECODER Functional Description MASTER CE Dual Port RAM BUSYL BUSYR SLAVE CE Dual Port RAM BUSYR BUSYL BUSYR Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by using the IDT70125 (SLAVE). In the IDT70125, the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. BUSYL , 2654 drw 14 Figure 3. Busy and chip enable routing for both width and depth expansion with 70121 (Master) and 70125 (Slave) RAMs. inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. 14 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX X XXX X Device Power Speed Package Type X X Process/ Temperature Range Blank I (1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green J 52-pin PLCC (J52-1) 25 35 45 55 Commercial Only Commercial & Industrial Commercial Only Commercial Only L S Low Power Standard Power 70121 18K (2K x 9-Bit) MASTER Dual-Port RAM w/ Interrupt 18K (2K x 9-Bit) SLAVE Dual-Port RAM w/ Interrupt 2654 drw 15 70125 , Speed in nanoseconds NOTE: 1. Industrial temperature: for other speeds, packages and powers contact your sales office. Datasheet Document History 01/06/99: 06/03/99: 05/28/04: 04/05/06: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Page 3 Changed storage temperature parameter from -55 to +125 to -65 to +150 Clarified TA parameter footnote Page 4 DC Electrical parameters–changed test condition wording from "open" to "disabled" Page 9 Changed ±500mV to 0mV in notes Page 2 Added date revision for pin configuration Page 4, 6, 8,10&12 Added Industrial temp to column headings for 35ns speed to DC and AC Electrical Characteristics Page 4 Removed Industrial temp from 25, 45 & 55ns speeds from DC Electrical Characteristics Page 3, 4, 6, 8,10&12 Removed Industrial temp footnote from all tables Page 10 Corrected error in AC BUSY timing tables changing 71V33 to 70121 and changing 71V43 to 70125 Page 15 Added Industrial temp offering to 35ns ordering information Page 1 & 15 Replaced old TM logo with new TM logo Page 6 Footnote reference 5 removed from AC Electrical Characteristics READ table Page 1 Changed wording of footnote 1 from "INT is totem-pole output" to "INT is non-tr-stated push-pull output" Page 5 Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns Page 1 Added green availability to features Page 15 Added green indicator to ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: 408-284-2794 [email protected] The IDT logo is a registered trademark of Integrated Device Technology, Inc. 15 APRIL 05, 2006