Maxim MAX11060GUU 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adc Datasheet

19-5741; Rev 1; 4/11
KIT
ATION
EVALU
LE
B
A
IL
A
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24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
The MAX11040K/MAX11060 are 24-/16-bit, 4-channel,
simultaneous-sampling, sigma-delta analog-to-digital
converters (ADCs). The devices allow simultaneous
sampling of as many as 32 channels using a built-in
cascade feature to synchronize as many as eight
devices. The serial interface of the devices allows reading data from all the cascaded devices using a single
command. Four modulators simultaneously convert
each fully differential analog input with a programmable
data output rate ranging from 0.25ksps to 64ksps. The
devices achieve 106dB SNR at 16ksps and 117dB SNR
at 1ksps (MAX11040K). The devices operate from a
single +3V supply. The differential analog input range is
±2.2V when using the internal reference; an external
reference is optional. Each input is overvoltage protected up to ±6V without damage. The devices use an
internal crystal oscillator or an external source for clock.
The devices are compatible with SPI™, QSPI™,
MICROWIRE™, and DSP-compatible 4-wire serial interfaces. An on-board interface logic allows one serial interface (with a single chip select) to control up to eight
cascaded devices or 32 simultaneous sampling analog
input channels.
The devices are ideally suited for power-management
systems. Each channel includes an adjustable sampling phase enabling internal compensation for phase
shift due to external dividers, transformers, or filters at
the inputs. The output data rate is adjustable with a
0.065% resolution (at 16ksps or below) to track the
varying frequency of a periodic input. A SYNC input
allows periodic alignment of the conversion timing of
multiple devices with a remote timing source.
The devices are available in a 38-pin TSSOP package specified over the -40°C to +105°C industrial temperature range.
Applications
Power-Protection Relay Equipment
Features
o Four Fully Differential Simultaneously Sampled
Channels
o Cascadable for Up to 32 Channels of
Simultaneous Sampling
o 106dB (MAX11040K) SNR at 16ksps
o 117dB (MAX11040K) SNR at 1ksps
o 0.25% Error Over a 1000:1 Dynamic Range,
Processed Over 16.7ms (MAX11040K)
o ±2.2V Full-Scale Input Range
o ±6V Overvoltage Protected Inputs
o Internal Crystal Oscillator
o 2.5V, 50ppm/°C Internal Reference or External
Reference
o Programmable Output Data Rate
0.25ksps to 64ksps Range
0.065% Resolution
o Programmable Sampling Phase
0 to 333µs Delay in 1.33µs Steps
o SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire
Serial Interface
o Cascadable Interface Allows Control of Up to
Eight Devices with a Single CS Signal
o 3.0V to 3.6V Analog Supply Voltage
o 2.7V to VAVDD Digital Supply Voltage
o 38-Pin TSSOP Package
Functional Diagram
OVRFLW
AIN0+
DRDYIN
AIN1REF1
AIN2+
Medical Instrumentation
REF2
AIN3+
PART
TEMP RANGE
MAX11040KGUU+
-40°C to +105°C
38 TSSOP
MAX11060GUU+
-40°C to +105°C
38 TSSOP
SYNC
DIGITAL
FILTER
REF0
AIN1+
Multiphase Power Systems
Industrial Data-Acquisition Systems
Ordering Information
24-/16-BIT
ADC
AIN0-
FAULT
AIN2-
24-/16-BIT
ADC
DIGITAL
FILTER
24-/16-BIT
ADC
DIGITAL
FILTER
24-/16-BIT
ADC
DIGITAL
FILTER
DRDYOUT
REGISTERS AND
DIGITAL
CONTROL
SERIAL
INTERFACE
CASCIN
CASCOUT
CS
SCLK
AIN3-
DIN
DOUT
REF3
PIN-PACKAGE
MAX11040K
MAX11060
2.5V
REFERENCE
REFIO
CRYSTAL
OSCILLATOR
+Denotes a lead(Pb)-free/RoHS-compliant package.
AGND
XIN
XOUT
CLKOUT
DGND
MICROWIRE is a trademark of National Semiconductor Corp.
SPI/QSPI are trademarks of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX11040K/MAX11060
General Description
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ABSOLUTE MAXIMUM RATINGS
AIN_ _ to AGND (VAVDD < 3V or VDVDD < 2.7V or
FAULTDIS = 1 or SHDN = 1 or
fXIN CLOCK < 20MHz)........................................-3.5V to +3.5V
REFIO, REF_ to AGND............................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
TSSOP (derated 13.7mW/°C above +70°C) ..............1096mW
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
AVDD to AGND ........................................................-0.3V to +4V
DVDD to DGND ......................................-0.3V to (VAVDD + 0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
DIN, SCLK, CS, XIN, SYNC, DRDYIN,
CASCIN to DGND..............................-0.3V to (VDVDD + 0.3V)
DOUT, DRDYOUT, CASCOUT, CLKOUT,
XOUT to DGND..................................-0.3V to (VDVDD + 0.3V)
FAULT, OVRFLW to DGND ...................................-0.3V to +4.0V
AIN_+ to AIN_- ......................................................-6.0V to +6.0V
AIN_ _ to AGND (VAVDD ≥ 3V, VDVDD ≥ 2.7V, FAULTDIS = 0,
SHDN = 0, fXIN CLOCK ≥ 20MHz)....................-6.0V to +6.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
Differential Nonlinearity
DNL
Integral Nonlinearity (Note 3)
INL
MAX11040K
24
MAX11060
16
Bits
24-bit no missing code (MAX11040K);
16-bit no missing code (MAX11060)
0.1
TA = +25°C and +105°C (MAX11040K)
0.001
TA = -40°C (MAX11040K)
Gain Error
(Note 4)
Offset-Error Drift
(Note 5)
Gain-Error Drift
(Note 5)
Change in Gain Error vs. fOUT
fOUT = 0.25ksps to 64ksps
0.004
0.006
MAX11060
Offset Error
LSB
%FS
0.001
-1
+1
mV
-1
+1
%FS
Channel-to-Channel Gain Matching
0.5
ppm/°C
1
ppm/°C
< 0.025
% FS
0.03
% FS
DYNAMIC SPECIFICATIONS (62.5Hz sine-wave input, 2.17VP-P)
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
THD
(Note 6) (MAX11040K)
103
(Note 6) (MAX11060)
SINAD
-94
TA = -40°C (MAX11040K)
-90
SFDR
93
TA = -40°C (MAX11040K)
89
Relative Accuracy (Note 7)
2
98
dB
94
TA = +25°C and +105°C (MAX11040K)
94
TA = -40°C (MAX11040K)
89
MAX11060
dB
-106
TA = +25°C and +105°C (MAX11040K)
MAX11060
Spurious-Free Dynamic Range
dB
TA = +25°C and +105°C (MAX11040K)
MAX11060
Signal-to-Noise Plus Distortion
106
94.5
100
dB
100
0.1%FS input (MAX11040K)
0.25
6.0%FS input (MAX11040K)
0.005
_______________________________________________________________________________________
%
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Bandwidth
CONDITIONS
MIN
-3dB
Latency
(Note 8)
Passband Flatness
From DC to 1.4kHz
Amplitude-Dependent Phase Error
FS vs. 0.1% FS
TYP
MAX
3.4
UNITS
kHz
405
μs
< 0.1
dB
< 0.01
0.12
Degrees
Channel-to-Channel Phase Matching
0.0001
Degrees
Phase-Error Drift
0.001
Degrees
Channel-to-Channel Isolation
-130
dB
109
dB
Common-Mode Rejection
CMRR
ANALOG INPUTS (AIN_+, AIN_-)
Differential FS Input Range
VIN
VAIN_+ - VAIN_-
-2.2
+2.2
V
Single-Ended Positive Input Range
VAIN_+
Referenced to AGND
-2.2
+2.2
V
Single-Ended Negative Input Range
VAIN_-
Referenced to AGND
-2.2
+2.2
V
2.65
V
Positive Fault Threshold
VPFT
VAIN_+ or VAIN_- (Note 9)
2.25
Negative Fault Threshold
VNFT
VAIN_+ or VAIN_- (Note 9)
-2.65
Fault Pin Response Time
-2.25
2.5
Input Impedance
ZIN
DC Leakage Current
Input Sampling Rate
VNFT ≤ VIN ≤ VPFT
V
μs
130
kΩ
VIN < VNFT or VIN > VPFT
> 0.5
IIN
VAIN_+ = VAIN_-
±0.01
fS
fS = fXINCLOCK/8
3.072
Msps
4.0
pF
Input Sampling Capacitance
±1
μA
INTERNAL REFERENCE
REFIO Output Voltage
VREF
TA = TMAX
2.4
2.5
2.6
V
REFIO Output Resistance
1
kΩ
REFIO Temp Drift
50
ppm/°C
REFIO Long-Term Stability
200
ppm/
1000hr
3
μVRMS
75
dB
REFIO Output Noise
REFIO Power-Supply Rejection
PSRR
EXTERNAL REFERENCE
REFIO Input Voltage
VREF
2.3
2.7
V
REFIO Sink Current
200
μA
REFIO Source Current
200
μA
REFIO Input Capacitance
10
pF
24.576
MHz
CRYSTAL OSCILLATOR (XIN, XOUT)
Tested Resonant Frequency
(Note 10)
Maximum Crystal ESR
30
Ω
Oscillator Startup Time
<2
ms
10
ppm/°C
10
pF
Oscillator Stability
VDVDD = 3.3V, excluding crystal
Maximum Oscillator Load
_______________________________________________________________________________________
3
MAX11040K/MAX11060
ELECTRICAL CHARACTERISTICS (continued)
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 x
VDVDD
V
DIGITAL INPUTS (SCLK, CS, DIN, SYNC, CASCIN, DRDYIN, XIN)
Input Low Voltage
VIL
Input High Voltage
VIH
Input Hysteresis
VHYS
VDVDD = 3.0V
V
100
IL
±0.01
CIN
15
Input Leakage Current
Input Capacitance
0.7 x
VDVDD
mV
±1
μA
pF
CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT)
Output Low Voltage
VOL
ISINK = 5mA
Output High Voltage
VOH
ISOURCE = 1mA
Three-State Leakage Current
Three-State Capacitance
0.15 x
VDVDD
0.85 x
VDVDD
V
ILT
±1
COUT
V
15
μA
pF
OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT)
Output Low Voltage
VOL
ISINK = 5mA
Output High Voltage
VOH
Internal pullup only
0.15 x
VDVDD
0.85 x
VDVDD
Internal Pullup Resistance
V
V
30
kΩ
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
Digital Supply Voltage
DVDD
3.0
3.6
VAVDD
V
Normal operation
25
35
mA
Shutdown and fXINCLOCK = 0Hz
0.1
5
μA
Normal operation
11
15
mA
Shutdown and fXINCLOCK = 0Hz
0.3
μA
AC Positive-Supply Rejection
VAVDD = 3.3V + 100mVP-P at 1kHz
70
dB
DC Positive-Supply Rejection
VAVDD = VDVDD = 3.0V to 3.6V
75
dB
Human Body Model
2.5
kV
Analog Supply Current (Note 11)
IAVDD
Digital Supply Current (Note 11)
IDVDD
2.7
V
ESD PROTECTION
All Pins
ESD
TIMING CHARACTERISTICS (Figures 7–10)
SCLK Clock Period
tSCP
50
ns
SCLK Pulse Width (High and Low)
tPW
20
ns
DIN or CS to SCLK Fall Setup
tSU
10
ns
SCLK Fall to DIN Hold
tHD
0
ns
SCLK Rise to CS Rise
tCSH1
0
ns
4
_______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SCLK Rise to DOUT Valid
SYMBOL
tDOT
CONDITIONS
CLOAD = 30pF
MIN
TYP
MAX
1.5
10
16
CLOAD = 100pF
< 16
UNITS
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 30pF
0.3
20
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 30pF
0.7
16
ns
CS Pulse Width
tCSW
16
CASCIN-to-SCLK Rise Setup
tSC
16
ns
SCLK Rise to CASCOUT Valid
tCOT
SYNC Pulse Width
tSYN
2
XIN
Clock
Cycles
XIN Clock Pulse Width
tXPW
16
ns
ns
CLOAD = 100pF
20
DRDYIN to DRDYOUT
tDRDY
CLOAD = 30pF
20
XIN Clock to DRDYOUT Delay
tXDRDY
DRDYIN = DGND
40
XIN Clock Period
tXP
40
ns
ns
ns
ns
XIN Clock to SYNC Setup
tSS
(Note 12)
16
ns
SYNC to XIN Clock Hold
tHS
(Note 12)
5
ns
XIN-to-CLKOUT Delay
Power-On Reset Delay
tXCD
40
(Note 13)
<1
ns
ms
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at VAVDD = VDVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The relative accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
_______________________________________________________________________________________
5
MAX11040K/MAX11060
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (MAX11040K)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 =
CREF3 = 1μF, TA = +25°C, unless otherwise noted.)
250
0.5
1.5
2.5
DIFFERENTIAL INPUT VOLTAGE (V)
MAX11040K/11060 toc03
1 MILLION 62.5Hz CYCLES
0.1
0.01
0.001
0.10030
-0.5
0.10024
0
-1.5
0.10018
50
-0.005
-2.5
0.10012
100
-0.004
0.10006
-0.003
0.10000
150
0.09994
200
-0.002
0.09988
0
-0.001
300
1
MAXIMUM EXPECTED ERROR (%)
350
0.09982
0.001
MAX11040K/11060 toc02
400
INSTANCES
0.002
0.09976
0.003
450
0.09970
0.004
INL (% FS)
500
MAX11040K/11060 toc01
0.005
MAXIMUM EXPECTED ERROR OF CALCULATED
RMS AMPLITUDE vs. INPUT AMPLITUDE
HISTOGRAM OF RMS AMPLITUDE
AT 0.1% FS
INL vs. DIFFERENTIAL INPUT VOLTAGE
0.01
0.1
1
10
100
INPUT AMPLITUDE (% FS)
RMS AMPLITUDE (% FS)
100
90
-40
-60
-80
60Hz SINE-WAVE INPUT
-60
1
10
-120
-120
-160
-180
0
0
1000 2000 3000 4000 5000 6000 7000 8000
1000 2000 3000 4000 5000 6000 7000 8000
OUTPUT DATA RATE (ksps)
FREQUENCY (Hz)
FREQUENCY (Hz)
RMS AMPLITUDE
vs. INPUT FREQUENCY
RMS AMPLITUDE GAIN ERROR
vs. OUTPUT DATA RATE
RMS AMPLITUDE
vs. SOURCE RESISTANCE
-0.2
-0.3
-0.4
0.03
0.02
0.01
0
-0.01
-0.02
100
1000
INPUT FREQUENCY (Hz)
10,000
0
-1
-2
-3
-4
-5
-6
-0.03
-7
-0.04
-8
-0.05
-0.5
1
MAX11040K/11060 toc09
-0.1
0.04
RMS AMPLITUDE (dB)
0
0.05
MAX11040K/11060 toc08
MAX11040K/11060 toc07
0.1
10
-100
-140
100
RMS AMPLITUDE GAIN ERROR (%)
0.1
-80
-100
-140
80
6
MAX11040K/11060 toc05
60Hz SINE-WAVE INPUT
-20
-40
AMPLITUDE (dB FS)
110
0
AMPLITUDE (dB FS)
SNR (dB)
120
FFT vs. FREQUENCY AT 0.1% FULL SCALE
FFT vs. FREQUENCY AT FULL SCALE
MAX11040K/11060 toc04
130
MAX11040K/11060 toc06
SIGNAL-TO-NOISE RATIO
vs. OUTPUT DATA RATE
RMS AMPLITUDE (dB)
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
-9
100
1000
10,000
OUTPUT DATA RATE (Hz)
100,000
10
100
1000
10,000
SOURCE RESISTANCE (Ω)
_______________________________________________________________________________________
100,000
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
-120
0.04
0.02
0
-0.02
-0.04
0.06
1000
1500
-0.10
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR
vs. TEMPERATURE
0.2
0
-0.2
-0.4
0.8
VAVDD = VDVDD = 3.3V
0.2
0
-0.2
-0.8
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
47
76
105
0
-0.02
-0.04
-0.06
-0.08
-0.10
-1.0
3.2
18
-0.4
-0.6
3.1
-11
GAIN ERROR DRIFT
0.4
-0.8
3.0
-40
TEMPERATURE (°C)
0.6
-0.6
-1.0
3.6
MAX11040K/11060 toc14
0.4
3.5
1.0
GAIN ERROR (% FSR)
MAX11040K/11060 toc13
0.6
-0.04
-0.08
INPUT FREQUENCY (Hz)
AVDD = DVDD
0.8
0
-0.02
-0.06
2000
1.0
0.02
-0.08
GAIN ERROR (%)
500
0
0.04
-0.06
-0.10
-130
GAIN ERROR (% FSR)
MAX11040K/11060 toc11
0.06
AVDD = DVDD
0.08
MAX11040K/11060 toc15
-110
AVDD = DVDD
0.08
OFFSET ERROR vs. TEMPERATURE
0.10
OFFSET ERROR (% FSR)
-100
0.10
OFFSET ERROR (% FSR)
-90
THD (dB)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11040K/11060 toc10
-80
MAX11040K/11060 toc12
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
-40
-15
10
35
TEMPERATURE (°C)
60
85
0 100 200 300 400 500 600 700 800 900 1000
TIME (hr)
_______________________________________________________________________________________
7
MAX11040K/MAX11060
Typical Operating Characteristics (MAX11040K continued)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 =
CREF3 = 1μF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (MAX11040K continued)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 =
CREF3 = 1μF, TA = +25°C, unless otherwise noted.)
IDVDD
10
20
IAVDD
15
10
5
5
0
0
IDVDD
500
MAX11040K/11060 toc18
25
IAVDD
15
VAVDD = VDVDD = 3.3V
AVDD = DVDD
400
SUPPLY CURRENT (nA)
25
SUPPLY CURRENT (mA)
AVDD = DVDD
MAX11040K/11060 toc17
30
MAX11040K/11060 toc16
30
20
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
300
200
IDVDD
100
IAVDD
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-11
18
47
76
105
3.0
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
3.1
3.2
3.4
CRYSTAL OSCILLATOR STARTUP TIME
MAX11040K/11060 toc20
VAVDD = VDVDD = 3.6V
800
CLKOUT
500mV/div
600
IAVDD
400
IDVDD
200
0
-40
-11
18
47
76
105
40μs/div
TEMPERATURE (°C)
8
3.3
SUPPLY VOLTAGE (V)
MAX11040K/11060 toc19
1000
0
-40
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (nA)
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
_______________________________________________________________________________________
3.5
3.6
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
TOP VIEW
+
AIN0- 1
38 AIN2-
AIN0+ 2
37 AIN2+
REF0 3
36 REF2
AGND 4
35 AGND
AIN1- 5
34 AIN3-
AIN1+ 6
33 AIN3+
REF1 7
AGND 8
MAX11040K
MAX11060
32 REF3
31 AGND
REFIO 9
30 AVDD
AGND 10
29 AGND
DGND 11
28 DGND
DVDD 12
27 DVDD
CASCIN 13
26 XIN
CASCOUT 14
25 XOUT
CS 15
24 SYNC
SCLK 16
23 DRDYIN
DIN 17
22 DRDYOUT
DOUT 18
21 CLKOUT
FAULT 19
20 OVRFLW
TSSOP
Pin Description
PIN
NAME
1
AIN0-
Negative Analog Input Channel 0
2
AIN0+
Positive Analog Input Channel 0
3
REF0
ADC0 Buffered Reference Voltage. Bypass REF0 with a 1μF capacitor to AGND.
4, 8, 10,
29, 31, 35
AGND
Analog Ground
5
AIN1-
Negative Analog Input Channel 1
6
AIN1+
Positive Analog Input Channel 1
7
REF1
ADC1 Buffered Reference Voltage. Bypass REF1 with a 1μF capacitor to AGND.
REFIO
Reference Voltage Output/Input. Reference voltage for analog-to-digital conversion. In internal reference
mode, the reference buffer provides a +2.5V nominal output. In external reference mode, overdrive REFIO
with an external reference between 2.3V to 2.7V. Bypass REFIO with a 1μF capacitor to AGND.
9
FUNCTION
_______________________________________________________________________________________
9
MAX11040K/MAX11060
Pin Configuration
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
MAX11040K/MAX11060
Pin Description (continued)
PIN
NAME
11, 28
DGND
Digital Ground
12, 27
DVDD
Positive Digital Supply Voltage. Bypass each DVDD to DGND with a 1μF capacitor in parallel with a
0.01μF capacitor as close as possible to the device.
13
14
10
CASCIN
FUNCTION
Cascade Input. A logic-low on CASCIN while CS is a logic-low during the last cycle of a byte signals the
device to perform the requested data transfer during subsequent bytes using DIN and DOUT. Once the
requested transfer is completed, the part three-states DOUT and ignores DIN until a new command is
issued. CASCIN is clocked in at the rising edge of SCLK. Connect CASCIN to DGND when not daisy
chaining multiple devices. See the Multiple Device Connection section for connection recommendations.
Cascade Output. CASCOUT is driven low during the last cycle of the last byte of a data transfer to signal
the next device in the daisy-chain to begin transferring data on the next byte. CASCOUT changes after
CASCOUT
the rising edge of SCLK. Leave CASCOUT unconnected when not daisy chaining multiple devices. See
the Multiple Device Connection section.
15
CS
Active-Low Chip-Select Input. A falling edge on CS while CASCIN is a logic-low enables DIN and DOUT
for data transfer. A logic-high on CS prevents data from being clocked in on DIN and places DOUT in a
high-impedance state.
16
SCLK
Serial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the
rising edge of SCLK. SCLK must idle high (CPOL = 1).
17
DIN
Serial Data Input. Data at DIN is clocked in on the falling edge of SCLK.
18
DOUT
Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by a
falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the
appropriate number of data bytes have been transferred in response to the requested command. Data is
clocked out at DOUT on the rising edge of SCLK.
19
FAULT
Active-Low Overvoltage Fault Indicator Output. FAULT goes low when any analog input goes outside the fault
threshold range (between VPFT and VNFT). The FAULT output is open drain with a 30kΩ internal pullup
resistor, allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
20
OVRFLW
Active-Low Channel Data Overflow Output. OVRFLW goes low when a conversion result goes outside the
voltage range bounded by the positive and negative full scale on one or more of the analog input
channels or when FAULT goes low. The OVRFLW output is open drain with a 30kΩ internal pullup resistor,
allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
21
CLKOUT
Buffered Clock Output. When the XTALEN bit in the configuration register is 1 and a crystal is installed
between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the
XTALEN bit to 0 places CLKOUT in a high-impedance state.
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
PIN
22
23
NAME
FUNCTION
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the
DRDYOUT availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when
DRDYIN = 1. See the Multiple Device Connection section.
DRDYIN
Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When
DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple
Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices.
24
SYNC
Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that
multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals
by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain.
Connect SYNC to DGND for single device operation. See the Multiple Device Connection section.
25
XOUT
Crystal Oscillator Output. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator. Leave XOUT unconnected when driving with an external frequency. See
the Crystal Oscillator section.
26
XIN
Crystal Oscillator/Clock Input. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator or drive XIN with an external clock and leave XOUT unconnected. See
the Crystal Oscillator section.
30
AVDD
Positive Analog Supply Voltage. Bypass to AGND with a 1μF capacitor in parallel with a 0.01μF capacitor
as close as possible to the device.
32
REF3
ADC3 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
33
AIN3+
Positive Analog Input Channel 3
34
AIN3-
Negative Analog Input Channel 3
36
REF2
ADC2 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
37
AIN2+
Positive Analog Input Channel 2
38
AIN2-
Negative Analog Input Channel 2
______________________________________________________________________________________
11
MAX11040K/MAX11060
Pin Description (continued)
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
MAX11040K/MAX11060
Typical Operating Circuit
1µF
3.3V
3.3V
0.01µF
20pF
DVDD
XIN
AIN0+
AIN0REF0
1µF
AIN1+
AIN1-
The devices operate from a single 3.0V to 3.6V analog
supply and a 2.7V to VAVDD digital supply. The 4-wire
serial interface is SPI/QSPI/MICROWIRE and DSP compatible.
1µF
0.01µF
AVDD
AIN0+
AIN0-
24.576MHz
XOUT
20pF
AIN1+
AIN1REF1
MAX11040K CLKOUT
MAX11060 CASCOUT
CASCIN
1µF
AIN2+
AIN2-
AIN2+
AIN2-
OVRFLW
FAULT
REF2
1µF
CS
AIN3+
AIN3-
the effective sample rate of the ADC, is software programmable.
AIN3+
AIN3REF3
1µF
SCLK
DIN
DOUT
MICROCONTROLLER
OR DSP
ADC Modulator
Each channel of the devices performs analog-todigital conversion on its input using a dedicated
switched-capacitor sigma-delta modulator. The modulator converts the input signal into low-resolution digital data
for which the average value represents the digitized signal information at 3.072Msps for a 24.576MHz XIN clock.
This data stream is then presented to the digital filter for
processing to remove the high-frequency noise that creates a high-resolution 24-/16-bit output data stream.
The input sampling network of the analog input consists
of a pair of 4pF capacitors (C SAMPLE ), the bottom
plates of which are connected to AIN_+ and AIN_- during the track phase and then shorted together during
the hold phase (see Figure 1). The internal switches
have a total series resistance of 400Ω. Given a
24.576MHz XIN clock, the switching frequency is
3.072MHz. The sampling phase lasts for 120ns.
SYNC
DRDYOUT
REFIO
1µF
AGND
DRDYIN
DGND
MAX11040K
MAX11060
TRACK
AIN_+
CSAMPLE+
Detailed Description
The MAX11040K/MAX11060 are 24-/16-bit, simultaneous-sampling, 4-channel, sigma-delta ADCs including
support for synchronized sampling and daisy chaining
of the serial interface across multiple (up to eight)
devices. The serial interface of the set of synchronized
devices behaves as one device. Each channel includes
a differential analog input, a sigma-delta modulator, a
digital decimation filter, an independent programmable
sampling delay, and a buffered reference signal from
the internal or an external reference. The device contains an internal crystal oscillator. The output data rate,
12
HOLD
TO ADC
CSAMPLE-
AIN_TRACK
RON
RON
AVDD/2
Figure 1. Simplified Track/Hold Stage
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Since the transfer function of a digital filter is repeatable
and predictable, it is possible to correct for frequencydependent attenuation in downstream software. See
the Compensating for the Rolloff of the Digital Filter in a
Typical FFT Analysis section. The transfer function is
defined by the following equation:
⎛
⎛
fAIN ⎞ ⎞
⎜ fSAMPLE × sin ⎜ π ×
⎟
fSAMPLE ⎟⎠ ⎟
⎝
Gain(fAIN ) = ⎜⎜
⎛
⎞⎟
fAIN
⎜ fXINCLOCK × sin ⎜ π ×
⎟
⎜⎝
fXINCLOCK ⎟⎠ ⎟⎠
⎝
3
× (FIR _ Gain (fAIN ))
MAX11040K fig02
1
0
GAIN (dB)
-1
-2
-3
-4
-5
-6
0
0.04
0.08
0.12
0.16
0.20
0.24
0.28
fAIN/fSAMPLE
Figure 2. Digital Filter Response
Table 1. Bandwidth vs. Output Data Rate
OUTPUT DATA
RATE (ksps)
-3dB BANDWIDTH
(kHz)
-0.1dB BANDWIDTH
(kHz)
0.5
0.11
0.05
1
0.21
0.11
2
0.42
0.22
4
0.85
0.43
8
1.69
0.87
10
2.11
1.09
12
2.54
1.31
16
3.38
1.74
32
6.78
3.48
64
13.5
6.96
where:
Gain is the filter gain.
fAIN is the analog input frequency.
fSAMPLE is the programmed output data rate, nominally
16kHz.
f XINCLOCK is the clock frequency at XIN, nominally
24.576MHz.
FIR_Gain (fAIN) is the normalized gain of the FIR filter
with the following filter coefficients, as a function of the
analog input frequency f AIN. These coefficients are
applied at the output data rate:
+ 0.022
- 0.074
- 0.036
+ 0.312
+ 0.552
+ 0.312
- 0.036
- 0.074
+ 0.022
______________________________________________________________________________________
13
MAX11040K/MAX11060
Digital Filter
The devices contain an on-chip digital lowpass filter
that processes the data stream from each modulator
and generates the high-resolution output data. The lowpass filter frequency response is determined by the
programmable output data rate. At the nominal 16ksps
output data rate, the -3dB bandwidth of the filter is
3.4kHz. The passband flatness is better than ±0.1dB
from 0 to 1.74kHz. The notches are located at 5.75kHz
and 7.195kHz. These frequencies scale linearly with the
output data rate. See Figure 2 and Table 1 for the frequency response at different data rates.
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Modulator Clock
The modulator clock is created by dividing the frequency at the XIN input by a factor of 8. The XIN input is driven either directly by an external clock or by the
on-chip crystal oscillator.
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) with a 24.576MHz operating frequency connected between XIN and XOUT, as shown in Figure 3.
As in any crystal-based oscillator circuit, the oscillator
frequency is sensitive to the capacitive load (CL). CL is
the capacitance that the crystal needs from the oscillator circuit and not the capacitance of the crystal. The
input capacitance across XIN and XOUT is 1.5pF.
Choose a crystal with a 24.576MHz oscillation frequency and an ESR less than 30Ω, such as the MP35 from
RXD Technologies. See Figure 3 for the block diagram
of the crystal oscillator. Set XTALEN = 1 in the configuration register to enable the crystal oscillator. The
CLKOUT output provides a buffered version of the
clock that is capable of driving eight devices, allowing
synchronized operation from a single crystal. See the
Multiple Device Synchronization section in the
Applications Information section.
External Clock
To use an external clock, set XTALEN = 0 in the
Configuration register and connect an external clock
source (20MHz–25MHz) to XIN. CLKOUT becomes
high impedance.
MAX11040K
MAX11060
20pF
XIN
24.576MHz
OSCILLATOR
24.576MHz
20pF
XOUT
Analog Input Overvoltage
and Fault Protection
The full-scale differential input range of the devices is
±0.88VREF. The converter accurately represents any
input for which the positive and negative analog inputs
are separated by a magnitude of less than 0.88VREF.
The device includes special circuitry that protects it
against voltages on the analog inputs up to +6V.
Setting FAULTDIS = 1 disables the protection circuitry.
There are two mechanisms of overvoltage detection
and protection: full-scale overflow and overvoltage
fault. Full-scale overflow occurs if the magnitude of the
applied input voltage on any one or more channels is
greater than 0.88VREF. In this case, the digital output is
clipped to positive or negative full scale and the OVRFLW
flag goes low. Overvoltage fault occurs if the magnitude of an applied input voltage on any one or more
channels goes outside the fault-detection thresholds.
The reaction to an overvoltage fault is dependent on
whether the fault-protection circuitry is enabled. If
enabled, the input-protection circuits engage and the
FAULT flag goes low. A full-scale overflow or an overvoltage fault condition on any one channel does not
affect the output data for the other channels.
The input protection circuits allow up to ±6V relative to
AGND on each input, and up to ±6V differentially
between AIN+ and AIN-, without damaging the devices
only if the following conditions are satisfied: power is
applied, the devices are not in shutdown mode, a clock
frequency of at least 20MHz is available at XIN, and
FAULTDIS = 0. The analog inputs allow up to ±3.5V relative to AGND when either devices are placed in shutdown mode, the clock stops, or FAULTDIS = 1.
During an overvoltage fault condition, the impedance
between AIN_+ and AIN_- reduces to as low as 0.5kΩ.
The output structure and cascading features of FAULT
and OVRFLW are discussed in the Multiple Device
Digital Interface section.
Analog Input Overflow
Detection and Recovery (OVRFLW)
The OVRFLW flag is set based on the ADC conversion
result. When the applied voltage on one or more analog
inputs goes outside the positive or negative full scale
(±0.88VREF), OVRFLW asserts after a delay defined by
the latency of the converter, coincident with the DRDYOUT
of the full-scale clamped conversion result (see Figure
4). The specifics of the latency are discussed earlier in
the data sheet in the Latency section.
Figure 3. Crystal Oscillator Input
14
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Overvoltage-Fault Detection and Recovery (FAULT)
With overvoltage-fault protection enabled (FAULTDIS =
0), FAULT immediately transitions from a high to low
when any of the analog inputs go outside the voltage
range bounded by the fault-detection thresholds VPFT
and VNFT.
Once the analog inputs return back within the fault
thresholds, the FAULT interrupt output goes high after a
delay called the fault-recovery time. The fault-recovery
time is:
20 x tDOUT < fault-recovery time < 25 x tDOUT
where tDOUT is the data output period determined by
fXINCLOCK and the selected output data rate.
In the event the analog input voltage changes between
the ADC full scale and the fault threshold faster than
the latency of the converter, the ADC conversion result
prematurely jumps to the full-scale value when a fault is
detected (see Detection Discontinuity in Figure 4).
During a fault condition and the subsequent faultrecovery time, the ADC conversion result remains at full
scale. This creates a discontinuity in the digital conversion result only if the fault recovery time is greater than
the latency plus the time that the input changes
between the fault threshold and the ADC full scale (see
Recovery Discontinuity in Figure 4). Neither of these
steps occur if the fault-protection circuitry is disabled
(FAULTDIS = 1), or if the input is slow relative to the
above descriptions (see Figure 5).
For data rates faster than 32ksps (FSAMPC = 111), the
converter output may contain invalid data for up to
188μs after FAULT returns high. To prevent this behavior, disable the overvoltage-fault protection by setting
the FAULTDIS bit in the configuration register to 1 when
using FSAMPC = 111, and limit the analog input swing
to ±3.5V.
FAULT-DETECTION
THRESHOLD
(VPFT OR |VNFT|)
|AIN+ - AIN-|
DETECTION
DISCONTINUITY
RECOVERY
DISCONTINUITY
FULL SCALE
(|0.88VREF|)
LATENCY
RECOVERY TIME
DIGITAL OUTPUT
DATA AT DOUT
LATENCY
LATENCY
LATENCY
FAULT
OVRFLW
Figure 4. High-Frequency Analog Input Overvoltage Detection and Recovery
______________________________________________________________________________________
15
MAX11040K/MAX11060
When the analog input voltage changes between the
ADC full scale and the fault threshold faster than the
latency of the converter, OVRFLW goes low with the
FAULT output. OVRFLW remains invalid until a valid
clock frequency is available at XIN.
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
FAULT-DETECTION
THRESHOLD
(VPFT OR |VNFT|)
|AIN+ - AIN-|
LATENCY
LATENCY
LATENCY
FULL SCALE
(|0.88VREF|)
RECOVERY TIME
DIGITAL OUTPUT
DATA AT DOUT
LATENCY
FAULT
OVRFLW
Figure 5. Low-Frequency Analog Input Overvoltage Detection and Recovery
Reference
The devices operate with either a +2.5V internal
bandgap reference or an external reference source
between +2.3V and +2.7V applied at REFIO. Bypass
REFIO and each REF_ to AGND with a 1μF capacitor.
The reference voltage sets the positive and negative
full-scale voltage according to the following formula:
±FS = ±0.88 VREFIO
The reference voltage at REFIO (external or internal) is
individually buffered to generate the reference voltages
at REF0 to REF3 (see Figure 6.) These independent
buffers minimize the potential for crosstalk between
each of the internal ADCs.
Serial Interface
The devices’ interface is fully compatible with SPI/DSP
standard serial interfaces (compatible with SPI modes
CPOL = 1, CPHA = 0). The serial interface provides
access to four on-chip registers: Sampling Instant
Control register (32 bits), Data Rate Control register (16
bits), Configuration register (8 bits), and Data register
(96 bits). All serial-interface commands begin with a
command byte, which addresses a specific register,
followed by data bytes with a data length that depends
on the specific register addressed and the number of
16
REF0
REF1
REF2
REF3
REFIO
+2.5V
REFERENCE
Figure 6. REFIO Input
devices cascaded (see Figures 7, 8, and the Registers
section).
The serial interface consists of eight signals: CS,
SCLK, DIN, DOUT, CASCIN, CASCOUT, DRDYIN,
and DRDYOUT. CASCIN, CASCOUT, DRDYIN, and
DRDYOUT are used for daisy chaining multiple devices
together. See the Multiple Device Connection section
for details on how to connect CASCIN, CASCOUT,
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ferred MSB first. Drive CS high to disable the interface
and place DOUT in a high-impedance state.
An interface operation with the devices takes effect on
the last rising edge of SCLK. If CS goes high before the
complete transfer, the write is ignored. Every data
transfer is initiated by the command byte. The command byte consists of an R/W bit and 7 address bits
(see Table 2.) Figures 7 and 8 show the timing for read
and write operations, respectively.
tCSW
tSU
CS
tPW
tPW
tSCP
tDCD
SCLK
tSU
R/W A6 A5 A4 A3 A2 A1 A0
DIN
tDOT
tHD
DOUT
tCSH1
COMMAND ADDRESS
HIGH-Z
HIGH-Z
B7 B6 B5 B4 B3 B2 B1 B0
tDOE
DATA LENGTH (NUMBER OF BYTES) DEPENDS
ON THE REGISTER BEING READ (SEE TABLE 2)
DRDYIN
tDRDY
DATA READY
DRDYOUT
Figure 7. General Read-Operation Timing Diagram
tCSW
tSU
CS
tCSH1
R/W A6 A5 A4 A3 A2 A1 A0
DIN
B7
B6 B5 B4 B3
B2 B1
B0
tHD
SCLK
tPW
tSU
tPW
DOUT
HIGH-Z
tSCP
DATA LENGTH (NUMBER OF BYTES) DEPENDS ON
THE REGISTER BEING WRITTEN (SEE TABLE 2)
HIGH-Z
Figure 8. General Write-Operation Timing Diagram
______________________________________________________________________________________
17
MAX11040K/MAX11060
DRDYIN, and DRDYOUT. For single-device applications,
connect CASCIN and DRDYIN to DGND and drive CS
low to transfer data in and out of the devices. With
DRDYIN low, a falling edge at the data-ready signal output (DRDYOUT) indicates that new conversion results
are available for reading in the 96-bit data register. A
falling edge on SCLK clocks in data at DIN. Data at
DOUT changes on the rising edge of SCLK and is valid
on the falling edge of SCLK. DIN and DOUT are trans-
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Registers
The devices include four registers accessible by 7
command bytes. The command bytes provide read
and write access to the Data Rate Control register, the
Sampling Instant Control register, and the Configuration
register, and read access to the Data register. See
Table 2. Figure 9 shows the CASCIN and CASOUT
timing diagram. Figure 10 is the XIN clock, CLKOUT,
SYNC, and DRDYOUT timing diagram.
SCLK
tCOT
CASCOUT
(DEVICE n)
CASCIN
(DEVICE n+1)
Table 2. Command Bytes
tSC
Figure 9. CASCIN and CASCOUT Timing Diagram
tXPW
tXP
XIN CLOCK
R/W
ADDRESS
[A6:A0]
DATA
LENGTH*
0
1000000
32 x n** bits
Write Sampling Instant
Control Register
1
1000000
32 x n bits
Read Sampling Instant
Control Register
0
1010000
16 bits
Write Data-Rate Control
Register
1
1010000
16 bits
Read Data-Rate Control
Register
0
1100000
8 x n bits
Write Configuration
Register
1
1100000
8 x n bits
Read Configuration
Register
1
1110000
96 x n bits
Read Data Register
tXCD
CLKOUT
tHS
tSS
SYNC
tSYN
tXDRDY
DRDYOUT
Figure 10. XIN Clock, CLKOUT, SYNC, and DRDYOUT Timing
Diagram
18
FUNCTION
*All data lengths are proportional to the number of cascaded
devices except for reads and writes to the Data Rate Control
register. When accessing the Data Rate Control register, the
data length is fixed at 16 bits. These 16 bits are automatically
written to all cascaded devices.
**n is the total number of cascaded devices.
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
which is 1.3μs to 333μs with fXINCLOCK at 24.576MHz
(see Table 3.)
Configuration Register
The Configuration register contains 5 bits that control the
functionality of the devices. The default state is 0x00.
The data length of the Configuration register is 8 bits
per cascaded device (see Table 4).
Table 3. Sampling Instant Control Register
BIT
NAME
DESCRIPTION
[31:24]
Channel 0 sample instant adjust. PHI0 delays sampling instant on channel 0 by 32 XIN clock cycles per
PHI0[7:0]
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
[23:16]
PHI1[7:0]
Channel 1 sample instant adjust. PHI1 delays sampling instant on channel 1 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
[15:8]
PHI2[7:0]
Channel 2 sample instant adjust. PHI2 delays sampling instant on channel 2 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
[7:0]
PHI3[7:0]
Channel 3 sample instant adjust. PHI3 delays sampling instant on channel 3 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
Table 4. Configuration Register
BIT
NAME
7
SHDN
6
RST
5
EN24BIT
Enable 24-bit resolution bit for the MAX11040K. Set EN24BIT high to enable the 24-bit data output. Set
EN24BIT low to enable 19-bit data output with device address and channel address tags. Tables 5 and 6
specify the Data register for both states of this bit. Set to 0 for MAX11060.
XTALEN
Internal oscillator enable bit. When using the on-chip crystal oscillator as the clock source, set XTALEN high
to enable the crystal oscillator and provide a buffered version of the crystal clock at the CLKOUT output.
When using an external clock source, set XTALEN low to disable the internal crystal oscillator and threestate the CLKOUT output. Connect the external clock source to the XIN input.
4
3
DESCRIPTION
Shutdown bit. Set SHDN high to place the device in shutdown mode. In shutdown mode, the internal
oscillator, fault circuitry, and internal bandgap reference are turned off. Set SHDN low for normal operation.
Reset bit. Set RST high to reset all registers to the default states except for the RST bit, and realign
sampling clocks and output data.
Overvoltage fault-protection disable bit. Set FAULTDIS high to disable the overvoltage fault-protection
circuits. For FAULTDIS = 0, the absolute maximum input range is ±6V. Analog inputs beyond the faultdetection threshold range trip the fault-protection circuits. The output remains clipped for a fault-recovery
FAULTDIS
time (typically < 1.57ms) after the inputs return within the fault-detection threshold range. For FAULTDIS =
1, the absolute maximum input range is only ±3.5V, but there is no fault-recovery delay. See the
Overvoltage Fault Detection and Recovery (FAULT) section.
2
PDBUF
[1:0]
Reserved
PDBUF = 1 disables the internal reference buffer. Use this mode when an external reference is used;
otherwise, PDBUF should be set to 0 to enable the internal reference buffer.
Must set to 0.
______________________________________________________________________________________
19
MAX11040K/MAX11060
Sampling Instant Control Register
By default, the devices sample all 4 input channels
simultaneously. To delay the sampling instant on one or
more channels, program the appropriate byte in the
Sampling Instant Control register. The delay of the
actual sampling instant of each individual channel from
the default sampling instant (PHI_[7:0] = 0x00) is
adjustable between 32 to 819,121 XIN clock cycles,
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Data Register
The Data register contains the results of the ADC conversion. The result is reported in two’s complement format. The register contains one or two pieces of
information, depending on the state of EN24BIT in the
Configuration register. When EN24BIT is set to zero, the
Data register contains the ADC data truncated to 19
bits, followed by the device and channel addresses
(see Table 5). When EN24BIT is set to one, the data
contained in the Data register represents the 24-bit
conversion (see Table 6). The data length of the Data
register is 96 bits for each cascaded device. Figure 11
shows the sequence of the conversion result output of
all channels for two cascaded devices. Table 7 is the
data register for the MAX11060.
If the results are not read back prior to completion of
the next conversion, the data is overwritten.
Table 5. Data Register (EN24BIT = 0) (MAX11040K)
BIT
NAME
[95:77]
CH0DATA[18:0]
[76:74]
IC[2:0]
[73:72]
00
[71:53]
CH1DATA[18:0]
[52:50]
IC[2:0]
[49:48]
01
[47:29]
CH2DATA[18:0]
[28:26]
IC[2:0]
[25:24]
10
[23:5]
CH3DATA[18:0]
[4:2]
IC[2:0]
[1:0]
11
DESCRIPTION
Channel 0 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
Channel 1 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
Channel 2 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
Channel 3 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 3 address tag = 11
Table 6. Data Register (EN24BIT = 1) (MAX11040K)
BIT
NAME
[95:72]
CH0DATA[23:0]
Channel 0 24-bit conversion result (two’s complement)
DESCRIPTION
[71:48]
CH1DATA[23:0]
Channel 1 24-bit conversion result (two’s complement)
[47:24]
CH2DATA[23:0]
Channel 2 24-bit conversion result (two’s complement)
[23:0]
CH3DATA[23:0]
Channel 3 24-bit conversion result (two’s complement)
Table 7. Data Register (MAX11060)
20
BIT
NAME
[95:80]
CH0DATA[15:0]
[79:77]
000
[76:74]
IC[2:0]
[73:72]
00
[71:56]
CH1DATA[15:0]
[55:53]
000
[52:50]
IC[2:0]
[49:48]
01
[47:32]
CH2DATA[15:0]
DESCRIPTION
Channel 0 16-bit conversion result (two’s complement)
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
Channel 1 16-bit conversion result (two’s complement)
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
Channel 2 16-bit conversion result (two’s complement)
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
BIT
NAME
[31:29]
000
[28:26]
IC[2:0]
[25:24]
10
[23:8]
CH3DATA[15:0]
[7:5]
000
[4:2]
IC[2:0]
[1:0]
11
MAX11040K/MAX11060
Table 7. Data Register (MAX11060) (continued)
DESCRIPTION
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
Channel 3 16-bit conversion result (two’s complement)
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 3 address tag = 11
CS
DIN
SCLK
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
DOUT
CHANNEL 0
DEVICE 0
CHANNEL 1
DEVICE 0
CHANNEL 2
DEVICE 0
CHANNEL 3
DEVICE 0
CHANNEL 0
DEVICE 1
CHANNEL 1
DEVICE 1
CHANNEL 2
DEVICE 1
CHANNEL 3
DEVICE 1
CASCOUT0
(CASCIN0 = 0)
DEVICE 1 TAKES OVER SPI BUS
CASCOUT1
DRDYOUT0
(DRDYIN0 = 0)
DRDYOUT1
DEVICE 0 DATA READY
DEVICE 0 AND DEVICE 1 DATA READY
Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices
Data Rate Control Register
The Data Rate Control register controls the output data
period, which corresponds to the output data rate of
the ADC. The data period is controlled by both a
coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0])
adjustment (see Table 8).
The final data rate is derived by dividing the XIN clock
frequency by a divider value. The divider value is a
function of FSAMPC[2:0] and FSAMPF[10:0]:
Data Rate = fXINCLOCK/Divider
Divider = Coarse Cycle Factor x 384 + Fine Cycle
Factor x FSAMPF[10:0]
Note: Fractional results for the divider are rounded
down to the nearest integer. Coarse cycle factor and
fine cycle factor come from Table 8. The effect of
FSAMPF[10:0] in the formula has limitations as noted in
the table.
Examples of output data rate vs. FSAMPC[2:0] and
FSAMPF[10:0] are shown in Table 9. Table 10 shows
typical device performance for various data rate settings.
______________________________________________________________________________________
21
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
The data length of the Data-Rate Control register is 16
bits total for writes and reads (see Table 2). Changes to
the Data-Rate Control register take effect after 16 conversion periods (Figure 12), i.e., the ADC continues to
operate at the old data rate for another 16 periods. Also,
the last sample at the old data rate (sample 16 in Figure
12) may contain some noise component and should be
discarded. Changes in data rate should be limited to
±5% for correct operation. The data rate register should
not be updated more than once every 32 data rate periods.
Note: Write to the data rate register in the time window of
10ns after the rising edge of DRDYOUT and 100ns
before the falling edge of DRDYOUT.
The digital filter determines the latency. Latency is
defined as the time between the effective point in time
that a sample is taken and when the resulting digital data
1
2
is available for reading (DRDYOUT goes low). The latency of the converter is specified by the following equation:
Latency = (6 x tDOUT) + (PHI x 1.3μs) + 30μs
where tDOUT is the data output period (inverse of the
programmed sample rate) determined by XINCLOCK
and the selected output data rate, and PHI is the programmed sampling instant delay for the channel in question (0 ≤ PHI ≤ 255). The latency is approximately 405μs
at 16ksps.
Because the two filters operate at different output data
rates, a skew builds up between them over the 16 samples that both are in operation. For example, at 30ksps,
the minimum data rate step size is 0.125%; so over 16
samples, the difference becomes 2%. This causes the
period from sample 16 to sample 17 to be different by
this amount.
15
16
17
DRDYOUT
CS
CHANGE DATA RATE
DATA AT THE OLD
DATA RATE
DATA AT THE NEW
DATA RATE
DATA READ
Figure 12. Timing Diagram for a Data-Rate Change
22
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
BITS
NAME
MAX11040K/MAX11060
Table 8. Data-Rate Control Register
DESCRIPTION
Output data rate coarse adjust bits. FSAMPC[2:0] sets the coarse cycle factor.
FSAMPC
[15:13]
FSAMPC[2:0]
[12:11]
Reserved
Coarse Cycle
Factor
Sample Rate in ksps
(fXIN CLOCK = 24.576MHz)
000
4
16
001
128
0.5
010
64
1
011
32
2
100
16
4
101
8
8
110
2
32
111
1
64
Set to 0.
Output data rate fine adjusts bits. FSAMPF[10:0] increases the output data period by a number of
XIN clock cycles. This number is the value of the register times the fine cycle factor. Values of
FSAMPF greater than 1535 have no additional effect.
[10:0]
FSAMPF[10:0]
FSAMPC
XIN Fine Cycle Factor
000
1 cycle
001
32 cycles
010
16 cycles
011
8 cycles
100
4 cycles
101
2 cycles
110
1 cycle
111
1 cycle
Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0]
FSAMPC[2:0]
001
010
011
FSAMPF[10:0]
OUTPUT DATA
RATE (sps)
OUTPUT DATA PERIOD
(24.576MHz CLOCK CYCLES)
11xxxxxxxxx
250.1
98272
10111111111
250.1
98272
00000000001
499.7
49184
00000000000
500.0
49152
11xxxxxxxxx
500.2
49136
10111111111
500.2
49136
00000000001
999.3
24592
00000000000
1000.0
24576
11xxxxxxxxx
1000.3
24568
10111111111
1000.3
24568
00000000001
1998.7
12296
00000000000
2000.0
12288
FSAMPF OUTPUT DATA PERIOD
RESOLUTION
(24.576MHz CLOCK CYCLES)
32
16
8
______________________________________________________________________________________
23
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and
FSAMPF[10:0] (continued)
FSAMPC[2:0]
100
101
000
110
111
FSAMPF[10:0]
OUTPUT DATA
RATE (sps)
OUTPUT DATA PERIOD
(24.576MHz CLOCK CYCLES)
11xxxxxxxxx
2000.7
12284
10111111111
2000.7
12284
00000000001
3997.4
6148
00000000000
4000.0
6144
11xxxxxxxxx
4001.3
6142
10111111111
4001.3
6142
00000000001
7994.8
3074
00000000000
8000.0
3072
11xxxxxxxxx
8002.6
3071
10111111111
8002.6
3071
00000000001
15990
1537
00000000000
16000
1536
11xxxxxxxxx
16010
1535
1011111111x
16010
1535
0000000001x
31958
769
0000000000x
32000
768
11xxxxxxxxx
32042
767
101111111xx
32042
767
000000001xx
63834
385
000000000xx
64000
384
FSAMPF OUTPUT DATA PERIOD
RESOLUTION
(24.576MHz CLOCK CYCLES)
4
2
1
1
1
Table 10. Typical Performance vs. Output Data Rate
OUTPUT
DATA RATE
(ksps)
24
-3dB
-0.1dB
BANDWIDTH BANDWIDTH
(kHz)
(kHz)
FAULT
LATENCY
SNR OF 24-BIT
RECOVERY
(µs)
DATA (dB)
TIME (µs)
RELATIVE
ACCURACY OF
256 DATA
POINTS (%)
RELATIVE
ACCURACY OF
SINGLE CYCLE
AT 60Hz (%)
0.5
0.11
0.05
12030
16375
117
0.04
0.23
1
0.21
0.11
6030
8375
115
0.05
0.20
2
0.42
0.22
3030
4375
113
0.06
0.17
4
0.85
0.43
1530
2375
111
0.08
0.16
8
1.69
0.87
780
1375
108
0.11
0.16
10
2.11
1.09
630
1175
107
0.13
0.16
12
2.54
1.31
530
1042
106
0.14
0.16
16
3.38
1.74
405
875
105
0.16
0.16
32
6.78
3.48
218
625
97
0.40
0.28
64
13.5
6.96
124
500
81
2.51
1.26
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Multiple Device Digital Interface
Figure 13 shows the most common way to daisy chain
the digital interface of multiple devices.
SPI bus arbitration is performed using CASCIN and
CASCOUT. A falling edge at the CASCIN input of device
n, which is driven by the CASCOUT of device n-1,
allows device n to take over the SPI bus until all expected data is written or read; at this point, device n pulls its
CASCOUT output low. Similarly, CASCOUT of device n
drives CASCIN of device n+1. Figures 12 and 14 show
read operations, including CASCIN and CASCOUT timings, for two cascaded devices and eight cascaded
devices, respectively. The operation described above
applies to all register operations except for writes to the
Data-Rate Control register. A fixed 16-bit word is written
to the Data-Rate Control registers of all devices in the
chain, independent of the number of cascaded devices
(see Figure 15). Reading from the Data-Rate Control
register returns 16 bits per cascaded device.
Connecting the open-drain OVRFLW output of all
devices together creates one signal that summarizes
the overflow information of all devices. This is also true
of the FAULT output. Connecting together these outputs from multiple devices has the effect of a “wire
NOR.” Any device that has an active condition on these
outputs is allowed to pull the line low.
SYNC
SYNC
SYNC
CS
CS
CS
SCLK
SCLK
SCLK
DIN
DIN
DIN
MAX11040K
MAX11060
DSP OR
MICROCONTROLLER
CASCIN
MAX11040K
MAX11060
CASCOUT
DRDYIN
CASCIN
DEVICE 0
CASCIN
DRDYOUT
DRDYIN
DEVICE n
DEVICE n+1
FAULT
FAULT
FAULT
OVRFLW
OVRFLW
OVRFLW
DOUT
XIN
CASCOUT
DRDYIN
MAX11040K
MAX11060
XOUT CLKOUT
DOUT
XIN
DOUT
XIN
CASCADE UP TO 8 DEVICES
Figure 13. Daisy Chaining Multiple Devices
______________________________________________________________________________________
25
MAX11040K/MAX11060
Multiple Device Connection
Daisy chain up to eight devices for applications that
require up to 32 simultaneously sampled inputs over a
single SPI-/DSP-compatible serial interface with a single
chip-select signal, and single interface commands that
apply to all devices in the chain. The eight devices effectively operate as one device.
There are two aspects to cascading multiple devices:
the digital interface and the mechanism for keeping
multiple devices sampling simultaneously.
There are many configurations for connecting multiple
devices; one is described in the next section, others
are described in the Synchronizing Multiple Devices
section within the Applications Information section.
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
There are two ways to use a single line to indicate that
all devices have their data ready, depending on
whether they are clocked synchronously. If all devices
have the same XIN clock and have been synchronized
using SYNC or reset commands, the DRDYOUT of any
device in the chain is used to represent all of them.
Alternatively, if the devices use a different XIN clock,
connect DRDYIN of device 0 to ground, and connect
DRDYIN of device n to the DRDYOUT of device n-1 for
all devices. DRDYOUT does not go low until DRDIN is
low and the conversion of the device is complete. In this
configuration, DRDYOUT of the last device goes low only
when all devices in the chain have their data ready.
tCSW
CS
DIN
SCLK
DOUT
DEVICE 0
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
DEVICE 6
DEVICE 7
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
Figure 14. Configuration Register Read Operation Timing Diagram for Eight Cascaded Devices
26
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
MAX11040K/MAX11060
CS
DIN
B15 B14 B13
X
X B10 B9
B8
B7 B6 B5 B4 B3 B2 B1 B0
SCLK
HIGH-Z
HIGH-Z
DOUT
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
X = RESERVED
Figure 15. Data Rate Controller Register Write Operation Timing Diagram for Eight Cascaded Devices
______________________________________________________________________________________
27
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
OUT with a period tS. The effect of a SYNC falling edge
as shown in Figure 16 is described in sequence below:
SYNC for Simultaneous
Sampling with Multiple Devices
The SYNC input permits multiple devices to sample
simultaneously. The mismatch between the power-up
reset of multiple devices causes the devices to begin
conversion at different times. After a falling edge on the
SYNC input, the device completes the current conversion and then synchronizes subsequent conversions
(see Figure 16).
Upon a SYNC falling edge, the devices measure the time
between the SYNC falling edge to the preceding DRDYOUT falling edge, wait until the next DRDYOUT falling
edge, then pause the ADC for the measured amount of
time. Figure 16 shows an example where the converter
is regularly sampling the input and producing a DRDY-
1) A SYNC falling edge is issued two XIN clock cycles
after the DRDYOUT event 2.
2) The converter remembers the two XIN clock cycles,
and completes the current sample, issuing DRDYOUT
event 3 a period of tS after DRDYOUT event 2.
3) Then, the converter pauses for the remembered time
period, two XIN clock cycles for this example.
4) Correspondingly, DRDYOUT event 4 is issued two
XIN cycles later than it would have without the
SYNC falling edge.
5) The process continues as normal with DRDYOUT
event 5 appearing tS after DRDYOUT event 4.
NOTE: THE LATENCY IS NOT TO SCALE.
tS
1
tS
DELAY 2
CYCLES
tS
2
tS
3
AIN_
4
tS
5
6
tS
tS
tS
tS
tS
XIN
DRDYOUT
1
2
3
4
5
SYNC
MEASURE
PAUSE
Figure 16. Effect of a SYNC Falling Edge
28
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
OUTPUT CODE
FS = +0.88 x VREFIO
ZS = 0
011..110
-FS = -0.88 x VREFIO
000...011
000...010
000...001
000...000
111...111
See the Multiple Device Synchronization section for different ways to use the SYNC input.
111...110
Transfer Function
100...001
Figures 17 shows the bipolar I/O transfer function.
Code transitions occur halfway between successiveinteger LSB values. Output coding is binary, with 1 LSB
= (0.88 x VREFIO) x 2/524,288 in 19-bit mode, (0.88 x
VREFIO) x 2/16,777,216 in 24-bit mode, and (0.88 x
VREFIO) x 2/65536 for the MAX11060.
Power-On Reset
FULL-SCALE
TRANSITION
011...111
1 LSB =
2(0.88 x VREFIO)
2N*
*N = 19 FOR 19-BIT TRANSFER
FUNCTION,
N = 24 FOR 24-BIT TRANSFER
FUNCTION
N = 16 FOR MAX11060
100...000
-FS
0
DIFFERENTIAL INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 17. ADC Transfer Function
The serial interface, logic, digital filter, and modulator
circuits reset to zero at power-up. The power-on reset
circuit releases this reset no more than 1ms after
VDVDD rises above 2V.
______________________________________________________________________________________
29
MAX11040K/MAX11060
Referring back to the analog input, since the entire sampling section of the converter also paused for two clock
cycles, the sampling point for sample 5 is also paused
by two clock cycles, possibly creating a small disturbance at the SYNC falling edge. This disturbance is filtered with the digital filter, which makes it less distinct.
If the SYNC falling edge occurred during the same XIN
clock period as the DRDYOUT signal, the disturbance
does not affect the periodic timing since the SYNC
falling edge would demand a pause of zero XIN clock
cycles. Hence, connecting the DRDYOUT of one converter to the SYNC inputs of many converters, as illustrated in Figure 13, aligns the sampling of the
converters on the first SYNC falling edge, but does not
disturb a regular sampling process for future samples.
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Applications Information
Multiple Device Synchronization
Synchronizing Multiple Devices
Using a Shared XIN Clock Source
To synchronize multiple devices sharing a single XIN
clock source, transition the SYNC input that is shared
by all devices high to low. When an external sync
source is not available, connect DRDYOUT of one
device to the SYNC input of all devices in the chain.
The devices ignore any SYNC transitions applied during the power-on reset.
Synchronizing Multiple Devices
Using Independent XIN Clock Sources
If it is undesirable to connect the XIN clock sources
together, due to EMI or other reasons; use DRDYIN,
DRDYOUT, and SYNC to align the conversion timing as
shown in Figure 18. This minimizes the effects of drift
between the clock sources by resynchronizing after
each conversion when DRDYOUT transitions low. In
this configuration, the maximum correction caused by a
SYNC edge is one XIN clock cycle.
The resulting sampling rate is determined by the sampling
frequency of the device with the slowest clock source,
plus the delay through the DRDYIN to DRDYOUT chain
between this slowest device and the end of the chain.
Synchronizing Multiple Devices
to an Independent Clock Source
To periodically synchronize multiple devices to an independent timing source, connect the timing source to
the SYNC inputs of the devices. If minimal jitter is
important in the application, program the devices to a
frequency slightly slower than the external frequency,
such that SYNC falling edges only occur a short time
after the DRDYOUT signals.
SYNC
SYNC
SYNC
CS
CS
CS
SCLK
SCLK
SCLK
DIN
DIN
DIN
MAX11040K
MAX11060
DSP OR
MICROCONTROLLER
MAX11040K
MAX11060
MAX11040K
MAX11060
CASCIN
CASCOUT
CASCIN
CASCOUT
CASCIN
DRDYIN
DRDYOUT
DRDYIN
DRDYOUT
DRDYIN
DEVICE 0
DEVICE n
DEVICE n+1
FAULT
FAULT
FAULT
OVRFLW
OVRFLW
OVRFLW
DOUT
XIN
DRDYOUT
XOUT CLKOUT
DOUT
XIN
XOUT
DOUT
XIN
XOUT
CASCADE UP TO 8 DEVICES
Figure 18. One Crystal per Device and All SYNC Inputs Driven by DRDYOUT of the Last Device in the Chain
30
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Example:
Assume f AIN_ = 60Hz, f S = 16ksps, and eight total
devices in the chain.
Device 1 has the longest tDRDYOUT_TO_SYNC delay,
therefore the worst-case SYNC error.
If device 1 has the fastest XIN clock in the chain, and
device 2 has the slowest XIN clock in the chain, and
they differ by 0.1%, device 1 completes its conversion
as much as 0.1% earlier than device 2. Hence, the
delay of device 2 is:
0.1% x (1/16kHz ) = 62.5ns
The signal then propagates down the chain at a time
delay of nominally 20ns for each device.
The total delay back to the SYNC falling edge after
going through six additional delays is:
tDELAY = 62.5ns + 6 x 20ns = 182.5ns
Maximum % Error = 2π x fIN x tDRDYOUT_TO_SYNC x
100% = 2 x π x 60Hz x 182.5ns x 100% = 0.007%
The above error is relative to the signal level, not to the
full scale of the data converter.
NOTE: THE LATENCY IS NOT TO SCALE.
tS
tS
1
tS
2
tS
3
AIN_
tDRYOUT_TO_SYNC
4
tS
5
tS
tS
6
tS
tS
DRDYOUT
1
2
3
4
SYNC
PAUSE FOR
tDRYOUT_TO_SYNC
MEASURE
tDRYOUT_TO_SYNC
1
RECONSTRUCTED
DIGITAL OUTPUT
2
3
4
DISCONTINUITY DUE TO SYNC EVENT
5
6
Figure 19. Example of Discontinuity in Reconstructed Digital Output Due to SYNC Falling Edge with a Large DRDYOUT-to-SYNC Delay
______________________________________________________________________________________
31
MAX11040K/MAX11060
Signal Distortion at SYNC Falling Edges
Each SYNC falling edge causes a disruption in the digital filter timing proportional to the delay from the previous falling edge of DRDYOUT to the falling edge of
SYNC. Any analysis of the output data that assumes a
uniform sampling period sees an error proportional to
that delay, with a maximum value determined by the
maximum derivative of the analog input. Figure 19
shows the effect of this discontinuity at output sample 5.
Assuming a 60Hz ±2.2V sine wave, the maximum possible error on any given sample caused by a SYNC
falling edge is:
VERROR_MAX = 2.2V x 2π x 60Hz x tDRDYOUT_TO_SYNC
= 0.83μV/ns x tDRDYOUT_TO_SYNC
The delay from DRDYOUT to SYNC is quantized to
within one cycle of the 24.576MHz clock. SYNC pulses
that are asynchronous to DRDYOUT may cause large
errors. To eliminate this error, use a single clock source
for all devices and avoid disrupting the output data timing with SYNC pulses while making high-precision
measurements. Alternately, minimize the delay from
DRDYOUT to SYNC to minimize the error.
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Source Impedance and
Input Sampling Network
The source impedance that drives the analog inputs
affects the sampling period.
Low-Impedance Sources
Minimize the source impedance to ensure the input
capacitor fully charges during the sampling phase.
The required source resistance is defined by the
equation below:
RSOURCE _ MAX <
=
tSAMP
⎛ 1 ⎞
K x CSAMP x In⎜
⎟
⎝ Error ⎠
120ns
⎛ 1 ⎞
1.5 x 4pF x In⎜
⎟
⎝ Error ⎠
− RINT
− 2600Ω
where K = 1.5 and RINT = 2600Ω.
For example, the required source resistance to achieve
0.1% accuracy is:
120ns
RSOURCE _ MAX <
− 2600Ω
⎛ 1 ⎞
1.5 x 4pF x ln⎜
⎟
⎝ 0.1% ⎠
=
=
120ns
− 2600Ω
1.5 x 4pF x ln(1000)
120ns
− 2600Ω = 294Ω
1.5 x 4pF x 6.91
High-Impedance Sources
If the source impedance is greater than
R SOURCE_MAX , as defined in the Low-Impedance
Sources section, place a 0.1μF bypass capacitor
between AIN_+ and AIN_- to provide transient charge.
The average switched-capacitor load with a proper
bypass capacitor and XIN clock frequency =
24.576MHz is equivalent to a 130kΩ resistor connected between AIN_+ and AIN_-. This resistance is independent of the value of the 0.1μF bypass capacitor. If
another XIN clock frequency is chosen, this resistance
is directly proportional to the XIN clock period.
Although the addition of a bypass capacitor helps charge
the devices’ 0 input capacitor, some gain error due to
resistive drop across the source resistance still remains.
Calculate this gain error using the following equation:
ΔGain =
32
RSOURCE
RSOURCE
=
RSOURCE + RLOAD
RSOURCE + 130kΩ
Analog Filtering
The analog filtering requirements in front of the devices
are considerably reduced compared to a conventional
converter with no on-chip filtering. The internal digital
filter has significant rejection of signals higher than the
Nyquist frequency of the output data rate that would
alias back into the sampled signal.
The internal digital filter does not provide rejection
close to the harmonics of the 3.072MHz modulator frequency. For example, assuming an output data rate of
16ksps if the XIN clock is set to 24.576MHz, then the
band between 3.0686MHz and 3.0750MHz is not
explicitly filtered. Since this unfiltered band is very
small compared to its actual frequency, very little
broadband noise enters through this mechanism. If
focused narrowband noise in this band is present, a
simple analog filter can create significant attenuation at
this frequency because the ratio of passband-to-stopband frequency is large.
In addition, because the device’s common-mode rejection extends out to several 100kHz, the common-mode
noise susceptibility in this frequency range is substantially reduced.
Providing additional filtering in some applications
ensures that differential noise signals outside the frequency band of interest do not saturate the analog
modulator.
The modulator saturates if the input voltage exceeds its
full scale (±2.2V). The digital filter does not prevent a
large signal in the filter stopband from saturating the
modulator. If signals outside the band of interest cause
violation of this full scale while accurate conversion of
passband signals is desired, then additional analog filtering is required to prevent saturation.
Compensating for the Rolloff of
the Digital Filter in Typical FFT Analysis
To calculate FIR_GAIN(fAIN_):
1) Decide the number of evenly spaced frequencies
between DC and the Nyquist frequency of the output
data rate at which correction factors are desired,
which is usually the same as the FFT result.
2) Create an array with a length that is 2x the number of
the desired frequencies. (Again, the result is likely to
correlate with the time domain array that is loaded
into an FFT algorithm.)
3) Fill this array with the filter coefficients provided in
the Digital Filter section. Fill the rest of the array with
zeros.
4) Take an FFT of this array. The result represents the
response of the devices’ built-in FIR filter.
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
1) Calculate the inverse (1/x) of the equation provided
in the Digital Filter section for each frequency in the
FFT.
2) Multiply the FFT of the devices’ output data by the
result of the above step.
Power Supplies
AVDD and DVDD provide power to the devices. The
AVDD powers up the analog section, while the DVDD
powers up the digital section. The power supply for
AVDD and DVDD ranges from +3.0V to +3.6V and 2.7V
to VAVDD, respectively. Bypass AVDD to AGND with a
1μF electrolytic capacitor in parallel with a 0.1μF ceramic
capacitor and bypass DVDD to DGND with a 1μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor. For improved performance, place the bypass
capacitors as close as possible to the device.
Layout, Grounding, and Bypassing
The best layout and grounding design always comes
from a thorough analysis of the complete system. This
includes the signal source’s dependence and sensitivity on ground currents, and knowledge of the various
currents that could travel through the various potential
grounding paths.
Use PCBs with separate analog and digital ground
planes. Connect the two ground planes together only at
the devices’ GND input. Isolate the digital supply from
the analog with a low-value resistor (10Ω) or ferrite
bead when the analog and digital supplies come from
the same source.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PCB
ground trace impedance of only 0.05Ω creates an error
voltage of approximately 250μV.
Ensure that digital and analog signal lines are kept separate. Do not run digital (especially the SCLK and DOUT)
lines parallel to any analog lines or under the devices.
Lay out the traces in perpendicular directions when a
digital line and an analog line cross each other.
Bypass AVDD to the analog ground plane with a 0.1μF
capacitor in parallel with a 1μF to 10μF low-ESR capacitor. Keep capacitor leads short for best supply-noise
rejection. Bypass REF+ and REF- with a 0.1μF capacitor to GND. Place all bypass capacitors as close as
possible to the device for optimum decoupling.
Crystal Layout
Follow these basic layout guidelines when placing a
crystal on a PCB with the devices to avoid coupled
noise:
1) Place the crystal as close as possible to XIN and
XOUT. Keeping the trace lengths between the crystal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae.” Keep the XIN and XOUT lines
close to each other to minimize the loop area of the
clock lines. Keeping the trace lengths short also
decreases the amount of stray capacitance.
2) Keep the crystal solder pads and trace width to XIN
and XOUT as small as possible. The larger these
bond pads and traces are, the more likely it is that
noise will couple from adjacent signals.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled from
adjacent signals.
4) Ensure that no signals on other PCB layers run
directly below the crystal or below the traces to XIN
and XOUT. The more the crystal is isolated from
other signals on the board, the less likely for noise to
couple into the crystal.
5) Place a local ground plane on the PCB layer immediately below the crystal guard ring. This helps to
isolate the crystal from noise coupling from signals
on other PCB layers.
Note: Keep the ground plane in the vicinity of the
crystal only and not on the entire board.
______________________________________________________________________________________
33
MAX11040K/MAX11060
To compensate the result of an FFT for the devices’ output data:
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Package Information
Chip Information
PROCESS: BiCMOS
34
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
38 TSSOP
U38+3
21-0081
90-0140
______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
REVISION
NUMBER
REVISION
DATE
0
2/11
Initial release of the MAX11040K
—
1
4/11
Initial release of the MAX11060
1
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX11040K/MAX11060
Revision History