NSC COP325C Single-chip 1k and 2k cmos microcontroller Datasheet

COP424C, COP425C, COP426C, COP324C, COP325C,
COP326C and COP444C, COP445C, COP344C, COP345C
Single-Chip 1k and 2k CMOS Microcontrollers
General Description
Features
The COP424C, COP425C, COP426C, COP444C and
COP445C fully static, Single-Chip CMOS Microcontrollers
are members of the COPSTM family, fabricated using double-poly, silicon gate microCMOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP424C and COP444C are 28 pin
chips. The COP425C and COP445C are 24-pin versions (4
inputs removed) and COP426C is 20-pin version with 15 I/O
lines. Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost.
These microcontrollers are appropriate choices in many demanding control environments especially those with human
interface.
The COP424C is an improved product which replaces the
COP420C.
Y
COPSTM , MicrobusTM , and MICROWIRETM are trademarks of National Semiconductor Corp.
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Lowest power dissipation (50 mW typical)
Fully static (can turn off the clock)
Power saving IDLE state and HALT mode
4 ms instruction time, plus software selectable clocks
2k x 8 ROM, 128 x 4 RAM (COP444C/COP445C)
1k x 8 ROM, 64 x 4 RAM (COP424C/COP425C/
COP426C)
23 I/O lines (COP444C and COP424C)
True vectored interrupt, plus restart
Three-level subroutine stack
Single supply operation (2.4V to 5.5V)
Programmable read/write 8-bit timer/event counter
Internal binary counter register with MICROWIRETM
serial I/O capability
General purpose and TRI-STATEÉ outputs
LSTTL/CMOS output compatible
MicrobusTM compatible
Software/hardware compatible with COP400 family
Extended temperature range devices COP324C/
COP325C/COP326C and COP344C/COP345C (b40§ C
to a 85§ C)
Military devices (b55§ C to a 125§ C) to be available
Block Diagram
* Not available on COP426C/COP326C
TL/DD/5259 – 1
FIGURE 1
C1995 National Semiconductor Corporation
TL/DD/5259
RRD-B30M105/Printed in U. S. A.
COP424C, COP425C, COP426C, COP324C, COP325C, COP326C and COP444C, COP445C,
COP344C, COP345C Single-Chip 1k and 2k CMOS Microcontrollers
April 1992
COP424C/COP425C/COP426C and COP444C/COP445C
Absolute Maximum Ratings
Supply Voltage (VCC)
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
6V
Voltage at any Pin
Total Allowable Source Current
Total Allowable Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(soldering, 10 seconds)
b 0.3V to VCC a 0.3V
25 mA
25 mA
0§ C to a 70§ C
b 65§ C to a 150§ C
300§ C
DC Electrical Characteristics 0§ CsTAs70§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Notes 4, 5)
Max
Units
2.4
5.5
0.1 VCC
V
V
120
700
3000
mA
mA
mA
40
12
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
b 30
b 330
mA
b1
a1
mA
7
pF
0.4
V
V
0.2
V
V
b 330
b 80
mA
mA
mA
mA
mA
mA
Peak to Peak
Supply Current
(Note 1)
VCC e 2.4V, tc e 64 ms
VCC e 5.0V, tc e 16 ms
VCC e 5.0V, tc e 4 ms
(tc is instruction cycle time)
HALT Mode Current
(Note 2)
VCC e 5.0V, FIN e 0 kHz
VCC e 2.4V, FIN e 0 kHz
Input Voltage Levels
RESET, CKI, D0 (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Input Pull-Up Current
Min
0.9 VCC
0.7 VCC
VCC e 4.5V, VIN e 0
Hi-Z Input Leakage
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Standard Outputs
VCC e 5.0V g 10%
IOH eb100 mA
IOL e 400 mA
IOH eb10 mA
IOL e 10 mA
Output Current Levels (except CKO)
Sink (Note 6)
Source (Standard Option)
Source (Low Current Option)
CKO Current Levels (As Clock Out)
d4
Sink
d8
d 16
d4
Source
d8
d 16
(
(
2.7
VCCb0.2
VCC e 4.5V, VOUT e VCC
VCC e 2.4V, VOUT e VCC
VCC e 4.5V, VOUT e 0V
VCC e 2.4V, VOUT e 0V
VCC e 4.5V, VOUT e 0V
VCC e 2.4V, VOUT e 0V
VCC e 4.5V, CKI e VCC, VOUT e VCC
VCC e 4.5V, CKI e 0V, VOUT e 0V
1.2
0.2
b 0.5
b 0.1
b 30
b6
0.3
0.6
1.2
b 0.3
b 0.6
b 1.2
mA
mA
mA
mA
mA
mA
Allowable Sink/Source Current per Pin
(Note 6)
5
mA
Allowable Loading on CKO (as HALT)
100
pF
0.7
1.6
mA
mA
a 2.5
mA
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
VCC e 4.5V, VIN e 0.2VCC
VCC e 4.5V, VIN e 0.7VCC
TRI-STATE or Open Drain
Leakage Current
b 2.5
2
COP324C/COP325C/COP326C and COP344C/COP345C
Absolute Maximum Ratings
Supply Voltage
Voltage at any Pin
Total Allowable Source Current
Total Allowable Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(soldering, 10 seconds)
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
6V
b 0.3V to VCC a 0.3V
25 mA
25 mA
b 40§ C to a 85§ C
b 65§ C to a 150§ C
300§ C
DC Electrical Characteristics b40§ CsTAs a 85§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Notes 4, 5)
Max
Units
3.0
5.5
0.1 VCC
V
V
180
800
3600
mA
mA
mA
60
30
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
Peak to Peak
Supply Current
(Note 1)
VCC e 3.0V, tc e 64 ms
VCC e 5.0V, tc e 16 ms
VCC e 5.0V, tc e 4 ms
(tc is instruction cycle time)
HALT Mode Current
(Note 2)
VCC e 5.0V, FIN e 0 kHz
VCC e 3.0V, FIN e 0 kHz
Input Voltage Levels
RESET, CKI, DO (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Input Pull-Up Current
Min
0.9 VCC
0.7 VCC
VCC e 4.5V, VIN e 0
Hi-Z Input Leakage
b 30
b 440
mA
b2
a2
mA
7
pF
0.4
V
V
0.2
V
V
b 440
b 200
mA
mA
mA
mA
mA
mA
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Standard Outputs
VCC e 5.0V g 10%
IOH eb100 mA
IOL e 400 mA
IOH eb10 mA
IOL e 10 mA
Output Current Levels (except CKO)
Sink (Note 6)
Source (Standard Option)
Source (Low Current Option)
CKO Current Levels (As Clock Out)
d4
Sink
d8
d 16
d4
Source
d8
d 16
(
(
2.7
VCCb0.2
VCC e 4.5V, VOUT e VCC
VCC e 3.0V, VOUT e VCC
VCC e 4.5V, VOUT e 0V
VCC e 3.0V, VOUT e 0V
VCC e 4.5V, VOUT e 0V
VCC e 3.0V, VOUT e 0V
VCC e 4.5V, CKI e VCC, VOUT e VCC
VCC e 4.5V, CKI e 0V, VOUT e 0V
1.2
0.2
b 0.5
b 0.1
b 30
b8
0.3
0.6
1.2
b 0.3
b 0.6
b 1.2
Allowable Sink/Source Current per
Pin (Note 6)
Allowable Loading on CKO (as HALT)
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
VCC e 4.5V, VIN e 0.2VCC
VCC e 4.5V, VIN e 0.7VCC
TRI-STATE or Open Drain
Leakage Current
b5
3
mA
mA
mA
mA
mA
mA
5
mA
100
pF
0.9
2.1
mA
mA
a5
mA
COP424C/COP425C/COP426C and COP444C/COP445C
AC Electrical Characteristics 0§ CsTAs70§ C unless otherwise specified.
Parameter
Conditions
Instruction Cycle Time (tc)
Operating CKI
Frequency
d 4 mode
d 8 mode
d 16 mode
d 4 mode
d 8 mode
d 16 mode
Duty Cycle (Note 4)
VCCt4.5V
4.5VlVCCt2.4V
(
(
VCCt4.5V
4.5VlVCCt2.4V
Max
Units
4
16
DC
DC
ms
ms
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
40
60
%
Rise Time (Note 4)
f1 e 4 MHz External Clock
60
ns
Fall Time (Note 4)
f1 e 4 MHz External Clock
40
ns
Instruction Cycle Time
RC Oscillator (Note 4)
R e 30k g 5%, VCC e 5V
C e 82 pF g 5% ( d 4 Mode)
5
11
ms
G Inputs
SI Input
VCCt 4.5V
All Others
VCCt 4.5V
4.5VlVCCt2.4V
tc/4 a .7
0.3
1.7
0.25
1.0
Inputs: (See Figure 3 )
tSETUP
tHOLD
f1 e 4 MHz
Min
(
Output Propagation Delay
tPD1, tPD0
tPD1, tPD0
VOUT e 1.5V, CL e 100 pF, RL e 5k
VCCt 4.5V
4.5VlVCCt2.4V
Microbus Timing
Read Operation (Figure 4 )
Chip Select Stable before RD btCSR
Chip Select Hold Time for RD btRCS
RD Pulse WidthbtRR
Data Delay from RD btRD
RD to Data Floating btDF (Note 4)
CL e 50 pF, VCC e 5V g 5%
ms
ms
ms
ms
ms
1.0
4.0
ms
ms
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
65
20
400
Write Operation (Figure 5 )
Chip Select Stable before WR btCSW
Chip Select Hold Time for WR btWCS
WR Pulse WidthbtWW
Data Set-Up Time for WR btDW
Data Hold Time for WR btWD
INTR Transition Time from WR btWI
65
20
400
320
100
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to VCC, L lines in TRI-STATE mode and
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 6: SO output sink current must be limited to keep VOL less than 0.2VCC when part is running in order to prevent entering test mode.
4
COP324C/COP325C/COP326C and COP344C/COP345C
AC Electrical Characteristics b40§ CsTAs a 85§ C unless otherwise specified.
Parameter
Conditions
Instruction Cycle Time (tc)
Operating CKI
Frequency
d 4 mode
d 8 mode
d 16 mode
d 4 mode
d 8 mode
d 16 mode
Duty Cycle (Note 4)
VCCt4.5V
4.5VlVCCt3.0V
(
(
VCCt4.5V
4.5VlVCCt3.0V
Max
Units
4
16
DC
DC
ms
ms
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
40
60
%
Rise Time (Note 4)
f1 e 4 MHz external clock
60
ns
Fall Time (Note 4)
f1 e 4 MHz external clock
40
ns
Instruction Cycle Time
RC Oscillator (Note 4)
R e 30k g 5%, VCC e 5V
C e 82 pF g 5% ( d 4 Mode)
11
ms
Inputs: (See Figure 3 )
tSETUP
tHOLD
f1 e 4 MHz
Min
G Inputs
SI Inputs
VCCt 4.5V
All Others
VCCt 4.5V
4.5VlVCCt3.0V
(
Output Propagation Delay
tPD1, tPD0
tPD1, tPD0
VOUT e 1.5V, CL e 100 pF, RL e 5k
VCCt 4.5V
4.5VlVCCt3.0V
Microbus Timing
Read Operation (Figure 4 )
Chip Select Stable before RD btCSR
Chip Select Hold Time for RD btRCS
RD Pulse WidthbtRR
Data Delay from RD btRD
RD to Data Floating btDF (Note 4)
CL e 50 pF, VCC e 5V g 5%
5
tc/4 a .7
0.3
1.7
0.25
1.0
ms
ms
ms
ms
ms
1.0
4.0
ms
ms
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
65
20
400
Write Operation (Figure 5 )
Chip Select Stable before WR btCSW
Chip Select Hold Time for WR btWCS
WR Pulse WidthbtWW
Data Set-Up Time for WR btDW
Data Hold Time for WR btWD
INTR Transition Time from WR btWI
65
20
400
320
100
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to VCC, L lines in TRI-STATE mode and
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 6: SO output sink current must be limited to keep VOL less than 0.2VCC when part is running in order to prevent entering test mode.
5
Connection Diagrams
DIP and S.O. Wide
DIP and S.O. Wide
TL/DD/5259 – 2
Top View
TL/DD/5259–16
Order Number COP325C-XXX/D, COP445C-XXX/D,
COP425C-XXX/D or COP345C-XXX/D
See NS Hermetic Package D24C
(Prototype Package Only)
Order Number COP325C-XXX/N, COP345C-XXX/N,
COP425C-XXX/N or COP445C-XXX/N
See NS Molded Package N24A
Order Number COP325C-XXX/WM, COP345C-XXX/WM,
COP425C-XXX/WM or COP445C-XXX/WM
See NS Surface Mount Package M24B
Top View
Order Number COP326C-XXX/D
or COP426C-XXX/D
See NS Hermetic Package D20A
(Prototype Package Only)
Order Number COP326C-XXX/N
or COP426C-XXX/N
See NS Molded Package N20A
Order Number COP326C-XXX/WM
or COP426C-XXX/WM
See NS Surface Mount Package M20B
Dual-In-Line Package
TL/DD/5259 – 3
Top View
Order Number COP324C-XXX/D, COPC324-XXX/WM, COP344C-XXX/D,
COP424C-XXX/D, COPC424-XXX/WM or COP444C-XXX/D
See NS Hermetic Package D28C
(Prototype Package Only)
Order Number COP324C-XXX/N, COP344C-XXX/N, COPC344-XXX/WM,
COP424C-XXX/N, COP444C-XXX/N or COPC444-XXX/WM
See NS Molded Package N28B
FIGURE 2
Pin
L7 – L0
G3 – G0
D3 – D0
IN3 – IN0
SI
SO
Description
Pin
8-bit bidirectional port with TRI-STATE
4-bit bidirectional I/O port
4-bit output port
4-bit input port (28-pin package only)
Serial input or counter input
Serial or general purpose output
SK
CKI
CKO
RESET
VCC
GND
6
Description
Logic controlled clock output
Chip oscillator input
Oscillator output, HALT I/O port or general
purpose input
Reset input
Most positive power supply
Ground
Functional Description
The internal architecture is shown in Figure 1 . Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a
logic ‘‘0’’.
For ease of reading only the COP424C/425C/COP426C/
444C/445C are referenced; however, all such references
apply equally to COP324C/325C/COP326C/344C/345C.
INTERNAL LOGIC
The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most I/O,
arithmetic, logic, and data memory access operations. It can
also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch or T counter,
to input 4 bits of L I/O ports data, to input 4-bit G, or IN
ports, and to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instructions. When the T counter overflows, an overflow flag will be
set (see SKT and IT instructions below). The T counter is
cleared on reset. A functional block diagram of the timer/
counter is illustrated in Figure 10a .
Four general-purpose inputs, IN3-IN0, are provided. IN1,
IN2 and IN3 may be selected, by a mask-programmable option as Read Strobe, Chip Select, and Write Strobe inputs,
respectively, for use in Microbus application.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
In the dual clock mode, D0 latch controls the clock selection
(see dual oscillator below).
The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port. G0 may be mask-programmed
as an output for Microbus applications.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control. With
the Microbus option selected, Q can also be loaded with the
8-bit contents of the L I/O ports upon the occurrence of a
write strobe from the host CPU.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M. As explained above, the
Microbus option allows L I/O port data to be latched into the
Q register.
PROGRAM MEMORY
Program Memory consists of ROM, 1024 bytes for the
COP424C/425C/426C and 2048 bytes for the COP444C/
445C. These bytes of ROM may be program instructions,
constants or ROM addressing data.
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequential 11-bit binary count value.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
DATA MEMORY
Data memory consists of a 512-bit RAM for the COP444C/
445C, organized as 8 data registers of 16 c 4-bit digits.
RAM addressing is implemented by a 7-bit B register whose
upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits
(Bd) select 1 of 16 4-bit digits in the selected data register.
Data memory consists of a 256-bit RAM for the COP424C/
425C/426C, organized as 4 data registers of 16 c 4-bits
digits. The B register is 6 bits long. Upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions.
The Bd register also serves as a source register for 4-bit
data sent directly to the D outputs.
7
Functional Description (Continued)
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output equals
the value of EN3. With EN0 reset, SIO is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. The SK outputs SKL ANDed with
the instruction cycle clock.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input
state.
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE I/O and COPS peripherals, or as a
binary counter (depending on the contents of the EN register). Its contents can be exchanged with A.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN register:
0. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon
TL/DD/5259 – 4
FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode)
TL/DD/5259 – 5
FIGURE 4. Microbus Read Operation Timing
TL/DD/5259 – 6
FIGURE 5. Microbus Write Operation Timing
8
Functional Description (Continued)
d. The instruction at hex address 0FF must be a NOP.
3. EN3, in conjunction with EN0, affects the SO output. With
EN0 set (binary counter option selected) SO will output
the value loaded into EN3. With EN0 reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to ‘‘0’’.
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
MICROBUS INTERFACE
The COP444C/424C has an option which allows it to be
used as a peripheral microprocessor device, inputting and
outputting data from and to a host microprocessor (mP).
IN1, IN2 and IN3 general purpose inputs become Microbus
compatible read-strobe, chip-select, and write-strobe lines,
respectively. IN1 becomes RD Ð a logic ‘‘0’’ on this input
will cause Q latch data to be enabled to the L ports for input
to the uP. IN2 becomes CS Ð a logic ‘‘0’’ on this line selects the COP444C/424C as the uP peripheral device by
enabling the operation of the RD and WR lines and allows
for the selection of one of several peripheral components.
IN3 becomes WR Ð a logic ‘‘0’’ on this line will write bus
data from the L ports to the Q latches for input to the
COP444C/424C. G0 becomes INTR a ‘‘ready’’ output, reset
by a write pulse from the uP on the WR line, providing the
‘‘handshaking’’ capability necessary for asynchronous data
transfer between the host CPU and the COP444C/424C.
This option has been designed for compatibility with National’s Microbus Ð a standard interconnect system for 8-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See Microbus National Publication.) The functioning and timing relationships between the signal lines affected by this option are as specified for the Microbus interface, and are given in the AC electrical characteristics and
shown in the timing diagrams (Figures 4 and 5 ). Connection
of the COP444C/424C to the Microbus is shown in Figure 6 .
INTERRUPT
The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
(PC a 1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to
hex address 0FF (the last word of page 3) and EN1 is
reset.
b. An interrupt will be recognized only on the following conditions:
1. EN1 has been set.
2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction
cycles wide has occurred on the IN1 input.
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and successive LBIs have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed).
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address 0FF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will enable any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
TL/DD/5259 – 7
FIGURE 6. Microbus Option Interconnect
TABLE I. Enable Register Modes Ð Bits EN0 and EN3
EN0 EN3
0
0
0
1
1
0
1
1
SIO
Shift
Register
Shift
Register
Binary
Counter
Binary
Counter
SI
SO
SK
Input to Shift
0
If SKL e 1,SK e clock
Register
If SKL e 0,SK e 0
Input to Shift Serial If SKL e 1,SK e clock
Register
out If SKL e 0,SK e 0
Input to
0
SK e SKL
Counter
Input to
1
SK e SKL
Counter
9
Functional Description (Continued)
TIMER
INITIALIZATION
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 7 must be
connected to the RESET pin (the conditions in Figure 7
must be met). The RESET pin is configured as a Schmitt
trigger input. If not used, it should be connected to VCC.
Initialization will occur whenever a logic ‘‘0’’ is applied to the
RESET input, providing it stays low for at least three instruction cycle times.
The timer can be operated as a time-base counter.
The instruction cycle frequency generated from CKI passes
through a 2-bit divide-by-4 prescaler. The output of this prescaler increments the 8-bit T counter thus providing a 10-bit
timer. The pre-scaler is cleared during execution of a CAMT
instruction and on reset.
For example, using a 4 MHz crystal with a divide-by-16 option, the instruction cycle frequency of 250 kHz increments
the 10-bit timer every 4 ms. By presetting the counter and
detecting overflow, accurate timeouts between 16 ms
(4 counts) and 4.096 ms (1024 counts) are possible. Longer
timeouts can be achieved by accumulating, under software
control, multiple overflows.
Note: If CKI clock is less than 32 kHz, the internal reset logic (option
Ý29 e 1) MUST be disabled and the external RC circuit must be used.
HALT MODE
The COP444C/445C/424C/425C/426C is a FULLY STATIC circuit; therefore, the user may stop the system oscillator
at any time to halt the chip. The chip may also be halted by
the HALT instruction or by forcing CKO high when it is
mask-programmed as an HALT I/O port. Once in the HALT
mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when
halted. All information is retained until continuing. The chip
may be awakened by one of two different methods:
TL/DD/5259–8
FIGURE 7. Power-Up Circuit
# Continue function: by forcing CKO low, if it mask-pro-
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA
(clear A register).
grammed as an HALT I/O port, the system clock is reenabled and the circuit continues to operate from the
point where it was stopped.
# Restart: by forcing the RESET pin low (see Initialization).
TL/DD/5259 – 9
Crystal or Resonator
Crystal
Value
32 kHz
455 kHz
2.096 MHz
4.0 MHz
RC Controlled Oscillator ( g 5% R, g 5% C)
Component Values
R1
220k
5k
2k
1k
R2
20M
10M
1M
1M
C1(pF)
30
80
30
30
R
C
C2(pF)
30k
60k
6–36
40
6–36
6–36
82 pF
100 pF
Note: 15k s R s 150k
50 pF s C s 150 pF
FIGURE 8. Oscillator Component Values
10
Cycle
Time
5 – 11 ms
12 – 24 ms
VCC
t 4.5V
2.4 – 4.5V
Functional Description (Continued)
c. RC Controlled Oscillator. CKI is configured as a single pin
RC controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT I/O port or a general purpose input.
d. Dual oscillator. By selecting the dual clock option, pin D0
is now a single pin oscillator input. Two configurations are
available: RC controlled Schmitt trigger oscillator or external oscillator.
The user may software select between the D0 oscillator
(in that case, the instruction cycle time equals the D0
oscillation frequency divided by 4) by setting the D0 latch
high or the CKI (CKO) oscillator by resetting D0 latch low.
Note that even in dual clock mode, the counter, if maskprogrammed as a time-base counter, is always connected to the CKI oscillator.
For example, the user may connect up to a 1 MHz RC
circuit to D0 for faster processing and a 32 kHz watch
crystal to CKI and CKO for minimum current drain and
time keeping.
Note: CTMA instruction is not allowed when chip is running
from D0 clock.
The HALT mode is the minimum power dissipation state.
Note: If the user has selected dual-clock with D0 as external
oscillator (option 30 e 2) AND the COP444C/424C is
running with the D0 clock, the HALT mode Ð either
hardware or software Ð will NOT be entered. Thus,
the user should switch to the CKI clock to HALT. Alternatively, the user may stop the D0 clock to minimize power.
CKO PIN OPTIONS
a. Two-pin oscillator Ð (Crystal). See Figure 9A .
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. The HALT mode may be
entered by program control (HALT instruction) which
forces CKO high, thus inhibiting the crystal network. The
circuit can be awakened only by forcing the RESET pin to
a logic ‘‘0’’ (restart).
b. One-pin oscillator Ð (RC or external). See Figure 9B .
If a one-pin oscillator system is chosen, two options are
available for CKO:
# CKO can be selected as the HALT I/O port. In that
case, it is an I/O flip-flop which is an indicator of the
HALT status. An external signal can over-ride this pin
to start and stop the chip. By forcing a high level to
CKO, the chip will stop as soon as CKI is high and
CKO output will stay high to keep the chip stopped if
the external driver returns to high impedance state.
By forcing a low level to CKO, the chip will continue
and CKO will stay low.
Figures 10A and 10B show the clock and timer diagrams
with and without Dual clock.
COP445C AND COP425C 24-PIN PACKAGE OPTION
If the COP444C/424C is bonded in a 24-pin package, it becomes the COP445C/425C, illustrated in Figure 2 , Connection diagrams. Note that the COP445C/425C does not contain the four general purpose IN inputs (IN3 – IN0). Use of
this option precludes, of course, use of the IN options, interrupt feature, external event counter feature, and the
Microbus option which uses IN1 – IN3. All other options are
available for the COP445C/425C.
Note: If user selects the 24-pin package, options 9, 10, 19
and 20 must be selected as a ‘‘0’’ (load to VCC on the
IN inputs). See option list.
# As another option, CKO can be a general purpose input, read into bit 2 of A (accumulator) upon execution
of an INIL instruction.
OSCILLATOR OPTIONS
There are four basic clock oscillator configurations available
as shown by Figure 8 .
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals
the crystal frequency optionally divided by 4, 8 or 16.
b. External Oscillator. The external frequency is optionally
divided by 4, 8 or 16 to give the instruction cycle time.
CKO is the HALT I/O port or a general purpose input.
Block Diagram
COP426C 20-PIN PACKAGE OPTION
If the COP425C is bonded as 20-pin device it becomes the
COP426C. Note that the COP426C contains all the
COP425C pins except D0, D1, G0, and G1.
(Continued)
TL/DD/5259 – 10
FIGURE 9A. Halt Mode Ð Two-Pin Oscillator
11
Block Diagram
(Continued)
TL/DD/5259 – 11
FIGURE 9B. Halt Mode Ð One-Pin Oscillator
TL/DD/5259 – 12
FIGURE 10A. Clock and Timer without Dual-Clock
TL/DD/5259 – 13
FIGURE 10B. Clock and Timer with Dual-Clock
12
Instruction Set
Table II is a symbol table providing internal architecture, instruction operan and operation symbols used in the instruction set table.
Table III provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruction.
TABLE II. Instruction Set Table Symbols
Symbol
Instruction Operand Symbols
Definition
d
r
4-bit operand field, 0 – 15 binary (RAM digit select)
3(2)-bit operand field, 0 – 7(3) binary
(RAM register select)
a
11-bit operand field, 0 – 2047 (1023)
y
4-bit operand field, 0 – 15 (immediate data)
RAM(x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
Internal Architecture Symbols
A
B
Br
4-bit accumulator
7-bit RAM address register (6-bit for COP424C)
Upper 3 bits of B (register address)
(2-bit for COP424C)
Bd
Lower 4 bits of B (digit address)
C
1-bit carry register
D
4-bit data output port
EN
4-bit enable register
G
4-bit general purpose I/O port
IL
two 1-bit (IN0 and IN3) latches
IN
4-bit input port
L
8-bit TRI-STATE I/O port
M
4-bit contents of RAM addressed by B
PC
11-bit ROM address program counter
Q
8-bit latch for L port
SA,SB,SC 11-bit 3-level subroutine stack
SIO
4-bit shift register and counter
SK
Logic-controlled clock output
SKL
1-bit latch for SK output
T
8-bit timer
Operational Symbols
a
b
x
Ý
e
A
Z
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
One’s complement of A
Exclusive-or
Range of values
TABLE III. COP444C/445C Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
À 0011 À 0000 À
A a C a RAM(B) x A
Carry x C
Carry
Add with Carry, Skip on
Carry
ADD
31
À 0011 À 0001 À
A a RAM(B) x A
None
Add RAM to A
ADT
xA
4A
À 0100 À 1010 À
A a 1010
None
Add Ten to A
5b
À 0101 À
AayxA
Carry
Add Immediate. Skip on
Carry (y i 0)
CASC
10
À 0001 À 0000 À
A a RAM(B) a C x A
Carry x C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
À 0000 À 0000 À
0xA
None
Clear A
COMP
40
À 0100 À 0000 À
AxA
None
Ones complement of A to A
AISC
y
y
À
NOP
44
À 0100 À 0100 À
None
None
No Operation
RC
32
À 0011 À 0010 À
‘‘0’’ x C
None
Reset C
SC
22
À 0010 À 0010 À
‘‘1’’ x C
None
Set C
XOR
02
À 0000 À 0010 À
A Z RAM(B) x A
None
Exclusive-OR RAM with A
13
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
Description
TRANSFER CONTROL INSTRUCTIONS
JID
FF
À 1111 À 1111 À
ROM (PC10:8 A,M) x PC7:0
None
Jump Indirect (Notes 1, 3)
JMP
a
6b
bb
À 0110 À 0 À a10:8 À
À a7:0 À
a x PC
None
Jump
JP
a
bb
À 1 À a6:0 À
(pages 2,3 only)
or
À 11 À a5:0 À
(all other pages)
a x PC6:0
None
Jump within Page (Note 4)
bb
a x PC5:0
JSRP
a
bb
À 10 À a5:0 À
PC a 1 x SA x SB x SC
00010 x PC10:6
a x PC5:0
None
Jump to Subroutine Page
(Note 5)
JSR
a
6b
bb
À 0110 À 1 À a10:8 À
À a7:0 À
PC a 1 x SA x SB x SC
a x PC
None
Jump to Subroutine
RET
48
À 0100 À 1000 À
SC x SB x SA x PC
None
Return from Subroutine
RETSK
49
À 0100 À 1001 À
SC x SB x SA x PC
Always Skip
on Return
Return from Subroutine
then Skip
HALT
33
38
33
39
À 0011 À 0011 À
À 0011 À 1000 À
À 0011 À 0011 À
À 0011 À 1001 À
None
HALT Processor
None
IDLE till Timer
Overflows then Continues
IT
MEMORY REFERENCE INSTRUCTIONS
CAMT
33
3F
À 0011 À 0011 À
À 0011 À 1111 À
A x T7:4
RAM(B) x T3:0
None
Copy A, RAM to T
CTMA
33
2F
À 0011 À 0011 À
À 0010 À 1111 À
T7:4 x RAM(B)
T3:0 x A
None
Copy T to RAM, A (Note 9)
CAMQ
33
3C
À 0011 À 0011 À
À 0011 À 1100 À
A x Q7:4
RAM(B) x Q3:0
None
Copy A, RAM to Q
CQMA
33
2C
À 0011 À 0011 À
À 0010 À 1100 À
Q7:4 x RAM(B)
Q3:0 x A
None
Copy Q to RAM, A
b5
À 00 À r À 0101 À
(r e 0:3)
RAM(B) x A
Br Z r x Br
None
Load RAM into A,
Exclusive-OR Br with r
23
À 0010 À 0011 À
À0 À r À d À
RAM(r,d) x A
None
bb
Load A with RAM pointed
to directly by r,d
BF
À 1011 À 1111 À
ROM(PC10:8,A,M) x Q
SB x SC
None
Load Q Indirect (Note 3)
LD
LDD
r
r,d
LQID
RMB
0
1
2
3
4C
45
42
43
À 0100 À 1100 À
À 0100 À 0101 À
À 0100 À 0010 À
À 0100 À 0011 À
0 x RAM(B)0
0 x RAM(B)1
0 x RAM(B)2
0 x RAM(B)3
None
Reset RAM Bit
SMB
0
1
2
3
4D
47
46
4B
À 0100 À 1101 À
À 0100 À 0111 À
À 0100 À 0110 À
À 0100 À 1011 À
1 x RAM(B)0
1 x RAM(B)1
1 x RAM(B)2
1 x RAM(B)3
None
Set RAM Bit
14
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
Description
MEMORY REFERENCE INSTRUCTIONS (Continued)
y x RAM(B)
Bd a 1 x Bd
None
Store Memory Immediate
1 and Increment Bd
À 00 À r À 0110 À
(r e 0:3)
RAM(B) Ý A
Br Z r x Br
None
Exchange RAM with A,
Exclusive-OR Br with r
À 0010 À 0011 À
À1À r À d À
RAM(r,d) Ý A
None
Exchange A with RAM
Pointed to Directly by r,d
STII
y
7b
À 0111 À
X
r
b6
23
XAD
r,d
bb
y
À
XDS
r
b7
À 00 À r À 0111 À
(r e 0:3)
RAM(B) Ý A
Bdb1 x Bd
Br Z r x Br
Bd
decrements
past 0
Exchange RAM with A
and Decrement Bd.
Exclusive-OR Br with r
XIS
r
b4
À 00 À r À 0100 À
(r e 0:3)
RAM(B) Ý A
Bd a 1 x Bd
Br Z r x Br
Bd
increments
past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
REGISTER REFERENCE INSTRUCTIONS
CAB
50
À 0101 À 0000 À
A x Bd
None
Copy A to Bd
CBA
4E
À 0100 À 1110 À
Bd x A
None
Copy Bd to A
bb
À 00 À r À (d – 1) À
(r e 0:3:
d e 0,9:15)
or
À 0011 À 0011 À
À1À r À d À
(any r, any d)
r,d x B
Skip until
not a LBI
Load B Immediate with r,d
(Note 6)
33
6b
À 0011 À 0011 À
À 0110 À y À
y x EN
None
Load EN Immediate (Note 7)
12
À 0001 À 0010 À
A Ý Br
None
Exchange A with Br (Note 8)
SKC
20
À 0010 À 0000 À
C e ‘‘1’’
Skip if C is True
SKE
21
À 0010 À 0001 À
A e RAM(B)
Skip if A Equals RAM
33
21
À 0011 À 0011 À
À 0010 À 0001 À
G3:0 e 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
À 0011 À 0011 À
À 0000 À 0001 À
À 0001 À 0001 À
À 0000 À 0011 À
À 0001 À 0011 À
0
1
2
3
01
11
03
13
À 0000 À 0001 À
À 0001 À 0001 À
À 0000 À 0011 À
À 0001 À 0011 À
RAM(B)0 e 0
RAM(B)1 e 0
RAM(B)2 e 0
RAM(B)3 e 0
Skip if RAM Bit is Zero
41
À 0100 À 0001 À
A time-base
counter carry
has occurred
since last test
Skip on Timer
(Note 3)
LBI
r,d
33
bb
LEI
y
XABR
TEST INSTRUCTIONS
SKGZ
SKGBZ
SKMBZ
SKT
1st byte
*
2nd byte
15
Skip if G Bit is Zero
G0 e 0
G1 e 0
G2 e 0
G3 e 0
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
Description
INPUT/OUTPUT INSTRUCTIONS
ING
33
2A
À 0011 À 0011 À
À 0010 À 1010 À
GxA
None
Input G Ports to A
ININ
33
28
À 0011 À 0011 À
À 0010 À 1000 À
IN x A
None
Input IN Inputs to A
(Note 2)
INIL
33
29
À 0011 À 0011 À
À 0010 À 1001 À
IL3, CKO,‘‘0’’, IL0 x A
None
Input IL Latches to A
(Note 3)
INL
33
2E
À 0011 À 0011 À
À 0010 À 1110 À
L7:4 x RAM(B)
L3:0 x A
None
Input L Ports to RAM,A
OBD
33
3E
À 0011 À 0011 À
À 0011 À 1110 À
Bd x D
None
Output Bd to D Outputs
33
5b
À 0011 À 0011 À
À 0101 À y À
yxG
None
Output to G Ports
Immediate
OMG
33
3A
À 0011 À 0011 À
À 0011 À 1010 À
RAM(B) x G
None
Output RAM to G Ports
XAS
4F
À 0100 À 1111 À
A Ý SIO, C x SKL
None
Exchange A with SIO
(Note 3)
OGI
y
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBI is a single-byte instruction if d e 0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data minus 1 ,
e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112).
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: For 2K ROM devices, A
Ý Br (0 x A3). For 1K ROM devices, A Ý Br (0,0 x A3, A2).
Note 9: Do not use CTMA instruction when dual-clock option is selected and part is running from D0 clocks.
16
Description of Selected Instructions
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and IN0 lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a ‘‘1’’ will be placed in A2. A0 is input into A1.
IL latches are cleared on reset. IL latches are not available
on the COP445C/425C, and COP426C.
XAS INSTRUCTION
XAS (Exchange A with SIO) copies C to the SKL latch and
exchanges the accumulator with the 4-bit contents of the
SIO register. The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the
value of the EN register. If SIO is selected as a shift register,
an XAS instruction can be performed once every 4 instruction cycles to effect a continuous data stream.
INSTRUCTION SET NOTES
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, they are
still fetched from the program memory. Thus program
paths take the same number of cycles whether instructions are skipped or executed except for JID, and LQID.
c. The ROM is organized into pages of 64 words each. The
Program Counter is a 11-bit binary counter, and will count
through page boundaries. If a JP, JSRP, JID, or LQID is
the last word of a page, it operates as if it were in the next
page. For example: a JP located in the last word of a
page will jump to a location in the next page. Also, a JID
or LQID located in the last word of every fourth page (i.e.
hex address 0FF, 1FF, 2FF, 3FF, 4FF, etc.) will access
data in the next group of four pages.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 11-bit word
PC10:PC8,A,M. LQID can be used for table lookup or code
conversion such as BCD to seven-segment. The LQID instruction ‘‘pushes’’ the stack (PC a 1 x SA x SB x SC)
and replaces the least significant 8 bits of the PC as follows:
A x PC(7:4), RAM(B) x PC(3:0), leaving PC(10), PC(9)
and PC(8) unchanged. The ROM data pointed to by the new
address is fetched and loaded into the Q latches. Next, the
stack is ‘‘popped’’ (SC x SB x SA x PC), restoring the
saved value of PC to continue sequential program execution. Since LQID pushes SB x SC, the previous contents
of SC are lost.
Note: LQID uses 2 instruction cycles if executed, one if skipped.
Note: The COP424C/425C/426C needs only 10 bits to address its ROM.
Therefore, the eleventh bit (P10) is ignored.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not
affected by JID.
Power Dissipation
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, the user should run
at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full
supply levels to insure that outputs are not loaded down and
that inputs are not at some intermediate level which may
draw current. Any input with a slow rise or fall time will draw
additional current. A crystal or resonator generated clock
input will draw additional current. An R/C oscillator will draw
even more current since the input is a slow rising signal.
If using an external squarewave oscillator, the following
equation can be used to calculate operating current drain.
Note: JID uses 2 instruction cycles if executed, one if skipped.
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of the T
counter overflow latch (see internal logic, above), executing
the next program instruction if the latch is not set. If the
latch has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features
associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than
relying on an external input signal.
Note: If the most significant bit of the T counter is a 1 when a CAMT instruction loads the counter, the overflow flag will be set. The following
sample of codes should be used when loading the counter:
ICO e IQ a V c 40 c Fi a V c 1400 c Fi/Dv
where ICO e chip operating current drain in microamps
quiescent leakage current (from curve)
CKI frequency in MegaHertz
chip VCC in volts
divide by option selected
CAMT ; load T counter
SKT
; skip if overflow flag is set and reset it
NOP
IT INSTRUCTION
The IT (idle till timer) instruction halts the processor and
puts it in an idle state until the time-base counter overflows.
This idle state reduces current drain since all logic (except
the oscillator and time base counter) is stopped.
For example at 5 volts VCC and 400 kHz (divide by 4)
ICO e 20 a 5 c 40 c 0.4 a 5 c 1400 c 0.4/4
ICO e 20 a 80 a 700 e 800 mA
At 2.4 volts VCC and 30 kHz (divide by 4)
ICO e 6 a 2.4 c 40 c 0.03 a 2.4 c 1400 c 0.03/4
ICO e 6 a 2.88 a 25.2 e 34.08 mA
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0,
CKO and 0 into A. The IL3 and IL0 latches are set if a lowgoing pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0
inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction cycles. Execution
of an INIL inputs IL3 and IL0 into A3 and A0 respectively,
17
Power Dissipation (Continued)
c. Open Drain Ð An N-channel device to ground only, allowing external pull-up as required by the user’s application.
If an IT instruction is executed, the chip goes into the IDLE
mode until the timer overflows. In IDLE mode, the current
drain can be calculated from the following equation:
d. Standard TRI-STATE L Output Ð A CMOS output buffer
similar to a. which may be disabled by program control.
e. Low-Current TRI-STATE L Output Ð This is the same as
d. above except that the sourcing current is much less.
f. Open-Drain TRI-STATE L Output Ð This has the N-channel device to ground only.
Ici e IQ a V c 40 c Fi
For example, at 5 volts VCC and 400 kHz
Ici e 20 a 5 c 40 c 0.4 e 100 mA
The total average current will then be the weighted average
of the operating current and the idle current:
Ita e ICO c
where:
All inputs have the following options:
g. Input with on chip load device to VCC.
h. Hi-Z input which must be driven by the users logic.
To
Ti
a Ici c
To a Ti
To a Ti
When using either the G or L I/O ports as inputs, a pull-up
device is necessary. This can be an external device or the
following alternative is available: Select the low-current output option. Now, by setting the output registers to a logic
‘‘1’’ level, the P-channel devices will act as the pull-up load.
Note that when using the L ports in this fashion the Q registers must be set to a logic ‘‘1’’ level and the L drivers MUST
BE ENABLED by an LEI instruction (see description above).
All output drivers use one or more of three common devices
numbered 1 to 3. Minimum and maximum current (IOUT and
VOUT) curves are given in Figure 12 for each of these devices to allow the designer to effectively use these I/O configurations.
Ita e total average current
ICO e operating current
Ici e idle current
To e operating time
Ti e idle time
I/O OPTIONS
Outputs have the following optional configurations, illustrated in Figure 11 :
a. Standard Ð A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to VCC, compatible with CMOS and LSTTL.
b. Low Current Ð This is the same configuration as a.
above except that the sourcing current is much less.
a. Standard Push-Pull Output
b. Low Current Push-Pull Output
d. Standard TRI-STATE ‘‘L’’ Output
c. Open-Drain Output
e. Low Current TRI-STATE
‘‘L’’ Output
f. Open Drain TRI-STATE
‘‘L’’ Output
TL/DD/5259 – 14
h. Hi-Z Input
g. Input with Load
FIGURE 11. Input/Output Configurations
18
Power Dissipation (Continued)
Minimum Sink Current
Standard
Minimum Source Current
Low Current Option
Minimum Source Current
COP444C/424C/445C/425C
Low Current Option
Maximum Source Current
COP344C/345C/324C/325C
Low Current Option
Maximum Source Current
Maximum Quiescent Current
TL/DD/5259 – 15
FIGURE 12. Input/Output Characteristics
Option List
Option 4: RESET input
e 0: load device to VCC
e 1: Hi-Z input
Option 5: L7 Driver
The COP444C/445C/424C/425C/COP426C mask-programmable options are assigned numbers which correspond with the COP444C/424C pins.
The following is a list of options. The options are programmed at the same time as the ROM pattern to provide
the user with the hardware flexibility to interface to various
I/O components using little or no external circuitry.
PLEASE FILL OUT THE OPTION TABLE on the next page.
Xerox the option data and send it in with your disk or
EPROM.
Option 1 e 0: Ground Pin Ð no options available
Option
e 0:
e 1:
e 2:
e 3:
Option
e 0:
e 1:
e 2:
e 4:
e 5:
e 6:
e 7:
e 0: Standard TRI-STATE push-pull output
e 1: Low-current TRI-STATE push-pull output
e 2:
Option
Option
Option
Option
e 0:
e 1:
Option
Option
2: CKO Pin
clock generator output to crystal/resonator
HALT I/O port
general purpose input with load device to VCC
general purpose input, high-Z
3: CKI input
Crystal controlled oscillator input divide by 4
Crystal controlled oscillator input divide by 8
Crystal controlled oscillator input divide by 16
Single-pin RC controlled oscillator (divide by 4)
External oscillator input divide by 4
External oscillator input divide by 8
External oscillator input divide by 16
Option
Option
Option
Option
Option
Option
e 0:
e 1:
e 2:
19
Open-drain TRI-STATE output
6: L6 Driver Ð (same as option 5)
7: L5 Driver Ð (same as option 5)
8: L4 Driver Ð (same as option 5)
9: IN1 input
load device to VCC
Hi-Z input
10: IN2 input Ð (same as option 9)
11 e 0: VCC Pin Ð no option available
12: L3 Driver Ð (same as option 5)
13: L2 Driver Ð (same as option 5)
14: L1 Driver Ð (same as option 5)
15: L0 Driver Ð (same as option 5)
16: SI input Ð (same as option 9)
17: SO Driver
Standard push-pull output
Low-current push-pull output
Open-drain output
Option List (Continued)
Option 32: Microbus
Option 18: SK Driver Ð (same as option 17)
e 0: Normal
e 1: Microbus (opt. Ý31 must e 0)
Option 19: IN0 Input Ð (same as option 9)
Option 20: IN3 Input Ð (same as option 9)
Option 21: G0 I/O Port Ð (same as option 17)
Option 22: G1 I/O Port Ð (same as option 17)
Option 23: G2 I/O Port Ð (same as option 17)
Option 24: G3 I/O Port Ð (same as option 17)
Option 25: D3 Output Ð (same as option 17)
Option 26: D2 Output Ð (same as option 17)
Option 27: D1 Output Ð (same as option 17)
Option 28: D0 Output Ð (same as option 17)
Option 29: Internal Initialization Logic
e 0: Normal operation
e 1: No internal initialization logic
Option 30: Dual Clock
e 0: Normal operation
e 1: Dual Clock. D0 RC oscillator
(opt. Ý28 must e 2)
e 2: Dual Clock. D0 ext. clock input
Option 33: COP bonding
(1k and 2K Microcontroller)
e 0: 28-pin package
e 1: 24-pin package
e 2: Same die purchased in both
24 and 28 pin version.
(1K Microcontroller only)
e 3: 20-pin package
e 4: 28- and 20-pin package
e 5: 24- and 20-pin package
e 6: 28-, 24- and 20-pin package
Note:Ðif opt. Ý33 e 1 or 2 then opt.Ý9, 10, 19, 20 and 32
must e 0Ðif opt. Ý33 e 3, 4, 5 or 6 then opt. Ý9, 10, 19,
20, 21, 22, 30 and 32 must e 0.
(
Option 31: Timer
e 0: No Option Available
Option Table
The following option information is to be sent to National along with the EPROM.
OPTION DATA
OPTION DATA
IS: GROUND PIN
OPTION 17 VALUE e
IS: SO DRIVER
2 VALUE e
IS: CKO PIN
OPTION 18 VALUE e
IS: SK DRIVER
OPTION
3 VALUE e
IS: CKI INPUT
OPTION 19 VALUE e
IS: IN0 INPUT
OPTION
4 VALUE e
IS: RESET INPUT
OPTION 20 VALUE e
IS: IN3 INPUT
OPTION
5 VALUE e
IS: L(7) DRIVER
OPTION 21 VALUE e
IS: G0 I/O PORT
OPTION
6 VALUE e
IS: L(6) DRIVER
OPTION 22 VALUE e
IS: G1 I/O PORT
OPTION
7 VALUE e
IS: L(5) DRIVER
OPTION 23 VALUE e
IS: G2 I/O PORT
OPTION
8 VALUE e
IS: L(4) DRIVER
OPTION 24 VALUE e
IS: G3 I/O PORT
OPTION
9 VALUE e
IS: IN1 INPUT
OPTION 25 VALUE e
IS: D3 OUTPUT
OPTION 10 VALUE e
IS: IN2 INPUT
OPTION 26 VALUE e
IS: D2 OUTPUT
OPTION 11 VALUE e
IS: VCC PIN
OPTION 27 VALUE e
IS: D1 OUTPUT
OPTION 12 VALUE e
IS: L(3) DRIVER
OPTION 28 VALUE e
IS: D0 OUTPUT
OPTION 13 VALUE e
IS: L(2) DRIVER
OPTION 29 VALUE e
IS: INT INIT LOGIC
OPTION 14 VALUE e
IS: L(1) DRIVER
OPTION 30 VALUE e
IS: DUAL CLOCK
OPTION 15 VALUE e
IS: L(0) DRIVER
OPTION 31 VALUE e
OPTION 16 VALUE e
IS: SI INPUT
OPTION 32 VALUE e
IS: MICROBUS
OPTION 33 VALUE e
IS: COP BONDING
OPTION
1 VALUE e
OPTION
0
20
0
IS: TIMER
21
Physical Dimensions inches (millimeters)
20-Lead Hermetic Dual-In-Line Package (D)
Order Number COP326C-XXX/D, COP426C-XXX/D
NS Package Number D20A
24-Lead Hermetic Dual-In-Line Package (D)
Order Number COP425C-XXX/D, COP325C-XXX/D,
COP445C-XXX/D, COP345C-XXX/D
NS Package Number D24C
22
Physical Dimensions inches (millimeters) (Continued)
28-Lead Hermetic Dual-In-Line Package (D)
Order Number COP424C-XXX/D, COP324C-XXX/D,
COP444C-XXX/D, COP344C-XXX/D
NS Package Number D28C
20-Lead Molded Dual-In-Line Package (N)
Order Number COP426C-XXX/N and COP326C-XXX/N
NS Package Number N20A
23
COP424C, COP425C, COP426C, COP324C, COP325C, COP326C and COP444C, COP445C,
COP344C, COP345C Single-Chip 1k and 2k CMOS Microcontrollers
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Dual-In-Line Package (N)
Order Number COP425C-XXX/N, COP325C-XXX/N,
COP445C-XXX/N, COP345C-XXX/N
NS Package Number N24A
28-Lead Molded Dual-In-Line Package (N)
Order Number COP424C-XXX/N, COP324C-XXX/N,
COP444C-XXX/N, COP344C-XXX/N
NS Package Number N28B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.