Multiformat SDTV Video Decoder
ADV7189B
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, Noise Shaped Video®, 12-bit ADCs
Clocked from a single 28 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive-Digital-Line-Length-Tracking (ADLLT™), signal
processing, and enhanced FIFO management gives miniTBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
12 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit/10-bit/16-bit/20-bit)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.4% typ
Differential phase: 0.4° typ
Programmable video controls
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for close captioning, WSS, CGMS, EDTV,
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
2 temperature grades: 0°C to +70°C and –40°C to +85°C
80-lead LQFP Pb-free package
APPLICATIONS
High-end DVD recorders
Video projectors
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Professional video products
AVR receivers
GENERAL DESCRIPTION
The ADV7189B integrated video decoder automatically detects
and converts a standard analog baseband television signal, compatible with worldwide standards NTSC, PAL, and SECAM into
4:2:2 component video data-compatible with 20-, 16-, 10-, and
8-bit CCIR601/CCIR656.
The 12 analog input channels accept standard composite,
S-Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an
input video signal peak-to-peak range of 0.5 V to 1.6 V.
Alternatively, these can be bypassed for manual settings.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in linelocked, clock-based systems. This makes the device ideally
suited for a broad range of applications with diverse analog
video characteristics, including tape-based sources, broadcast
sources, security/surveillance cameras, and professional
systems.
The fixed 54 MHz clocking of the ADCs and datapath for
all modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length variation.
The output control signals allow glueless interface connections
in almost any application. The ADV7189B modes are set up
over a 2-wire, serial, bidirectional port (I2C-compatible).
The 12-bit accurate A/D conversion provides professional
quality video performance and is unmatched. This allows
true 10-bit resolution in the 10-bit output mode.
The ADV7189B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7189B is packaged in a
small, 80-lead LQFP Pb-free package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADV7189B
TABLE OF CONTENTS
Introduction ...................................................................................... 4
General Setup.............................................................................. 21
Analog Front End ......................................................................... 4
SD Color Controls...................................................................... 23
Standard Definition Processor ................................................... 4
Clamp Operation........................................................................ 25
Functional Block Diagram .............................................................. 5
Luma Filter .................................................................................. 26
Specifications..................................................................................... 6
Chroma Filter.............................................................................. 29
Electrical Characteristics............................................................. 6
Gain Operation........................................................................... 30
Video Specifications..................................................................... 7
Chroma Transient Improvement (CTI) .................................. 34
Timing Specifications .................................................................. 8
Digital Noise Reduction (DNR) ............................................... 34
Analog Specifications................................................................... 8
Comb Filters................................................................................ 35
Thermal Specifications ................................................................ 9
AV Code Insertion and Controls ............................................. 38
Timing Diagrams.......................................................................... 9
Synchronization Output Signals............................................... 40
Absolute Maximum Ratings.......................................................... 10
Sync Processing .......................................................................... 48
ESD Caution................................................................................ 10
VBI Data Decode ....................................................................... 48
Pin Configuration and Function Descriptions........................... 11
Pixel Port Configuration ............................................................... 60
Analog Front End ........................................................................... 13
MPU Port Description................................................................... 61
Analog Input Muxing ................................................................ 13
Register Accesses ........................................................................ 62
Global Control Registers ............................................................... 16
Register Programming............................................................... 62
Power-Save Modes...................................................................... 16
I2C Sequencer.............................................................................. 62
Reset Control .............................................................................. 16
I2C Register Maps ........................................................................... 63
Global Pin Control ..................................................................... 17
I2PC Register Map Details ........................................................... 67
16H
I2C Interrupt Register Map ....................................................... 68
Global Status Registers................................................................... 19
51H
17H
I2C Programming Examples.......................................................... 90
Identification............................................................................... 19
52H
18H
Status 1 ......................................................................................... 19
Examples Using 28 MHz Clock................................................ 90
53H
SD Autodetection Result ........................................................... 19
19H
Status 2 ......................................................................................... 19
Examples Using 27 MHz Clock................................................ 94
54H
120H
PCB Layout Recommendations.................................................... 97
5H
Status 3 ......................................................................................... 19
12H
Analog Interface Inputs ............................................................. 97
12H
Standard Definition Processor (SDP).......................................... 20
56H
Power Supply Decoupling ......................................................... 97
123H
SD Luma Path ............................................................................. 20
57H
PLL ............................................................................................... 97
124H
SD Chroma Path......................................................................... 20
58H
Digital Outputs (Both Data and Clocks) ................................ 97
125H
Sync Processing........................................................................... 21
59H
VBI Data Recovery..................................................................... 21
Digital Inputs .............................................................................. 98
60H
126H
Antialiasing Filters ..................................................................... 98
61H
Rev. B | Page 2 of 104
127H
ADV7189B
Crystal Load Capacitor Value Selection...................................98
62H
128H
Typical Circuit Connection ...........................................................99
63H
129H
Outline Dimensions......................................................................101
64H
130H
Ordering Guide .........................................................................101
65H
13H
REVISION HISTORY
9/05—Rev. A to Rev. B
Changes to Table 1 ............................................................................6
Changes to Table 2 ............................................................................7
Changes to Table 3 and Table 4 .......................................................8
Changes to Table 5 ............................................................................9
Changes to Figure 6.........................................................................13
Changes to Table 8 ..........................................................................14
Update Table Formatting................................................................19
Update Page Layout ........................................................................29
Change to Table 34..........................................................................31
Update Table Formatting................................................................39
Change to Table 55..........................................................................40
Changes to Figure 21 ......................................................................42
Update Page Formatting.................................................................49
Change Footnote Numbering in Table 84....................................67
Change to Table 85..........................................................................68
Change to Table 87..........................................................................90
Change to Table 88..........................................................................91
Change to Table Numbering..........................................................94
7/05—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changes to Features ..........................................................................1
Changes to Analog Specifications...................................................6
Changes to Table 7 ..........................................................................11
Changes to Clamp Operation Section..........................................26
Changes to Table 30 ........................................................................29
Changes to Figure 12, Figure 13, Figure 14, and Figure 15 .......30
Added CSFM[2:0] C-Shaping Filter Mode, Address 0x17[7]
Section and Changes to Figure 16.................................................31
Changes to Luma Gain Section.....................................................32
Changes to Table 54 ........................................................................41
Changes to VSEHO VS End Horizontal Position Odd,
Address 0x33[7] Section.................................................................42
Changes to Table 55 ........................................................................44
Changes to Table 84 ........................................................................69
Changes to Table 85 .......................................................................73
Changes to Table 86 ........................................................................91
Changes to Table 87 ........................................................................92
Changes to Table 88 ........................................................................93
Changes to Table 89 ........................................................................94
Added XTAL Load Capacitor Value Section...............................99
Inserted Figure 44; Renumbered Sequentially ............................99
Changes to Figure 46 ....................................................................101
Updated Outline Dimensions......................................................102
Changes to Ordering Guide.........................................................102
9/04—Revision 0: Initial Version
Rev. B | Page 3 of 104
ADV7189B
INTRODUCTION
The ADV7189B is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface enables
performance video decoding and conversion in line-locked,
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources,
security/ surveillance cameras, and professional systems.
ANALOG FRONT END
The ADV7189B analog front end comprises three 12-bit noise
shaped video ADCs that digitize the analog video signal before
applying it to the standard definition processor. The analog front
end employs differential channels to each ADC to ensure high
performance in mixed-signal applications.
The front end also includes a 12-channel input mux that
enables multiple video signals to be applied to the ADV7189B.
Current and voltage clamps are positioned in front of each
ADC to ensure the video signal remains within the range of
the converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7189B.
The ADCs are configured to run in 4× oversampling mode.
STANDARD DEFINITION PROCESSOR
The ADV7189B is capable of decoding a large selection of baseband video signals in composite, S-Video, and component
formats. The video standards supported by the ADV7189B
include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc,
NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7189B
can automatically detect the video standard and process it
accordingly. The ADV7189B has a 5-line, super-adaptive, 2D
comb filter that gives superior chrominance and luminance
separation when decoding a composite video signal. This highly
adaptive filter automatically adjusts its processing mode
according to video standard and signal quality with no user
intervention required. Video user controls such as brightness,
contrast, saturation, and hue are also available within the
ADV7189B.
The ADV7189B implements a patented adaptive-digital-linelength-tracking (ADLLT) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7189B to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The ADV7189B contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The ADV7189B can process a variety of VBI data services,
such as closed captioning (CC), wide screen signaling (WSS),
copy generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7189B
is fully Macrovision certified; detection circuitry enables
Type I, Type II, and Type III protection levels to be identified
and reported to the user. The decoder is also fully robust to all
Macrovision signal inputs.
Rev. B | Page 4 of 104
04983-0-001
12
INPUT
MUX
SCLK
SDA
ALSB
CVBS
S-VIDEO
YPrPb
AIN1–AIN12
A/D
CLAMP
12
12
12
SERIAL INTERFACE
CONTROL AND VBI DATA
SYNC PROCESSING AND
CLOCK GENERATION
A/D
A/D
CLAMP
CLAMP
Figure 1.
Rev. B | Page 5 of 104
CONTROL
AND DATA
ADV7189B
SYNC AND
CLK CONTROL
DECIMATION AND
DOWNSAMPLING
FILTERS
DATA
PREPROCESSOR
12
12
CHROMA
DIGITAL
FINE
CLAMP
STANDARD
AUTODETECTION
MACROVISION
DETECTION
GAIN
CONTROL
LINE
LENGTH
PREDICTOR
GAIN
CONTROL
GLOBAL CONTROL
CHROMA
FILTER
SYNC
EXTRACT
LUMA
FILTER
VBI DATA RECOVERY
CHROMA
DEMOD
FSC
RECOVERY
LUMA
DIGITAL
FINE
CLAMP
STANDARD DEFINITION PROCESSOR
CHROMA
2D COMB
(4H MAX)
CTI
C-DNR
AV
CODE
INSERTION
L-DNR
LUMA
2D COMB
(4H MAX)
FREE RUN
OUTPUT CONTROL
SYNTHESIZED
LLC CONTROL
CHROMA
RESAMPLE
RESAMPLE
CONTROL
LUMA
RESAMPLE
20
10
10
INTRQ
SFL
LLC2
LLC1
FIELD
VS
HS
PIXEL
DATA
ADV7189B
FUNCTIONAL BLOCK DIAGRAM
OUTPUT FORMATTER
ADV7189B
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range,
unless otherwise specified.
Table 1.
Parameter 1, 2
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current 3
0F
1F
Symbol
Test Conditions
N
INL
DNL
BSL at 54 MHz
BSL at 54 MHz
VIH
VIL
IIN
2F
3F
Typ
Max
Unit
–1.5/+2.5
–0.7/+0.7
12
±8
–0.95/+2
Bits
LSB
LSB
0.8
+50
+10
10
V
V
μA
μA
pF
0.4
50
10
20
V
V
μA
μA
pF
2
All other pins
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current 4
Min
–50
–10
CIN
VOH
VOL
ILEAK
ISOURCE = 0.4 mA
ISINK = 3.2 mA
2.4
All other pins
Output Capacitance
POWER REQUIREMENTS 5
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
COUT
4F
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
1.65
3.0
1.65
3.15
CVBS input 6
YPrPb input 7
5F
6F
Power-Down Current
Power-Up Time
IPWRDN
tPWRUP
1
Temperature range: TMIN to TMAX, –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ)
The min/max specifications are guaranteed over this range.
3
Pin 36 and Pin 79.
4
Pin 1, Pin 2, Pin 5 to Pin 8, Pin 12, Pin 17 to Pin 24, Pin 32 to Pin 35, Pin 73 to Pin 76, and Pin 80.
5
Guaranteed by characterization.
6
ADC1 powered on.
7
All three ADCs powered on.
2
Rev. B | Page 6 of 104
1.8
3.3
1.8
3.3
82
2
10.5
85
180
1.5
20
2
3.6
2.0
3.45
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
ADV7189B
VIDEO SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V;
operating temperature range, unless otherwise specified.
Table 2.
Parameter 1, 2
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
0F
1F
Analog Front End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
FSC Subcarrier Lock Range
Color Lock In Time
Sync Depth Range
Color Burst Range
Vertical Lock Time
Autodetection Switch Speed
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
1
2
Symbol
Test Conditions
DP
DG
LNL
CVBS I/P, modulate 5-step
CVBS I/P, modulate 5-step
CVBS I/P, 5-step
Luma ramp
Luma flat field
Min
61
63
Typ
Max
Unit
0.4
0.4
0.4
0.6
0.6
0.7
Degrees
%
%
63
65
60
–5
40
dB
dB
dB
+5
70
±1.3
60
20
5
200
200
2
100
HUE
CL_AC
1
1
0.4
0.3
0.1
Degrees
%
%
%
Degrees
%
1
1
%
%
5
CVBS, 1 V I/P
CVBS, 1 V I/P
Temperature range: TMIN to TMAX, –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ).
The min/max specifications are guaranteed over this range.
Rev. B | Page 7 of 104
%
Hz
Hz
Lines
%
%
Fields
Lines
400
ADV7189B
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating
temperature range, unless otherwise specified.
Table 3.
Parameter 1, 2
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
2F
3F
Symbol
Typ
Max
Unit
±50
MHz
ppm
400
t1
t2
t3
t4
t5
t6
t7
t8
kHz
μs
μs
μs
μs
ns
ns
ns
μs
0.6
1.3
0.6
0.6
100
300
300
0.6
5
t9:t10
t13
Data Output Transitional Time
t14
Propagation Delay to Hi Z
Max Output Enable Access Time
Min Output Enable Access Time
t15
t16
t17
2
Min
28.6363
LLC1 Rising to LLC2 Rising
LLC1 Rising to LLC2 Falling
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
1
Test Conditions
ms
45:55
t11
t12
55:45
% duty
cycle
ns
ns
0.5
0.5
Negative clock edge to start of
valid data (tACCESS = t10 – t13)
End of valid data to negative
clock edge (tHOLD = t9 + t14)
3.4
ns
2.4
ns
6
7
4
ns
ns
ns
Temperature range: TMIN to TMAX, –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ).
The min/max specifications are guaranteed over this range.
ANALOG SPECIFICATIONS
Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating
temperature range, unless otherwise specified. Recommended Analog input video signal range 0.5 V to 1.5 V, typically 1 V p-p.
Table 4.
Parameter 1, 2
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
4F
1
2
5F
Symbol
Test Condition
Clamps switched off
Temperature range: TMIN to TMAX, –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ).
The min/max specifications are guaranteed over this range.
Rev. B | Page 8 of 104
Min
Typ
0.1
10
0.75
0.75
60
60
Max
Unit
μF
MΩ
mA
mA
μA
μA
ADV7189B
THERMAL SPECIFICATIONS
Table 5.
Parameter 1, 2
THERMAL CHARACTERISTICS
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal Resistance (Still Air)
6F
1
2
7F
Symbol
Test Conditions
Min
θJC
θJA
4-layer PCB with solid ground plane
4-layer PCB with solid ground plane
7.6
38.1
Temperature range: TMIN to TMAX, –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ)
The min/max specifications are guaranteed over this range.
TIMING DIAGRAMS
t3
t5
t3
SDA
t4
t7
t2
t8
Figure 2. I2C Timing
t9
t10
OUTPUT LLC 1
t11
t12
OUTPUT LLC 2
t13
04997-0-004
t14
OUTPUTS P0–P19, VS,
HS, FIELD,
SFL
Figure 3. Pixel Port and Control Output Timing
OE
t15
t16
Figure 4. OE Timing
Rev. B | Page 9 of 104
04983-0-005
P0–P19, HS,
VS, FIELD,
SFL
t17
04983-0-003
t1
t6
SCLK
Typ
Max
Unit
°C/W
°C/W
ADV7189B
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
AVDD to GND
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO – PVDD
DVDDIO – DVDD
AVDD – PVDD
AVDD – DVDD
Digital Inputs Voltage to DGND
Digital Output Voltage to DGND
Analog Inputs to AGND
Maximum Junction Temperature
(TJ Max)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
Rating
4V
4V
2.2 V
2.2 V
4V
–0.3 V to +0.3 V
–0.3 V to +0.3 V
–0.3 V to +2 V
–0.3 V to +2 V
–0.3 V to +2 V
–0.3 V to +2 V
–0.3 V to DVDDIO + 0.3 V
–0.3 V to DVDDIO + 0.3 V
AGND – 0.3 V to AVDD + 0.3 V
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
–65°C to +150°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 10 of 104
ADV7189B
FIELD
OE
NC
NC
P16
P17
P18
P19
DVDD
DGND
NC
NC
SCLK
SDA
ALSB
NC
RESET
NC
AIN6
AIN12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VS 1
60 AIN5
HS 2
59 AIN11
DGND 3
58 AIN4
DVDDIO 4
57 AIN10
P15 5
56 AGND
P14 6
55 CAPC2
P13 7
54 CAPC1
P12 8
53 AGND
DGND 9
52 CML
ADV7189B
DVDD 10
51 REFOUT
TOP VIEW
(Not to Scale)
INTRQ 11
50 AVDD
SFL 12
49 CAPY2
NC 13
48 CAPY1
DGND 14
47 AGND
DVDDIO 15
46 AIN3
NC 16
45 AIN9
P11 17
44 AIN2
P10 18
43 AIN8
P9 19
42 AIN1
34
35
36
37
38
39
40
AGND
AGND
NC = NO CONNECT
Figure 5. 80-Lead LQFP Pin Configuration
Rev. B | Page 11 of 104
04983-0-002
33
PVDD
LLC1
32
ELPF
LLC2
31
PWRDN
NC
30
P0
P4
29
P1
P5
28
P2
27
P3
26
DGND
25
DVDD
24
XTAL
23
XTAL1
22
P6
41 AIN7
21
P7
P8 20
ADV7189B
Table 7. Pin Function Descriptions
Pin No.
3, 9, 14, 31, 71
39, 40, 47, 53,
56
4, 15
10, 30, 72
50
38
42, 44, 46, 58,
60, 62, 41, 43,
45, 57, 59, 61
11
Mnemonic
DGND
AGND
Type
G
G
Function
Digital Ground.
Analog Ground.
DVDDIO
DVDD
AVDD
PVDD
AIN1toAIN12
P
P
P
P
I
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 86.
No Connect Pins.
132H
NC
13, 16, 25, 63,
65, 69, 70, 77,
78
35 to32, 24 to
17, 8 to 5,
76 to 73
2
1
80
67
68
66
P0–P19
O
Video Pixel Output Port.
HS
VS
FIELD
SDA
SCLK
ALSB
O
O
O
I/O
I
I
64
RESET
I
27
LLC1
O
26
LLC2
O
29
XTAL
I
28
XTAL1
O
36
PWRDN
I
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).
This pin selects the I2C address for the ADV7189B. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7189B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7189B. Nominally 27 MHz,
but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189B.
Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7189B. In crystal mode, the crystal
must be a fundamental crystal.
A logic low on this pin places the ADV7189B in a power-down mode. Refer to Power
Management Register in the I2C Register Maps section for more options on power-down
modes for the ADV7189B.
When set to a logic low, OE enables the pixel output bus, P19 toP0 of the ADV7189B. A logic
high on the OE pin places Pins P19 to P0, HS, VS, SFL into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 46.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video
encoder.
Internal Voltage Reference Output. Refer to Figure 46 for a recommended capacitor network for
this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 46 for a
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin.
13H
79
OE
I
37
ELPF
I
12
SFL
O
51
REFOUT
O
52
CML
O
48, 49
54, 55
CAPY1, CAPY2
CAPC1, CAPC2
I
I
134H
135H
136H
137H
138H
Rev. B | Page 12 of 104
ADV7189B
ANALOG FRONT END
ANALOG INPUT MUXING
INSEL[3:0]
INTERNAL
MAPPING
FUNCTIONS
AIN1
AIN7
AIN2
AIN8
AIN3
AIN9
AIN4
AIN10
AIN5
AIN11
AIN6
AIN12
1
ADC0_SW[3:0]
0
ADC0
AIN3
AIN9
AIN4
AIN10
AIN5
AIN11
AIN6
AIN12
1
ADC1_SW[3:0]
0
ADC1
AIN2
AIN8
AIN5
AIN11
AIN6
AIN12
1
ADC2_SW[3:0]
0
ADC2
04983-0-006
AIN1
AIN7
AIN2
AIN8
AIN3
AIN9
AIN4
AIN10
AIN5
AIN11
AIN6
AIN12
ADC_SW_MAN_EN
Figure 6. Internal Pin Connections
The ADV7189B has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder. Figure 6 outlines the overall structure of the input
muxing provided in the ADV7189B.
139H
As can be seen in Figure 6, there are two different ways in which
the analog input muxes can be controlled:
140H
•
•
Control via functional registers (INSEL). Using INSEL[3:0]
simplifies the setup of the muxes, and minimizes crosstalk
between channels by pre-assigning the input channels.
This is referred to as ADI recommended input muxing.
Control via an I2C manual override (ADC_sw_man_en,
ADC0_sw, ADC1_sw, ADC2_sw). This is provided for
applications with special requirements, for example,
number/combinations of signals that would not be
served by the pre-assigned input connections. This is
referred to as manual input muxing.
ADI Recommended Input Muxing
A maximum of 12 CVBS inputs can be connected and decoded
by the ADV7189B. As seen in Figure 5, this means the sources
have to be connected to adjacent pins on the IC. This calls for a
careful design of the PCB layout, for example, ground shielding
between all signals routed through tracks that are physically
close together.
142H
INSEL[3:0] Input Selection, Address 0x00[3:0]
The INSEL bits allow the user to select an input channel as well
as the input format. Depending on the PCB connections, only
a subset of the INSEL modes are valid. The INSEL[3:0] does
not only switch the analog input muxing, it also configures the
standard definition processor core to process CVBS (Comp),
S-Video (Y/C), or component (YPbPr) format.
Refer to Figure 7 for an overview of the two methods of
controlling the ADV7189B’s input muxing.
14H
Rev. B | Page 13 of 104
ADV7189B
CONNECTING
ANALOG SIGNALS
TO ADV7189
ADI-RECOMMENDED
INPUT MUXING; SEE TABLE 9
SET INSEL[3:0] FOR REQUIRED
MUXING CONFIGURATION
NO
SET INSEL[3:0] TO
CONFIGURE ADV7189B TO
DECODE VIDEO FORMAT:
CVBS: 0000
YC: 0110
YPrPb: 1001
USE MANUAL INPUT MUXING
(ADC_SW_MAN_EN, ADC0_SW,
ADC1_SW, ADC2_SW)
04983-0-007
YES
Figure 7. Input Muxing Overview
Table 8. Input Channel Switching Using INSEL[3:0]
INSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Analog Input Pins
Video Format
CVBS1 = AIN1 (default)
Composite
CVBS2 = AIN2
Composite
CVBS3 = AIN3
Composite
CVBS4 = AIN4
Composite
CVBS5 = AIN5
Composite
CVBS6 = AIN6
Composite
Y1 = AIN1
YC
C1 = AIN4
YC
Y2 = AIN2
YC
C2 = AIN5
YC
Y3 = AIN3
YC
C3 = AIN6
YC
Y1 = AIN1
YPrPb
PB1 = AIN4
YPrPb
PR1 = AIN5
YPrPb
Y2 = AIN2
YPrPb
PB2 = AIN3
YPrPb
PR2 = AIN6
YPrPb
CVBS7 = AIN7
Composite
CVBS8 = AIN8
Composite
CVBS9 = AIN9
Composite
CVBS10 = AIN10
Composite
CVBS11 = AIN11
Composite
Table 9. Input Channel Assignments
Input
Channel
AIN7
AIN1
AIN8
AIN2
AIN9
AIN3
AIN10
AIN4
AIN11
AIN5
AIN12
AIN6
Pin
No.
41
42
43
44
45
46
57
58
59
60
61
62
ADI Recommended Input Muxing Control
INSEL[3:0]
CVBS7
CVBS1
YC1-Y
YPrPb1-Y
CVBS8
CVBS2
YC2-Y
YPrPb2-Y
CVBS9
CVBS3
YC3-Y
YPrPb2-Pb
CVBS10
CVBS4
YC1-C
YPrPb1-Pb
CVBS11
CVBS5
YC2-C
YPrPb1-Pr
Not Available
CVBS6
YC3-C
YPrPb2-Pr
ADI-recommended input muxing is designed to minimize
crosstalk between signal channels and to obtain the highest
level of signal integrity. Table 9 summarizes how the PCB layout should connect analog video signals to the ADV7189B.
143H
It is strongly recommended to connect any unused analog input
pins to AGND to act as a shield.
Inputs AIN7 to AIN11 should be connected to AGND when
only six input channels are used. This improves the quality
of the sampling due to better isolation between channels.
AIN12 is not under the control of INSEL[3:0]. It can only be
routed to ADC0/ADC1/ADC2 by manual muxing. See Table 10
for further details.
14H
Rev. B | Page 14 of 104
ADV7189B
This means INSEL must be used to tell the ADV7189B whether
the input signal is of component, YC, or CVBS format.
Manual Input Muxing
By accessing a set of manual override muxing registers, the
analog input muxes of the ADV7189B can be controlled
directly. This is referred to as manual input muxing.
Manual input muxing overrides other input muxing control
bits, for example, INSEL. The manual muxing is activated by
setting the ADC_SW_MAN_EN bit. It only affects the analog
switches in front of the ADCs.
This means if the settings of INSEL and the manual input
muxing registers (ADC0/1/2_sw) contradict each other, the
ADC0/ADC1/ADC2_sw settings apply and INSEL is ignored.
Manual input muxing controls only the analog input muxes.
INSEL[3:0] still has to be set so the follow-on blocks process
the video data in the correct format.
Restrictions in the channel routing are imposed by the analog
signal routing inside the IC; every input pin cannot be routed
to each ADC. Refer to Figure 6 for an overview on the routing
capabilities inside the chip. The three mux sections can be
controlled by the reserved control signal buses ADC0/ADC1/
ADC2_sw[3:0]. Table 10 explains the control words used.
145H
146H
SETADC_sw_man_en, Manual Input Muxing Enable,
Address C4[7]
ADC0_sw[3:0], ADC0 Mux Configuration, Address 0xC3[3:0]
ADC1_sw[3:0], ADC1 Mux Configuration, Address 0xC3[7:4]
ADC2_sw[3:0], ADC2 Mux Configuration, Address 0xC4[3:0]
Table 10. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1)
ADC0_sw[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC0 Connected To:
No Connection
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
No Connection
No Connection
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
No Connection
ADC1_sw[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC1 Connected To:
No Connection
No Connection
No Connection
AIN3
AIN4
AIN5
AIN6
No Connection
No Connection
No Connection
No Connection
AIN9
AIN10
AIN11
AIN12
No Connection
Rev. B | Page 15 of 104
ADC2_sw[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC2 Connected To:
No Connection
No Connection
AIN2
No Connection
No Connection
AIN5
AIN6
No Connection
No Connection
No Connection
AIN8
No Connection
No Connection
AIN11
AIN12
No Connection
ADV7189B
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
PWRDN_ADC_0, Address 0x3A[3]
POWER-SAVE MODES
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
Power-Down
PDBP, Address 0x0F[2]
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
The digital core of the ADV7189B can be shut down by using a
pin (PWRDN) and a bit (PWRDN, see below). The PDBP controls which of the two has the higher priority. The default is to
give the pin (PWRDN) priority. This allows the user to have the
ADV7189B powered down by default.
PWRDN_ADC_1, Address 0x3A[2]
When PDBD is 0 (default), the digital core power is controlled
by the PWRDN pin (the bit is disregarded).
PWRDN_ADC_2, Address 0x3A[1]
When PDBD is 1, the bit has priority (the pin is disregarded).
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
PWRDN, Address 0x0F[5]
Setting the PWRDN bit switches the ADV7189B into a chipwide power-down mode. The power down stops the clock
from entering the digital section of the chip, thereby freezing
its operation. No I2C bits are lost during power down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I2C interface itself is unaffected,
and remains operational in power-down mode.
The ADV7189B leaves the power-down state if the PWRDN bit
is set to 0 (via I2C), or if the overall part is reset using the
RESET pin.
Note: PDBP must be set to 1 for the PWRDN bit to power down
the ADV7189B.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7189B is in chip-wide power down.
ADC Power-Down Control
RESET CONTROL
Chip Reset (RES), Address 0x0F[7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7189B, issues a full chip reset. All I2C registers get reset to
their default values. Note: Some register bits do not have a reset
value specified. They keep their last written value. These bits are
marked as having a reset value of x in the register table. After
the reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the RES bit, or initiating a reset via the pin, the
part returns to the default mode of operation with respect to
its primary mode of operation. All I2C bits are loaded with
their default values, making this bit self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I2C writes are
performed.
The ADV7189B contains three 12-bit ADCs (ADC 0, ADC 1,
and ADC 2). If required, it is possible to power down each ADC
individually.
The I2C master controller receives a no-acknowledge condition on the ninth clock cycle when chip reset is implemented.
See the MPU Port Description section for a full description.
The ADCs should be powered down when in:
When RES is 0 (default), operation is normal.
•
CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
When RES is 1, the reset sequence starts.
•
S-Video mode. ADC 2 should be powered down to save on
power consumption.
147H
Rev. B | Page 16 of 104
ADV7189B
Individual drive strength controls are provided via the
DR_STR_XX bits.
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03[6]
This bit allows the user to three-state the output drivers of the
ADV7189B.
Upon setting the TOD bit, the P[19:0], HS, VS, FIELD, and SFL
pins are three-stated.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Drivers and the Timing Signals Output
Enable sections.
148H
149H
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TIM_OE is 0 (default), HS, VS, and FIELD are threestated according to the TOD bit.
When TIM_OE is 1, HS, VS, and FIELD are forced active all
the time.
Drive Strength Selection (Data)
DR_STR[1:0] Address 0xF4[5:4]
For EMC and crosstalk reasons, it can be desirable to strengthen
or weaken the drive strength of the output drivers. The
DR_STR[1:0] bits affect the P[19:0] output drivers.
For more information on three-state control, refer to the Drive
Strength Selection (Clock) and the Drive Strength Selection
(Sync) sections.
154H
15H
The ADV7189B supports three-stating via a dedicated pin.
When set high, the OE pin three-states the output drivers for
P[19:0], HS, VS, FIELD, and SFL. The output drivers are threestated if the TOD bit or the OE pin is set high.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Table 11. DR_STR_C Function
DR_STR_C[1:0]
00
01 (default)
10
11
Description
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
Three-State LLC Drivers
TRI_LLC, Address 0x1D[7]
Drive Strength Selection (Clock)
DR_STR_C[1:0] Address 0xF4[3:2]
This bit allows the output drivers for the LLC1 pin and LLC2
pin of the ADV7189B to be three-stated. For more information
on three-state control, refer to the Three-State Output Drivers
and the Timing Signals Output Enable sections.
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the Drive Strength Selection (Sync) and the Drive
Strength Selection (Data) sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 12. DR_STR_C Function
150H
15H
156H
DR_STR_C[1:0]
00
01 (default)
10
11
157H
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
Description
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
Timing Signals Output Enable
TIM_OE, Address 0x04[3]
Drive Strength Selection (Sync)
DR_STR_S[1:0] Address 0xF4[1:0]
The TIM_OE bit should be regarded as an addition to the
TOD bit. Setting it high forces the output drivers for HS, VS,
and FIELD into the active (that is, driving) state even if the
TOD bit is set. If set to low, the HS, VS, and FIELD pins are
three-stated dependent on the TOD bit. This functionality is
useful if the decoder is to be used as a timing generator only.
This may be the case if only the timing signals are to be
extracted from an incoming signal, or if the part is in freerun mode where a separate chip can output, for instance, a
company logo.
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are driven.
For more information, refer to the Drive Strength Selection
(Clock) and the Drive Strength Selection (Data) sections.
158H
159H
Table 13. DR_STR_S Function
DR_STR_S[1:0]
00
01 (default)
10
11
For more information on three-state control, refer to the ThreeState Output Drivers and the Three-State LLC Drivers sections.
152H
153H
Rev. B | Page 17 of 104
Description
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
ADV7189B
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN Address 0x04[1]
Polarity LLC Pin
PCLK Address 0x37[0]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as GenLock) from the ADV7189B
core to an encoder in a decoder-encoder back-to-back
arrangement.
The polarity of the clock that leaves the ADV7189B via the
LLC1 and LLC2 pins can be inverted using the PCLK bit.
When EN_SFL_PIN is 0 (default), the subcarrier frequency
lock output is disabled.
When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.
Changing the polarity of the LLC clock output can be necessary
to meet the setup-and-hold time expectations of follow-on
chips.
Note: This bit also inverts the polarity of the LLC2 clock.
When PCLK is 0, the LLC output polarity is inverted.
When PCLK is 1 (default), the LLC output polarity is normal
(as per the Timing Diagrams).
160H
Rev. B | Page 18 of 104
ADV7189B
GLOBAL STATUS REGISTERS
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7189B. The other three registers
contain status bits from the ADV7189B.
Table 15. STATUS 1 Function
STATUS 1[7:0]
0
1
Bit Name
IN_LOCK
LOST_LOCK
IDENTIFICATION
2
3
FSC_LOCK
FOLLOW_PW
4
5
6
7
AD_RESULT.0
AD_RESULT.1
AD_RESULT.2
COL_KILL
IDENT[7:0] Address 0x11[7:0]
This register provides identification of the revision of
the ADV7189B.
An identification value of 0x11 indicates the ADV7189,
released silicon.
An identification value of 0x13 indicates the ADV7189B silicon.
STATUS 2
STATUS_2[7:0], Address 0x12[7:0]
STATUS 1
Table 16. STATUS 2 Function
STATUS_1[7:0] Address 0x10[7:0]
STATUS 2[7:0]
0
Bit Name
MVCS DET
1
MVCS T3
2
MV_PS DET
3
MV_AGC DET
4
5
LL_NSTD
FSC_NSTD
6
7
Reserved
Reserved
This read-only register provides information about the internal
status of the ADV7189B. These bits are used to set VS free run
(coast) frequency. See the VS_Coast[1:0], Address
0xF9[3:2]section and COL[2:0] Count Out-of-Lock, Address
0x51[5:3] for information on the timing.
16H
162H
Depending on the setting of the FSCLE bit, the Status[0] and
Status[1] are based solely on horizontal timing information or
on the horizontal timing and lock status of the color subcarrier.
See the FSCLE FSC Lock Enable, Address 0x51[7] section.
163H
SD AUTODETECTION RESULT
AD_RESULT[2:0] Address 0x10[6:4]
The AD_RESULT[2:0] bits report back on the findings from
the autodetection block. For more information on enabling
the autodetection block, see the General Setup section. For
information on configuring it, see the Autodetection of SD
Modes section.
164H
165H
Table 14. AD_RESULT Function
AD_RESULT[2:0]
000
001
010
011
100
101
110
111
Description
NTSM-MJ
NTSC-443
PAL-M
PAL-60
PAL-BGHID
SECAM
PAL-Combination N
SECAM 525
Description
In lock (right now).
Lost lock (since last read of
this register).
FSC locked (right now).
AGC follows peak white
algorithm.
Result of autodetection.
Result of autodetection.
Result of autodetection.
Color kill active.
Description
Detected Macrovision color
striping.
Macrovision color striping
protection. Conforms to
Type 3 if high, to Type 2 if
low.
Detected Macrovision
pseudo sync pulses.
Detected Macrovision AGC
pulses.
Line length is nonstandard.
FSC frequency is
nonstandard.
STATUS 3
STATUS_3[7:0], Address 0x13[7:0]
Table 17. STATUS 3 Function
STATUS 3[7:0]
0
Bit Name
INST_HLOCK
1
2
GEMD
SD_OP_50HZ
3
4
FREE_RUN_ACT
Description
Horizontal lock indicator
(instantaneous).
Gemstar Detect.
Flags whether 50 Hz or
60 Hz is present at output.
Reserved for future use.
ADV7189B outputs a blue
screen (see the DEF_VAL_EN
Default Value Enable,
Address 0x0C[0] section).
Field length is correct for
currently selected video
standard.
Interlaced video detected
(field sequence found).
Reliable sequence of
swinging bursts detected.
16H
5
STD_FLD_LEN
6
INTERLACED
7
PAL_SW_LOCK
Rev. B | Page 19 of 104
ADV7189B
STANDARD DEFINITION PROCESSOR (SDP)
STANDARD DEFINITION PROCESSOR
MACROVISION
DETECTION
DIGITIZED CVBS
DIGITIZED Y (YC)
DIGITIZED CVBS
DIGITIZED C (YC)
VBI DATA
RECOVERY
LUMA
DIGITAL
FINE
CLAMP
CHROMA
DIGITAL
FINE
CLAMP
CHROMA
DEMOD
STANDARD
AUTODETECTION
SLLC
CONTROL
LUMA
FILTER
GAIN
CONTROL
LUMA
RESAMPLE
SYNC
EXTRACT
LINE
LENGTH
PREDICTOR
RESAMPLE
CONTROL
CHROMA
FILTER
GAIN
CONTROL
CHROMA
RESAMPLE
LUMA
2D COMB
AV
CODE
INSERTION
CHROMA
2D COMB
VIDEO DATA
OUTPUT
MEASUREMENT
BLOCK (= >I2C)
VIDEO DATA
PROCESSING
BLOCK
04983-0-008
FSC
RECOVERY
Figure 8. Block Diagram of the Standard Definition Processor
A block diagram of the ADV7189B’s standard definition
processor (SDP) is shown in Figure 8.
SD CHROMA PATH
The ADV7189B block can handle standard definition video in
CVBS, YC, and YPrPb formats. It can be divided into a luminance and chrominance path. If the input video is of a composite
type (CVBS), both processing paths are fed with the CVBS input.
•
Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal.
•
Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal.
Chroma Demodulation. This block employs a color subcarrier (FSC) recovery unit to regenerate the color subcarrier
for any modulated chroma scheme. The demodulation
block then performs an AM demodulation for PAL and
NTSC and an FM demodulation for SECAM.
•
Luma Filter Block. This block contains a luma decimation
filter (YAA) with a fixed response, and some shaping filters
(YSH) that have selectable responses.
Chroma Filter Block. This block contains a chroma
decimation filter (CAA) with a fixed response, and some
shaping filters (CSH) that have selectable responses.
•
Gain Control. Automatic gain control (AGC) can operate
on several different modes, including gain based on the
color subcarrier’s amplitude, gain based on the depth of
the horizontal sync pulse on the luma channel, or fixed
manual gain.
•
Chroma Resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic linelength errors of the incoming video signal.
The input signal is processed by the following blocks:
167H
SD LUMA PATH
The input signal is processed by the following blocks:
•
•
•
Luma Gain Control. The automatic gain control (AGC)
can operate on a variety of different modes, including gain
based on the depth of the horizontal sync pulse, peak white
mode, and fixed manual gain.
•
Luma Resample. To correct for line-length errors and
dynamic line-length changes, the data is digitally resampled.
•
Luma 2D Comb. The two-dimensional comb filter
provides YC separation.
•
AV Code Insertion. At this point, the decoded luma (Y)
signal is merged with the retrieved chroma values. AV
codes (as per ITU-R. BT-656) can be inserted.
Chroma 2D Comb. The two-dimensional, 5-line,
superadaptive comb filter provides high quality YC
separation in case the input signal is CVBS.
•
AV Code Insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma
values. AV codes (as per ITU-R. BT-656) can be inserted.
•
Rev. B | Page 20 of 104
ADV7189B
SYNC PROCESSING
GENERAL SETUP
The ADV7189B extracts syncs embedded in the video data
stream. There is currently no support for external HS/VS
inputs. The sync extraction has been optimized to support
imperfect video sources such as VCRs with head switches. The
actual algorithm used employs a coarse detection based on a
threshold crossing followed by a more detailed detection using
an adaptive interpolation algorithm. The raw sync information
is sent to a line-length measurement and prediction block. The
output of this is then used to drive the digital resampling
section to ensure that the ADV7189B outputs 720 active pixels
per line.
Video Standard Selection
The sync processing on the ADV7189B also includes the
following specialized postprocessing blocks that filter and
condition the raw sync information retrieved from the
digitized analog video.
The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal circumstances,
this should not be necessary. The VID_SEL[3:0] bits default to
an autodetection mode that supports PAL, NTSC, SECAM, and
variants thereof. The following section provides more information on the autodetection system.
Autodetection of SD Modes
To guide the autodetect system of the ADV7189B, individual enable bits are provided for each of the supported video
standards. Setting the relevant bit to 0 inhibits the standard
from being detected automatically. Instead, the system picks
the closest of the remaining enabled standards. The results of
the autodetection can be read back via the status registers. See
the Global Status Registers section for more information.
168H
•
•
Vsync Processor. This block provides extra filtering of
the detected Vsyncs to give improved vertical lock.
VID_SEL[3:0] Address 0x00[7:4]
Hsync Processor. The Hsync processor is designed to filter
incoming Hsyncs that are corrupted by noise, providing
much improved performance for video signals with stable
time base but poor SNR.
VID_SEL[3:0]
0000 (default)
Table 18. VID_SEL Function
0001
VBI DATA RECOVERY
0010
The ADV7189B can retrieve the following information from
the input video:
0011
•
Wide-screen signaling (WSS)
•
Copy generation management system (CGMS)
•
Closed captioning (CC)
•
Macrovision protection presence
•
EDTV data
•
Gemstar-compatible data slicing
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The ADV7189B is also capable of automatically detecting
the incoming video standard with respect to
•
Color subcarrier frequency
•
Field rate
•
Line rate
Description
Autodetect (PAL BGHID) <–> NTSC J (no
pedestal), SECAM.
Autodetect (PAL BGHID) <–> NTSC M
(pedestal), SECAM.
Autodetect (PAL N) (pedestal) <–> NTSC J (no
pedestal), SECAM.
Autodetect (PAL N) (pedestal) <–> NTSC M
(pedestal), SECAM.
NTSC J (1).
NTSC M (1).
PAL 60.
NTSC 4.43 (1).
PAL BGHID.
PAL N[= PAL BGHID (with pedestal)].
PAL M (without pedestal).
PAL M.
PAL Combination N.
PAL Combination N (with pedestal).
SECAM.
SECAM (with pedestal).
AD_SEC525_EN Enable Autodetection of SECAM 525
Line Video, Address 0x07[7]
Setting AD_SEC525_EN to 0 (default), disables the
autodetection of a 525-line system with a SECAM style,
FM-modulated color component.
The ADV7189B can configure itself to support PAL-BGHID,
PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM
50 Hz/60 Hz, NTSC4.43, and PAL60.
Setting AD_SEC525_EN to 1 enables the detection.
AD_SECAM_EN Enable Autodetection of SECAM,
Address 0x07[6]
Setting AD_SECAM_EN to 0 disables the autodetection of
SECAM.
Setting AD_SECAM_EN to 1 (default) enables the detection.
Rev. B | Page 21 of 104
ADV7189B
AD_N443_EN Enable Autodetection of NTSC 443,
Address 0x07[5]
SFL_INV Subcarrier Frequency Lock Inversion
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection.
This bit controls the behavior of the PAL switch bit in the SFL
(GenLock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems as follows:
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
AD_P60_EN Enable Autodetection of PAL60,
Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(GenLock Telegram) bit directly, while the later ones invert the
bit prior to using it. The reason for this is the inversion
compensated for the 1-line delay of an SFL (GenLock Telegram)
transmission.
Setting AD_P60_EN to 1 (default) enables the detection.
AD_PALN_EN Enable Autodetection of PAL N,
Address 0x07[3]
Setting AD_PALN_EN to 0 disables the detection of the
PAL N standard.
As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also,
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180° phase shift occurs.
Setting AD_PALN_EN to 1 (default) enables the detection.
AD_PALM_EN Enable Autodetection of PAL M,
Address 0x07[2]
Setting AD_PALM_EN to 0 disables the autodetection of PAL M.
Setting AD_PALM_EN to 1 (default), enables the detection.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
SFL_INV Address 0x41[6]
AD_NTSC_EN Enable Autodetection of NTSC,
Address 0x07[1]
Setting AD_NTSC_EN to 0 disables the detection of standard
NTSC.
Setting AD_NTSC_EN to 1 (default) enables the detection.
Setting SFL_INV[6] to 0 makes the part SFL-compatible with
ADV7190/ADV7191/ADV7194 encoders.
Setting SFL_INV to 1 (default) makes the part SFL-compatible
with ADV717x/ADV7173x encoders.
Lock-Related Controls
AD_PAL_EN Enable Autodetection of PAL,
Address 0x07[0]
Setting AD_PAL_EN to 0 disables the detection of standard PAL.
Lock information is presented to the user through Bits[1:0] of
the Status 1 register. See the STATUS_1[7:0] Address 0x10[7:0]
section. Figure 9 outlines the signal flow and the controls available to influence the way the lock status information is generated.
169H
170H
Setting AD_PAL_EN to 1 (default) enables the detection.
SELECT THE RAW LOCK SIGNAL
SRLS
1
0
0
1
FSC LOCK
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS 1 [0]
MEMORY
STATUS 1 [1]
04983-0-009
TIME_WIN
FREE_RUN
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TAKE FSC LOCK INTO ACCOUNT
FSCLE
Figure 9. Lock-Related Signal Path
Rev. B | Page 22 of 104
ADV7189B
Table 20. CIL Function
SRLS Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
•
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming video.
It reacts quickly.
•
The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into unlocked state, and reports this via Status 0[1:0]. It counts
the value in lines of video.
Setting SRLS to 1 selects the time_win signal.
FSCLE FSC Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status
of the color subcarrier loop is taken into account when the
overall lock status is determined and presented via Bits[1:0]
in Status Register 1. This bit must be set to 0 when operating
the ADV7189B in YPrPb component mode in order to generate
a reliable HLOCK status bit.
Setting FSCLE to 0 (default) makes the overall lock status
dependent on only the horizontal sync lock.
Setting FSCLE to 1 makes the overall lock status dependent on
the horizontal sync lock and FSC lock.
Table 21. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
Description
1
2
5
10
100
500
1000
100000
SD COLOR CONTROLS
VS_Coast[1:0], Address 0xF9[3:2]
These registers allow the user to control picture appearance
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamping, although both controls affect the signal’s dc level.
These bits are used to set VS free-run (coast) frequency.
Table 19. VS_COAST[1:0] Function
01
10
11
Description
1
2
5
10
100
500
1000
100000
COL[2:0] Count Out-of-Lock, Address 0x51[5:3]
Setting SRLS to 0 (default) selects the free_run signal.
VS_COAST[1:0]
00 (default)
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
Description
Auto coast mode—follows VS
frequency from last video input
Forces 50 Hz coast mode
Forces 60 Hz coast mode
Reserved
CON[7:0] Contrast Adjust, Address 0x08[7:0]
This register allows the user to adjust the contrast of the picture.
Table 22. CON Function
CIL[2:0] Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state and reports this via Status 0[1:0]. It counts
the value in lines of video.
CON[7:0]
0x80 (default)
0x00
0xFF
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address
0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only. The user can adjust the saturation of the picture.
Table 23. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
0x80 (default)
0x00
0xFF
Rev. B | Page 23 of 104
Description
Chroma gain = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
ADV7189B
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM
and does not work on component video inputs (YPrPb).
SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address
0xE4[7:0]
This register allows the user to control the gain of the Cr
channel only.
Table 24. SD_SAT_Cr Function
SD_SAT_Cr[7:0]
0x80 (default)
0x00
0xFF
Table 28. HUE Function
Description
Chroma gain = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
HUE[7:0]
0x00 (default)
0x7F
0x80
SD_OFF_Cb[7:0] SD Offset Cb Channel, Address
0xE1[7:0]
DEF_Y[5:0] Default Value Y, Address 0x0C[7:2]
This register allows the user to select an offset for data on the
Cr channel only and adjust the hue of the picture. There is a
functional overlap with the Hue[7:0] register.
Table 25. SD_OFF_Cb Function
SD_OFF_Cb[7:0]
0x80 (default)
0x00
0xFF
Description
Phase of the chroma signal = 0°
Phase of the chroma signal = –90°
Phase of the chroma signal = +90°
Description
0 offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
SD_OFF_Cr[7:0] SD Offset Cr Channel, Address
0xE2[7:0]
This register allows the user to select an offset for data on the
Cr channel only and adjust the hue of the picture. There is a
functional overlap with the Hue[7:0] register.
When the ADV7189B loses lock on the incoming video signal
or when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
•
If DEF_VAL_AUTO_EN bit is set to high, and the
ADV7189B lost lock to the input video signal. This is
the intended mode of operation (automatic mode).
•
The DEF_VAL_EN bit is set, regardless of the lock status of
the video decoder. This is a forced mode that can be useful
during configuration.
The DEF_Y[5:0] values define the 6 MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 10-bit
mode, the output is Y[9:0] = {DEF_Y[5:0], 0, 0, 0, 0}.
Table 26. SD_OFF_Cr Function
DEF_Y[5:0] is 0x0D (Blue) is the default value for Y.
SD_OFF_Cr[7:0]
0x80 (default)
0x00
0xFF
Register 0x0C has a default value of 0x36.
Description
0 offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
BRI[7:0] Brightness Adjust, Address 0x0A[7:0]
This register controls the brightness of the video signal through
the ADV7189B. It allows the user to adjust the brightness of the
picture.
Table 27. BRI Function
BRI[7:0]
0x00 (default)
0x7F
0xFF
DEF_C[7:0] Default Value C, Address 0x0D[7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value.
It defines the 4 MSBs of Cr and Cb values to be output if
•
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7189B can’t lock to the input video (automatic mode).
•
DEF_VAL_EN bit is set to high (forced output).
The data that is finally output from the ADV7189B for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.
Description
Offset of the luma channel = 0IRE
Offset of the luma channel = +100IRE
Offset of the luma channel = –100IRE
In full 10-bit output mode, two extra LSBs of value 00 are
appended.
HUE[7:0] Hue Adjust, Address 0x0B[7:0]
This register contains the value for the color hue adjustment.
It allows the user to adjust the hue of the picture.
DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb.
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
Rev. B | Page 24 of 104
ADV7189B
DEF_VAL_EN Default Value Enable, Address 0x0C[0]
The clamping can be divided into two sections:
This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions for DEF_Y and DEF_C for additional
information. In this mode, the decoder also outputs a stable
27 MHz clock, HS, and VS.
•
Clamping before the ADC (analog domain): current sources.
•
Clamping after the ADC (digital domain): digital
processing block.
Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by the
DEF_VAL_AUTO_EN bit.
The ADCs can digitize an input signal only if it resides within
the ADC’s 1.6 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.
Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values.
This overrides picture data even if the decoder is locked.
The primary task of the analog clamping circuits is to ensure
the video signal stays within the valid ADC input window, so
the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the
analog domain as long as the video signal fits the ADC range.
DEF_VAL_AUTO_EN Default Value Automatic Enable,
Address 0x0C[1]
This bit enables the automatic use of the default values for Y, Cr,
and Cb when the ADV7189B cannot lock to the video signal.
Setting DEF_VAL_AUTO_EN to 0 disables free-run mode.
If the decoder is unlocked, it outputs noise.
Setting DEF_VAL_EN to 1 (default) enables free-run mode.
A colored screen set by the user-programmable Y, Cr, and Cb
values is displayed when the decoder loses lock.
CLAMP OPERATION
The input video is ac-coupled into the ADV7189B through a
0.1 μF capacitor. The recommended range of the input video
signal range be 0.5 V to 1.6 V (typically 1 V p-p). If the signal
exceeds the range, it cannot be processed correctly in the decoder.
Because the input is ac-coupled into the decoder, its dc value
needs to be restored. This process is referred to as clamping the
video. This section explains the general process of clamping on
the ADV7189B and shows the different ways in which a user can
configure its behavior.
The ADV7189B uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 10.
The analog processing channel shown is replicated three times
inside the IC. While only one single channel (and only one
ADC) is needed for a CVBS signal, two independent channels
are needed for YC (S-VHS) type signals, and three independent
channels are needed to allow component signals (YPrPb) to
be processed.
17H
ANALOG
VIDEO
INPUT
The clamping scheme has to complete two tasks. It must be
able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level
during normal operation.
For quickly acquiring an unknown video signal, the large current
clamps can be activated. It is assumed the amplitude of the
video signal is of a nominal value at this point. Control of the
coarse and fine current clamp parameters is performed automatically by the decoder.
Standard definition video signals may have excessive noise
on them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp is unsuitable
for this type of video signal. Instead, the ADV7189B employs a
set of four current sources that cause coarse (>0.5 mA) and fine
(<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see Figure 10).
172H
COARSE
CURRENT
SOURCES
ADC
DATA
PREPROCESSOR
(DPP)
CLAMP CONTROL
Figure 10. Clamping Overview
Rev. B | Page 25 of 104
SDP
WITH DIGITAL
FINE CLAMP
04983-0-010
FINE
CURRENT
SOURCES
After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Since the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations can occur. Dynamic
changes in the dc level lead to visually objectionable artifacts so
it is recommended not to use dynamic changes.
ADV7189B
The following sections describe the I2C signals that can be
used to influence the behavior of the clamping block on the
ADV7189B.
The luma antialias filter decimates the oversampled video
using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating
out-of-band components. The luma antialias filter (YAA)
has a fixed response.
CCLEN Current Clamp Enable, Address 0x14[4]
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This can be
useful if the incoming analog video signal is clamped externally.
•
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
DCT[1:0] Digital Clamp Timing, Address 0x15[6:5]
The clamp timing register determines the time constant of the
digital fine clamp circuitry. It is important to realize that the
digital fine clamp reacts very quickly because it is supposed to
immediately correct any residual dc level error for the active
line. The time constant of the digital fine clamp must be much
quicker than the one from the analog blocks.
The ADV7189B has two responses for the shaping filter:
one that is used for good quality CVBS, component, and
S-VHS type sources, and a second for nonstandard CVBS
signals.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, it is recommended to use the
comb filters for YC separation.
Table 29. DCT Function
DCT[1:0]
00
01
10 (default)
11
Luma shaping filters (YSH). The shaping filter block is
a programmable low-pass filter with a wide variety of
responses. It can be used to selectively reduce the luma
video signal bandwidth (needed prior to scaling, for
example). For some video sources that contain high
frequency noise, reducing the bandwidth of the luma
signal improves visual picture quality. A follow-on video
compression stage can work more efficiently if the video
is low-pass filtered.
Description
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
Determined by the ADV7189B, depending on
the I/P video parameters
•
Digital resampling filter. This block is used to allow dynamic
resampling of the video signal to alter parameters such as the
time base of a line of video. Fundamentally, the resampler is
a set of low-pass filters. The actual response is chosen by the
system with no requirement for user intervention.
Figure 12 through Figure 15 show the overall response of all
filters together. Unless otherwise noted, the filters are set into
a typical wideband mode.
173H
DCFE Digital Clamp Freeze Enable, Address 0x15[4]
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.
When DCFE is 0 (default), the digital clamp is operational.
When DCFE is 1, the digital clamp loop is frozen.
LUMA FILTER
Data from the digital fine clamp block is processed by three sets
of filters. Note: The data format at this point is CVBS for CVBS
input or luma only for Y/C and YPrPb input formats.
•
Luma antialias filter (YAA). The ADV7189B receives video
at a rate of 27 MHz. (In the case of 4× oversampled video,
the ADCs sample at 54 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the ADV7189B is always 27 MHz.) The ITU-R BT.601
recommends a sampling frequency of 13.5 MHz.
174H
Y-Shaping Filter
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. YC separation must aim for the best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
YC separation can be achieved by using the internal comb filters
of the ADV7189B. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (FSC). For good quality
CVBS signals, this relationship is known; the comb filter
algorithms can be used to separate out luma and chroma with
high accuracy.
With nonstandard video signals, the frequency relationship may
be disturbed, and the comb filters may not be able to remove all
crosstalk artifacts in an optimum fashion without the assistance
of the shaping filter block.
Rev. B | Page 26 of 104
ADV7189B
YSFM[4:0] Y-Shaping Filter Mode, Address 0x17[4:0]
An automatic mode for Y-shaped filtering is provided. In this
mode, the ADV7189B evaluates the quality of the incoming
video signal and selects the filter responses in accordance with
the signal quality and video standard. YFSM, WYSFMOVR,
and WYSFM allow the user to manually override these
automatic decisions in part or in full.
The Y-shaping filter mode bits allow the user to select from
a wide range of low-pass and notch filters. When switched in
automatic mode, the filter is selected based on other register
selections, for example, detected video standard, as well as
properties extracted from the incoming video itself, for example,
quality, time base stability. The automatic selection always picks
the widest possible bandwidth for the video input encountered.
The luma shaping filter has three control registers:
•
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (dependent on video quality and
video standard).
•
WYSFMOVR allows the user to manually override the
WYSFM decision.
•
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality CVBS, component (YPrPb),
and S-VHS (YC) input signals.
•
If the YSFM settings specify a filter (that is, YSFM is set
to values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
•
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals, wide
band filters are used.
WYSFMOVR Wideband Y-Shaping Filter Override,
Address 0x18[7]
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]
settings for good quality video signals. For more information,
refer to the general discussion of the luma-shaping filters in the
Y-Shaping Filter section and the flowchart shown in Figure 11.
In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (since they can successfully
be combed) as well as for luma components of YPrPb and YC
sources, since they need not be combed. For poor quality signals,
the system selects from a set of proprietary shaping filter
responses that complements comb filter operation in order to
reduce visual artifacts. The decisions of the control logic are
shown in Figure 11.
176H
When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.
Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].
175H
SET YSFM
YES
YSFM IN AUTO MODE?
00000 OR 00001
NO
VIDEO
QUALITY
BAD
GOOD
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
USE YSFM SELECTED
FILTER REGARDLESS FOR
GOOD AND BAD VIDEO
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 11. YSFM and WYSFM Control Flowchart
Rev. B | Page 27 of 104
04983-0-011
WYSFMOVR
1
ADV7189B
Table 30. YSFM Function
YSFM[4:0]
0'0000
0'0001
(default)
0'0010
0'0011
0'0100
0'0101
0'0110
0'0111
0'1000
0'1001
0'1010
0'1011
0'1100
0'1101
0'1110
0'1111
1'0000
1'0001
1'0010
1'0011
1'0100
1'0101
1'0110
1'0111
1'1000
1'1001
1'1010
1'1011
1'1100
1'1101
1'1110
1'1111
Description
Automatic selection including a wide-notch
response (PAL/NTSC/SECAM)
Automatic selection including a narrow-notch
response (PAL/NTSC/SECAM)
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN 1
PAL NN 2
PAL NN 3
PAL WN 1
PAL WN 2
NTSC NN 1
NTSC NN 2
NTSC NN 3
NTSC WN 1
NTSC WN 2
NTSC WN 3
Reserved
WYSFM[4:0] Wide Band Y-Shaping Filter Mode,
Address 0x18[4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, for example, CVBS with
stable time base, luma component of YPrPb, luma component
of YC. The WYSFM bits are only active if the WYSFMOVR bit
is set to 1. See the general discussion of the shaping filter settings
in the Y-Shaping Filter section.
17H
Table 31. WYSFM Function
WYSFM[4:0]
0'0000
0'0001
0'0010
0'0011
0'0100
0'0101
0'0110
0'0111
0'1000
0'1001
0'1010
0'1011
0'1100
0'1101
0'1110
0'1111
1'0000
1'0001
1'0010
1'0011 (default)
1'0100–1'1111
Rev. B | Page 28 of 104
Description
Do not use
Do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Do not use
ADV7189B
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,
Y RESAMPLE
0
0
–10
AMPLITUDE (dB)
–20
–30
–40
–40
04983-0-012
–60
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
–70
0
179H
180H
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
0
–60
Chroma Antialias Filter (CAA). The ADV7189B oversamples the CVBS by a factor of 2 and the Chroma/UV
by a factor of 4. A decimating filter (CAA) is used to
preserve the active video band and to remove any out-ofband components. The CAA filter has a fixed response.
•
Chroma Shaping Filters (CSH). The shaping filter block
can be programmed to perform a variety of low-pass
responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression.
•
Digital Resampling Filter. This block is used to allow
dynamic resampling of the video signal to alter parameters
such as the time base of a line of video. Fundamentally, the
resampler is a set of low-pass filters. The actual response is
chosen by the system without user intervention.
–80
04983-0-013
–100
–120
10
12
•
–40
6
8
FREQUENCY (MHz)
10
Data from the digital fine clamp block is processed by three sets
of filters. Note: the data format at this point is CVBS for CVBS
inputs, or chroma only for Y/C or Cr/Cb interleaved for YCrCb
input formats.
–20
4
6
8
FREQUENCY (MHz)
CHROMA FILTER
178H
2
4
Figure 15 . NTSC Notch Filter Response
The filter plots in Figure 12 show the S-VHS 1 (narrowest) to
S-VHS 18 (widest) shaping filter settings. Figure 14 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in Figure 15.
0
2
12
Figure 12. Y S-VHS Combined Responses
AMPLITUDE (dB)
–30
–50
–50
12
Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
The plots in Figure 16 show the overall response of all filters
together.
0
18H
–10
–20
–30
–40
–50
04983-0-015
AMPLITUDE (dB)
–20
04983-0-015
AMPLITUDE (dB)
–10
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 14. PAL Notch Filter Response
Rev. B | Page 29 of 104
ADV7189B
CSFM[2:0] C-Shaping Filter Mode, Address 0x17[7]
GAIN OPERATION
The C-shaping filter mode bits allow the user to select from a
range of low-pass filters, SH1 to SH5, and wideband mode for
the chrominance signal. The auto-selection options
automatically select from the filter options to give the specified
response. (See settings 000 and 001 in Table 32).
The gain control within the ADV7189B is done on a purely
digital basis. The input ADCs support a 12-bit range, mapped
into a 1.6 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADCs include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
182H
Table 32. CSFM Function
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
Description
Autoselect 1.5 MHz bandwidth
Autoselect 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
Wideband mode
As shown in Figure 17, the ADV7189B can decode a video signal
as long as it fits into the ADC window. The two components to
this are the amplitude of the input signal and the dc level it resides
on. The dc level is set by the clamping circuitry (see the Clamp
Operation section).
184H
185H
If the amplitude of the analog video signal is too high, clipping
can occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
0
The minimum supported amplitude of the input video is
determined by the ADV7189B’s ability to retrieve horizontal
and vertical timing and to lock to the colorburst, if present.
ATTENUATION (dB)
–10
–20
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
–30
–40
The possible AGC modes are summarized in Table 33.
186H
04983-0-016
–50
–60
1
2
3
4
FREQUENCY (MHz)
5
6
Figure 16. Chroma Shaping Filter Responses
Figure 16 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in
the Luma Gain and the Chroma Gain sections.
183H
187H
18H
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7189B)
MAXIMUM
VOLTAGE
ADC
DATA
PREPROCESSOR
(DPP)
SDP
(GAIN SELECTION ONLY)
GAIN
CONTROL
MINIMUM
VOLTAGE
CLAMP
LEVEL
Figure 17. Gain Control Overview
Rev. B | Page 30 of 104
04983-0-017
0
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating, and the AGC determined
gain at the time of the freeze to stay active until the loop is
either unfrozen or the gain mode of operation is changed.
ADV7189B
Table 33. AGC Modes
Input Video Type
Any
CVBS
Luma Gain
Manual gain luma.
Dependent on horizontal sync depth.
Chroma Gain
Manual gain chroma.
Dependent on color burst amplitude.
Taken from luma path.
Dependent on color burst amplitude.
Taken from luma path.
Dependent on color burst amplitude.
Taken from luma path.
Dependent on color burst amplitude.
Taken from luma path.
Taken from luma path.
Peak White.
Y/C
Dependent on horizontal sync depth.
Peak White.
YPrPb
Dependent on horizontal sync depth.
Luma Gain
LAGC[2:0] Luma Automatic Gain Control, Address
0x2C[7:0]
Table 35. LAGT Function
The luma automatic gain control mode bits select the mode of
operation for the gain control in the luma path. There are ADI
internal parameters to customize the peak white gain control.
Contact ADI sakes for more information.
Table 34. LAGC Function
LAGC[2:0]
000
001
010 (default)
011
100
101
110
111
LAGT[1:0]
00
01
10
11 (default)
Description
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LG[11:0] Luma Gain, Address 0x2F[3:0]; Address
0x30[7:0]; LMG[11:0] Luma Manual Gain, Address
0x2F[3:0]; Address 0x30[7:0]
Description
Manual fixed gain (use LMG[11:0])
AGC (blank level to sync tip); peak white
algorithm off
AGC (blank level to sync tip); peak white
algorithm on
Reserved
Reserved
Reserved
Reserved
Freeze gain
Luma Gain[11:0] is a dual-function register. If written to, a
desired manual luma gain can be programmed. This gain
becomes active if the LAGC[2:0] mode is switched to manual
fixed gain. Equation 1 shows how to calculate a desired gain. If
read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, this is one of
the following values:
LAGT[1:0] Luma Automatic Gain Timing, Address
0x2F[7:6]
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. Note this register only has an effect if the LAGC[2:0]
register is set to 001, 010, 011, or 100 (automatic gain control
modes).
•
Luma automatic gain value (LAGC[2:0] set to any of the
automatic modes)
If peak white AGC is enabled and active (see the
STATUS_1[7:0] Address 0x10[7:0] section), the actual gain
update speed is dictated by the peak white AGC loop and, as a
result, the LAGT settings have no effect. As soon as the part
leaves peak white AGC, LAGT becomes relevant again.
189H
Table 36. LG/LMG Function
LG[11:0]/LMG[11:0]
LMG[11:0] = X
Read/Write
Write
LG[11:0]
Read
The update speed for the peak white algorithm can be
customized by the use of internal parameters. Contact ADI
for more information.
Rev. B | Page 31 of 104
Luma _ Gain =
(0 < LG ≤ 4095)
2048
Description
Manual gain for
luma path
Actually used gain
= 0...2
(1)
ADV7189B
For example, program the ADV7189B into manual fixed gain
mode with a desired gain of 0.89:
Table 38. Betacam Levels
1.
Use Equation 1 to convert the gain:
0.89 × 2048 = 1822.72
2.
Truncate to integer value:
1822.72 = 1822
Name
Y
Range
3.
Convert to hexadecimal:
1822d = 0x71E
4.
Split into two registers and program:
Luma Gain Control 1[3:0] = 0x7
Luma Gain Control 2[7:0] = 0x1E
5.
Enable Manual Fixed Gain Mode:
Set LAGC[2:0] to 000
U and
V
Range
Sync
Depth
If YPrPb data is routed through the ADV7189B, the automatic
gain control modes can target different video input levels, as
outlined in. Note the BETACAM bit is valid only if the input
mode is YPrPb (component). The BETACAM bit sets the target
value for AGC operation. A review of the following sections is
useful.
•
–505 to
+505
286
SMPTE
(mV)
0 to
700
–350
to
+350
300
MII (mV)
0 to 700 (incl.
7.5%
pedestal)
–324 to +324
300
INSEL[3:0] Input Selection, Address 0x00[3:0] to find out
how component video (YPrPb) can be routed through the
ADV7189B.
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0]
must be set to the appropriate mode to enable the peak white or
average video mode in the first place. For more information, refer
to the LAGC[2:0] Luma Automatic Gain Control, Address
0x2C[7:0] section.
193H
Setting PW_UPD to 0 updates the gain once per video line.
Setting PW_UPD to 1 (default) updates the gain once per field.
190H
Video Standard Selection to select the various standards,
for example, with and without pedestal.
Chroma Gain
CAGC[1:0] Chroma Automatic Gain Control,
Address 0x2C[1:0]
19H
The automatic gain control (AGC) algorithms adjust the levels
based on the setting of the BETACAM bit. See Table 37.
192H
Table 37. BETACAM Function
BETACAM
0 (default)
1
286
Betacam
Variant
(mV)
0 to 714
PW_UPD Peak White Update, Address 0x2B[0]
BETACAM Enable Betacam Levels, Address 0x01[5]
•
Betacam
(mV)
0 to 714
(incl. 7.5%
pedestal)
–467 to +467
Description
Assuming YPrPb is selected as input format.
Selecting PAL with pedestal selects MII.
Selecting PAL without pedestal selects SMPTE.
Selecting NTSC with pedestal selects MII.
Selecting NTSC without pedestal selects SMPTE.
Assuming YPrPb is selected as input format.
Selecting PAL with pedestal selects BETACAM.
Selecting PAL without pedestal selects BETACAM
variant.
Selecting NTSC with pedestal selects BETACAM.
Selecting NTSC without pedestal selects
BETACAM variant.
The two bits of color automatic gain control mode select
the basic mode of operation for automatic gain control in the
chroma path.
Table 39. CAGC Function
CAGC[1:0]
00
01
10 (default)
11
Description
Manual fixed gain (use CMG[11:0]).
Use luma gain for chroma.
Automatic gain (based on color burst).
Freeze chroma gain.
CAGT[1:0] Chroma Automatic Gain Timing,
Address 0x2D[7:6]
The chroma automatic gain timing register allows the user
to influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0]
register is set to 10 (automatic gain).
Table 40. CAGT Function
CAGT[1:0]
00
01
10
11 (default)
Rev. B | Page 32 of 104
Description
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
ADV7189B
CG[11:0] Chroma Gain, Address 0x2D[3:0];
Address 0x2E[7:0]; CMG[11:0] Chroma Manual Gain,
Address 0x2D[3:0]; Address 0x2E[7:0]
Chroma Gain[11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] mode is switched to manual
fixed gain. Refer to Equation 2 for calculating a desired gain. If
read back, this register returns the current gain value. Depending
on the setting in the CAGC[1:0] bits, this is either
Chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode)
•
Chroma automatic gain value (CAGC[1:0] set to any of the
automatic modes)
CKILLTHR[2:0] Color Kill Threshold, Address 0x3D[6:4]
Table 41. CG/CMG Function
Read/Write
Write
CG[11:0]
Read
Chroma _ Gain =
Description
Manual gain for chroma
path.
Currently active gain.
(0 < CG ≤ 4095)
1024
= 0...4
(2)
Convert the readback value to decimal
0x47A = 1146d
2.
Apply Equation 2 to convert the readback value
1146/1024 = 1.12
The CKILLTHR[2:0] bits allow the user to select a threshold
for the color kill function. The threshold applies to only QAMbased (NTSC and PAL) or FM-modulated (SECAM) video
standards.
To enable the color kill function, the CKE bit must be set. For
settings 000, 001, 010, and 011, chroma demodulation inside
the ADV7189B may not work satisfactorily for poor input
video signals.
Table 42. CKILLTHR Function
For example, freezing the automatic gain loop and reading back
the CG[11:0] register results in a value of 0x47A.
1.
The color kill option only works for input signals with a modulated chroma part. For component input (YPrPb), there is no
color kill.
Setting CKE to 0 disables color kill.
Setting CKE to 1 (default), enables color kill.
•
CG[11:0]/CMG[11:0]
CMG[11:0]
If color kill is enabled and if the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
CKE Color Kill Enable, Address 0x2B[6]
The color kill enable bit allows the optional color kill function
to be switched on or off.
CKILLTHR[2:0]
000
001
010
011
100 (default)
101
110
111
For QAM-based video standards (PAL and NTSC) as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
Rev. B | Page 33 of 104
Description
SECAM
NTSC, PAL
No color kill.
Kill at < 0.5%
Kill at < 5%.
Kill at < 1.5%
Kill at < 7%.
Kill at < 2.5%
Kill at < 8%.
Kill at < 4.0%
Kill at < 9.5%.
Kill at < 8.5% (default)
Kill at < 15%.
Kill at < 16.0%
Kill at < 32%.
Kill at < 32.0%
Reserved for ADI
internal use only. Do
not select.
ADV7189B
CHROMA TRANSIENT IMPROVEMENT (CTI)
The signal bandwidth allocated for chroma is typically much
smaller than that of luminance. In the past, this was a valid
way to fit a color video signal into a given overall bandwidth
because the human eye is less sensitive to chrominance than
to luminance.
The uneven bandwidth, however, can lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 18). Due to the higher bandwidth, the signal transition
of the luma component is usually a lot sharper than that of the
chroma component. The color edge is not sharp but is blurred,
in the worst case, over several pixels.
For the alpha blender to be active, the CTI block must be
enabled via the CTI_EN bit.
Setting CTI_AB_EN to 0 disables the CTI alpha blender.
Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend
mixing function.
CTI_AB[1:0] Chroma Transient Improvement Alpha
Blend, Address 0x4D[3:2]
194H
DEMODULATED
CHROMA
SIGNAL
For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit, and the alpha blender must be
switched on via CTI_AB_EN.
LUMA SIGNAL WITH A
TRANSITION, ACCOMPANIED
BY A CHROMA TRANSITION
ORIGINAL, "SLOW" CHROMA
TRANSITION PRIOR TO CTI
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI
Sharp blending maximizes the effect of CTI on the picture, but
can also increase the visual impact of small amplitude, high
frequency chroma noise.
04983-0-018
LUMA
SIGNAL
The CTI_AB[1:0] controls the behavior of alpha-blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
Table 43. CTI_AB Function
CTI_AB[1:0]
00
Figure 18. CTI Luma/Chroma Transition
The chroma transient improvement block examines the input
video data. It detects transitions of chroma, and can be programmed to “steepen” the chroma edges in an attempt to
artificially restore lost color bandwidth. The CTI block,
however, operates only on edges above a certain threshold
to ensure that noise is not emphasized. Care has also been
taken to ensure that edge ringing and undesirable saturation
or hue distortion are avoided.
Chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitation. For
those types of signals, it is strongly recommended to enable the
CTI block via CTI_EN.
CTI_EN Chroma Transient Improvement Enable,
Address 0x4D[0]
The CTI_EN bit enables the CTI function. If set to 0, the CTI
block is inactive and the chroma transients are left untouched.
01
10
11 (default)
Description
Sharpest mixing between sharpened and original
chroma signal.
Sharp mixing.
Smooth mixing.
Smoothest alpha blend function.
CTI_C_TH[7:0] CTI Chroma Threshold, Address
0x4E[7:0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying how big the amplitude step in a chroma transition is to be
steepened by the CTI block. Programming a small value into
this register causes even smaller edges to be steepened by the
CTI block. Making CTI_C_TH[7:0] a large value causes the
block to only improve large transitions.
The default value for CTI_C_TH[7:0] is 0x08, indicating
the threshold for the chroma edges prior to CTI.
DIGITAL NOISE REDUCTION (DNR)
Setting CTI_EN to 1 (default) enables the CTI block.
Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and
their removal, therefore, improves picture quality.
CTI_AB_EN Chroma Transient Improvement
Alpha Blend Enable, Address 0x4D[1]
DNR_EN Digital Noise Reduction Enable, Address
0x4D[5]
The CTI_AB_EN bit enables an alpha-blend function within
the CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
The DNR_EN bit enables the DNR block or bypasses it.
Setting CTI_EN to 0 disables the CTI block.
Setting DNR_EN to 0 bypasses DNR (disables it).
Setting DNR_EN to 1 (default) enables digital noise reduction
on the luma data.
Rev. B | Page 34 of 104
ADV7189B
DNR_TH[7:0] DNR Noise Threshold, Address 0x50[7:0]
NTSC Comb Filter Settings
The DNR_TH[7:0] value is an unsigned 8-bit number used to
determine the maximum edge that is interpreted as noise and
therefore blanked from the luma data. Programming a large
value into DNR_TH[7:0] causes the DNR block to interpret
even large transients as noise and remove them. The effect on
the video data is, therefore, more visible.
Used for NTSC-M/J CVBS inputs.
Programming a small value causes only small transients to be
seen as noise and to be removed.
The recommended DNR_TH[7:0] setting for A/V inputs is
0x04, and the recommended DNR_TH[7:0] setting for tuner
inputs is 0x0A.
The default value for DNR_TH[7:0] is 0x08, indicating the
threshold for maximum luma edges to be interpreted as noise.
COMB FILTERS
The comb filters of the ADV7189B have been greatly improved
to automatically handle video of all types, standards, and levels
of quality. The NTSC and PAL configuration registers allow the
user to customize comb filter operation, depending on which
video standard is detected (by autodetection) or selected (by
manual programming). In addition to the bits listed in this
section, there are some further ADI internal controls; contact
ADI sales for more information.
NSFSEL[1:0] Split Filter Selection NTSC, Address
0x19[3:2]
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
gives better performance on diagonal lines, but leaves more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.
Table 44. NSFSEL Function
NSFSEL[1:0]
00 (default)
01
10
11
Description
Narrow
Medium
Medium
Wide
CTAPSN[1:0] Chroma Comb Taps NTSC, Address
0x38[7:6]
Table 45. CTAPSN Function
CTAPSN[1:0]
00
01
10 (default)
11
Rev. B | Page 35 of 104
Description
Do not use.
NTSC chroma comb adapts 3 lines (3 taps) to
2 lines (2 taps).
NTSC chroma comb adapts 5 lines (5 taps) to
3 lines (3 taps).
NTSC chroma comb adapts 5 lines (5 taps) to
4 lines (4 taps).
ADV7189B
CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38[5:3]
Table 46. CCMN Function
CCMN[2:0]
0xx (default)
Description
Adaptive comb mode.
Configuration
Adaptive 3-line chroma comb for CTAPSN = 01.
Adaptive 4-line chroma comb for CTAPSN = 10.
Adaptive 5-line chroma comb for CTAPSN = 11.
100
101
Disable chroma comb.
Fixed chroma comb (top lines of line memory).
110
Fixed chroma comb (all lines of line memory).
111
Fixed chroma comb (bottom lines of line memory).
Fixed 2-line chroma comb for CTAPSN = 01.
Fixed 3-line chroma comb for CTAPSN = 10.
Fixed 4-line chroma comb for CTAPSN = 11.
Fixed 3-line chroma comb for CTAPSN = 01.
Fixed 4-line chroma comb for CTAPSN = 10.
Fixed 5-line chroma comb for CTAPSN = 11.
Fixed 2-line chroma comb for CTAPSN = 01.
Fixed 3-line chroma comb for CTAPSN = 10.
Fixed 4-line chroma comb for CTAPSN = 11.
YCMN[2:0] Luma Comb Mode NTSC, Address 0x38[2:0]
Table 47.YCMN Function
YCMN[2:0]
0xx (default)
100
101
110
111
Description
Adaptive comb mode.
Disable luma comb.
Fixed luma comb (top lines of line memory).
Fixed luma comb (all lines of line memory).
Fixed luma comb (bottom lines of line memory).
Configuration
Adaptive 3-line (3 taps) luma comb.
Use low-pass/notch filter; see the Y-Shaping Filter section.
Fixed 2-line (2 taps) luma comb.
Fixed 3-line (3 taps) luma comb.
Fixed 2-line (2 taps) luma comb.
195H
Table 48. PSFSEL Function
PAL Comb Filter Settings
Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, PAL60, and NTSC443 CVBS inputs.
PSFSEL[1:0] Split Filter Selection PAL, Address 0x19[1:0]
The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl, but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.
PSFSEL[1:0]
00
01 (default)
10
11
Rev. B | Page 36 of 104
Description
Narrow
Medium
Wide
Widest
ADV7189B
CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6]
Table 49. CTAPSP Function
CTAPSP[1:0]
00
01
Description
Do not use.
PAL chroma comb adapts 5 lines (3 taps) to
3 lines (2 taps); cancels cross luma only.
PAL chroma comb adapts 5 lines (5 taps) to
3 lines (3 taps); cancels cross luma and hue error less well.
PAL chroma comb adapts 5 lines (5 taps) to
4 lines (4 taps); cancels cross luma and hue error well.
10
11 (default)
CCMP[2:0] Chroma Comb Mode PAL, Address 0x39[5:3]
Table 50. CCMP Function
CCMP[2:0]
0xx (default)
Description
Adaptive comb mode.
Configuration
Adaptive 3-line chroma comb for CTAPSP = 01.
Adaptive 4-line chroma comb for CTAPSP = 10.
Adaptive 5-line chroma comb for CTAPSP = 11.
100
101
Disable chroma comb.
Fixed chroma comb (top lines of line memory).
110
Fixed chroma comb (all lines of line memory).
111
Fixed chroma comb (bottom lines of line memory).
Fixed 2-line chroma comb for CTAPSP = 01.
Fixed 3-line chroma comb for CTAPSP = 10.
Fixed 4-line chroma comb for CTAPSP = 11.
Fixed 3-line chroma comb for CTAPSP = 01.
Fixed 4-line chroma comb for CTAPSP = 10.
Fixed 5-line chroma comb for CTAPSP = 11.
Fixed 2-line chroma comb for CTAPSP = 01.
Fixed 3-line chroma comb for CTAPSP = 10.
Fixed 4-line chroma comb for CTAPSP = 11.
YCMP[2:0] Luma Comb Mode PAL, Address 0x39[2:0]
Table 51. YCMP Function
YCMP[2:0]
0xx (default)
100
101
110
111
Description
Adaptive comb mode.
Disable luma comb.
Fixed luma comb (top lines of line memory).
Fixed luma comb (all lines of line memory).
Fixed luma comb (bottom lines of line memory).
Configuration
Adaptive 5 lines (3 taps) luma comb.
Use low-pass/notch filter, see the Y-Shaping Filter section.
Fixed 3 lines (2 taps) luma comb.
Fixed 5 lines (3 taps) luma comb.
Fixed 3 lines (2 taps) luma comb.
Rev. B | Page 37 of 104
196H
ADV7189B
AV CODE INSERTION AND CONTROLS
This section describes the I2C-based controls that affect:
•
Insertion of AV codes into the data stream.
•
Data blanking during the vertical blank interval (VBI).
•
The range of data values permitted in the output data
stream.
•
In an 8-/10-bit-wide output interface (Cb/Y/Cr/Y interleaved
data), the AV codes are defined as FF/00/00/AV, with AV being
the transmitted word that contains information about H/V/F.
In this output interface mode, the following assignment takes
place: Cb = FF, Y = 00, Cr = 00, and Y = AV.
In a 16-/20-bit output interface where Y and Cr/Cb are delivered
via separate data buses, the AV code is over the whole
16/20 bits. The SD_DUP_AV bit allows the user to replicate the
AV codes on both busses, so the full AV sequence can be found
on the Y bus as well as on the Cr/Cb bus. See Figure 19.
The relative delay of luma vs. chroma signals.
Note: Some of the decoded VBI data is being inserted during the horizontal blanking interval. See the Gemstar Data
Recovery section for more information.
198H
197H
When SD_DUP_AV is 0 (default), the AV codes are in single
fashion (to suit 8-/10-bit interleaved data output).
BT656-4 ITU Standard BT-R.656-4 Enable, Address
0x04[7]
When SD_DUP_AV is 1, the AV codes are duplicated (for
16-/20-bit interfaces).
The ITU has changed the position for toggling of the V bit
within the SAV EAV codes for NTSC between Revisions 3 and
Revision 4. The BT656-4 standard bit allows the user to select
an output mode that is compliant with either the previous or the
new standard. For further information, review the standard at
www.itu.int.
VBI_EN Vertical Blanking Interval Data Enable,
Address 0x03[7]
The VBI enable bit allows data such as intercast and closedcaption data to be passed through the luma channel of the
decoder with a minimal amount of filtering. All data for Line 1
to Line 21 is passed through and available at the output port.
The ADV7189B does not blank the luma data, and automatically
switches all filters along the luma data path into their widest
bandwidth. For active video, the filter settings for YSH and YPK
are restored.
Note the standard change affects NTSC only, and has no
bearing on PAL.
When BT656-4 is 0 (default), the BT656-3 specification is used.
The V bit goes low at EAV of Lines 10 and 273.
When BT656-4 is 1, the BT656-4 specification is used.
The V bit goes low at EAV of Lines 20 and 283.
Refer to the BL_C_VBI Blank Chroma during VBI section for
information on the chroma path.
SD_DUP_AV Duplicate AV Codes, Address 0x03[0]
When VBI_EN is 0 (default), all video lines are filtered/scaled.
Depending on the output interface width, it can be necessary to
duplicate the AV codes from the luma path into the chroma path.
When VBI_EN is 1, only the active video region is filtered/scaled.
SD_DUP_AV = 1
SD_DUP_AV = 0
FF
00
00
16-/20-BIT INTERFACE
AV
Y
00
AV
8-/10-BIT INTERFACE
Y
Cb/Y/Cr/Y
INTERLEAVED
Cr/Cb DATA BUS
FF
00
00
AV
Cb
FF
00
FF
00
00
AV
Cb
AV CODE SECTION
AV CODE SECTION
AV CODE SECTION
Figure 19. AV Code Duplication Control
Rev. B | Page 38 of 104
Cb
04983-0-019
16-/20-BIT INTERFACE
Y DATA BUS
ADV7189B
BL_C_VBI Blank Chroma During VBI, Address 0x04[2]
LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]
Setting BL_C_VBI high, the Cr and Cb values of all VBI lines
are blanked. This is done so any data that may arrive during
VBI is not decoded as color and output through Cr and Cb.
As a result, it is possible to send VBI lines into the decoder,
then output them through an encoder again, undistorted.
Without this blanking, any wrongly decoded color is encoded
by the video encoder; therefore, the VBI lines are distorted.
The Luma Timing Adjust register allows the user to specify a
timing difference between chroma and luma samples.
Setting BL_C_VBI to 0 decodes and outputs color during VBI.
Setting BL_C_VBI to 1 (default) blanks Cr and Cb values
during VBI.
AV codes (as per ITU-R BT-656, formerly known as CCIR-656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and are not to be used for active
video. Additionally, the ITU specifies that the nominal range
for video should be restricted to values between 16 and 235
for luma and 16 to 240 for chroma.
The RANGE bit allows the user to limit the range of values
output by the ADV7189B to the recommended value range.
This bit ensures the reserved values of 255d (0xFF) and 00d
(0x00) are not presented on the output pins unless they are
part of an AV code header.
Table 52. RANGE Function
16 ≤ Y ≤ 235
1 ≤ Y ≤ 254
AUTO_PDC_EN Automatic Programmed Delay Control,
Address 0x27[6]
Enabling the AUTO_PDC_EN function activates a function
within the ADV7189B that automatically programs the LTA[1:0]
and CTA[2:0] to have the chroma and luma data match delays
for all modes of operation. If set, manual registers LTA[1:0]
and CTA[2:0] are not used by the ADV7189B. If the automatic
mode is disabled (via setting the AUTO_PDC_EN bit to 0), the
values programmed into the LTA[1:0] and CTA[2:0] registers
become active.
When AUTO_PDC_EN is 0, the ADV7189B uses the LTA[1:0]
and CTA[2:0] values for delaying luma and chroma samples.
Refer to the LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]
and the CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]
sections.
19H
CVBS input LTA[1:0] = 00
•
YC input LTA[1:0] = 01
•
YPrPb input LTA[1:0] = 01
LTA[1:0]
00 (default)
01
10
11
Description
No delay.
Luma 1 CLK (37 ns) delayed.
Luma 2 CLK (74 ns) early.
Luma 1 CLK (37 ns) early.
CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]
The Chroma timing adjust register allows the user to specify a
timing difference between chroma and luma samples. This can
be used to compensate for external filter group delay differences
in the luma vs. chroma path, and to allow a different number of
pipeline delays while processing the video downstream. Review
this functionality together with the LTA[1:0] register.
The chroma can be delayed/advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where one can
no longer delay by luma pixel steps.
Description
16 ≤ C/P ≤ 240
1 ≤ C/P ≤ 254
20H
•
Table 53. LTA Function
RANGE Range Selection, Address 0x04[0]
RANGE
0
1 (default)
Note there is a certain functionality overlap with the CTA[2:0]
register. For manual programming, use the following defaults:
For manual programming, use the following defaults:
•
CVBS input CTA[2:0] = 011.
•
YC input CTA[2:0] = 101.
•
YPrPb input CTA[2:0] = 110.
Table 54. CTA Function
CTA[2:0]
000
001
010
011 (default)
100
101
110
111
When AUTO_PDC_EN is 1 (default), the ADV7189B automatically determines the LTA and CTA values to have luma
and chroma aligned at the output.
Rev. B | Page 39 of 104
Description
Not used.
Chroma + 2 chroma pixel (early).
Chroma + 1 chroma pixel (early).
No delay.
Chroma – 1 chroma pixel (late).
Chroma – 2 chroma pixel (late).
Chroma – 3 chroma pixel (late).
Not used.
ADV7189B
SYNCHRONIZATION OUTPUT SIGNALS
HSE[10:0] HS End, Address 0x34[2:0], Address 0x36[7:0]
HS Configuration
The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge with
respect to an internal counter that is reset to 0 immediately after
EAV Code FF, 00, 00, XY (see Figure 20). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count[0].
The following controls allow the user to configure the behavior
of the HS output pin only:
•
Beginning of HS signal via HSB[10:0]
•
End of HS signal via HSE[10:0]
•
Polarity of HS using PHS
20H
The default value of HSE[10:0] is 000, indicating that the HS
pulse ends zero pixels after falling edge of HS.
For example:
The HS Begin and HS End registers allow the user to freely
position the HS output (pin) within the video line. The values
in HSB[10:0] and HSE[10:0] are measured in pixel units from
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
1.
To shift the HS toward active video by 20 LLC1s, add
20 LLC1s to both HSB and HSE, that is, HSB[10:0] =
[00000010110], HSE[10:0] = [00000010100].
2.
To shift the HS away from active video by 20 LLC1s,
add 1696 LLC1s to both HSB and HSE (for NTSC), that
is, HSB[10:0] =[1101010010], HSE[10:0] = [11010100000]
(1696 is derived from the NTSC total number of pixels =
1716).
HSB[10:0] HS Begin, Address 0x34[6:4], Address
0x35[7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF, 00, 00, XY (see Figure 20). HSB is set to
00000000010b, which is 2 LLC1 clock cycles from count[0].
To move 20 LLC1s away from active video is equal to subtracting
20 from 1716 and adding the result in binary to both HSB[10:0]
and HSE[10:0].
201H
PHS Polarity HS, Address 0x37[7]
The default value of HSB is 0x002, indicating that the HS pulse
starts two pixels after the falling edge of HS.
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active high.
When PHS is 1, HS is active low.
Table 55. HS Timing Parameters (See Figure 20)
203H
Standard
NTSC
NTSC Square
Pixel
PAL
HS Begin Adjust
(HSB[10:0]) (Default)
00000000010b
00000000010b
HS End Adjust
(HSE[10:0]) (Default)
00000000000b
00000000000b
Characteristic
HS to Active Video (LLC1
Clock Cycles)
(C in Figure 20) (Default)
272
276
00000000010b
00000000000b
284
204H
Active Video
Samples/Line
(D in Figure 20)
720Y + 720C = 1440
640Y + 640C = 1280
Total LLC1
Clock Cycles
(E in Figure 20)
1716
1560
720Y + 720C = 1440
1728
205H
206H
LLC1
PIXEL
BUS
Cr
ACTIVE
VIDEO
Y
FF
00
00
XY
80
10
80
10
EAV
80
10
FF
00
H BLANK
00
SAV
XY
Cb
Y
Cr
Y
Cb
Y
Cr
ACTIVE VIDEO
HS
HSB[10:0]
C
D
D
E
E
Figure 20. HS Timing
Rev. B | Page 40 of 104
04983-0-020
HSE[10:0]
4 LLC1
ADV7189B
VS and FIELD Configuration
VSBHO VS Begin Horizontal Position Odd, Address 0x32[7]
The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as to generate
embedded AV codes:
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
•
ADV encoder-compatible signals via NEWAVMODE
•
PVS, PF
•
HVSTIM
•
VSBHO, VSBHE
•
VSEHO, VSEHE
•
For NTSC control:
When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
VSBHE VS Begin Horizontal Position Even, Address 0x32[6]
•
NVBEGDELO, NVBEGDELE, NVBEGSIGN,
NVBEG[4:0]
•
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
•
•
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSBHE is 0 (default), the VS pin goes high at the middle
of a line of video (even field).
When VSBHE is 1, the VS pin changes state at the start of a line
(even field).
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
VSEHO VS End Horizontal Position Odd, Address 0x33{7]
•
PVBEGDELO, PVBEGDELE, PVBEGSIGN,
PVBEG[4:0]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
•
PVENDDELO, PVENDDELE, PVENDSIGN,
PVEND[4:0]
When VSEHO is 0, the VS pin goes low (inactive) at the middle
of a line of video (odd field).
•
PFTOGDELO, PFTOGDELE, PFTOGSIGN,
PFTOG[4:0]
When VSEHO is 1 (default), the VS pin changes state at the
start of a line (odd field).
For PAL control:
NEWAVMODE New AV Mode, Address 0x31[4]
VSEHE VS End Horizontal Position Even, Address 0x33[6]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit ADI encoders. No adjustments are possible.
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
Setting NEWAVMODE to 1 (default) enables the manual
position of the VSYNC, Field, and AV codes using
Registers 0x34 to 0x37 and Register 0xE5 to 0xEA. Default
register settings are CCIR656 compliant; see Figure 21 for NTSC
and Figure 26 for PAL. For recommended manual user settings,
see Table 56 and Figure 22 for NTSC; see Table 57 and Figure 27
for PAL.
207H
208H
209H
210H
21H
21H
The HVSTIM bit allows the user to select where the VS signal
is being asserted within a line of video. Some interface circuitry
can require VS to go low while HS is low.
When HVSTIM is 1, the start of the line is relative to HSB.
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
PVS Polarity VS, Address 0x37[5]
HVSTIM Horizontal VS Timing, Address 0x31[3]
When HVSTIM is 0 (default) the start of the line is relative
to HSE.
When VSEHE is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (even field).
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high. When PVS is 1, VS is
active low.
PF Polarity FIELD, Address 0x37[3]
The polarity of the FIELD pin can be inverted using the PF bit.
When PF is 0 (default), FIELD is active high. When PF is 1,
FIELD is active low.
Rev. B | Page 41 of 104
ADV7189B
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
OUTPUT
VIDEO
H
V
NVBEG[4:0] = 0x5
1BT.656-4
NVEND[4:0] = 0x4
REG 0x04. BIT 7 = 1
F
NFTOG[4:0] = 0x3
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
283
284
285
OUTPUT
VIDEO
H
V
NVBEG[4:0] = 0x5
1BT.656-4
NVEND[4:0] = 0x4
REG 0x04. BIT 7 = 1
F
04983-0-021
NFTOG[4:0] = 0x3
1APPLIES
IF NEMAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 21. NTSC Default (BT.656). The polarity of H, V, and F is embedded in the data.
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x0
FIELD
OUTPUT
NVEND[4:0] = 0x3
NFTOG[4:0] = 0x5
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
284
285
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVEND[4:0] = 0x3
NFTOG[4:0] = 0x5
Figure 22. NTSC Typical Vsync/Field Positions Using Register Writes Shown in Table 56
213H
Rev. B | Page 42 of 104
04983-0-022
NVBEG[4:0] = 0x0
FIELD
OUTPUT
ADV7189B
Table 56. Recommended User Settings for NTSC (See Figure 22)
214H
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE5
0xE6
0xE7
Register Name
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Position Control 1
Hsync Position Control 2
Hsync Position Control 3
Polarity
NTSV_V_Bit_Beg
NTSC_V_Bit_End
NTSC_F_Bit_Tog
1
NVBEGSIGN
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
NVBEGDELO NTSC Vsync Begin Delay on Odd Field,
Address 0xE5[7]
0
When NVBEGDELO is 0 (default), there is no delay.
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
NOT VALID FOR USER
PROGRAMMING
Setting NVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to NVBEG.
NVBEGDELE NTSC Vsync Begin Delay on Even Field,
Address 0xE5[6]
ODD FIELD?
YES
NO
NVBEGDELO
NVBEGDELE
Setting NVBEGDELE to 1 delays Vsync going high on an even
field by a line relative to NVBEG.
1
NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]
1
0
0
ADDITIONAL
DELAY BY
1 LINE
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user
manual programming.
ADDITIONAL
DELAY BY
1 LINE
Setting NVBEGSIGN to 1 (default), advances the start of Vsync.
Not recommended for user programming.
VSBHO
0
0
ADVANCE BY
0.5 LINE
NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]
The default value of NVBEG is 00101, indicating the NTSC
Vsync begin position.
1
ADVANCE BY
0.5 LINE
VSYNC BEGIN
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
04983-0-023
1
VSBHE
Figure 23. NTSC Vsync Begin
Rev. B | Page 43 of 104
ADV7189B
1
NVENDSIGN
ADVANCE END OF
VSYNC BY NVEND[4:0]
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
0
NFTOGDELO NTSC Field Toggle Delay on Odd Field,
Address 0xE7[7]
DELAY END OF VSYNC
BY NVEND[4:0]
When NFTOGDELO is 0 (default), there is no delay.
NOT VALID FOR USER
PROGRAMMING
NO
Setting NFTOGDELO to 1 delays the field toggle/transition
on an odd field by a line relative to NFTOG.
NVENDDELE
NFTOGDELE NTSC Field Toggle Delay on Even Field,
Address 0xE7[6]
ODD FIELD?
YES
NVENDDELO
When NFTOGDELE is 0 (default), there is no delay.
1
0
0
ADDITIONAL
DELAY BY
1 LINE
1
Setting NFTOGDELE to 1 delays the field toggle/transition on
an even field by a line relative to NFTOG.
ADDITIONAL
DELAY BY
1 LINE
1
VSEHO
1
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
VSEHE
0
0
NFTOGSIGN
0
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
1
NOT VALID FOR USER
PROGRAMMING
ADVANCE BY
0.5 LINE
VSYNC END
ODD FIELD?
04983-0-024
ADVANCE BY
0.5 LINE
YES
NO
NFTOGDELO
NFTOGDELE
Figure 24. NTSC Vsync End
0
0
ADDITIONAL
DELAY BY
1 LINE
When NVENDDELO is 0 (default), there is no delay.
Setting NVENDDELO to 1 delays Vsync from going low on
an odd field by a line relative to NVEND.
1
ADDITIONAL
DELAY BY
1 LINE
FIELD
TOGGLE
NVENDDELE NTSC Vsync End Delay on Even Field,
Address 0xE6[6]
Figure 25. NTSC FIELD Toggle
NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7[5]
When NVENDDELE is set to 0 (default), there is no delay.
Setting NFTOGSIGN to 0 delays the field transition. Set for
user manual programming.
Setting NVENDDELE to 1 delays Vsync from going low on
an even field by a line relative to NVEND.
NVENDSIGN NTSC Vsync End Sign, Address 0xE6[5]
Setting NFTOGSIGN to 1 (default) advances the field
transition. Not recommended for user programming.
Setting NVENDSIGN to 0 (default) delays the end of Vsync.
Set for user manual programming .
NFTOG[4:0] NTSC Field Toggle, Address 0xE7[4:0]
Setting NVENDSIGN to 1 advances the end of Vsync. Not
recommended for user programming.
NVEND NTSC[4:0] Vsync End, Address 0xE6[4:0]
The default value of NVEND is 00100, indicating the NTSC
Vsync end position.
04983-0-025
1
NVENDDELO NTSC Vsync End Delay on Odd Field,
Address 0xE6[7]
The default value of NFTOG is 00011, indicating the
NTSC Field toggle position.
For all NTSC/PAL FIELD timing controls, both the F bit
in the AV code and the FIELD signal on the FIELD
pin are modified.
Rev. B | Page 44 of 104
ADV7189B
Table 57. Recommended User Settings for PAL (See Figure 27)
215H
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
Register Name
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Position. Control 1
Hsync Position. Control 2
Hsync Position. Control 3
Polarity
PAL_V_Bit_Beg
PAL_V_Bit_End
PAL_F_Bit_Tog
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0x29
0x41
0x84
0x06
FIELD 1
622
623
624
625
1
2
3
4
5
6
7
8
9
10
22
23
24
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
PVEND[4:0] = 0x4
F
PFTOG[4:0] = 0x3
FIELD 2
310
311
312
313
314
315
316
317
318
319
320
321
322
335
336
337
OUTPUT
VIDEO
H
V
PVEND[4:0] = 0x4
04983-0-026
PVBEG[4:0] = 5
F
PFTOG[4:0] = 0x3
Figure 26. PAL Default (BT.656). The polarity of H, V, and F is embedded in the data.
Rev. B | Page 45 of 104
ADV7189B
FIELD 1
622
623
624
1
625
2
3
4
5
6
7
8
9
10
11
23
24
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
FIELD
OUTPUT
PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
FIELD 2
310
311
312
314
313
315
316
317
318
319
320
321
322
323
336
337
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
04983-0-027
PVBEG[4:0] = 0x1
FIELD
OUTPUT
Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in Table 57
216H
1
PVBEGSIGN
PVBEGDELO PAL Vsync Begin Delay on Odd Field,
Address 0xE8[7]
0
When PVBEGDELO is 0 (default), there is no delay.
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
NOT VALID FOR USER
PROGRAMMING
PVBEGDELE PAL Vsync Begin Delay on Even Field,
Address 0xE8[6]
ODD FIELD?
YES
Setting PVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to PVBEG.
NO
When PVBEGDELE is 0, there is no delay.
PVBEGDELO
1
Setting PVBEGDELE to 1 (default) delays Vsync going high on
an even field by a line relative to PVBEG.
PVBEGDELE
0
0
ADDITIONAL
DELAY BY
1 LINE
1
PVBEGSIGN PAL Vsync Begin Sign, Address 0xE8[5]
Setting PVBEGSIGN to 0 delays the beginning of Vsync. Set for
user manual programming.
ADDITIONAL
DELAY BY
1 LINE
Setting PVBEGSIGN to 1 (default) advances the beginning of
Vsync. Not recommended for user programming.
VSBHO
VSBHE
PVBEG[4:0] PAL Vsync Begin, Address 0xE8[4:0]
0
0
ADVANCE BY
0.5 LINE
The default value of PVBEG is 00101, indicating the PAL Vsync
begin position.
1
ADVANCE BY
0.5 LINE
VSYNC BEGIN
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
04983-0-028
1
Figure 28. PAL Vsync Begin
Rev. B | Page 46 of 104
ADV7189B
1
PVENDSIGN
ADVANCE END OF
VSYNC BY PVEND[4:0]
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
0
PFTOGDELO PAL Field Toggle Delay on Odd Field,
Address 0xEA[7]
DELAY END OF VSYNC
BY PVEND[4:0]
When PFTOGDELO is 0 (default), there is no delay.
NOT VALID FOR USER
PROGRAMMING
Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.
ODD FIELD?
YES
NO
PVENDDELO
PFTOGDELE PAL Field Toggle Delay on Even Field,
Address 0xEA[6]
PVENDDELE
When PFTOGDELE is 0, there is no delay.
1
0
0
ADDITIONAL
DELAY BY
1 LINE
1
Setting PFTOGDELE to 1 (default) delays the F toggle/
transition on an even field by a line relative to PFTOG.
ADDITIONAL
DELAY BY
1 LINE
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA[5]
Setting PFTOGSIGN to 0 delays the field transition. Set for user
manual programming.
VSEHO
0
0
ADVANCE BY
0.5 LINE
Setting PFTOGSIGN to 1 (default) advances the field transition.
Not recommended for user programming.
1
PFTOG PAL Field Toggle, Address 0xEA[4:0]
ADVANCE BY
0.5 LINE
VSYNC END
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
04983-0-029
1
VSEHE
For all NTSC/PAL field timing controls, the F bit in the AV
code and the Field signal on the FIELD/DE pin are modified.
Figure 29. PAL Vsync End
PVENDDELO PAL Vsync End Delay on Odd Field,
Address 0xE9[7]
1
When PVENDDELO is 0 (default), there is no delay.
PFTOGSIGN
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
Setting PVENDDELO to 1 delays Vsync going low on an odd
field by a line relative to PVEND.
PVENDDELE PAL Vsync End Delay on Even Field,
Address 0xE9[6]
0
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES
NO
PFTOGDELO
PFTOGDELE
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays Vsync going low on an even
field by a line relative to PVEND.
1
0
0
1
PVENDSIGN PAL Vsync End Sign, Address 0xE9[5]
Setting PVENDSIGN to 1 advances the end of Vsync.
Not recommended for user programming.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
FIELD
TOGGLE
PVEND[4:0] PAL Vsync End, Address 0xE9[4:0]
Figure 30. PAL F Toggle
The default value of PVEND is 10100, indicating the PAL Vsync
end position.
Rev. B | Page 47 of 104
04983-0-030
Setting PVENDSIGN to 0 (default) delays the end of Vsync.
Set for user manual programming.
ADV7189B
SYNC PROCESSING
The ADV7189B has two additional sync processing blocks that
postprocess the raw synchronization information extracted from
the digitized input video. If desired, the blocks can be disabled via
the following two I2C bits.
The Gemstar-compatible data is not available in the I2C
registers, and is inserted into the data stream only during
horizontal blanking.
WSSD Wide Screen Signaling Detected, Address 0x90[0]
ENHSPLL Enable Hsync Processor, Address 0x01[6]
Logic 1 for this bit indicates the data in the WSS1 and WSS2
registers is valid.
The Hsync processor is designed to filter incoming Hsyncs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
Setting ENHSPLL to 0 disables the Hsync processor.
When WSSD is 0, no WSS is detected and confidence in the
decoded data is low.
Setting ENHSPLL to 1 (default) enables the Hsync processor.
ENVSPROC Enable Vsync Processor, Address 0x01[3]
This block provides extra filtering of the detected Vsyncs to give
improved vertical lock.
Setting ENVSPROC to 0 disables the Vsync processor.
Setting ENVSPROC to 1 (default) enables the Vsync processor.
VBI DATA DECODE
The following low data rate VBI signals can be decoded by the
ADV7189B:
•
Wide screen signaling (WSS)
•
Copy generation management systems (CGMS)
•
Closed captioning (CC)
•
EDTV
•
Gemstar 1× and 2× compatible data recovery
CCAPD Closed Caption Detected, Address 0x90[1]
Logic 1 for this bit indicates the data in the CCAP1 and CCAP2
registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When CCAPD is 0, no CCAP signals are detected and
confidence in the decoded data is low.
When CCAPD is 1, the CCAP sequence is detected and
confidence in the decoded data is high.
EDTVD EDTV Sequence Detected, Address 0x90[2]
Logic 1 for this bit indicates the data in the EDTV1, 2, 3
registers is valid.
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this
testing is contained in a confidence bit in the VBI Info[7:0]
register. Users are encouraged to first examine the VBI Info
register before reading the corresponding data registers. All
VBI data decode bits are read-only.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
All VBI data registers are double-buffered with the field signals. This means that data is extracted from the video lines
and appears in the appropriate I2C registers with the next
field transition. They are then static until the next field.
The user should start an I2C read sequence with VS by first
examining the VBI Info register. Then, depending on what data
was detected, the appropriate data registers should be read.
The data registers are filled with decoded VBI data even if their
corresponding detection bits are low; it is likely that bits within
the decoded data stream are wrong.
The closed captioning data (CCAP) is available in the I2C
registers, and is also inserted into the output video data
stream during horizontal blanking.
When WSSD is 1, WSS is detected and confidence in the
decoded data is high.
When EDTVD is 0, no EDTV sequence is detected. Confidence
in decoded data is low.
When EDTVD is 1, an EDTV sequence is detected. Confidence
in decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90[3]
Logic 1 for this bit indicates the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
When CGMSD is 0, no CGMS transmission is detected and
confidence in the decoded data is low.
When CGMSD is 1, the CGMS sequence is decoded and
confidence in the decoded data is high.
Rev. B | Page 48 of 104
ADV7189B
Figure 31 shows the bit correspondence between the analog
video waveform and the WSS1/WSS2 registers. WSS2[7:6]
are undetermined and should be masked out by software.
CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2[2]
217H
For certain video sources, the CRC data bits can have an invalid
format. In such circumstances, the CRC checksum validation
procedure can be disabled. The CGMSD bit goes high if the
rising edge of the start bit is detected within a time window.
EDTV Data Registers
EDTV1[7:0], Address 0x93[7:0],
EDTV2[7:0], Address 0x94[7:0],
EDTV3[7:0], Address 0x95[7:0]
When CRC_ENABLE is 0, no CRC check is performed.
The CGMSD bit goes high if the rising edge of the start bit
is detected within a time window.
Figure 32 shows the bit correspondence between the analog
video waveform and the EDTV1/EDTV2/EDTV3 registers.
218H
When CRC_ENABLE is 1 (default), CRC checksum is used to
validate the CGMS sequence. The CGMSD bit goes high for a
valid checksum. ADI recommended setting.
EDTV3[7:6] are undetermined and should be masked out by
software. EDTV3[5] is reserved for future use and, for now,
contains a 0. The three LSBs of the EDTV waveform are
currently not supported.
Wide Screen Signaling Data
WSS1[7:0], Address 0x91[7:0], WSS2[7:0], Address
0x92[7:0]
WSS1[7:0]
0
RUN-IN
SEQUENCE
1
2
3
4
5
WSS2[5:0]
6
7
0
1
2
3
4
5
START
CODE
ACTIVE
VIDEO
04983-0-031
11.0μs
38.4μs
42.5μs
Figure 31. WSS Data Extraction
Table 58. WSS Access Information
Signal Name
WSS1[7:0]
WSS2[5:0]
Register Location
WSS 1[7:0]
WSS 2[5:0]
Address
145d
0x91
146d
0x92
EDTV1[7:0]
0
1
EDTV2[7:0]
Register Default Value
Readback Only
Readback Only
EDTV3[5:0]
2
NOT SUPPORTED
4
5
6
7
0
1 2 3 4
5
6 7
0
1 2
3
4
5
04983-0-032
3
Figure 32. EDTV Data Extraction
Table 59. EDTV Access Information
Signal Name
EDTV1[7:0]
EDTV2[7:0]
EDTV3[7:0]
Register Location
EDTV 1[7:0]
EDTV 2[7:0]
EDTV 3[7:0]
147d
148d
149d
Address
0x93
0x94
0x95
Rev. B | Page 49 of 104
Register Default Value
Readback Only
Readback Only
Readback Only
ADV7189B
Closed Caption Data Registers
CCAP1[7:0], Address 0x99[7:0],
CCAP2[7:0], Address 0x9A[7:0]
CGMS Data Registers
CGMS1[7:0], Address 0x96[7:0],
CGMS2[7:0], Address 0x97[7:0],
CGMS3[7:0], Address 0x98[7:0]
Figure 34 shows the bit correspondence between the analog
video waveform and the CCAP1/CCAP2 registers. CCAP1[7]
contains the parity bit from the first word. CCAP2[7] contains
the parity bit from the second word. Refer to the GDECAD
Gemstar Decode Ancillary Data Format, Address 0x4C[0]
section.
20H
Figure 33 shows the bit correspondence between the analog
video waveform and the CGMS1/CGMS2/CGMS3 registers.
CGMS3[7:4] are undetermined and should be masked out
by software.
219H
+100 IRE
REF
CGMS1[7:0]
+70 IRE
0
1
2
3
4
5
CGMS2[7:0]
6
7
0
1
2
3
4
CGMS3[3:0]
5
6
7
0
1
2
3
0 IRE
04983-0-033
49.1μs ± 0.5μs
–40 IRE
11.2μs
CRC SEQUENCE
2.235μs ± 20ns
Figure 33. CGMS Data Extraction
Table 60. CGMS Access Information
Register Location
CGMS 1[7:0]
CGMS 2[7:0]
CGMS 3[3:0]
150d
151d
152d
10.5 ± 0.25μs
Address
0x96
0x97
0x98
Register Default Value
Readback Only
Readback Only
Readback Only
12.91μs
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
CCAP2[7:0]
CCAP1[7:0]
S
T
A
R
T
50 IRE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
BYTE 0
40 IRE
P
A
R
I
T
Y
P
A
R
I
T
Y
BYTE 1
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003μs
27.382μs
33.764μs
Figure 34. Closed-Caption Data Extraction
Table 61. CCAP Access Information
Signal Name
CCAP1[7:0]
CCAP2[7:0]
Register Location
CCAP 1[7:0]
CCAP 2[7:0]
153d
154d
Address
0x99
0x9A
Rev. B | Page 50 of 104
Register Default Value
Readback Only
Readback Only
04983-0-034
Signal Name
CGMS1[7:0]
CGMS2[7:0]
CGMS3[3:0]
ADV7189B
Letterbox Detection
Incoming video signals may conform to different aspect ratios
(16:9 wide screen of 4:3 standard). For certain transmissions in
the wide screen format, a digital sequence (WSS) is transmitted
with the video signal. If a WSS sequence is provided, the aspect
ratio of the video can be derived from the digitally decoded bits
WSS contains.
In the absence of a WSS sequence, letterbox detection can
be used to find wide screen signals. The detection algorithm
examines the active video content of lines at the start and end
of a field. If black lines are detected, this may indicate the
currently shown picture is in wide screen format.
The active video content (luminance magnitude) over a line of
video is summed together. At the end of a line, this accumulated
value is compared with a threshold, and a decision is made as to
whether or not a particular line is black. The threshold value
needed may depend on the type of input signal; some control
is provided via LB_TH[4:0].
Detection at the Start of a Field
The ADV7189B expects a section of at least six consecutive
black lines of video at the top of a field. Once those lines are
detected, Register LB_LCT[7:0] reports back the number of
black lines that were actually found. By default, the ADV7189B
starts looking for those black lines in sync with the beginning of
active video, for example, straight after the last VBI video line.
LB_SL[3:0] allows the user to set the start of letterbox detection
from the beginning of a frame on a line-by-line basis. The
detection window closes in the middle of the field.
There is no letterbox detected bit. The user is asked to read the
LB_LCT[7:0] and LB_LCB[7:0] register values and to conclude
whether or not the letterbox-type video is present in software.
LB_LCT[7:0] Letterbox Line Count Top, Address
0x9B[7:0]; LB_LCM[7:0] Letterbox Line Count Mid,
Address 0x9C[7:0]; LB_LCB[7:0] Letterbox Line Count
Bottom, Address 0x9D[7:0]
Table 62. LB_LCx Access Information
Signal Name
LB_LCT[7:0]
LB_LCM[7:0]
LB_LCB[7:0]
Address
0x9B
0x9C
0x9D
Register Default Value
Readback only
Readback only
Readback only
LB_TH[4:0] Letterbox Threshold Control, Address
0xDC[4:0]
Table 63. LB_TH Function
LB_TH[4:0]
01100
(default)
01101 to
10000
00000 to
01011
Description
Default threshold for detection of black lines.
Increase threshold (need larger active video
content before identifying nonblack lines).
Decrease threshold (even small noise levels can
cause the detection of nonblack lines).
LB_SL[3:0] Letterbox Start Line, Address 0xDD[7:4]
The LB_SL[3:0] bits are set at 0100b by default. This means the
letterbox detection window starts after the EDTV VBI data line.
For an NTSC signal this window is from Line 23 to Line 286.
Changing the bits to 0101, the detection window starts on
Line 24 and ends on Line 287.
Detection at the End of a Field
LB_EL[3:0] Letterbox End Line, Address 0xDD[3:0]
The ADV7189B expects at least six continuous lines of black
video at the bottom of a field before reporting back the number
of lines actually found via the LB_LCB[7:0] value. The activity
window for letterbox detection (end of field) starts in the middle
of an active field. Its end is programmable via LB_EL[3:0].
The LB_EL[3:0] bits are set at 1101b by default. This means the
letterbox detection window ends with the last active video line.
For an NTSC signal, this window is from Line 262 to Line 525.
Detection at the Midrange
Some transmissions of wide screen video include subtitles
within the lower black box. If the ADV7189B finds at least two
black lines followed by more nonblack video, for example, the
subtitle, and is then followed by the remainder of the bottom
black block, it reports back a midcount via LB_LCM[7:0]. If no
subtitles are found, LB_LCM[7:0] reports the same number as
LB_LCB[7:0].
Changing the bits to 1100, the detection window starts on
Line 261 and ends on Line 254.
Gemstar Data Recovery
The Gemstar-compatible data recovery block (GSCD) supports
1× and 2× data transmissions. In addition, it can serve as a
closed-caption decoder. Gemstar-compatible data transmissions
can occur only in NTSC. Closed-caption data can be decoded
in both PAL and NTSC.
There is a 2-field delay in the reporting of any line count
parameters.
Rev. B | Page 51 of 104
ADV7189B
Each data packet starts immediately after the EAV code of the
preceding line.
The block is configured via I2C in the following ways:
2H
GDECEL[15:0] allow data recovery on selected video lines
on even fields to be enabled and disabled.
•
GDECOL[15:0] enable the data recovery on selected lines
for odd fields.
•
GDECAD configures the way in which data is embedded
in the video data stream.
Figure 35 and Table 64 show the overall structure of the data
packet.
23H
Entries within the packet are as follows:
The recovered data is not available through I2C, but is being
inserted into the horizontal blanking period of an
ITU-R. BT656-compatible data stream. The data format
is intended to comply with the recommendation by the
International Telecommunications Union, ITU-R BT.1364.
See Figure 35. For more information, see the ITU website
at www.itu.ch.
•
Fixed preamble sequence of 0x00, 0xFF, 0xFF.
•
Data identification word (DID). The value for the DID
marking a Gemstar or CCAP data packet is 0x140 (10-bit
value).
•
Secondary data identification word (SDID), which contains
information about the video line from which data was
retrieved, whether the Gemstar transmission was of 1× or
2× format, and whether it was retrieved from an even or
odd field.
•
Data count byte, giving the number of user data-words that
follow.
•
User data section.
•
Optional padding to ensure that the length of the user
data-word section of a packet is a multiple of four bytes
(requirement as set in ITU-R BT.1364).
•
Checksum byte.
21H
The format of the data packet depends on the following criteria:
•
Transmission is 1× or 2×.
•
Data is output in 8-bit or 4-bit format (see the description
of the GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C[0] bit).
• Data is closed caption (CCAP) or Gemstar compatible.
Data packets are output if the corresponding enable bit is set
(see the GDECEL and GDECOL descriptions), and if the
decoder detects the presence of data. This means for video
lines where no data has been decoded, no data packet is
output even if the corresponding line enable bit is set.
DATA IDENTIFICATION
00
FF
FF
DID
Table 64 lists the values within a generic data packet that is
output by the ADV7189B in 10-bit format.
24H
SECONDARY DATA IDENTIFICATION
SDID
DATA
COUNT
PREAMBLE FOR ANCILLARY DATA
OPTIONAL PADDING
BYTES
USER DATA
CHECK
SUM
04983-0-035
•
USER DATA (4 OR 8 WORDS)
Figure 35. Gemstar and CCAP Embedded Data Packet (Generic)
Table 64. Generic Data Output Packet
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D[9]
0
1
1
0
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
D[8]
0
1
1
1
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
D[7]
0
1
1
0
EF
0
0
0
0
0
0
0
0
0
CS[7]
D[6]
0
1
1
1
2X
0
0
0
0
0
0
0
0
0
CS[6]
D[5]
0
1
1
0
0
CS[5]
D[4]
0
1
1
0
D[3]
0
1
1
0
Line[3:0]
0
DC[1]
Word1[7:4]
Word1[3:0]
Word2[7:4]
Word2[3:0]
Word3[7:4]
Word3[3:0]
Word4[7:4]
Word4[3:0]
CS[4]
CS[3]
Rev. B | Page 52 of 104
D[2]
0
1
1
0
DC[0]
CS[2]
D[1]
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
D[0]
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count (DC)
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
Checksum
ADV7189B
Table 65. Data Byte Allocation
2×
1
1
0
0
Raw Information Bytes
Retrieved from the Video Line
4
4
2
2
GDECAD
0
1
0
1
•
Gemstar Bit Names
•
DID. The data identification value is 0x140 (10-bit value).
Care has been taken that in 8-bit systems, the 2 LSBs do
not carry vital information.
•
EP and !EP. The EP bit is set to ensure even parity on the
data-word D[8:0]. Even parity means there is always an
even number of 1s within the D[8:0] bit arrangement.
This includes the EP bit. !EP describes the logic inverse of
EP and is output on D[9]. The !EP is output to ensure that
the reserved codes of 00 and FF cannot happen.
•
•
•
EF. Even field identifier. EF = 1 indicates that the data was
recovered from a video line on an even field.
DC[1:0]
10
01
01
01
CS[8:2]. The checksum is provided to determine the
integrity of the ancillary data packet. It is calculated by
summing up D[8:2] of DID, SDID, the Data Count byte,
and all UDWs, and ignoring any overflow during the
summation. Since all data bytes that are used to calculate
the checksum have their 2 LSBs set to 0, the CS[1:0] bits
are also always 0.
!CS[8] describes the logic inversion of CS[8]. The value
!CS[8] is included in the checksum entry of the data packet
to ensure that the reserved values of 0x00 and 0xFF do not
occur.
Table 66 to Table 69 outline the possible data packages.
28H
29H
Line[3:0]. This entry provides a unique code for each of the
possible 16 source lines of video from which Gemstar data
may have been retrieved. See Table 74 and Table 75.
Half-byte output mode is selected by setting CDECAD = 0;
full-byte output mode is selected by setting CDECAD = 1.
See the GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section.
230H
26H
DC[1:0]. Data count value. The number of user data-words
in the packet divided by 4. The number of user data-words
(UDW) in any packet must be an integral number of 4.
Padding is required at the end if necessary (requirement
as set in ITU-R BT.1364). See Table 65.
Gemstar 1× Format
Half-byte output mode is selected by setting CDECAD = 0,
full-byte output mode is selected by setting CDECAD = 1.
See the GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section.
27H
•
Padding Bytes
0
0
0
2
Gemstar 2× Format, Half-Byte Output
2×. This bit indicates whether the data sliced was in
Gemstar 1× or 2× format. A high indicates 2× format.
25H
•
User Data-Words
(Including Padding)
8
4
4
4
The 2× bit determines whether the raw information
retrieved from the video line was 2 or 4 bytes. The state
of the GDECAD bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes)
or whether they are split into nibbles (that is, two bytes
transmitted as four half bytes). Padding bytes are then
added where necessary.
Rev. B | Page 53 of 104
231H
ADV7189B
Table 66. Gemstar 2× Data, Half-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D[9]
0
1
1
0
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
D[8]
0
1
1
1
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
D[7]
0
1
1
0
EF
0
0
0
0
0
0
0
0
0
CS[7]
D[6]
0
1
1
1
1
0
0
0
0
0
0
0
0
0
CS[6]
D[5]
0
1
1
0
0
CS[5]
D[4]
0
1
1
0
D[3]
0
1
1
0
Line[3:0]
0
1
Gemstar word1[7:4]
Gemstar word1[3:0]
Gemstar word2[7:4]
Gemstar word2[3:0]
Gemstar word3[7:4]
Gemstar word3[3:0]
Gemstar word4[7:4]
Gemstar word4[3:0]
CS[4]
CS[3]
D[2]
0
1
1
0
0
CS[2]
D[1]
0
1
1
0
0
0
0
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
Checksum
Table 67. Gemstar 2× Data, Full-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
D[8]
0
1
1
1
EP
EP
D[7]
0
1
1
0
EF
0
!CS[8]
CS[8]
CS[7]
D[6]
D[5]
0
0
1
1
1
1
1
0
1
0
0
Gemstar Word1[7:0]
Gemstar Word2[7:0]
Gemstar Word3[7:0]
Gemstar Word4[7:0]
CS[6]
CS[5]
D[4]
D[3]
0
0
1
1
1
1
0
0
Line[3:0]
0
0
D[2]
0
1
1
0
CS[4]
CS[2]
CS[3]
1
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
User data-words
User data-words
Checksum
Table 68. Gemstar 1× Data, Half-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
D[8]
0
1
1
1
EP
EP
EP
EP
EP
EP
CS[8]
D[7]
0
1
1
0
EF
0
0
0
0
0
CS[7]
D[6]
0
1
1
1
0
0
0
0
0
0
CS[6]
D[5]
0
1
1
0
0
CS[5]
D[4]
0
1
1
0
D[3]
0
1
1
0
Line[3:0]
0
0
Gemstar Word1[7:4]
Gemstar Word1[3:0]
Gemstar Word2[7:4]
Gemstar Word2[3:0]
CS[4]
CS[3]
Rev. B | Page 54 of 104
D[2]
0
1
1
0
1
CS[2]
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
User data-words
User data-words
Checksum
ADV7189B
Table 69. Gemstar 1× Data, Full-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
D[8]
0
1
1
1
EP
EP
D[7]
0
1
1
0
EF
0
1
1
!CS[8]
0
0
CS[8]
0
0
CS[7]
D[6]
D[5]
0
0
1
1
1
1
1
0
0
0
0
Gemstar Word1[7:0]
Gemstar Word2[7:0]
0
0
0
0
CS[6]
CS[5]
D[4]
0
1
1
0
0
D[3]
0
1
1
0
Line[3:0]
0
0
0
CS[4]
0
0
CS[3]
D[2]
0
1
1
0
1
0
0
CS[2]
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
Table 70. NTSC CCAP Data, Half-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
D[8]
0
1
1
1
EP
EP
EP
EP
EP
EP
CS[8]
D[7]
0
1
1
0
EF
0
0
0
0
0
CS[7]
D[6]
0
1
1
1
0
0
0
0
0
0
CS[6]
D[5]
0
1
1
0
1
0
CS[5]
D[4]
D[3]
0
0
1
1
1
1
0
0
0
1
0
0
CCAP Word1[7:4]
CCAP Word1[3:0]
CCAP Word2[7:4]
CCAP Word2[3:0]
CS[4]
CS[3]
D[2]
0
1
1
0
1
1
CS[2]
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
User data-words
User data-words
Checksum
Table 71. NTSC CCAP Data, Full-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
D[8]
0
1
1
1
EP
EP
D[7]
0
1
1
0
EF
0
1
1
!CS[8]
0
0
CS[8]
0
0
CS[7]
D[6]
D[5]
0
0
1
1
1
1
1
0
0
1
0
0
CCAP Word1[7:0]
CCAP Word2[7:0]
0
0
0
0
CS[6]
CS[5]
D[4]
0
1
1
0
0
0
D[3]
0
1
1
0
1
0
D[2]
0
1
1
0
1
1
0
0
CS[4]
0
0
CS[3]
0
0
CS[2]
Rev. B | Page 55 of 104
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
ADV7189B
PAL CCAP Data
NTSC CCAP Data
Half-byte output mode is selected by setting CDECAD = 0; the
full-byte mode is enabled by CDECAD = 1. See the GDECAD
Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section. The data packet formats are shown in
Table 70 and Table 71.
Half-byte output mode is selected by setting CDECAD = 0;
full-byte output mode is selected by setting CDECAD = 1.
See the GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C[0] section. Table 72 and Table 73 list the bytes
of the data packet.
NTSC closed-caption data is sliced on line 21d on even and odd
fields. The corresponding enable bit has to be set high. See the
section and the GDECOL[15:0] Gemstar Decoding Odd Lines,
Address 0x4A[7:0]; Address 0x4B[7:0]section.
PAL closed-caption data is sliced from Lines 22 and 335. The
corresponding enable bits have to be set.
23H
23H
234H
235H
236H
237H
238H
See the GDECEL[15:0] Gemstar Decoding Even Lines,
Address 0x48[7:0]; Address 0x49[7:0] section and the
GDECOL[15:0] Gemstar Decoding Odd Lines,
Address 0x4A[7:0]; Address 0x4B[7:0]section.
239H
240H
Table 72. PAL CCAP Data, Half-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
D[8]
0
1
1
1
EP
EP
EP
EP
EP
EP
CS[8]
D[7]
0
1
1
0
EF
0
0
0
0
0
CS[7]
D[6]
0
1
1
1
0
0
0
0
0
0
CS[6]
D[5]
0
1
1
0
1
0
CS[5]
D[4]
D[3]
0
0
1
1
1
1
0
0
0
1
0
0
CCAP Word1[7:4]
CCAP Word1[3:0]
CCAP Word2[7:4]
CCAP Word2[3:0]
CS[4]
CS[3]
D[2]
0
1
1
0
0
1
CS[2]
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
User data-words
User data-words
Checksum
Table 73. PAL CCAP Data, Full-Byte Mode
Byte
0
1
2
3
4
5
6
7
8
9
10
D[9]
0
1
1
0
!EP
!EP
D[8]
0
1
1
1
EP
EP
D[7]
0
1
1
0
EF
0
1
1
!CS[8]
0
0
CS[8]
0
0
CS[7]
D[6]
D[5]
0
0
1
1
1
1
1
0
0
1
0
0
CCAP Word1[7:0]
CCAP Word2[7:0]
0
0
0
0
CS[6]
CS[5]
D[4]
0
1
1
0
0
0
D[3]
0
1
1
0
1
0
D[2]
0
1
1
0
0
1
0
0
CS[4]
0
0
CS[3]
0
0
CS[2]
Rev. B | Page 56 of 104
D[1]
0
1
1
0
0
0
0
0
0
0
CS[1]
D[0]
0
1
1
0
0
0
0
0
0
0
CS[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
SDID
Data count
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
ADV7189B
GDECEL[15:0] Gemstar Decoding Even Lines,
Address 0x48[7:0]; Address 0x49[7:0]
Table 74. NTSC Line Enable Bits and Corresponding Line
Numbering
The 16 bits of the GDECEL[15:0] are interpreted as a collection
of 16 individual line decode enable signals. Each bit refers to a
line of video in an even field. Setting a bit to 1 enables the decoder
block to retrieve Gemstar or closed caption-compatible data on
that particular line. Setting a bit to 0 prevents the decoder from
trying to retrieve data. See Table 74 and Table 75.
Line[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
Line Number
(ITU-R BT.470)
10
11
12
13
14
15
16
17
18
19
20
21
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
22
23
24
25
273 (10)
274 (11)
275 (12)
276 (13)
277 (14)
278 (15)
279 (16)
280 (17)
281 (18)
282 (19)
283 (20)
284 (21)
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
12
13
14
15
285 (22)
286 (23)
287 (24)
288 (25)
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
241H
24H
To retrieve closed-caption data services on NTSC (Line 284),
GDECEL[11] must be set.
To retrieve closed caption data services on PAL (Line 335),
GDECEL[14] must be set.
The default value of GDECEL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the even field.
GDECOL[15:0] Gemstar Decoding Odd Lines,
Address 0x4A[7:0]; Address 0x4B[7:0]
The 16 bits of the GDECOL[15:0] form a collection of 16
individual line decode enable signals. See Table 74 and
Table 75.To retrieve closed caption data services on NTSC (Line
21), GDECOL[11] must be set.
243H
24H
To retrieve closed-caption data services on PAL (Line 22),
GDECOL[14] must be set.
The default value of GDEC0L[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the odd field.
GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C[0]
The decoded data from Gemstar-compatible transmissions
or closed-caption transmission is inserted into the horizontal
blanking period of the respective line of video. A potential
problem can arise if the retrieved data bytes have the value
0x00 or 0xFF. In an ITU-R BT.656-compatible data stream,
these values are reserved and used only to form a
fixed preamble.
The GDECAD bit allows the data to be inserted into the
horizontal blanking period in two ways:
•
Insert all data straight into the data stream, even the reserved
values of 0x00 and 0xFF, if they occur. This can violate the
output data format specification ITU-R BT.1364.
•
Split all data into nibbles and insert the half-bytes over
double the number of cycles in a 4-bit format.
When GDECAD is 0 (default), the data is split into half-bytes
and inserted.
When GDECAD is 1, the data is output straight in 8-bit format.
Rev. B | Page 57 of 104
Comment
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar or
closed caption
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar or
closed caption
Gemstar
Gemstar
Gemstar
Gemstar
ADV7189B
6
Table 75. PAL Line Enable Bits and
Corresponding Line Numbering
4
2
0
–2
–4
–6
04983-0-043
–8
–10
–12
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
Figure 36. NTSC IF Compensation Filter Responses
6
4
2
0
–2
–4
–6
–8
3.0
04983-0-045
Comment
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
AMPLITUDE (dB)
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
AMPLITUDE (dB)
Line[3:0]
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
Line Number
(ITU-R BT.470)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
321 (8)
322 (9)
323 (10)
324 (11)
325 (12)
326 (13)
327 (14)
328 (15)
329 (16)
330 (17)
331 (18)
332 (19)
333 (20)
334 (21)
335 (22)
336 (23)
3.5
4.0
4.5
5.0
5.5
6.0
FREQUENCY (MHz)
Figure 37. PAL IF Compensation Filter Responses
See Table 86 for programming details.
247H
I2C Interrupt System
P
P
The ADV7189B has a comprehensive interrupt register set. This
map is located in the Register Access. See Table 85 for details of
the interrupt register map. How to access this map is described
in Figure 38.
248H
249H
IF Compensation Filter
IFFILTSEL[2:0] IF Filter Select Address 0xF8[2:0]
COMMON I2C SPACE
ADDRESS 0x00 => 0x3F
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input as would be
observed on tuner outputs. Figure 36 and Figure 37 show IF
filter compensation for NTSC and PAL.
ADDRESS 0x0E BIT 6,5 = 00b
ADDRESS 0x0E BIT 6,5 = 01b
I2C SPACE
REGISTER ACCESS PAGE 1
ADDRESS 0x40 => 0xFF
I2C SPACE
REGISTER ACCESS PAGE 2
ADDRESS 0x40 => 0x4C
NORMAL REGISTER SPACE
INTERRUPT REGISTER SPACE
246H
The options for this feature are as follows:
•
Bypass Mode (default)
•
NTSC—consists of three filter characteristics
•
PAL—consists of three filter characteristics
Figure 38. Register Access, Page 1 and Page 2
Rev. B | Page 58 of 104
04983-0-044
245H
ADV7189B
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[1:0]
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0].
Table 77. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
00 (default)
01
10
11
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[7:6]
Table 76. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
00 (default)
01
10
11
Description
3 Xtal periods
15 Xtal periods
63 Xtal periods
Active until cleared
Description
Open drain
Drive low when active
Drive high when active
Reserved
Multiple Interrupt Events
When the active-until-Cleared interrupt duration is selected
and the event that caused the interrupt is no longer in force,
the interrupt persists until it is masked or cleared.
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7189B does not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits since more than one can be active.
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as follows:
For example, if the ADV7189B loses lock, an interrupt is
generated and the INTRQ pin goes low. If the ADV7189B
returns to the locked state, INTRQ continues to drive low
until the SD_LOCK bit is either masked or cleared.
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits
Address 0x40 (Interrupt Space)[5:4]
Interrupt Drive Level
Table 78. MV_INTRQ_SEL
The ADV7189B resets with open drain enabled and all
interrupts masked off. Therefore, INTRQ is in a high
impedance state after reset. 01 or 10 has to be written to
INTRQ_OP_SEL[1:0] for a logic level to be driven out
from the INTRQ pin.
MV_INTRQ_SEL[1:0]
00
01 (default)
10
11
It is also possible to write to a register in the ADV7189B that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
Description
Reserved
Pseudo sync only
Color stripe only
Either pseudo sync or color stripe
Additional information relating to the interrupt system is
detailed in Table 84.
Rev. B | Page 59 of 104
250H
ADV7189B
PIXEL PORT CONFIGURATION
The ADV7189B has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs.
Table 79 and Table 80 summarize the various functions that the
ADV7189B pins can have in different modes of operation.
SWPC Swap Pixel Cr/Cb, Address 0x27[7]
The ordering of components, for example, Cr vs. Cb,
CHA/B/C, can be changed. Refer to the SWPC Swap Pixel
Cr/Cb, Address 0x27[7] section. Table 79 indicates the default
positions for the Cr/Cb components.
When SWPC is 1, the Cr and Cb values can be swapped.
251H
This bit allows Cr and Cb samples to be swapped.
25H
When SWPC is 0 (default), no swapping is allowed.
253H
LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F[6:4]
254H
The following I2C write allows the user to select between the
LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7189B pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 80 for details.
The LLC2 signal is useful for LLC2-compatible wide bus
(16-/20-bit) output modes. See OF_SEL[3:0] for additional
information. The LLC2 signal and data on the data bus are
synchronized. By default, the rising edge of LLC1/LLC2 is
aligned with the Y data; the falling edge occurs when the data
bus holds C data. The polarity of the clock, and therefore the
Y/C assignments to the clock edges, can be altered by using
the Polarity LLC pin.
25H
The default LLC frequency output on the LLC1 pin is approximately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the
LLC1 pin stays at the higher rate of 27 MHz. For information
on outputting the nominal 13.5 MHz clock on the LLC1 pin,
see the LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F[6:4] section.
256H
When LLC_PAD_SEL[2:0] is 000 (default), the output is
nominally 27 MHz LLC on the LLC1 pin.
When LLC_PAD_SEL[2:0] is 101, the output is nominally
13.5 MHz LLC on the LLC1 pin.
Table 79. P19 to P0 Output/Input Pin Mapping
Processor, Format, and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 10-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Video Out, 20-Bit, 4:2:2
19
18
17
Data Port Pins P[19:0]
13 12 11 10 9 8
16 15 14
YCrCb[7:0] OUT
YCrCb[9:0] OUT
Y[7:0] OUT
Y[9:0] OUT
7
6
5
4
3
2
1
CrCb[7:0] OUT
CrCb[9:0] OUT
Table 80. Standard Definition Pixel Port Modes
Function
OF_SEL[3:0]
0000
0001
0010
0011 (default)
0110-1111
Format
10-Bit at LLC1 4:2:2
20-Bit at LLC2 4:2:2
16-Bit at LLC2 4:2:2
8-Bit at LLC1 4:2:2
Reserved
P[19:12]
YCrCb[9:2]
Y[9:2]
Y[7:0]
YCrCb[7:0]
Pixel Port Pins P[19:0]
P[19:10]
P[11:10]
P[9:2]
YCrCb[1:0]
Three-State
Y[1:0]
CrCb[9:2]
Three-state
CrCb[7:0]
Three-state
Three-state
Reserved. Do not use.
Rev. B | Page 60 of 104
P9[9:0]
P[1:0]
Three-State
CrCb[1:0]
Three-state
Three-state
0
ADV7189B
MPU PORT DESCRIPTION
The R/W bit determines the direction of the data. Logic 0 on
the LSB of the first byte means the master writes information
to the peripheral. Logic 1 on the LSB of the first byte means the
master reads information from the peripheral.
The ADV7189B supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK),
carry information between the ADV7189B and the system I2C
master controller. Each slave device is recognized by a unique
address. The ADV7189B’s I2C port allows the user to set up and
configure the decoder and to read back captured VBI data. The
ADV7189B has four possible slave addresses for both read and
write operations, depending on the logic level on the ALSB pin.
These four unique addresses are shown in Table 81. The
ADV7189B’s ALSB pin controls Bit 1 of the slave address. By
altering the ALSB, it is possible to control two ADV7189Bs in
an application without having a conflict with the same slave
address. The LSB (Bit 0) sets either a read or write operation.
Logic 1 corresponds to a read operation; Logic 0 corresponds to
a write operation.
The ADV7189B acts as a standard slave device on the bus.
The data on the SDA pin is eight bits long, supporting the
7-bit addresses plus the R/W bit. The ADV7189B has 249
subaddresses to enable access to the internal registers. It
therefore interprets the first byte as the device address and
the second byte as the starting subaddress. The subaddresses
auto-increment, allowing data to be written to or read from
the starting subaddress. A data transfer is always terminated
by a stop condition. The user can also access any unique
subaddress register on a one-by-one basis without having
to update all the registers.
257H
Table 81. I2C Address for ADV7189B
R/W
0
1
0
1
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7189B does
not issue an acknowledge and returns to the idle condition.
Slave Address
0x40
0x41
0x42
0x43
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition
on SDA while SCLK remains high. This indicates that an
address/data stream follows. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCLK lines, waiting for
the start condition and the correct transmitted address.
If in auto-increment mode the user exceeds the highest
subaddress, the following action is taken:
1.
In read mode, the highest subaddress register contents
continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A noacknowledge condition is when the SDA line is not pulled
low on the ninth pulse.
2.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7189B, and the part returns to the idle condition.
SDATA
SCLOCK
S
1–7
8
9
1–7
8
9
START ADDR R/W ACK SUBADDRESS ACK
1–7
DATA
8
9
P
ACK
STOP
04983-0-036
Figure 39. Bus Data Transfer
WRITE
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR
A(S)
DATA
LSB = 0
READ
SEQUENCE
S SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
DATA
A(S)
A(S) P
LSB = 1
SUB ADDR
A(S) S
SLAVE ADDR A(S)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
DATA
A(M)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 40. Read and Write Sequence
Rev. B | Page 61 of 104
DATA
A(M) P
04983-0-037
ALSB
0
0
1
1
ADV7189B
REGISTER ACCESSES
I2C SEQUENCER
The MPU can write to or read from most of the ADV7189B’s
registers, excepting the registers that are read-only or writeonly. The subaddress register determines which register the next
read or write operation accesses. All communications with the
part through the bus start with an access to the subaddress
register. Then, a read/write operation is performed from/to the
target address, which then increments to the next address until
a stop command on the bus is performed.
An I2C sequencer is used when a parameter exceeds eight bits,
and is therefore distributed over two or more I2C registers, for
example, HSB[11:0].
REGISTER PROGRAMMING
When such a parameter is changed using two or more I2C write
operations, the parameter can hold an invalid value for the time
between the first I2C being completed and the last I2C being
completed. In other words, the top bits of the parameter can
already hold the new value while the remaining bits of the
parameter still hold the previous value.
This section describes the configuration of each register. The
communications register is an 8-bit, write-only register. After
the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
Table 82 lists the various operations under the control of the
Subaddress register for the control port.
To avoid this problem, the I2C sequencer holds the already
updated bits of the parameter in local memory; all bits of the
parameter are updated together once the last register write
operation has completed.
Register Select (SR7–SR0)
•
All I2C registers for the parameter in question must be
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first followed by 0x35.
•
No other I2C taking place between the two (or more) I2C
writes for the sequence. For example, for HSB[10:0], write
to Address 0x34 first immediately followed by 0x35.
258H
The correct operation of the I2C sequencer relies on the
following:
These bits are set up to point to the required starting address.
Rev. B | Page 62 of 104
ADV7189B
I2C REGISTER MAPS
Table 82. Common and Normal (Page 1) Register Map Details
Register Name
Input Control
Video Selection
Reserved
Output Control
Extended Output Control
Reserved
Reserved
Autodetect Enable
Contrast
Reserved
Brightness
Hue
Default Value Y
Default Value C
ADI Control
Power Management
Status 1
Ident
Status 2
Status 3
Analog Clamp Control
Digital Clamp Control 1
Reserved
Shaping Filter Control
Shaping Filter Control 2
Comb Filter Control
Reserved
ADI Control 2
Reserved
Pixel Delay Control
Reserved
Misc Gain Control
AGC Mode Control
Chroma Gain Control 1
Chroma Gain Control 2
Luma Gain Control 1
Luma Gain Control 2
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Position Control 1
Hsync Position Control 2
Hsync Position Control 3
Polarity
NTSC Comb Control
PAL Comb Control
ADC Control
Reserved
Manual Window Control
Reset Value
0000 0000
1100 1000
0000 0100
0000 1100
01xx 0101
0000 0000
0000 0010
0111 1111
1000 0000
1000 0000
0000 0000
0000 0000
0011 0110
0111 1100
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0001 0010
0100 xxxx
xxxx xxxx
0000 0001
1001 0011
1111 0001
xxxx xxxx
0000 0xxx
xxxx xxxx
0101 1000
xxxx xxxx
1110 0001
1010 1110
1111 0100
0000 0000
1111 xxxx
xxxx xxxx
0001 0010
0100 0001
1000 0100
0000 0000
0000 0010
0000 0000
0000 0001
1000 0000
1100 0000
0001 0000
xxxx xxxx
0100 0011
Rev. B | Page 63 of 104
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Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 to 28
29
30 to 38
39
40 to 42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59 to 60
61
Subaddress
Hex
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A to 0x1C
0x1D
0x1E to 0x26
0x27
0x28 to 0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B to 0x3C
0x3D
ADV7189B
Register Name
Reserved
Resample Control
Reserved
Gemstar Ctrl 1
Gemstar Ctrl 2
Gemstar Ctrl 3
Gemstar Ctrl 4
GemStar Ctrl 5
CTI DNR Ctrl 1
CTI DNR Ctrl 2
Reserved
CTI DNR Ctrl 4
Lock Count
Reserved
Free Run Line Length 1
Reserved
VBI Info
WSS 1
WSS 2
EDTV 1
EDTV 2
EDTV 3
CGMS 1
CGMS 2
CGMS 3
CCAP 1
CCAP 2
Letterbox 1
Letterbox 2
Letterbox 3
Reserved
CRC Enable
Reserved
ADC Switch 1
ADC Switch 2
Reserved
Letterbox Control 1
Letterbox Control 2
Reserved
Reserved
Reserved
SD Offset Cb
SD Offset Cr
SD Saturation Cb
SD Saturation Cr
NTSC V Bit Begin
NTSC V Bit End
NTSC F Bit Toggle
PAL V Bit Begin
PAL V Bit End
PAL F Bit Toggle
Reserved
Reset Value
xxxx xxxx
0100 0001
xxxx xxxx
00000000
0000 0000
0000 0000
0000 0000
xxxx xxx0
1110 1111
0000 1000
xxxx xxxx
0000 1000
0010 0100
xxxx xxxx
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0001 1100
xxxx xxxx
xxxx xxxx
0xxx xxxx
xxxx xxxx
1010 1100
0100 1100
0000 0000
0000 0000
0001 0100
1000 0000
1000 0000
1000 0000
1000 0000
0010 0101
0000 0100
0110 0011
0110 0101
0001 0100
0110 0011
xxxx xxxx
Rev. B | Page 64 of 104
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Dec
62 to 64
65
66 to 71
72
73
74
75
76
77
78
79
80
81
82 to 142
143
144
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158 to 177
178
179 to 194
195
196
197 to 219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235 to 243
Subaddress
Hex
0x3E to 0x40
0x41
0x42 to 0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52 to 0x8E
0x8F
0x90
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E to 0xB1
0xB2
0xB2 to 0xC2
0xC3
0xC4
0xC5 to 0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB to 0xF3
ADV7189B
Register Name
Drive Strength
Reserved
IF Comp Control
VS Mode Control
Reset Value
xx01 0101
xxxx xxxx
0000 0000
0000 0000
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Dec
244
245 to 247
248
249
Subaddress
Hex
0xF4
0xF5 to 0xF7
0xF8
0xF9
Table 83. Common and Normal (Page 1) Register Map Bit Names
Register Name
Input Control
Video Selection
Reserved
Output Control
Extended
Output Control
Reserved
Reserved
Autodetect
Enable
Contrast
Reserved
Brightness
Hue
Default Value Y
Default Value C
ADI Control
Power
Management
Status 1
Ident
Status 2
Status 3
Analog Clamp
Control
Digital Clamp
Control 1
Reserved
Shaping Filter
Control
Shaping Filter
Control 2
Comb Filter
Control
Reserved
ADI Control 2
Reserved
Pixel Delay
Control
Reserved
Misc Gain
Control
AGC Mode
Control
Chroma Gain
Control 1
Chroma Gain
Control 2
Luma Gain
Control 1
Luma Gain
Control 2
Vsync Field
Control 1
Bit 7
VID_SEL.3
Bit 6
VID_SEL.2
ENHSPLL
Bit 5
VID_SEL.1
BETACAM
Bit 4
VID_SEL.0
Bit 3
INSEL.3
ENVSPROC
Bit 2
INSEL.2
Bit 1
INSEL.1
Bit 0
INSEL.0
VBI_EN
BT656-4
TOD
OF_SEL.3
OF_SEL.2
OF_SEL.1
TIM_OE
OF_SEL.0
BL_C_VBI
EN_SFL_PI
SD_DUP_AV
RANGE
AD_SEC525_EN
AD_SECAM_EN
AD_N443_EN
AD_P60_EN
AD_PALN_EN
AD_PALM_EN
AD_NTSC_EN
AD_PAL_EN
CON.7
CON.6
CON.5
CON.4
CON.3
CON.2
CON.1
CON.0
BRI.7
HUE.7
DEF_Y.5
BRI.6
HUE.6
DEF_Y.4
BRI.5
HUE.5
DEF_Y.3
BRI.4
HUE.4
DEF_Y.2
BRI.3
HUE.3
DEF_Y.1
BRI.2
HUE.2
DEF_Y.0
BRI.0
HUE.0
DEF_VAL_EN
DEF_C.7
DEF_C.6
DEF_C.5
DEF_C.4
SUB_USR_EN.0
DEF_C.3
DEF_C.2
BRI.1
HUE.1
DEF_VAL_AUTO
_EN
DEF_C.1
RES
PWRDN
COL_KILL
IDENT.7
AD_RESULT.2
IDENT.6
PAL SW LOCK
INTERLACE
AD_RESULT.1
IDENT.5
FSC NSTD
STD FLD LEN
DCT.1
DCT.0
CSFM.1
CSFM.0
CSFM.2
WYSFMOVR
TRI_LLC
EN28XTAL
VS_JIT_COMP_EN
SWPC
AUTO_PDC_EN
CTA.2
PDBP
AD_RESULT.0
IDENT.4
LL NSTD
FREE_RUN_ACT
CCLEN
FOLLOW_PW
IDENT.3
MV AGC DET
FSC_LOCK
IDENT.2
MV PS DET
SD_OP_50HZ
LOST_LOCK
IDENT.1
MVCS T3
GEMD
IN_LOCK
IDENT.0
MVCS DET
INST_HLOCK
YSFM.4
YSFM.3
YSFM.2
YSFM.1
YSFM.0
WYSFM.4
WYSFM.3
WYSFM.2
WYSFM.1
WYSFM.0
NSFSEL.1
NSFSEL.0
PSFSEL.1
PSFSEL.0
LTA.1
LTA.0
CTA.1
CTA.0
CKE
LAGC.2
CAGT.1
CAGT.0
CMG.7
CMG.6
LAGT.1
LGAT.0
LMG.7
LMG.6
DEF_C.0
PW_UPD
LAGC.1
CMG.5
LMG.5
LAGC.0
CAGC.1
CAGC.0
CMG.11
CMG.10
CMG.9
CMG.8
CMG.3
CMG.2
CMG.1
CMG.0
LMG.11
LMG.10
LMG.9
LMG.8
LMG.4
LMG.3
LMG.2
LMG.1
LMG.0
NEWAVMODE
HVSTIM
CMG.4
Rev. B | Page 65 of 104
ADV7189B
Register Name
Vsync Field
Control 2
Vsync Field
Control 3
Hsync Position
Control 1
Hsync Position
Control 2
Hsync Position
Control 3
Polarity
NTSC Comb
Control
PAL Comb
Control
ADC Control
Reserved
Manual
Window
Control
Reserved
Resample
Control
Reserved
Gemstar Ctrl 1
Gemstar Ctrl 2
Gemstar Ctrl 3
Gemstar Ctrl 4
Gemstar Ctrl 5
CTI DNR Ctrl 1
CTI DNR Ctrl 2
Reserved
CTI DNR Ctrl 4
Lock Count
Reserved
Free Run Line
Length 1
Reserved
VBI Info
WSS 1
WSS 2
EDTV 1
EDTV 2
EDTV 3
CGMS 1
CGMS 2
CGMS 3
CCAP 1
CCAP 2
Letterbox 1
Letterbox 2
Letterbox 3
Reserved
CRC Enable
Reserved
ADC Switch 1
ADC Switch 2
Reserved
Letterbox
Control 1
Letterbox
Control 2
Reserved
Reserved
Reserved
Bit 7
VSBHO
Bit 6
VSBHE
Bit 5
Bit 4
VSEHO
VSEHE
HSB.10
HSB.9
HSB.8
HSB.7
HSB.6
HSB.5
HSB.4
HSE.7
HSE.6
HSE.5
PHS
CTAPSN.1
CTAPSN.0
CTAPSP.1
CTAPSP.0
CKILLTHR.2
Bit 2
Bit 1
Bit 0
HSE.10
HSE.9
HSE.8
HSB.3
HSB.2
HSB.1
HSB.0
HSE.4
HSE.3
HSE.2
HSE.1
HSE.0
PVS
CCMN.2
CCMN.1
PF
CCMN.0
YCMN.2
YCMN.1
PCLK
YCMN.0
CCMP.2
CCMP.1
CCMP.0
YCMP.2
YCMP.1
YCMP.0
PWRDN_AD C_0
PWRDN_AD C_1
PWRDN_ADC_2
CKILLTHR.1
CKILLTHR.0
Bit 3
SFL_INV
GDECEL.15
GDECEL.7
GDECOL.15
GDECOL.7
GDECEL.14
GDECEL.6
GDECOL.14
GDECOL.6
GDECEL.13
GDECEL.5
GDECOL.13
GDECOL.5
GDECEL.12
GDECEL.4
GDECOL.12
GDECOL.4
GDECEL.11
GDECEL.3
GDECOL.11
GDECOL.3
GDECEL.10
GDECEL.2
GDECOL.10
GDECOL.2
GDECEL.9
GDECEL.1
GDECOL.9
GDECOL.1
CTI_C_TH.7
CTI_C_TH.6
DNR_EN
CTI_C_TH.5
CTI_C_TH.4
CTI_AB.1
CTI_C_TH.3
CTI_AB.0
CTI_C_TH.2
CTI_AB_EN
CTI_C_TH.1
GDECEL.8
GDECEL.0
GDECOL.8
GDECOL.0
GDECAD
CTI_EN
CTI_C_TH.0
DNR_TH.7
FSCLE
DNR_TH.6
SRLS
DNR_TH.5
COL.2
DNR_TH.4
COL.1
DNR_TH.3
COL.0
DNR_TH.2
CIL.2
DNR_TH.1
CIL.1
DNR_TH.0
CIL.0
LLC_PAD_SEL.2
LLC_PAD_SEL.1
LLC_PAD_SEL.0
WSS1.6
WSS2.6
EDTV1.6
EDTV2.6
EDTV3.6
CGMS1.6
CGMS2.6
CGMS3.6
CCAP1.6
CCAP2.6
LB_LCT.6
LB_LCM.6
LB_LCB.6
WSS1.5
WSS2.5
EDTV1.5
EDTV2.5
EDTV3.5
CGMS1.5
CGMS2.5
CGMS3.5
CCAP1.5
CCAP2.5
LB_LCT.5
LB_LCM.5
LB_LCB.5
WSS1.4
WSS2.4
EDTV1.4
EDTV2.4
EDTV3.4
CGMS1.4
CGMS2.4
CGMS3.4
CCAP1.4
CCAP2.4
LB_LCT.4
LB_LCM.4
LB_LCB.4
CGMSD
WSS1.3
WSS2.3
EDTV1.3
EDTV2.3
EDTV3.3
CGMS1.3
CGMS2.3
CGMS3.3
CCAP1.3
CCAP2.3
LB_LCT.3
LB_LCM.3
LB_LCB.3
EDTVD
WSS1.2
WSS2.2
EDTV1.2
EDTV2.2
EDTV3.2
CGMS1.2
CGMS2.2
CGMS3.2
CCAP1.2
CCAP2.2
LB_LCT.2
LB_LCM.2
LB_LCB.2
CCAPD
WSS1.1
WSS2.1
EDTV1.1
EDTV2.1
EDTV3.1
CGMS1.1
CGMS2.1
CGMS3.1
CCAP1.1
CCAP2.1
LB_LCT.1
LB_LCM.1
LB_LCB.1
WSSD
WSS1.0
WSS2.0
EDTV1.0
EDTV2.0
EDTV3.0
CGMS1.0
CGMS2.0
CGMS3.0
CCAP1.0
CCAP2.0
LB_LCT.0
LB_LCM.0
LB_LCB.0
WSS1.7
WSS2.7
EDTV1.7
EDTV2.7
EDTV3.7
CGMS1.7
CGMS2.7
CGMS3.7
CCAP1.7
CCAP2.7
LB_LCT.7
LB_LCM.7
LB_LCB.7
CRC_ENABLE
ADC1_SW.3
ADC_SW_M AN
LB_SL.3
ADC1_SW.2
LB_SL.2
ADC1_SW.1
LB_SL.1
ADC1_SW.0
ADC0_SW.3
ADC2_SW.3
ADC0_SW.2
ADC2_SW.2
ADC0_SW.1
ADC2_SW.1
ADC0_SW.0
ADC2_SW.0
LB_TH.4
LB_TH.3
LB_TH.2
LB_TH.1
LB_TH.0
LB_SL.0
LB_EL.3
LB_EL.2
LB_EL.1
LB_EL.0
Rev. B | Page 66 of 104
ADV7189B
Register Name
SD Offset Cb
SD Offset Cr
SD Saturation
Cb
SD Saturation
Cr
NTSC V Bit
Begin
NTSC V Bit End
NTSC F Bit
Toggle
PAL V Bit Begin
PAL V Bit End
PAL F Bit Toggle
Reserved
Drive Strength
Reserved
IF Comp Control
VS Mode
Control
Bit 7
SD_OFF_CB.7
SD_OFF_CR.7
SD_SAT_CB.7
Bit 6
SD_OFF_CB.6
SD_OFF_CR.6
SD_SAT_CB.6
Bit 5
SD_OFF_CB.5
SD_OFF_CR.5
SD_SAT_CB.5
Bit 4
SD_OFF_CB.4
SD_OFF_CR.4
SD_SAT_CB.4
Bit 3
SD_OFF_CB.3
SD_OFF_CR.3
SD_SAT_CB.3
Bit 2
SD_OFF_CB.2
SD_OFF_CR.2
SD_SAT_CB.2
Bit 1
SD_OFF_CB.1
SD_OFF_CR .1
SD_SAT_CB.1
Bit 0
SD_OFF_CB.0
SD_OFF_CR.0
SD_SAT_CB.0
SD_SAT_CR.7
SD_SAT_CR.6
SD_SAT_CR.5
SD_SAT_CR.4
SD_SAT_CR.3
SD_SAT_CR.2
SD_SAT_CR.1
SD_SAT_CR.0
NVBEGDEL O
NVBEGDEL E
NVBEGSIGN
NVBEG.4
NVBEG.3
NVBEG.2
NVBEG.1
NVBEG.0
NVENDDEL O
NFTOGDEL O
NVENDDEL E
NFTOGDEL E
NVENDSIGN
NFTOGSIGN
NVEND.4
NFTOG.4
NVEND.3
NFTOG.3
NVEND.2
NFTOG.2
NVEND.1
NFTOG.1
NVEND.0
NFTOG.0
PVBEGDEL O
PVENDDEL O
PFTOGDEL O
PVBEGDEL E
PVENDDEL E
PFTOGDEL E
PVBEGSIGN
PVENDSIGN
PFTOGSIGN
PVBEG.4
PVEND.4
PFTOG.4
PVBEG.3
PVEND.3
PFTOG.3
PVBEG.2
PVEND.2
PFTOG.2
PVBEG.1
PVEND.1
PFTOG.1
PVBEG.0
PVEND.0
PFTOG.0
DR_STR.1
DR_STR.0
DR_STR_C.1
DR_STR_C.0
DR_STR_S.1
DR_STR_S.0
VS_COAST_
MODE.1
IFFILTSEL.2
VS_COAST_
MODE.0
IFFILTSEL.1
EXTEND_VS_
MIN_FREQ
IFFILTSEL.0
EXTEND_VS_
MAX_FREQ
I2C REGISTER MAP DETAILS
P
P
The following registers are located in the Common I2C Register Maps and Register Access sections, Page 2.
Table 84. Interrupt (Page 2) Register Map Details 1
259H
8F
Register Name
Interrupt Config 0
Reset
Value
0001
x000
Reserved
Interrupt Status 1
Interrupt Clear 1
Interrupt Mask b1
x000
0000
x000
0000
Reserved
Interrupt Status 2
Subaddress
rw
rw
Dec
64
Hex
0x40
r
65
66
0x41
0x42
w
67
0x43
rw
68
0x44
r
69
70
0x45
0x46
Interrupt Clear 2
0xxx
0000
w
71
0x47
Interrupt Mask b2
0xxx
0000
rw
72
0x48
Raw Status 3
r
73
0x49
Interrupt Status 3
r
74
0x4A
7
6
5
4
INTRQ_DU
R_SEL.1
INTRQ_
DUR_SEL.0
MV_INTRQ
_SEL.1
MV_INTRQ
_SEL.0
MV_PS_
CS_Q
MV_PS_
CS_CLR
MV_PS_
CS_MSKB
SD_FR_
CHNG_Q
SD_FR_CH
NG_CLR
SD_FR_CH
NG_MSKB
xx00
0000
w
75
0x4B
Interrupt Mask b3
xx00
0000
rw
76
0x4C
1
SCM_LOCK
_CHNG_Q
SCM_LOCK
_CHNG_
CLR
SCM_LOCK
_CHNG_
MSKB
SD_AD_
CHNG_Q
SD_AD_CH
NG_CLR
SD_AD_
CHNG_
MSKB
To access the interrupt register map, the register access page[1:0] bits in register address 0x0E must be programmed to 01b.
Rev. B | Page 67 of 104
0
INTRQ_OP
_SEL.0
SD_
UNLOCK_Q
_MSKB
SD_LOCK_
Q
SD_LOCK_
CLR
SD_LOCK_
MSKB
CGMS_
CHNGD_Q
CGMS_
CHNGD_
CLR
CGMS_
CHNGD_
MSKB
GEMD_Q
CCAPD_Q
GEMD_CLR
CCAPD_
CLR
GEMD_
MSKB
CCAPD_
MSKB
SD_H_LOCK
SD_V_LOCK
SD_UNLOCK
SCM_LOCK
PAL_SW_L
K_CHNG_
CLR
PAL_SW_
LK_CHNG_
MSKB
1
INTRQ_OP
_SEL.1
_CLR
WSS_CHN
GD_Q
WSS_
CHNGD_
CLR
WSS_
CHNGD_
MSKB
PAL_SW_LK
2
MPU_STIM
_INTRQ
SD_UNLOCK
MPU_STIM
_INTRQ_Q
MPU_STIM
_INTRQ_
CLR
MPU_
STIM_INTR
Q_MSKB
_CHNG_Q
Interrupt Clear 3
3
SD_H_
LOCK_
CHNG_CLR
SD_OP_
50HZ
SD_V_LOCK
SD_OP_
_CHNG_Q
CHNG_Q
SD_V_LOCK SD_OP_
_CHNG_
CHNG_CLR
CLR
SD_H_
LOCK_
CHNG_MSKB
SD_V_
LOCK_
CHNG_MSKB
SD_H_LOCK
_CHNG_Q
SD_OP_
CHNG_MSKB
ADV7189B
I2C INTERRUPT REGISTER MAP
The following registers are located in Register Access Page 2.
Table 85. Interrupt (Page 2) Register Map Details
Subaddress
0x40
Register
Interrupt
Config 1
Register
Access
Page 2
Bit Description
INTRQ_OP_SEL[1:0].
Interrupt Drive Level Select
7
6
INTRQ_DUR_SEL[1:0].
Interrupt Duration Select
Reserved
Interrupt
Status 1
4
Bit
3
MPU_STIM_INTRQ[1:0].
Manual Interrupt Set Mode
2
1
0
0
1
1
0
0
1
0
1
x
x
0
1
0
1
Reserved
MV_INTRQ_SEL[1:0].
Macrovision Interrupt Select
0x41
0x42
5
x
0
0
1
1
x
0
1
0
1
x
0
0
1
1
0
1
0
1
x
x
x
x
SD_LOCK_Q
Read-Only
SD_UNLOCK_Q
0
1
Register
Access
Page 2
Reserved
Reserved
Reserved
SD_FR_CHNG_Q
0x43
Interrupt
Clear 1
These bits
can be
cleared or
masked in
Register
0x43 and
Register
0x44,
respectively.
x
0
1
No change
Denotes a change in the freerun status
No change
Pseudo sync / color striping
detected. See Reg 0x40
MV_INTRQ_SEL[1:0] for
selection
0
1
x
0
1
SD_UNLOCK_CLR
0
1
Reserved
Reserved
Reserved
SD_FR_CHNG_CLR
0
0
0
0
1
MV_PS_CS_CLR
Reserved
No change
SD input has caused the
decoder to go from an unlocked
state to a locked state
No change
SD input has caused the
decoder to go from a locked
state to an unlocked state
x
Write-Only
Register
Access
Page 2
Notes
x
MV_PS_CS_Q
Reserved
SD_LOCK_CLR
Comments
Open drain
Drive low when active
Drive high when active
Reserved
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 Xtal periods
15 Xtal periods
63 Xtal periods
Active until cleared
0
1
x
Rev. B | Page 68 of 104
Do not clear
Clears SD_LOCK_Q bit
Do not clear
Clears SD_UNLOCK_Q bit
Not used
Not used
Not used
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
Clears MV_PS_CS_Q bit
Not used
ADV7189B
Subaddress
0x44
Register
Interrupt
Mask 1
Bit Description
SD_LOCK_MSKB
7
6
5
4
Bit
3
2
SD_UNLOCK_MSKB
Read/Write
Register
Register
Access
Page 2
Reserved
Reserved
Reserved
SD_FR_CHNG_MSKB
Reserved
Reserved
Interrupt
Status 2
0
0
1
0
1
0
0
0
0
1
MV_PS_CS_MSKB
0x45
0x46
1
0
1
x
x
x
x
x
x
x
x
CCAPD_Q
x
0
1
Read-Only
Register
GEMD_Q
0
Register
Access
Page 2
1
CGMS_CHNGD_Q
0
1
WSS_CHNGD_Q
0
1
Reserved
Reserved
Reserved
MPU_STIM_INTRQ_Q
0x47
Interrupt
Clear 2
x
x
x
0
1
CCAPD_CLR
0
1
GEMD_CLR
0
1
Write-Only
Register
Access
Page 2
CGMS_CHNGD_CLR
0
1
WSS_CHNGD_CLR
Reserved
Reserved
Reserved
MPU_STIM_INTRQ_CLR
0
1
x
x
x
0
1
Rev. B | Page 69 of 104
Comments
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
Not used
Not used
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
Notes
Closed captioning not detected
in the input video signal
Closed captioning data
detected in the video input
signal
Gemstar data not detected in
the input video signal
Gemstar data detected in the
input video signal
No change detected in CGMS
data in the input video signal
A change is detected in the
CGMS data in the input video
signal
No change detected in WSS
data in the input video signal
A change is detected in the WSS
data in the input video signal
Not used
Not used
Not used
Manual interrupt not set
Manual interrupt set
Do not clear
Clears CCAPD_Q bit
Do not clear
Clears GEMD_Q bit
Do not clear
Clears CGMS_CHNGD_Q bit
Do not clear
Clears WSS_CHNGD_Q bit
Not used
Not used
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
These bits
can be
cleared or
masked by
Register
0x47 and
Register
0x48,
respectively.
ADV7189B
Subaddress
0x48
Register
Interrupt
Mask 2
Bit Description
CCAPD_MSKB
7
6
5
4
Bit
3
2
GEMD_MSKB
Read/
Write
Register
Access
Page 2
0x49
Raw Status
3
Read Only
Register
0
0
1
0
1
CGMS_CHNGD_MSKB
0
1
WSS_CHNGD_MSKB
Reserved
Reserved
Reserved
MPU_STIM_INTRQ_MSKB
1
0
1
0
0
0
0
1
SD_OP_50Hz
SD 60/50Hz frame rate at
output
SD_V_LOCK
0
1
0
1
Register
Access
Page 2
SD_H_LOCK
0
1
0x4A
Interrupt
Status 3
Read Only
Register
Register
Access
Page 2
Reserved
SCM_LOCK
SECAM Lock
Reserved
Reserved
Reserved
SD_OP_CHNG_Q
SD 60/50 Hz frame rate at
input
x
0
1
x
x
x
0
1
SD_V_LOCK_CHNG_Q
0
1
SD_H_LOCK_CHNG_Q
0
1
SD_AD_CHNG_Q
SD autodetect changed
x
SCM_LOCK_CHNG_Q
SECAM Lock
PAL_SW_LK_CHNG_Q
Reserved
Reserved
0
1
x
x
x
Rev. B | Page 70 of 104
Comments
Masks CCAPD_Q bit
Unmasks CCAPD_Q bit
Masks GEMD_Q bit
Unmasks GEMD_Q bit
Masks CGMS_CHNGD_Q bit
Unmasks CGMS_CHNGD_Q bit
Masks WSS_CHNGD_Q bit
Unmasks WSS_CHNGD_Q bit
Not used
Not used
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q
bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not
established
SD vertical sync lock
established
SD horizontal sync lock not
established
SD horizontal sync lock
established
Not used
SECAM lock not established
SECAM lock established
Not used
Not used
Not used
No change in SD signal standard
detected at the input
A change in SD signal standard
is detected at the input
No change in SD vertical sync
lock status
SD vertical sync lock status has
changed.
No change in SD horizontal sync
lock status
SD horizontal sync lock status
has changed
No change in AD_RESULT[2:0]
bits in Status Register 1
AD_RESULT[2:0] bits in Status
Register 1 have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging
burst lock status
PAL swinging burst lock status
has changed
Not used
Not used
Notes
These bits
cannot be
cleared or
masked.
Register
0x4A is used
for this
purpose.
These bits
can be
cleared and
masked by
Register
0x4B and
Register
0x4C,
respectively.
ADV7189B
Subaddress
0x4B
Register
Interrupt
Clear 3
Bit Description
SD_OP_CHNG_CLR
7
6
5
4
Bit
3
2
SD_V_LOCK_CHNG_CLR
Write Only
Register
Register
Access
Page 2
0
1
SD_AD_CHNG_CLR
0
1
SCM_LOCK_CHNG_CLR
0
1
PAL_SW_LK_CHNG_CLR
0x4C
Interrupt
Mask 2
0
1
x
x
0
1
SD_V_LOCK_CHNG_ MSKB
Read /
Write
Register
Register
Access
Page 2
0
1
SD_H_LOCK_CHNG_ MSKB
0
1
SD_AD_CHNG_ MSKB
0
1
SCM_LOCK_CHNG_ MSKB
0
1
PAL_SW_LK_CHNG_ MSKB
Reserved
Reserved
0
0
1
0
1
SD_H_LOCK_CHNG_CLR
Reserved
Reserved
SD_OP_CHNG_MSKB
1
0
1
x
x
Rev. B | Page 71 of 104
Comments
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
Clears SCM_LOCK_CHNG_Q bit
Do not clear
Clears PAL_SW_LK_CHNG_Q bit
Not used
Not used
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q
bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q
bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q
bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q
bit
Not used
Not used
Notes
ADV7189B
The following registers are located in the Common I2C Map and Register Access Page 1.
Table 86. Common and Normal (Page 1) Register Map Details
Subaddress
Register
Bit Description
0x00
Input
Control
INSEL[3:0]. The INSEL bits allow the
user to select an input channel as
well as the input format.
VID_SEL[3:0]. The VID_SEL bits
allow the user to select the input
video standard.
7 6
5
Bits
4 3
0
0
0
0
0
0
0
0
1
1
2
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0 0
0
0
0 0
0
1
0 0
1
0
0 0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Rev. B | Page 72 of 104
Comments
CVBS in on AIN1
CVBS in on AIN2
CVBS in on AIN3
CVBS in on AIN4
CVBS in on AIN5
CVBS in on AIN6
Y on AIN1, C on AIN4
Y on AIN2, C on AIN5
Y on AIN3, C on AIN6
Y on AIN1, Pb on AIN4, Pr
on AIN5
Y on AIN2, Pb on AIN3, Pr
on AIN6
CVBS in on AIN7
CVBS in on AIN8
CVBS in on AIN9
CVBS in on AIN10
CVBS in on AIN11
Auto-detect PAL (BGHID),
NTSC J (without pedestal),
SECAM
Auto-detect PAL (BGHID),
NTSC M (with pedestal),
SECAM
Auto-detect PAL (N), NTSC
J, SECAM (PAL with
pedestal)
Auto-detect PAL (N), NTSC
M, SECAM (PAL and NTSC
with pedestal)
NTSC(J)
NTSC(M)
PAL 60
NTSC 4.43
PAL BGHID
PAL N (BGHID without
pedestal)
PAL M (without pedestal)
PAL M
PAL combination N
PAL combination N
SECAM (with pedestal)
SECAM (with pedestal)
Notes
Composite
S-Video
YPbPr
Composite
ADV7189B
Subaddress
Register
Bit Description
0x01
Video
Selection
Reserved
ENVSPROC
7 6
Reserved
SD_DUP_AV. Duplicates the AV
codes from the luma into the
chroma path.
0x04
Extended
Output
Control
0
0
0
1
Drivers three-stated
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes
See also TIM_OE and
TRI_LLC
All lines filtered and scaled
Only active video region
filtered
0
1
0
1
BL_C_VBI. Blank Chroma during
VBI. If set, enables data in the VBI
region to be passed through the
decoder undistorted.
TIM_OE. Timing signals output
enable.
Reserved
Reserved
BT656-4. Allows the user to select
an output mode compatible with
ITU-R BT656-3/4.
1
0
0
1
Reserved
OF_SEL[3:0]. Allows the user to
choose from a set of output
formats.
TOD. Three-State Output Drivers.
This bit allows the user to threestate the output drivers: P[19:0], HS,
VS, FIELD, and SFL.
VBI_EN. Allows VBI data (Lines 1 to
21) to be passed through with only
a minimum amount of filtering
performed.
RANGE. Allows the user to select
the range of output values. Can be
BT656-compliant, or can fill the
whole accessible number range.
EN_SFL_PIN
2
0
0
1
ENHSPLL
Output
Control
Bits
4 3
Comments
Set to default
Disable Vsync processor
Enable Vsync processor
Set to default
Standard video input
Betacam input enable
Disable Hsync processor
Enable Hsync processor
Set to default
AV codes to suit 8-bit
interleaved data output
AV codes duplicated (for
16-bit interfaces)
Set as default
10-bit @ LLC1 4:2:2
ITU-R BT.656
20-bit @ LLC1 4:2:2
16-bit @ LLC1 4:2:2
8-bit @ LLC1 4:2:2
ITU-R BT.656
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Output pins enabled
Reserved
BETACAM
0x03
5
0
1
0
1
x
16 < Y < 235, 16 < C < 240
1 < Y < 254, 1 < C < 254
ITU-R BT.656
Extended range
SFL output is disabled
SFL information output on
the SFL pin
SFL output enables
encoder and decoder
to be connected
directly.
During VBI
Decode and output color
Blank Cr and Cb
HS, VS, F three-stated
HS, VS, F forced active
x
1
0
1
Rev. B | Page 73 of 104
BT656-3-compatible
BT656-4-compatible
Controlled by TOD
ADV7189B
Subaddress
Register
Bit Description
0x07
Autodetect
AD_PAL_EN. PAL B/G/I/H
autodetect enable.
Enable
7 6
5
Bits
4 3
2
AD_NTSC_EN. NTSC autodetect
enable.
1
0
0
1
0
1
AD_PALM_EN. PAL M autodetect
enable.
1
Enable
Disable
0
1
AD_P60_EN. PAL 60 autodetect
enable.
Enable
Disable
0
1
AD_N443_EN. NTSC443 autodetect
enable.
Enable
Disable
0
1
AD_SECAM_EN. SECAM autodetect
enable.
Enable
Disable
0
1
AD_SEC525_EN. SECAM 525
autodetect enable.
0x08
Contrast
Register
0x09
0x0A
Reserved
Brightness
Register
0x0B
Hue
Register
Default
Value Y
0x0C
CON[7:0]. Contrast adjust. This is
the user control for contrast
adjustment.
Reserved
BRI[7:0]. This register controls the
brightness of the video signal.
HUE[7:0]. This register contains the
value for the color hue adjustment.
DEF_VAL_EN. Default value enable.
Enable
Disable
0
1
1 0
0
0
0
0
0
0
1 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
1
DEF_VAL_AUTO_EN. Default value.
0
1
Enable
Luma gain = 1
Free-run mode dependent
on DEF_VAL_AUTO_EN
Force Free-run mode on
and output blue screen
Disable Free-run mode
Enable Automatic Freerun mode (blue screen)
0 0
1
1
0
1
0 1
1
1
1
1
0
0
Cr[7:0] = DEF_C[7:4],0, 0, 0,
0}
Cb[7:0] = DEF_C[3:0], 0, 0,
0, 0}
0
0
0
0
0
Set as default
Access User Reg Map
Access Interrupt Reg Map
Set as default
Default
Value C
DEF_C[7:0]. Default value C. The Cr
and Cb default values are defined
in this register.
0x0E
ADI Control
Reserved
SUB_USR_EN. Enables the user to
access the Interrupt map.
Reserved
0
1
0 0
Rev. B | Page 74 of 104
0x00 Gain = 0
0x80 Gain = 1;
0xFF Gain = 2
0x00 = 0IRE
0x7F = +100IRE
0x80 = –100IRE
Hue range =
–90° to +90°
DEF_Y[5:0]. Default value Y. This
register holds the Y default value.
0x0D
Notes
Enable
Disable
0
AD_PALN_EN. PAL N autodetect
enable.
Comments
Disable
Enable
Disable
Y[7:0] = {DEF_Y[5:0],0, 0}
When lock is lost,
Free-run mode can
be enabled to output
stable timing, clock,
and a set color.
Default Y value
output in Free-run
mode.
Default Cb/Cr value
output in Free-run
mode. Default values
give blue screen
output.
See Figure 38
260H
ADV7189B
Subaddress
Register
Bit Description
0x0F
Power
Reserved
7 6
5
Bits
4 3
2
1
0
0
0
Comments
Set to default
Notes
Management
PDBP. Power-down bit priority
selects between PWRDN bit or PIN.
0
Chip power down
controlled by pin
Bit has priority (pin
disregarded)
Set to default
System functional
Powered down
1
Reserved
PWRDN. Power down places the
decoder in a full power-down
mode.
Reserved
RES. Chip reset loads all I2C bits
with default values.
0x10
Status
Register 1.
Read-Only.
0
0
0
Set to default
Normal operation
1
Start reset sequence
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
x
x
0x12
IDENT
Read-Only
Status
Register 2.
Read-Only.
COL_KILL.
IDENT[7:0] Provides identification
on the revision of the part.
x
x
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x
x
x
Status
Register 3.
Read-Only.
Reserved
INST_HLOCK
x
x
x
x
x
MV color striping detected
MV color striping type
MV pseudo sync detected
MV AGC pulses detected
Nonstandard line length
Fsc frequency
nonstandard
x
See PDBP, 0x0F Bit 2.
Executing reset takes
approx. 2 ms. This bit
is self-clearing.
Provides information
about the internal
status of the
decoder.
Detected standard.
Color kill.
ADV7189B = 0x13
1 = Detected
0 = Type 2,
1 = Type 3
1 = Detected
1 = Detected
1 = Detected
1 = Detected
x
x
x
1 = horizontal lock
achieved
1 = Gemstar data detected
SD 60 Hz detected
SD 50 Hz detected
1 = Free-run mode active
1 = Field length standard
0
1 = Interlaced video
detected
1 = Swinging burst
detected
Set to default
Current sources switched
off
Current sources enabled
Set to default
x
x
x
x
x
x
Reserved
CCLEN. Current clamp enable
allows the user to switch off the
current sources in the analog front.
Reserved
x
x
GEMD
SD_OP_50HZ
Reserved
FREE_RUN_ACT
STD FLD_LEN
PAL_SW_LOCK
Analog
Clamp
Control
x
x
INTERLACED
0x14
x
MVCS DET
MVCS T3
MV PS DET
MV AGC DET
LL NSTD
FSC NSTD
0x13
FSC lock (right now) = 1
Peak white AGC mode
active = 1
NTSM-MJ
NTSC-443
PAL-M
PAL-60
PAL-BGHID
SECAM
PAL combination N
SECAM 525
Color kill is active = 1
x
0
0
0
0
1
1
1
1
In lock (right now) = 1
Lost lock (since last read) = 1
x
AD_RESULT[2:0]. Autodetection
result reports the standard of the
Input video.
0x11
0
0
1
0
0
1
0 0
Rev. B | Page 75 of 104
0
1
0
Unfiltered
SD Field rate detect
Blue screen output
Correct Field length
found
Field sequence found
Reliable swinging
burst sequence
ADV7189B
Subaddress
Register
Bit Description
0x15
Digital
Clamp
Control 1
Reserved
DCT[1:0]. Digital clamp timing
determines the time constant of
the digital fine clamp circuitry.
0x17
Shaping
Filter
Control
Reserved
YSFM[4:0]. Selects Y-Shaping Filter
mode when in CVBS only mode.
7 6
5
0
0
1
1
0
1
0
1
2
x
1
x
0
x
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 0
0 0
0
1
Comments
Set to default
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
TC dependent on video
Set to default
Auto wide notch for poor
quality sources or wideband filter with Comb for
good quality input
Auto narrow notch for
poor quality sources or
wideband filter with comb
for good quality input
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR601)
PAL NN1
PAL NN2
PAL NN3
PAL WN 1
PAL WN 2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
Auto selection 15 MHz
Auto selection 2.17 MHz
0
0
1
1
1
1
0
1
0
1
0
1
SH1
SH2
SH3
SH4
SH5
Wideband mode
0
Allows the user to select a wide
range of low-pass and notch filters.
If either auto mode is selected, the
decoder selects the optimum Y
filter depending on the CVBS video
source quality (good vs. bad).
CSFM[2:0].
C-Shaping Filter mode allows the
selection from a range of low-pass
chrominance filters, SH1to SH5, and
wideband mode.
Bits
4 3
0 x
1
1
0
0
1
1
Rev. B | Page 76 of 104
Notes
Decoder selects
optimum Y-shaping
filter depending on
CVBS quality.
If one of these modes
is selected, the
decoder does not
change filter modes.
Depending on video
quality, a fixed filter
response (the one
selected) is used for
good and bad quality
video.
Automatically selects
a C filter for the
specified bandwidth.
ADV7189B
Subaddress
Register
Bit Description
0x18
Shaping
Filter
Control 2
WYSFM[4:0]. Wideband Y-Shaping
Filter mode allows the user to
select which Y-shaping filter is used
for the Y component of Y/C, YPbPr,
B/W input signals; it is also used
when a good quality input CVBS
signal is detected. For all other
inputs, the Y-shaping filter chosen
is controlled by YSFM[4:0].
Reserved
WYSFMOVR. Enables the use of
automatic WYSFN filter.
7 6
0
5
Bits
4 3
0 0
0 0
0 0
0 0
0 0
0 0
2
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
Comments
Reserved. Do not use.
Reserved. Do not use.
SVHS 1
SVHS 2
SVHS 3
SVHS 4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
~
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
~
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
~
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
~
1
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
~
1
0
0
1
0x19
Comb Filter
Control
PSFSEL[1:0]. Controls the signal
bandwidth that is fed to the comb
filters (PAL).
NSFSEL[1:0]. Controls the signal
bandwidth that is fed to the comb
filters (NTSC).
0x1D
ADI Control
2
Reserved
Reserved
VS_JIT_COMP_EN
1 1
1
0
0
1
0
1
0
x
0
1
EN28XTAL
TRI_LLC
1
0
0
1
1
0
1
0
1
Rev. B | Page 77 of 104
0
0
1
1
0
1
0
1
x
x
Set to default
Auto selection of
best filter
Manual select filter
using WYSFM[4:0]
Narrow
Medium
Wide
Widest
Narrow
Medium
Medium
Wide
Set as default
Set to default
Enabled
Disabled
Use 27 MHz crystal
Use 28 MHz crystal
LLC pin active
LLC pin three-stated
Notes
ADV7189B
Subaddress
Register
Bit Description
0x27
Pixel Delay
Control
LTA[1:0]. Luma timing adjust allows
the user to specify a timing
difference between chroma and
luma samples.
7 6
Reserved
CTA[2:0]. Chroma timing adjust
allows a specified timing difference
between the luma and chroma
samples
0x2B
Misc Gain
Control
Bits
4 3
2
1
0
0
0
Comments
No delay
1
0
Luma 1 clk (37ns) delayed
1
0
Luma 2 clk (74ns) early
1
1
Luma 1 clk (37ns) early
0
0
0
0
0
1
1
1
1
AUTO_PDC_EN. Automatically
programs the LTA/CTA values so
that luma and chroma are aligned
at the output for all modes of
operation.
SWPC. Allows the Cr and Cb
samples to be swapped.
5
0
0
1
1
0
0
1
1
Set to 0
Not valid setting
Chroma +2 pixels (early)
Chroma +1 pixel (early)
No delay
Chroma −1 pixel (late)
Chroma −2 pixels (late)
Chroma −3 pixels (late)
Not valid setting
Use values in LTA[1:0] and
CTA[2:0] for delaying
luma/chroma
0
1
0
1
0
1
0
1
0
1
No swapping
1
Swap the Cr and Cb O/P
samples
Update once per video
line
Update once per field
PW_UPD. Peak white update
determines the rate of gain.
0
1
0x2C
AGC Mode
Control
Reserved
CAGC[1:0]. Chroma automatic gain
control selects the basic mode of
operation for the AGC in the
chroma path.
1
Reserved
0
0
0
0
Set to default
Color kill disabled
Color kill enabled
0
1
1
0
0
1
1
Reserved
LAGC[2:0]. Luma automatic gain
control selects the mode of
operation for the gain control in
the luma path.
CVBS mode
CTA[2:0] = 011b
S-Video mode
CTA[2:0] = 101b
YPrPb mode
CTA[2:0] = 110b
LTA and CTA values
determined automatically
0
Reserved
CKE. Color kill enable allows the
color kill function to be switched
on and off.
Notes
CVBS mode
LTA[1:0] = 00b;
S-Video mode
LTA[1:0] = 01b;PrPb
mode LTA[1:0] = 01b
1
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
Rev. B | Page 78 of 104
1
0
1
0
1
Set to default
Manual fixed gain
Use luma gain for chroma
Automatic gain
Freeze chroma gain
Set to 1
Manual fixed gain
AGC Peak white algorithm
off
AGC Peak white algorithm
on.
Reserved
Reserved
Reserved
Reserved
Freeze gain
Set to 1
Peak white must
be enabled.
See LAGC[2:0]
For SECAM color kill,
threshold is set at
8%.
See CKILLTHR[2:0]
Use CMG[11:0]
Based on color burst
Use LMG[11:0]
Blank level to sync tip
Blank level to sync tip
ADV7189B
Subaddress
Register
Bit Description
0x2D
Chroma
Gain
Control 1
CMG[11:8]. Chroma manual gain
can be used to program a desired
manual chroma gain. Reading back
from this register in AGC mode
gives the current gain.
Reserved
CAGT[1:0]. Chroma automatic gain
timing allows adjustment of the
chroma AGC tracking speed.
0x2E
Chroma
Gain
Control 2
CMG[7:0]. Chroma manual gain
lower 8 bits. See CMG[11:8] for
description.
0x2F
Luma Gain
Control 1
LMG[11:8]. Luma manual gain can
be used program a desired manual
chroma gain, or to read back the
actual gain value used.
Reserved
LAGT[1:0]. Luma automatic gain
timing allows adjustment of the
luma AGC tracking speed.
0x30
Luma Gain
Control 2
LMG[7:0]. Luma manual gain can be
used to program a desired manual
chroma gain or read back the
actual used gain value.
0x31
VS and
FIELD
Control 1
Reserved
HVSTIM. Selects where within a line
of video the VS signal is asserted.
7 6
0
0
1
1
0
0
1
0
1
0
5
Bits
4 3
0
1
1
0
1
0
0
1
1
x
0
1
0
1
x
x
0
2
1
1
0
0
0
0
0
0
0
x
x
x
x
1
x
x
x
x
x
0
1
0
0
1
NEWAVMODE. Sets the EAV/SAV
mode.
0
1
0x32
Vsync Field
Control 2
Reserved
Reserved
VSBHE
0 0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
VSBHO
0
1
0x33
Vsync Field
Control 3
Reserved
VSEHE
0
1
VSEHO
0
1
Rev. B | Page 79 of 104
Comments
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
CMG[11:0] = 750d; gain is
1 in NTSC
CMG[11:0] = 741d; gain is
1 in PAL
LAGC[1:0] settings decide
in which mode LMG[11:0]
operates
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LMG[11:0] = 1234dec; gain
is 1 in NTSC LMG[11:0] =
1266d; gain is 1 in PAL
Set to default
Start of line relative to HSE
Start of line relative to HSB
EAV/SAV codes generated
to suit ADI encoders
Manual VS/Field position
controlled by registers
0x32, 0x33, and 0xE5–
0xEA
Set to default
Set to default
VS goes high in the
middle of the line (even
field)
VS changes state at the
start of the line (even
field)
VS goes high in the
middle of the line (odd
field)
VS changes state at the
start of the line (odd field)
Set to default
VS goes low in the middle
of the line (even field)
VS changes state at the
start of the line (even
field)
VS goes low in the middle
of the line (odd field)
VS changes state at the
start of the line (odd field)
Notes
CAGC[1:0] settings
decide in which
mode CMG[11:0]
operates
Has an effect only if
CAGC[1:0] is set to
auto gain (10)
Min value is 0 dec
(G = –60 dB)
Max value is 3750
(Gain = 5)
Only has an effect if
LAGC[1:0] is set to
auto gain (001, 010,
011, or 100)
Min value
NTSC 1024 (G = 0.85)
PAL (G = 0.81)
Max value
NTSC 2468 (G = 2),
PAL = 2532 (G = 2)
HSE = Hsync end
HSB = Hsync begin
NEWAVMODE bit
must be set high.
NEWAVMODE bit
must be set high.
ADV7189B
Subaddress
Register
Bit Description
0x34
HS Position
Control 1
HSE[10:8]. HS end allows the
positioning of the HS output within
the video line.
Reserved
HSB[10:8]. HS begin allows the
positioning of the HS output within
the video line.
Reserved
HSB[7:0] See above, using
HSB[10:0] and HSE[10:0], the user
can program the position and
length of HS output signal.
HSE[7:0] See above.
0x35
HS Position
Control 2
0x36
HS Position
Control 3
Polarity
0x37
7 6
5
Bits
4 3
0
0
0
0
0 0
0
0
0 0
0
0
2
0
1
0
0
0
0
0
1
0
0
0
0
0
0
PCLK. Sets the polarity of LLC1.
0
1
0
Invert polarity
Normal polarity as per
timing diagrams
Set to 0
Active high
Active low
Set to 0
Active high
Active low
Set to 0
Active high
1
Active low
Reserved
PF. Sets the FIELD polarity.
0
0
1
Reserved
PVS. Sets the VS polarity.
Reserved
PHS. Sets HS polarity.
Comments
HS output ends HSE[10:0]
pixels after the falling
edge of Hsync
Set to 0
HS output starts HSB[10:0]
pixels after the falling
edge of Hsync
Set to 0
0
0
1
0
Rev. B | Page 80 of 104
0
Notes
Using HSB and HSE
the user can program
the position and
length of the output
Hsync
ADV7189B
Subaddress
Register
Bit Description
0x38
NTSC
Comb
Control
YCMN[2:0]. luma
comb mode, NTSC.
7 6
CCMN[2:0]. chroma
comb mode, NTSC.
CTAPSN[1:0]. chroma
comb taps, NTSC.
0
0
1
1
5
Bits
4 3
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
0
1
0
1
Rev. B | Page 81 of 104
2
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Comments
Adaptive 3-line, 3-tap
luma
Use low-pass notch
Fixed luma comb (2-line)
Fixed luma comb (3-Line)
Fixed luma comb (2-line)
3-line adaptive for
CTAPSN = 01
4-line adaptive for
CTAPSN = 10
5-line adaptive for
CTAPSN = 11
Disable chroma comb
Fixed 2-line for
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
Fixed 3-line for
CTAPSN = 01
Fixed 4-line for
CTAPSN = 10
Fixed 5-line for
CTAPSN = 11
Fixed 2-line for
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
Adapts 3 lines – 2 lines
Not used
Adapts 5 lines – 3 lines
Adapts 5 lines – 4 lines
Notes
Top lines of memory
All lines of memory
Bottom lines of
memory
Top lines of memory
All lines of memory
Bottom lines of
memory
ADV7189B
Subaddress
Register
Bit Description
0x39
PAL Comb
Control
YCMP[2:0]. luma comb mode, PAL.
7 6
CCMP[2:0]. chroma comb mode,
PAL.
CTAPSP[1:0]. chroma comb taps,
PAL.
5
Bits
4 3
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
2
0
1
0
0
0
1
1
1
1
0
1
1
1
0
0
0
1
0 0
0 1
1 0
1 1
0x3A
Reserved
PWRDN_ADC_2. Enables powerdown of ADC2.
0
0
1
PWRDN_ADC_1. Enables powerdown of ADC1.
0
1
PWRDN_ADC_0. Enables powerdown of ADC0.
0x3D
Manual
Window
Control
0
1
Reserved
Reserved
CKILLTHR[2:0]
0 0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
0
0
Rev. B | Page 82 of 104
0
1
1
Comments
Adaptive 5-line, 3-tap
luma comb
Use low-pass notch
Fixed luma comb
Fixed luma comb (5-line)
Fixed luma comb (3-line)
3-line adaptive for
CTAPSN = 01
4-line adaptive for
CTAPSN = 10
5-line adaptive for
CTAPSN = 11
Disable chroma comb
Fixed 2-line for
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
Fixed 3-line for
CTAPSN = 01
Fixed 4-line for
CTAPSN = 10
Fixed 5-line for
CTAPSN = 11
Fixed 2-line for
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
Not used
Adapts 5 lines – 3 lines
(2 taps)
Adapts 5 lines – 3 lines
(3 taps)
Adapts 5 lines – 4 lines
(4 taps)
Set as default
ADC2 normal operation
Power down ADC2
ADC1 normal operation
Power down ADC1
ADC0 normal operation
Power down ADC0
Set as default
Set to default
Kill at 0.5%
Kill at 1.5%
Kill at 2.5%
Kill at 4%
Kill at 8.5%
Kill at 16%
Kill at 32%
Reserved
Set to default
Notes
Top lines of memory
All lines of memory
Bottom lines of
memory
Top lines of memory
All lines of memory
Bottom lines of
memory
CKE = 1 enables the
color kill function
and must be enabled
for CKILLTHR[2:0] to
take effect.
ADV7189B
Subaddress
Register
Bit Description
0x41
Resample
Control
Reserved
SFL_INV. Controls the behavior of
the PAL switch bit.
7 6
5
0
Bits
4 3
1 0
2
0
1
0
0
0
0
1
Gemstar
Control 1
Gemstar
Control 2
Reserved.
GDECEL[15:8]. See the Comments
column.
GDECEL[7:0]. See the Comments
column
0
0 0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0x4A
Gemstar
Control 3
GDECOL[15:8]. See the Comments
column.
0 0
0
0
0
0
0
0
0x4B
Gemstar
Control 4
GDECOL[7:0]. See above.
0 0
0
0
0
0
0
0
0x4C
Gemstar
Control 5
GDECAD. Controls the manner in
which decoded Gemstar data is
inserted into the horizontal
blanking period.
0x48
0x49
0x4D
CTI DNR
Control 1
Reserved.
CTI_EN. CTI enable.
x
x
x
x
0x50
CTI DNR
Control 4
Split data into half byte
1
Output in straight 8-bit
format
x
0
1
Reserved.
DNR_EN. Enable or bypass the DNR
block.
CTI DNR
Control 2
x
0
0
1
1
0
1
0
1
0
0
1
Reserved.
CTI_CTH[7:0]. Specifies how big the
amplitude step must be to be
steepened by the CTI block.
1 1
0 0
0
0
1
0
0
0
DNR_TH[7:0]. Specifies the
maximum edge that is
interpreted as noise and is
therefore blanked.
0 0
0
0
1
0
0
0
Rev. B | Page 83 of 104
GDECOL[15:0]. 16
individual enable bits that
select the lines of video
(odd field lines 10 to 25)
that the decoder checks
for Gemstar-compatible
data.
0
0
1
CTI_AB_EN. Enables the mixing of
the transient improved chroma
with the original signal.
CTI_AB[1:0]. Controls the behavior
of the alpha-blend circuitry.
0x4E
x
Comments
Set to default
SFL compatible with
ADV7190/ADV7191/
ADV7194 encoders
SFL compatible with
ADV717x/ADV7173x
encoders
Set to default
GDECEL[15:0]. 16
individual enable bits that
select the lines of video
(even field lines 10 to 25)
that the decoder checks
for Gemstar-compatible
data.
Undefined
Disable CTI
Enable CTI
Disable CTI alpha blender
Enable CTI alpha blender
Sharpest mixing
Sharp mixing
Smooth
Smoothest
Set to default
Bypass the DNR block
Enable the DNR block
Set to default
Set to 0x04 for A/V input;
set to 0x0A for tuner input
Notes
LSB = Line 10
MSB = Line 25
Default = Do not
check for Gemstarcompatible data on
any lines (10 to 25) in
even fields
LSB = Line 10
MSB = Line 25
Default = Do not
check for Gemstarcompatible data on
any lines (10 to 25) in
odd fields
To avoid 00/FF code.
ADV7189B
Subaddress
Register
Bit Description
0x51
Lock Count
CIL[2:0]. Count-into-lock
determines the number of lines the
system must remain in lock before
showing a locked status.
5
Bits
4 3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
7 6
COL[2:0]. Count-out-of-lock
determines the number of lines the
system must remain out-of-lock
before showing a lost-locked
status.
SRLS. Select raw lock signal. Selects
the determination of the lock.
Status.
FSCLE. FSC lock enable.
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0x8F
0x90
Free Run
Line
Length 1
VBI Info
Reserved.
LLC_PAD_SEL[2:0]. Enables manual
selection of clock for LLC1 pin.
Reserved
WSSD. Screen signaling detected.
0
0
0
1
(Read-Only)
CCAPD. Closed-caption data.
0
1
EDTVD. EDTV sequence.
0
1
CGMSD. CGMS sequence.
0
1
0x91
WSS1
(Read-Only)
0x92
WSS2
(Read-Only)
0x93
WSS2
(Read-Only)
0x94
EDTV2
(Read-Only)
0x95
EDTV3
(Read-Only)
0x96
CGMS1
(Read-Only)
0x97
CGMS2
(Read-Only)
0x98
CGMS3
(Read-Only)
Reserved.
WSS1[7:0]
Wide screen signaling data.
WSS2[7:0]
Wide screen signaling data.
WSS2[7:0]
Wide screen signaling data.
EDTV2[7:0]
EDTV data register.
EDTV3[7:0]
EDTV data register.
CGMS1[7:0]
CGMS data register.
CGMS2[7:0]
CGMS data register.
CGMS3[7:0]
CGMS data register.
x
x
x
x
x
x
x
x
x
x
x
x
x x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Rev. B | Page 84 of 104
Comments
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
Over field with vertical
info
Line-to-line evaluation
Lock status set only by
horizontal lock
Lock status set by
horizontal lock and
subcarrier lock.
Set to default
LLC1 (nominal 27 MHz)
selected out on LLC1 pin
LLC2 (nominally 13.5 MHz)
selected out on LLC1 pin
Set to default
No WSS detected
WSS detected
No CCAP signals detected
CCAP sequence detected
No EDTV sequence
detected
EDTV sequence detected
No CGMS transition
detected
CGMS sequence decoded
Notes
For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010
Read-only status bits
WSS2[7:6] are
undetermined
EDTV3[7:6] are
undetermined
CGMS3[7:4] are
undetermined
EDTV3[5] is reserved
for future use
ADV7189B
Subaddress
Register
Bit Description
0x99
CCAP1
0x9A
CCAP2
CCAP1[7:0]
Closed caption data register.
CCAP2[7:0]
Closed caption data register.
LB_LCT[7:0]
Letterbox data register.
(Read Only)
(Read Only)
0x9B
Letterbox 1
(Read Only)
0x9C
Letterbox 2
(Read Only)
LB_LCM[7:0]
Letterbox 3
(Read Only)
LB_LCB[7:0]
CRC Enable
Write
Register
Reserved
CRC_ENABLE. Enable CRC
checksum decoded from CGMS
packet to validate CGMSD.
0x9D
0xB2
0xC3
ADC
SWITCH 1
7 6
x x
5
x
Bits
4 3
x x
2
x
1
x
0
x
Comments
CCAP1[7] contains parity
bit for Byte 0
x
x
x
x
x
x
x
x
CCAP2[7] contains parity
bit for Byte 0
x
x
x
x
x
x
x
x
x x
x
x
x
x
x
x
x x
x
x
x
x
x
x
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reports the number of
black lines detected at the
top of active video
Reports the number of
black lines detected in the
bottom half of active
video if subtitles are
detected
Reports the number of
black lines detected at the
bottom of active video
Set as default
Turn off CRC check
CGMSD goes high with
valid checksum
Set as default
No connection
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
No connection
No connection
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
No connection
No connection
No connection
No connection
AIN3
AIN4
AIN5
AIN6
No connection
No connection
No connection
No connection
AIN9
AIN10
AIN11
AIN12
No connection
Letterbox data register.
Letterbox data register.
0
1
Reserved
ADC0_SW[3:0]. Manual muxing
control for ADC0.
0 0
ADC1_SW[3:0]. Manual muxing
control for ADC1.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. B | Page 85 of 104
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Notes
This feature
examines the active
video at the start and
at the end of each
field. It enables
format detection
even if the video is
not accompanied by
a CGMS or WSS
sequence.
SETADC_sw_man_
en = 1
SETADC_sw_man_
en = 1
ADV7189B
Subaddress
Register
Bit Description
0xC4
ADC
SWITCH 2
ADC2_SW[3:0]. Manual muxing
control for ADC2.
0xDC
0xDE
0xDD
0xDF
0xE0
0xE1
Letterbox
Control 1
Letterbox
Control 2
SD Offset
Cb
0xE2
SD Offset
Cr
0xE3
SD
Saturation
Cb
SD
Saturation
Cr
0xE4
Reserved
ADC_SW_MAN_EN. Enable
manual setting of the input
signal muxing.
LB_TH[4:0]. Sets the threshold
value that determines if a line is
black.
Reserved
Reserved
LB_EL[3:0]. Programs the end line
of the activity window for LB
detection (end of field).
7 6
x
5
x
Bits
4 3
2
1
0
Comments
Notes
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No connection
No connection
AIN2
No connection
No connection
AIN5
AIN6
No connection
No connection
No connection
AIN8
No connection
No connection
AIN11
AIN12
No connection
SETADC_sw_man_
en = 1
x
0
1
1 0
0 0
Disable
Enable
1
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
Default threshold for the
detection of black lines.
Set as default
LB detection ends with
the last line of active
video on a field.
1100b: 262/525.
Letterbox detection
aligned with the start of
active video,
0100b: 23/286 NTSC.
LB_SL[3:0]. Program the start line
of the activity window for LB
detection (start of field).
0 1
0
0
Reserved
Reserved
SD_OFF_CB[7:0]. Adjusts the hue
by selecting the offset for the Cb
channel.
SD_OFF_CR[7:0]. Adjusts the hue
by selecting the offset for the Cr
channel.
SD_SAT_CB[7:0]. Adjusts the
saturation of the picture by
affecting gain on the Cb channel.
SD_SAT_CR[7:0]. Adjusts the
saturation of the picture by
affecting gain on the Cr channel.
0 0
0 0
1 0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1 0
0
0
0
0
0
0
1 0
0
0
0
0
0
0
Chroma gain = 0 dB
1 0
0
0
0
0
0
0
Chroma gain = 0 dB
Rev. B | Page 86 of 104
ADV7189B
Subaddress
Register
Bit Description
0xE5
NTSC V Bit
Begin
NVBEG[4:0]. How many lines after
lCOUNT rollover to set V high.
NVBEGSIGN
7 6
5
Bits
4 3
2
1
0
Comments
0
1
0
1
NTSC default (BT.656)
0
Set to low when manual
programming
Not suitable for user
programming
No delay
Additional delay by
1 line
No delay
Additional delay by
1 line
NTSC default (BT.656)
1
Set to low when manual
programming
Not suitable for user
programming
No delay
Additional delay by
1 line
No delay
Additional delay by
1 line
NTSC default
1
Set to low when manual
programming
Not suitable for user
programming
No delay
Additional delay by
1 line
No delay
Additional delay by
1 line
PAL default (BT.656)
0
0
1
NVBEGDELE. Delay V bit going
high by one line relative to
NVBEG (even field).
NVBEGDELO. Delay V bit going
high by one line relative to
NVBEG (odd field).
0xE6
NTSC V Bit
End
0
1
0
1
NVEND[4:0]. How many lines
after lCOUNT rollover to set V low.
NVENDSIGN
0
0
1
0
0
1
NVENDDELE. Delay V bit going
low by one line relative to NVEND
(even field).
NVENDDELO. Delay V bit going
low by one line relative to NVEND
(odd field).
0xE7
NTSC F Bit
Toggle
0
1
0
1
NFTOG[4:0]. How many lines after
lCOUNT rollover to toggle F signal.
NFTOGSIGN
0
0
0
1
0
1
NFTOGDELE. Delay F transition
by one line relative to NFTOG
(even field).
NFTOGDELO. Delay F transition
by one line relative to NFTOG
(odd field).
0xE8
PAL V Bit
Begin
0
1
0
1
PVBEG[4:0]. How many lines after
lCOUNT rollover to set V high.
PVBEGSIGN
0
0
0
1
PVBEGDELE. Delay V bit going
high by one line relative to
PVBEG (even field).
PVBEGDELO. Delay V bit going
high by one line relative to
PVBEG (odd field).
0
1
0
1
Rev. B | Page 87 of 104
1
0
Set to low when manual
programming
Not suitable for user
programming
No delay
Additional delay by
1 line
No delay
Additional delay by
1 line
Notes
ADV7189B
Subaddress
Register
Bit Description
0xE9
PAL V Bit
End
PVEND[4:0]. How many lines after
lCOUNT rollover to set V low.
PVENDSIGN
7 6
5
Bits
4 3
2
1
0
Comments
1
1
0
0
PAL default (BT.656)
1
Set to low when manual
programming
Not suitable for user
programming
No delay
Additional delay by
1 line
No delay
Additional delay by
1 line
PAL default (BT.656)
0
0
1
PVENDDELE. Delay V bit going
low by one line relative to PVEND
(even field).
PVENDDELO. Delay V bit going
low by one line relative to PVEND
(odd field).
0xEA
PAL F Bit
Toggle
0
1
0
1
PFTOG[4:0]. How many lines after
lCOUNT rollover to toggle F signal.
PFTOGSIGN
0
0
0
1
0
1
PFTOGDELE. Delay F transition by
one line relative to PFTOG (even
field).
PFTOGDELO. Delay F transition
by one line relative to PFTOG
(odd field).
0xF4
Drive
Strength
0
1
0
1
DR_STR_S[1:0]. Select the drive
strength for the sync output
signals.
DR_STR_C[1:0]. Select the drive
strength for the clock output
signal.
DR_STR[1:0]. Select the drive
strength for the data output
signals. Can be increased or
decreased for EMC or crosstalk
reasons.
0xF8
IF Comp
Control
Reserved
IFFILTSEL[2:0] IF filter selection
for PAL and NTSC
Reserved
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
x x
0 0
0
0
0
Rev. B | Page 88 of 104
Notes
Set to low when manual
programming
Not suitable for user
programming
No delay
Additional delay by
1 line
No delay
Additional delay by
1 line
Low drive strength (1x)
Medium-low drive
strength (2x)
Medium-high drive
strength (3x)
High drive strength (4x)
Low drive strength (1x)
Medium-low drive
strength (2x)
Medium-high drive
strength (3x)
High drive strength (4x)
Low drive strength (1x)
Medium-low drive
strength (2x)
Medium-high drive
strength (3x)
High drive strength (4x)
No delay
Bypass mode
2 MHz
5 MHz
−3 dB
−2 dB
−6 dB
−10 dB
Reserved
3 MHz
−2 dB
−5 dB
−7 dB
0dB
NTSC filters
+3.5 dB
+5 dB
6 MHz
+2 dB
+3 dB
+5 dB
PAL filters
ADV7189B
Subaddress
Register
Bit Description
0xF9
VS Mode
Control
EXTEND_VS_MAX_FREQ
7 6
5
Bits
4 3
2
1
0
Comments
0
Limit maximum Vsync
frequency to 66.25 Hz
(475 lines/frame)
Limit maximum Vsync
frequency to 70.09 Hz
(449 lines/frame)
Limit minimum Vsync
frequency to 42.75 Hz
(731 lines/frame)
Limit minimum Vsync
frequency to 39.51 Hz
(791 lines/frame)
Auto Coast mode
50 Hz Coast mode
60 Hz Coast mode
Reserved
1
EXTEND_VS_MIN_FREQ
0
1
VS_COAST_MODE[1:0]
Reserved
0
0
1
1
0 0
0
0
Rev. B | Page 89 of 104
0
1
0
1
Notes
This value sets up
the output coast
frequency.
ADV7189B
I2C PROGRAMMING EXAMPLES
EXAMPLES USING 28 MHz CLOCK
Mode 1 CVBS Input (Composite Video on AIN5)
All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10.
Table 87. Mode 1 CVBS Input
Register Address
0x00
0x03
0x15
0x17
0x1D
0x0F
0x3A
0x3D
0x3F
0x50
0x0E
Register Value
0x04
0x00
0x00
0x41
0x40
0x40
0x16
0xC3
0xE4
0x04
0x80
0x50
0x52
0x58
0x77
0x7C
0x7D
0x90
0x91
0x92
0x93
0x94
0xCF
0xD0
0xD5
0xD6
0xD7
0xE4
0xE5
0xE9
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0xC9
0x40
0x3C
0xCA
0xD5
0x50
0x4E
0xA0
0xDD
0xEA
0x3E
0x51
0x3E
0x0F
0x00
Notes
CVBS input on AIN5.
Enable 10-bit output on P19 to P10.
Slow down digital clamps.
Set CSFM to SH1.
Enable 28 MHz crystal.
TRAQ.
Power down ADC 1 and ADC 2.
MWE enable manual window.
BGB to 36.
Set DNR threshold to 4 for flat response.
ADI recommended programming sequence. This sequence must be followed exactly when setting
up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 90 of 104
ADV7189B
Mode 2 S-Video Input (Y on AIN1 and C on AIN4)
All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10.
Table 88. Mode 2 S-Video Input
Register Address
0x00
0x03
0x15
0x1D
0x0F
0x3A
0x3D
0x3F
0x50
0x0E
Register Value
0x06
0x00
0x00
0x40
0x40
0x12
0xC3
0xE4
0x04
0x80
0xB3
0x50
0x52
0x58
0x77
0x7C
0x7D
0x90
0x91
0x92
0x93
0x94
0xCF
0xD0
0xD6
0xE5
0xD5
0xD7
0xE4
0xE9
0xEA
0x0E
0xFE
0x20
0x18
0xED
0xC5
0x93
0x00
0xC9
0x40
0x3C
0xCA
0xD5
0x50
0x4E
0xDD
0x51
0xA0
0xEA
0x3E
0x3E
0x0F
0x00
Notes
Y1 = AIN1, C1 = AIN4.
Enable 10-bit output on P19 to P10.
Slow down digital clamps.
Enable 28 MHz crystal.
TRAQ.
Power down ADC 2.
MWE enable manual window.
BGB to 36.
Set DNR threshold to 4 for flat response.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 91 of 104
ADV7189B
Mode 3 YPrPb Input 525i/625i (Y on AIN2, Pr on AIN3, and Pb on AIN6)
All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10.
Table 89. Mode 3 YPrPb Input 525i/625i
Register Address
0x00
0x03
0x1D
0x0F
0x50
0x0E
Register Value
0x0A
0x00
0x40
0x40
0x04
0x80
0x52
0x58
0x77
0x7C
0x7D
0x90
0x91
0x92
0x93
0x94
0xCF
0xD0
0xD5
0xD6
0xE4
0xE5
0xE9
0x0E
0x18
0xED
0xC5
0x93
0x00
0xC9
0x40
0x3C
0xCA
0xD5
0x50
0x4E
0xA0
0xDD
0x3E
0x51
0x3E
0x00
Notes
Y2 = AIN2, Pr2 = AIN3, Pb2 = AIN6.
Enable 10-bit output on P19 toP10.
Enable 28 MHz crystal.
TRAQ.
Set DNR threshold to 4 for flat response.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 92 of 104
ADV7189B
Mode 4 CVBS Tuner Input PAL Only on AIN4
10-bit, ITU-R BT.656 output on P19 to P10.
Table 90. Mode 4 CVBS Tuner Input PAL Only
Register Address
0x00
0x03
0x07
0x15
0x17
0x19
0x1D
0x0F
0x3A
0x3D
0x3F
0x50
0x0E
Register Value
0x83
0x00
0x01
0x00
0x41
0xFA
0x40
0x40
0x16
0xC3
0xE4
0x0A
0x80
0x50
0x52
0x58
0x77
0x7C
0x7D
0x90
0x91
0x92
0x93
0x94
0xCF
0xD0
0xD5
0xD6
0xD7
0xE4
0xE5
0xE9
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0xC9
0x40
0x3C
0xCA
0xD5
0x50
0x4E
0xA0
0xDD
0xEA
0x3E
0x51
0x3E
0x0F
0x00
Notes
CVBS AIN4 Force PAL-only mode.
Enable 10-bit output on P19 to P10.
Enable PAL autodetection only.
Slow down digital clamps.
Set CSFM to SH1.
Stronger dot crawl reduction.
Enable 28 MHz crystal.
TRAQ.
Power down ADC 1 and ADC 2.
MWE enable manual window.
BGB to 36.
Set higher DNR threshold.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 93 of 104
ADV7189B
EXAMPLES USING 27 MHz CLOCK
Mode 1 CVBS Input (Composite Video on AIN5)
All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10.
Table 91. Mode 1 CVBS Input
Register Address
0x00
0x03
0x15
0x17
0x3A
0x50
0x0E
Register Value
0x04
0x00
0x00
0x41
0x16
0x04
0x80
0x50
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xD7
0xE4
0xE9
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0xEA
0x3E
0x3E
0x0F
0x00
Notes
CVBS input on AIN5.
Enable 10-bit output on P19 to P10.
Slow down digital clamps.
Set CSFM to SH1.
Power down ADC 1 and ADC 2.
Set DNR threshold to 4 for flat response.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 94 of 104
ADV7189B
Mode 2 S-Video Input (Y on AIN1 and C on AIN4)
All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10.
Table 92. Mode 2 S-Video Input
Register Address
0x00
0x03
0x15
0x3A
0x50
0x0E
Register Value
0x06
0x00
0x00
0x12
0x04
0x80
0x50
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xD7
0xE4
0xE9
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0xEA
0x3E
0x3E
0x0F
0x00
Notes
Y1 = AIN1, C1 = AIN4.
Enable 10-bit output on P19 to P10.
Slow down digital clamps.
Power down ADC 2.
Set DNR threshold to 4 for flat response.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Mode 3 YPrPb Input 525i/625i (Y on AIN2, Pr on AIN3, and Pb on AIN6)
All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10.
Table 93. Mode 3 YPrPb Input 525i/625i
Register Address
0x00
0x03
0x50
0x0E
Register Value
0x0A
0x00
0x04
0x80
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xE4
0xE9
0x0E
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0x3E
0x3E
0x00
Notes
Y2 = AIN2, Pr2 = AIN3, Pb2 = AIN6.
Enable 10-bit output on P19 to P10.
Set DNR threshold to 4 for flat response.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 95 of 104
ADV7189B
Mode 4 CVBS Tuner Input PAL Only on AIN4
10-bit, ITU-R BT.656 output on P19 to P10.
Table 94. Mode 4 CVBS Tuner Input PAL Only
Register Address
0x00
0x03
0x07
0x15
0x17
0x19
0x3A
0x50
0x0E
Register Value
0x83
0x00
0x01
0x00
0x41
0xFA
0x16
0x0A
0x80
0x50
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xD7
0xE4
0xE9
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0xEA
0x3E
0x3E
0x0F
0x00
Notes
CVBS AIN4 Force PAL only mode.
Enable 10-bit output on P19 to P10.
Enable PAL autodetection only.
Slow down digital clamps.
Set CSFM to SH1.
Stronger dot crawl reduction.
Power down ADC 1 and ADC 2.
Set higher DNR threshold.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 96 of 104
ADV7189B
PCB LAYOUT RECOMMENDATIONS
It is recommended to use a single ground plane for the entire
board. This ground plane should have a space between the
analog and digital sections of the PCB (see Figure 42).
26H
ADV7189B
ANALOG INTERFACE INPUTS
ANALOG
SECTION
Take care when routing the inputs on the PCB. Track lengths
should be kept to a minimum, and 75 Ω trace impedances
should be used when possible. Trace impedances other than
75 Ω increase the chance of reflections.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with
0.1 μF and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin.
Also, avoid placing the capacitor on the opposite side of the PC
board from the ADV7189B, as doing so interposes resistive vias
in the path. The bypass capacitors should be located between
the power plane and the power pin. Current should flow from
the power plane to the capacitor to the power pin. Do not make
the power connection between the capacitor and the power pin.
Placing a via underneath the 100 nF capacitor pads, down to the
power plane, is generally the best approach (see Figure 41).
DIGITAL
SECTION
04983-0-039
The ADV7189B is a high precision, high speed, mixed-signal
device. To achieve the maximum performance from the part, it
is important to have a well laid out PCB board. The following is
a guide for designing a board using the ADV7189B.
Figure 42. PCB Ground Layout
Experience has repeatedly shown that noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
In some cases, using separate ground planes is unavoidable.
For these cases, it is recommended to place a single ground
plane under the ADV7189B. The location of the split should be
under the ADV7189B. For this case, it is even more important
to place components wisely because the current loops are much
longer (current takes the path of least resistance). Here is an
example of a current loop: power plane to ADV7189B to digital
output trace to digital data receiver to digital ground plane to
analog ground plane.
261H
PLL
VDD
VIA TO SUPPLY
10nF
VIA TO GND
04983-0-038
GND
Place the PLL loop filter components as close as possible to
the ELPF pin. Do not place any digital or other high frequency
traces near these components. Use the values suggested in the
data sheet with tolerances of 10% or less.
100nF
Figure 41. Recommend Power Supply Decoupling
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
It is particularly important to maintain low noise and good
stability of PVDD. Careful attention must be paid to regulation,
filtering, and decoupling. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups
(AVDD, DVDD, DVDDIO, and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can, in turn, produce changes in the regulated
analog supply voltage. This is mitigated by regulating the analog
supply, or at least PVDD, from a different, cleaner, power source,
for example, from a 12 V supply.
Try to minimize the trace length that digital outputs have to
drive. Longer traces have higher capacitance, which require
more current, which causes more internal digital noise. Shorter
traces reduce the possibility of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7189B.
If series resistors are used, place them as close as possible to the
ADV7189B pins. However, try not to add vias or extra length to
the output trace to make the resistors closer.
If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7189B, creating more
digital noise on its power supplies.
Rev. B | Page 97 of 104
ADV7189B
DIGITAL INPUTS
CRYSTAL LOAD CAPACITOR VALUE SELECTION
The digital inputs on the ADV7189B are designed to work with
3.3 V signals, and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied
to the decoder.
ANTIALIASING FILTERS
For inputs from some video sources that are not bandwidth
limited, signals outside the video band can alias back into the
video band during A/D conversion and appear as noise on the
output video. The ADV7189B oversamples the analog inputs
by a factor of 4. This 54 MHz sampling frequency reduces the
requirement for an input filter; for optimal performance it is
recommended that an antialiasing filter be employed. The
recommended low cost circuit for implementing this buffer and
filter circuit for all analog input signals is shown in Figure 45.
Figure 44 shows an example reference clock circuit for the
ADV7189B. Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7189B. Small
variations in reference clock frequency can cause autodetection
issues and impair the ADV7189B performance.
265H
Note: Load capacitor values are dependent on crystal attributes.
The load capacitance given in a crystal data sheet specifies the
parallel resonance frequency within the tolerance at 25°C. It is
therefore important to design a circuit that matches the load
capacitance in order to achieve the frequency stipulated by the
manufacturer. For detailed crystal circuit design and optimization, an application note on crystal design considerations is
available for further reference.
263H
XTAL 1
XTAL
R = 1MΩ
C1 = 47pF
XTAL
28.63636MHz
C2 = 47pF
04983-0-046
The buffer is a simple emitter-follower using a single npn
transistor. The antialiasing filter is implemented using passive
components. The passive filter is a third-order Butterworth
filter with a −3 dB point of 9 MHz. The frequency response of
the passive filter is shown in Figure 43. The flat pass band up to
6 MHz is essential. The attenuation of the signal at the output of
the filter due to the voltage divider of R24 and R63 is compensated for in the ADV7189B part using the automatic gain
control. The ac-coupling capacitor at the input to the buffer
creates a high-pass filter with the biasing resistors for the
transistor. This filter has a cut-off of
Figure 44. Crystal Circuit
264H
Use the following guidelines to ensure correct operation:
{2 × π × (R39||R89) × C93}–1 = 0.62 Hz
It is essential the cutoff of this filter is less than 1 Hz to ensure
correct operation of the internal clamps within the part. These
clamps ensure that the video stays within the 5 V range of the
op amp used.
0
–20
•
Use the correct frequency crystal, which is
28.63636 MHz. Tolerance should be 50 ppm or better.
•
Use a parallel-resonant crystal.
•
Place a 1 MΩ shunt resistor across pins XTAL1 and
XTAL2 as is shown in Figure 45.
•
Know the CLOAD for the crystal part number selected.
The value of Capacitors C1 and C2 must match CLOAD
for the specific crystal part number in the user’s
system.
•
To find CLOAD use the following guideline:
C1 = C2 = C
C = 2(CLOAD − CS) − Cpg
Where Cpg is the pin to ground capacitance.
Approximately 4 pF to 10 pF.
–40
–60
CS is the PCB stray capacitance.
Approximately 2 pF to 3pF.
–80
For example:
–120
100k
CLOAD = 30 pF
C = 2(30 − 3) − 4
= 50 pF
Therefore two 47 pF capacitors can be chosen for
C1 and C2.
04983-0-040
–100
300k
1M
3M
10M
30M
100M
300M
1G
FREQUENCY (Hz)
Figure 43. Third-Order Butterworth Filter Response
Rev. B | Page 98 of 104
ADV7189B
TYPICAL CIRCUIT CONNECTION
Examples of how to connect the ADV7189B video decoder are shown in Figure 45 and Figure 46. For a detailed schematic diagram for
the ADV7189B, refer to the ADV7189B evaluation note.
26H
267H
AVDD_5V
BUFFER
R39
4.7kΩ
R38
75Ω
R53
56Ω
R89
5.6kΩ
C
B
IN
Q6
E
FILTER
L10
12μH
OUT
R24
470Ω
C95
22pF
AGND
C102
10pF
R63
820Ω
04983-0-041
C93
100μF
R43
0Ω
Figure 45. ADI Recommended Anti-Aliasing Circuit for All Input Channels
Rev. B | Page 99 of 104
ADV7189B
FERRITE BEAD
DVDDIO
(3.3V)
33μF
10μF
PVDD
(1.8V)
33μF
10μF
33μF
AGND
10μF
33μF
0.1μF
AGND
10μF
AIN1
AIN7
100nF
DVDDIO
ANTIALIAS
FILTER CIRCUIT
DGND
AVDD
DGND
100nF
PVDD
DGND
0.1μF
DVDD
AGND DGND
AIN8
AIN3
ANTIALIAS
FILTER CIRCUIT
AIN9
100nF
ADV7189B
AIN4
Pb
ANTIALIAS
FILTER CIRCUIT
100nF
CBVS
ANTIALIAS
FILTER CIRCUIT
100nF
AIN10
AIN5
AIN11
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
AIN6
RECOMMENDED ANTIALIAS FILTER
CIRCUIT IS SHOWN IN FIGURE 45 ON THE
PREVIOUS PAGE. THIS CIRCUIT INCLUDES
A 75Ω TERMINATION RESISTOR, INPUT
BUFFER AND ANTIALIASING FILTER.
0.01μF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DGND
0.01μF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
AGND
0.01μF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
AGND
0.01μF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DGND
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
AIN2
ANTIALIAS
FILTER CIRCUIT
100nF
AIN12
MULTIFORMAT
PIXEL
PORT
P19–P10 10-BIT ITU-R BT.656 PIXEL DATA @ 27MHz
P9–P0 Cb AND Cr 20-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
P19–P10 Y 20-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
AGND
AGND
CAPY1
+
0.1μF
10μF
0.1μF
1nF
CAPY2
LLC1
27MHz OUTPUT CLOCK
LLC2
13.5MHz OUTPUT CLOCK
0.1μF
AGND
CAPC1
+
10μF
0.1μF
1nF
CAPC2
AGND
+
OE
CML
10μF
0.1μF
+
10μF
NOTE:
1CAPACITOR VALUES
ARE DEPENDANT ON
XTAL ATTRIBUTES.
DVDDIO
SELECT I2C
ADDRESS
OUTPUT ENABLE I/P
REFOUT
0.1μF
INTERRUPT O/P
INTRQ
AGND
1MΩ
XTAL
28.63636MHz
XTAL1
47pF1
SFL
SFL O/P
HS
HS O/P
VS
VS O/P
FIELD
FIELD O/P
47pF1
DGND
DGND
DVSS
ALSB
DVDDIO
2kΩ
DVDDIO
ELPF
2kΩ
1.69kΩ
100Ω
SCLK
MPU INTERFACE
CONTROL LINES
10nF
82nF
100Ω
SDA
PVDD
DVDDIO
4.7kΩ
RESET
RESET
100nF
DGND
AGND
DGND
AGND
DGND
Figure 46. Typical Connection Diagram
Rev. B | Page 100 of 104
04983-0-042
Pr
0.1μF
AGND
AGND
FERRITE BEAD
DVDD
(1.8V)
Y
DGND
AGND
AGND
FERRITE BEAD
AVDD
(3.3V)
S-VIDEO
0.1μF
DGND
DGND
FERRITE BEAD
ADV7189B
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.20
16.00 SQ
15.80
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.10 MAX
COPLANARITY
SEATING
PLANE
VIEW A
20
41
40
21
VIEW A
0.65
BSC
LEAD PITCH
ROTATED 90° CCW
0.38
0.32
0.22
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 47. 80-Lead Low Profile Quad Flat Package[LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADV7189BKSTZ 2
ADV7189BBSTZ2
EVAL-ADV7189BEB
9F
10F
268H
Temperature Range
0°C to +70°C
–40°C to +85°C
Package Description
80-lead Low Profile Quad Flat Package (LQFP)
80-lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
1
Package Option
ST-80-2
ST-80-2
The ADV7189B is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each
device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-mount soldering at up to 255°C (±5°C). In addition, it is
backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional
reflow temperatures of 220°C to 235°C.
2
Z = Pb-free part.
Rev. B | Page 101 of 104
ADV7189B
NOTES
Rev. B | Page 102 of 104
ADV7189B
NOTES
Rev. B | Page 103 of 104
ADV7189B
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04983–0–9/05(B)
Rev. B | Page 104 of 104